A bc battery and a method of manufacturing the same

Abstract

The application discloses a BC battery and a preparation method thereof. The method comprises the following steps: providing an N-type silicon substrate; the N-type silicon substrate comprises a front surface and a back surface; preparing a textured structure on the front surface, and forming a multilayer passivation layer on the surface of the textured structure on the front surface away from the N-type silicon substrate; preparing a first tunneling oxide layer and a first doped layer in a first region; preparing a second tunneling oxide layer and a second doped layer in a second region; the thickness of the first tunneling oxide layer is smaller than that of the second tunneling oxide layer, and the thickness of the first doped layer is smaller than that of the second doped layer; screen printing and low-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer; the material of the first electrode is different from that of the second electrode, and a preset circular arc chamfer exists at the edges of the first electrode and the second electrode. By using the above method, the interface recombination loss is reduced, and the open circuit voltage and the photoelectric conversion efficiency are improved.

Description

Technical Field

[0001] This invention relates to the technical field of solar cells, and more particularly to a BC cell and its preparation method. Background Technology

[0002] Back-contact (BC) solar cells have become an important development direction for high-efficiency crystalline silicon photovoltaic technology due to their advantages such as no grid lines blocking the front side and high conversion efficiency.

[0003] Current BC cells use an N-type silicon substrate and form interdigitated P-type emitter regions and N-type field regions on the back side. This approach involves fabricating a textured structure and depositing a passivation antireflection layer on the front side of the cell, and fabricating a tunneling oxide layer and a doped polycrystalline silicon layer in the P / N region on the back side to form a passivation contact structure. Finally, silver paste is screen-printed and sintered to form the back electrode.

[0004] However, in existing designs, the tunneling oxide layer and doped layer in the P-type and N-type regions on the back side are designed with a uniform thickness, which cannot be optimized for the carrier transport characteristics of different regions. This results in high interface recombination loss, limiting further improvement in open-circuit voltage and photoelectric conversion efficiency. Secondly, the back electrode usually uses all-silver paste, which is costly and fails to differentiate the contact characteristics of different polarity regions. In addition, the electrode edges are usually right angles or sharp structures, which can easily generate electric field concentration under conditions such as local shading, exacerbating carrier recombination and potentially causing hot spot effects, affecting the long-term operational reliability of the battery. Summary of the Invention

[0005] This invention provides a BC battery and its fabrication method. By setting a tunneling oxide layer and a doped layer of gradient thickness in the first and second regions, it achieves precise adaptation to different carrier transport characteristics and effectively reduces interfacial recombination losses. At the same time, the use of partitioned composite metal electrodes and rounded chamfered electrode edges not only significantly reduces the amount of silver paste and contact resistance, but also reduces electric field concentration and hot spot risks, thereby improving the battery's conversion efficiency, reliability, and cost-effectiveness.

[0006] In a first aspect, the present invention provides a method for preparing a BC battery, comprising: An N-type silicon substrate is provided; the N-type silicon substrate includes a front side and a back side, the back side including a first region and a second region arranged in an alternating interdigitated pattern; A textured structure is fabricated on the front side, and a multilayer passivation layer is formed on the surface of the textured structure on the side facing away from the N-type silicon substrate. A first tunneling oxide layer and a first doped layer are prepared in the first region; A second tunneling oxide layer and a second doped layer are prepared in the second region; the thickness of the first tunneling oxide layer is less than the thickness of the second tunneling oxide layer, and the thickness of the first doped layer is less than the thickness of the second doped layer; The first region and the second region are screen printed and sintered at low temperature to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer; the materials of the first electrode and the second electrode are different, and the edges of the first electrode and the second electrode both have a preset rounded chamfer.

[0007] Optionally, a multilayer passivation layer is formed on the surface of the textured structure on the side facing away from the N-type silicon substrate, including: Using a first deposition process, under first preset conditions, a first passivation layer is formed on the surface of the textured structure on the side away from the N-type silicon substrate. Using a second deposition process, under second preset conditions, a second passivation layer is formed on the surface of the first passivation layer on the side away from the N-type silicon substrate; Using a third deposition process, under third preset conditions, a third passivation layer is formed on the surface of the second passivation layer on the side away from the N-type silicon substrate.

[0008] Optionally, the first preset conditions are: introducing a mixed solution of tetraethyl orthosilicate and ozone into the first deposition process; a deposition temperature of 250℃-300℃; a chamber pressure of 50Pa-150Pa; and a deposition rate of 0.08nm / cycle-0.12nm / cycle. The second preset conditions are: introducing a mixed solution of trimethylaluminum and deionized water into the second deposition process; a deposition temperature of 200℃-280℃; a chamber pressure of 60Pa-120Pa; and a deposition rate of 0.1nm / cycle-0.15nm / cycle. The third preset conditions are: introducing a mixed gas of silane and ammonia with a flow ratio of 1:8-1:12 into the third deposition process; a deposition temperature of 300℃-380℃; a chamber pressure of 200Pa-400Pa; and a radio frequency power of 300W-500W.

[0009] Optionally, the thickness of the first passivation layer is 1.5nm-2.5nm and the refractive index is 1.45-1.48; the thickness of the second passivation layer is 6nm-10nm and the refractive index is 1.60-1.65; and the thickness of the third passivation layer is 60nm-80nm and the refractive index is 2.05-2.15.

[0010] Optionally, a first tunneling oxide layer and a first doped layer are prepared in the first region, including: Using a fourth deposition process, under fourth preset conditions, a first tunneling oxide layer is formed in the first region; the fourth preset conditions are: a mixed gas of silane and oxygen is introduced into the fourth deposition process, the deposition temperature is 580℃-620℃, and the cavity pressure is 80Pa-120Pa. Using the fifth deposition process, under the fifth preset conditions, a first doped layer is formed on the surface of the first tunneling oxide layer on the side away from the N-type silicon substrate; the fifth preset conditions are that a mixed gas formed by silane and diborane is introduced into the fifth deposition process, the deposition temperature is 580℃-620℃, and the chamber pressure is 80Pa-120Pa.

[0011] Optionally, the thickness of the first tunneling oxide layer is 1.0 nm-1.4 nm, and the refractive index is 1.45-1.48; the thickness of the second tunneling oxide layer is 1.6 nm-2.0 nm, and the refractive index is 1.45-1.48; the thickness of the first doped layer is 18 nm-22 nm, and the sheet resistance is 40 Ω / □-70 Ω / □; the thickness of the second doped layer is 23 nm-27 nm, and the sheet resistance is 30 Ω / □-60 Ω / □.

[0012] Optionally, the preset chamfer radius is 8μm-15μm.

[0013] Optionally, the material of the first electrode is a silver-copper composite paste with a thickness of 18μm-25μm and a solid content of 85%-92%; the material of the second electrode is a nano-carbon-doped aluminum paste with a thickness of 20μm-28μm.

[0014] Optionally, after forming the first electrode in contact with the first doped layer and the second electrode in contact with the second doped layer, the method further includes: A barrier layer is prepared in the spacer region between the first region and the second region.

[0015] Secondly, the present invention provides a BC battery, which is prepared using the above-described BC battery preparation method.

[0016] The technical solution of this invention involves providing an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side, the back side including a first region and a second region arranged in an alternating interdigitated pattern; a textured structure is prepared on the front side, and a multilayer passivation layer is formed on the surface of the textured structure on the side of the front side facing away from the N-type silicon substrate; a first tunneling oxide layer and a first doped layer are prepared in the first region; a second tunneling oxide layer and a second doped layer are prepared in the second region; the thickness of the first tunneling oxide layer is less than the thickness of the second tunneling oxide layer, and the thickness of the first doped layer is less than the thickness of the second doped layer; the first region and the second region are screen printed and sintered at low temperature to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer; the materials of the first electrode and the second electrode are different, and the edges of both the first electrode and the second electrode have a preset rounded chamfer. Using the above method, by setting tunneling oxide and doped layers of gradient thickness in the first and second regions, precise adaptation to different carrier transport characteristics is achieved, effectively reducing interface recombination losses. At the same time, the use of partitioned composite metal electrodes and rounded chamfers at the electrode edges not only significantly reduces the amount of silver paste and contact resistance, but also reduces electric field concentration and hot spot risks, thereby improving the battery's conversion efficiency, reliability, and cost-effectiveness.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a method for preparing a BC battery according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a BC battery provided in an embodiment of the present invention; Figure 3 A flowchart illustrating another method for preparing a BC battery according to an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] In one embodiment, Figure 1 This is a flowchart of a method for preparing a BC battery according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a BC battery structure provided by an embodiment of the present invention. This embodiment is applicable to situations where interface recombination losses are reduced and open-circuit voltage and battery conversion efficiency are improved, such as... Figure 1 and Figure 2 As shown, the method includes: S110 provides an N-type silicon substrate.

[0023] The N-type silicon substrate includes a front side and a back side, with the back side including a first region and a second region arranged in an alternating interdigitated pattern.

[0024] Among them, N-type silicon substrate 1 refers to a single-crystal silicon wafer with electrons as the majority carriers. Its minority carrier (hole) lifetime is relatively long, making it suitable for making high-efficiency batteries.

[0025] Specifically, by setting interdigitated first and second regions on the back side of the N-type silicon substrate 1, the PN junction originally located on the front side is transferred to the back side, ensuring that all subsequently fabricated metal electrodes are located on the back side, thereby completely eliminating the light-blocking loss of the front-side gate lines. The front side then serves as a pure light-receiving surface, focusing on light trapping and passivation. This structural premise ensures that the incident light is absorbed and utilized to the maximum extent, laying the foundation for achieving high short-circuit current and high open-circuit voltage.

[0026] S120. A textured structure is prepared on the front side, and a multilayer passivation layer is formed on the surface of the textured structure on the side away from the N-type silicon substrate.

[0027] The textured structure 2 is a micron-sized pyramidal morphology formed on the silicon surface by alkaline or acidic etching solution, used to reduce the reflectivity of incident light and increase the propagation path of light within the silicon. The first composite passivation layer 3 is a thin film stack structure formed by sequentially depositing different materials on the textured structure 2 on the front side of the N-type silicon substrate 1, used to reduce the dangling bond density on the silicon surface, suppress carrier recombination, and also has anti-reflection function.

[0028] Specifically, a texturing process is used to fabricate a textured structure 2 on the front side of an N-type silicon substrate 1. This transforms the surface of the N-type silicon substrate 1 from a smooth, mirror-like surface to a rough, light-trapping surface, causing incident light to undergo multiple reflections and refractions between the textured structures 2 until it is fully absorbed by the silicon material, thereby maximizing the generation rate of photogenerated carriers. After forming the textured structure 2, multiple passivation layers 3 are sequentially formed on the side of the textured structure 2 facing away from the N-type silicon substrate 1. These multiple passivation layers 3 combine chemical passivation and field-effect passivation, effectively reducing the surface recombination rate and increasing the open-circuit voltage, which is fundamental to achieving high-efficiency batteries. In this embodiment, the method for fabricating the textured structure 2 may include, but is not limited to, using alkaline solutions (such as the KOH / IPA system) or acidic etching solutions (such as the HF / HNO3 system). Laser etching or reactive ion etching (RIE) can also be used to form a nanoscale textured structure. The specific method can be determined according to the actual situation and is not limited here. The method for preparing the multilayer passivation layer 3 may include, but is not limited to, atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or sputtering, etc. The specific method can be determined according to the actual situation and is not limited here.

[0029] S130, Prepare a first tunneling oxide layer and a first doped layer in the first region.

[0030] The first tunneling oxide layer 41 is an ultrathin silicon dioxide layer that allows majority carriers to tunnel through while blocking minority carrier recombination, thus achieving interface passivation. The first doped layer 42 is a P-type doped layer (i.e., the emitter region) formed in the first region. By doping the N-type silicon substrate 1 with group III elements (such as boron), a PN junction is formed, which is the core region for generating photovoltage.

[0031] Specifically, a first tunneling oxide layer 41 of a certain thickness is formed in the first region using a deposition process. After forming the first tunneling oxide layer 41, an intrinsic silicon layer of a certain thickness is deposited on the surface of the first tunneling oxide layer 41 on the side facing away from the N-type silicon substrate 1. Elemental doping is then performed on the intrinsic silicon layer, allowing elements to diffuse into it, thereby forming a first doped layer 42. In this embodiment, the preparation method of the first tunneling oxide layer 41 may include, but is not limited to, deposition via thermal oxidation, chemical oxidation, O3 oxidation, or ALD, etc., and the specific method can be determined according to the actual situation, without limitation. The preparation method of the first doped layer 42 may include, but is not limited to, depositing an intrinsic silicon layer via LPCVD or PECVD, followed by ion implantation, diffusion, or in-situ doping to form a doped layer of the desired doping type and concentration.

[0032] S140, Prepare a second tunneling oxide layer and a second doped layer in the second region.

[0033] The second tunneling oxide layer 51, like the first tunneling oxide layer 41, is an ultrathin silicon dioxide layer used to allow majority carriers to tunnel through while blocking minority carrier recombination, thus achieving interface passivation. The second doped layer 52 is an N-type doped layer formed in the second region. By doping the N-type silicon substrate 1 with a group 5 element (such as phosphorus), an N+ heavily doped layer of the same type as the N-type silicon substrate 1 is formed. The second doped layer 52 utilizes the band bending effect to form a back field, which can effectively repel minority carriers (holes) from moving to the back side, reduce back-side recombination, and improve ohmic contact with the metal electrode.

[0034] Specifically, a second tunneling oxide layer 51 of a certain thickness is formed in the second region using a deposition process. After forming the second tunneling oxide layer 51, an intrinsic silicon layer of a certain thickness is deposited on the surface of the second tunneling oxide layer 51 on the side facing away from the N-type silicon substrate 1. Elemental doping is then performed on the intrinsic silicon layer, allowing elements to diffuse into it, thereby forming a second doped layer 52. In this embodiment, the preparation method of the second tunneling oxide layer 51 may include, but is not limited to, deposition via thermal oxidation, chemical oxidation, O3 oxidation, or ALD, etc., and the specific method can be determined according to the actual situation, without limitation. The preparation method of the second doped layer 52 may include, but is not limited to, depositing an intrinsic silicon layer via LPCVD or PECVD, followed by ion implantation, diffusion, or in-situ doping to form a doped layer of the desired doping type and concentration.

[0035] It should be noted that in this embodiment, the thickness of the first tunneling oxide layer 41 is less than the thickness of the second tunneling oxide layer 51, and the thickness of the first doped layer 42 is less than the thickness of the second doped layer 52. Specifically, the first tunneling oxide layer 41 and the second tunneling oxide layer 51 are located on the surfaces of the first region (i.e., the P-type emitter region) and the second region (i.e., the N-type field region), respectively. Since the P-region requires more efficient majority carrier (hole) tunneling transport to reduce contact resistance, while the N-region has higher requirements for interface passivation to suppress minority carrier recombination, this embodiment designs the first tunneling oxide layer 41 to be thinner and the first doped layer 42 to be correspondingly thinner, achieving a gradient setting to prioritize efficient hole tunneling and low-resistance transport; at the same time, the second tunneling oxide layer 51 is designed to be thicker and the second doped layer 52 to be correspondingly thicker, in order to enhance the field-effect passivation capability and block electron diffusion to the interface recombination center. The advantage of this differentiated gradient design is that it can adapt to the different carrier transport and recombination suppression requirements of the P-region and N-region respectively, achieving both low contact resistance and high open-circuit voltage overall, thereby significantly improving the fill factor and photoelectric conversion efficiency of the battery. Testing showed that the open-circuit voltage increased to 735mV, and the photoelectric conversion efficiency reached 27.92%.

[0036] S150. Screen printing and low-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer.

[0037] The first electrode 6 and the second electrode 7 are metal grid lines that form ohmic contact with the P-type emitter region and the N-type back field region, respectively, to collect and conduct current; since they are all located on the back side, they are ensured not to contact each other through subsequent isolation structures.

[0038] Specifically, after forming the first doped layer 42 in the first region and the second doped layer 52 in the second region, electrode structures need to be fabricated to form ohmic contacts with the doped layers. Specifically, different types of conductive pastes are coated using a patterned printing method by screen printing and low-temperature sintering on the first and second regions respectively. The first region uses a metal paste, while the second region uses a different paste that is more cost-effective or has better contact characteristics. After printing, co-sintering is performed at a lower temperature to ensure good ohmic contact between the paste and the doped layers, while avoiding damage to the underlying passivation structure. After sintering, electrodes are formed on the surfaces of the first doped layer 42 and the second doped layer 52, respectively, namely, the first electrode 6 contacting the first doped layer 42 and the second electrode 7 contacting the second doped layer 52.

[0039] It should be noted that in this embodiment, the materials of the first electrode 6 and the second electrode 7 are different, and both the first electrode 6 and the second electrode 7 have preset rounded chamfers at their edges. That is, the first electrode 6 and the second electrode 7 use different conductive pastes (for example, the first electrode 6 uses a silver-copper composite paste to reduce contact resistance, while the second electrode 7 uses nano-carbon-doped aluminum paste to balance conductivity and cost reduction). The purpose is to optimize the ohmic contact quality based on the different metal-semiconductor contact characteristics of the two doped regions, thereby reducing the overall contact resistance and the amount of precious silver used, as well as reducing manufacturing costs and contact losses. Simultaneously, the edges of both electrodes are designed with preset rounded chamfers to eliminate the sharp electric field concentration effect that is easily generated at the ends of traditional rectangular or sharp-cornered electrodes, avoiding localized high electric fields that exacerbate carrier recombination, suppressing recombination current at the electrode edges, and thus effectively improving the battery's fill factor, photoelectric conversion efficiency, and long-term operational stability.

[0040] Tests show that the BC cells prepared by the above method have a cell conversion efficiency of up to 27.92%, a power temperature coefficient as low as -0.252% / ℃, a reliability efficiency degradation rate of only 4.16% under 3000h of damp heat testing, and a significant reduction in silver paste usage. They are suitable for high-efficiency bifacial photovoltaic modules and can be widely used in various photovoltaic power plants and distributed photovoltaic scenarios.

[0041] The technical solution of this invention involves providing an N-type silicon substrate; the N-type silicon substrate includes a front side and a back side, the back side including a first region and a second region arranged in an alternating interdigitated pattern; a textured structure is prepared on the front side, and a multilayer passivation layer is formed on the surface of the textured structure on the side of the front side facing away from the N-type silicon substrate; a first tunneling oxide layer and a first doped layer are prepared in the first region; a second tunneling oxide layer and a second doped layer are prepared in the second region; the thickness of the first tunneling oxide layer is less than the thickness of the second tunneling oxide layer, and the thickness of the first doped layer is less than the thickness of the second doped layer; the first region and the second region are screen printed and sintered at low temperature to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer; the materials of the first electrode and the second electrode are different, and the edges of both the first electrode and the second electrode have a preset rounded chamfer. Using the above method, by setting tunneling oxide and doped layers of gradient thickness in the first and second regions, precise adaptation to different carrier transport characteristics is achieved, effectively reducing interface recombination losses. At the same time, the use of partitioned composite metal electrodes and rounded chamfers at the electrode edges not only significantly reduces the amount of silver paste and contact resistance, but also reduces electric field concentration and hot spot risks, thereby improving the battery's conversion efficiency, reliability, and cost-effectiveness.

[0042] Optionally, the preset chamfer radius of the rounded chamfer is 8μm-15μm. For example, the preset chamfer radius can be 8μm, 10μm, 12μm, 13μm, 14μm or 15μm, etc., which can be determined according to the actual situation and is not limited here.

[0043] In another specific embodiment, the material of the first electrode 6 is a silver-copper composite paste with a thickness of 18μm-25μm and a solid content of 85%-92%; the material of the second electrode 7 is a nano-carbon-doped aluminum paste with a thickness of 20μm-28μm.

[0044] Specifically, in this embodiment, the first electrode 6 is made of a silver-copper composite paste, utilizing the high conductivity of silver and the low cost of copper to synergistically reduce contact resistance. The thickness of the first electrode 6 is controlled between 18μm and 25μm; for example, the thickness can be 18μm, 20μm, 22μm, 23μm, 24μm, or 25μm, etc., and can be determined according to actual conditions, without limitation. The solid content of the silver-copper composite paste is 85%-92%; for example, the solid content can be 85%, 86%, 88%, 90%, 91%, or 92%, and can be determined according to actual conditions, without limitation. The purpose of setting the thickness and solid content is to ensure electrode density and conductivity while avoiding excessive thickness that could lead to stress or light-blocking loss.

[0045] For the second electrode 7, the material of the second electrode 7 is aluminum paste doped with nano-carbon, so as to improve the contact performance between the aluminum paste and the N-type silicon substrate 1 and reduce the contact resistance by utilizing nano-carbon. The thickness of the second electrode 7 is controlled between 20μm and 28μm. For example, the thickness can be 20μm, 22μm, 23μm, 25μm, 27μm, or 28μm, etc., which can be determined according to the actual situation and is not limited here. The thickness can be slightly increased to compensate for the slight deficiency that the conductivity of aluminum-based materials is lower than that of silver. At the same time, the addition of nano-carbon can suppress the formation of aluminum spikes and improve the contact uniformity. The advantages of this setup are as follows: the first region (i.e., the P region) and the second region (i.e., the N region) each use the optimal paste adapted to their respective doping types. The P region uses silver-copper paste to achieve low resistance and low-cost conductivity, while the N region uses nano-carbon-doped aluminum paste to further reduce the amount of silver paste used and avoid the poor contact problem that is common in traditional pure aluminum electrodes. The differential thickness design ensures that both electrodes can achieve good ohmic contact and adhesion after co-sintering, thereby significantly reducing precious metal consumption, reducing contact recombination loss, and improving the fill factor and long-term reliability of the battery.

[0046] In another specific embodiment, Figure 3This is a flowchart of another method for fabricating a BC battery according to an embodiment of the present invention. This embodiment refines the specific implementation of the above embodiment S120, which involves forming a multilayer passivation layer on the surface of the textured structure on the side facing away from the N-type silicon substrate, as follows: Using a first deposition process, under first preset conditions, a first passivation layer is formed on the surface of the textured structure on the side away from the N-type silicon substrate. Using a second deposition process, under second preset conditions, a second passivation layer is formed on the surface of the first passivation layer on the side away from the N-type silicon substrate; Using a third deposition process, under third preset conditions, a third passivation layer is formed on the surface of the second passivation layer on the side away from the N-type silicon substrate.

[0047] Furthermore, the specific implementation of S130, and the fabrication of the first tunneling oxide layer and the first doped layer in the first region, is refined as follows: Using a fourth deposition process, under fourth preset conditions, a first tunneling oxide layer is formed in the first region; the fourth preset conditions are: a mixed gas of silane and oxygen is introduced into the fourth deposition process, the deposition temperature is 580℃-620℃, and the cavity pressure is 80Pa-120Pa. Using the fifth deposition process, under the fifth preset conditions, a first doped layer is formed on the surface of the first tunneling oxide layer on the side away from the N-type silicon substrate; the fifth preset conditions are that a mixed gas formed by silane and diborane is introduced into the fifth deposition process, the deposition temperature is 580℃-620℃, and the chamber pressure is 80Pa-120Pa.

[0048] Furthermore, after S150, forming the first electrode in contact with the first doped layer and the second electrode in contact with the second doped layer, the following steps are added: A barrier layer is prepared in the spacer region between the first region and the second region.

[0049] For details not covered in this embodiment, please refer to the above embodiments, which will not be repeated here.

[0050] refer to Figure 2 and Figure 3 As shown, the method includes: S210 provides an N-type silicon substrate.

[0051] The N-type silicon substrate includes a front side and a back side, with the back side including a first region and a second region arranged in an alternating interdigitated pattern.

[0052] Specifically, the resistivity of the silicon wafer on the N-type silicon substrate 1 is 1.5Ω•cm-3.0Ω•cm, and the thickness is selected as a single crystal silicon wafer within 120μm-150μm.

[0053] S220. A textured structure is prepared on the front side, and a first passivation layer is formed on the surface of the textured structure on the side away from the N-type silicon substrate using a first deposition process under a first preset condition.

[0054] The first preset conditions are: introducing a mixed solution of tetraethyl orthosilicate and ozone into the first deposition process; a deposition temperature of 250℃-300℃; a chamber pressure of 50Pa-150Pa; and a deposition rate of 0.08nm / cycle-0.12nm / cycle.

[0055] The first passivation layer 31 is directly covered on the surface of the textured structure 2 and is formed by thermal growth or chemical deposition to form an ultrathin silicon oxide layer. Its main function is to chemically passivate the dangling bonds on the silicon surface and reduce the interface state density. At the same time, it serves as a buffer layer for subsequent thin film growth to reduce interface stress.

[0056] Specifically, in preparing the textured structure 2 on the front side, an alkaline texturing process is used. The N-type silicon substrate 1 is placed in a potassium hydroxide texturing solution with a mass fraction of 1.5%-3.0%, and an alcohol / surfactant texturing additive is added, with a volume ratio of 3%-8%. Texturing is performed at a process temperature of 75℃-85℃ for 8-15 minutes to complete the texturing process. After the textured structure 2 is formed, the N-type silicon substrate 1 with the textured structure 2 is washed in pure water for 3-5 minutes. After washing, the N-type silicon substrate 1 is placed in a 1% dilute hydrochloric acid solution and neutralized at room temperature for 2 minutes. It is then rinsed with pure water and dried with hot air. The pyramid thickness of the textured structure 2 finally formed by the above texturing process is 1.5μm-4.5μm, preferably 2μm-4μm, and the weighted reflectivity of the front textured structure 2 is 1.0%-1.4%.

[0057] After forming the textured structure 2 on the front side, multiple passivation layers need to be prepared on the front side. In this embodiment, the passivation layers include a first passivation layer, a second passivation layer, and a third passivation layer. First, the first passivation layer is prepared. In this embodiment, a first deposition process is used, preferably atomic layer deposition (ALD). A mixed solution of tetraethyl orthosilicate (TEOS) and ozone (O3) is introduced into the first deposition process. Under the first preset conditions of a deposition temperature of 250℃-300℃, a chamber pressure of 50Pa-150Pa, and a deposition rate of 0.08nm / cycle-0.12nm / cycle, a first passivation layer 31 of a certain thickness is deposited on the surface of the textured structure 2 on the side facing away from the N-type silicon substrate 1. This prevents the second passivation layer 32 from directly contacting the N-type silicon substrate 1, suppresses interfacial polarization and carrier recombination, and improves the overall adhesion and structural stability of the film. In this embodiment, the material of the first passivation layer 31 is silicon dioxide.

[0058] Optionally, the thickness of the first passivation layer 31 formed in this embodiment is 1.5nm-2.5nm, and the refractive index is 1.45-1.48. For example, the thickness can be 1.5nm, 1.7nm, 1.9nm, 2.0nm, 2.2nm, 2.4nm, or 2.5nm, etc., and can be determined according to actual conditions, without limitation. In this embodiment, the thickness of the first passivation layer 31 is preferably 2.0nm. The refractive index can be 1.45, 1.46, 1.47, or 1.48, etc., and can be determined according to actual conditions, without limitation.

[0059] S230. Using a second deposition process, under second preset conditions, a second passivation layer is formed on the surface of the first passivation layer away from the N-type silicon substrate.

[0060] The second preset conditions are: a mixed solution of trimethylaluminum and deionized water is introduced into the second deposition process; the deposition temperature is 200℃-280℃; the chamber pressure is 60Pa-120Pa; and the deposition rate is 0.1nm / cycle-0.15nm / cycle. The second passivation layer 32 is a metal oxide film deposited on top of the first passivation layer 31. By utilizing the characteristic of fixing negative charges internally, a field-effect passivation is formed on the silicon surface, which effectively repels minority carriers (holes) from migrating to the surface and significantly suppresses surface recombination. It is especially suitable for the positive surface passivation of N-type silicon substrate 1.

[0061] Specifically, after the formation of the first passivation layer 31, a second passivation layer 32 is formed on the surface of the first passivation layer 31 away from the N-type silicon substrate 1. Specifically, a second deposition process is employed, preferably atomic layer deposition (ALD). This involves introducing a mixed solution of trimethylaluminum (TMA) and deionized water into the second deposition process, and under second preset conditions—a deposition temperature of 200℃-280℃, a chamber pressure of 60Pa-120Pa, and a deposition rate of 0.1nm / cycle-0.15nm / cycle—to deposit a second passivation layer 32 of a certain thickness on the surface of the first passivation layer 31 away from the N-type silicon substrate 1. This second passivation layer serves as an intermediate dielectric layer, matching the optical and mechanical properties of the upper and lower layers, while also possessing strong field-effect passivation capabilities. This achieves excellent minority carrier passivation of the N-type silicon substrate 1 surface, significantly reducing the surface recombination rate. In this embodiment, the material of the second passivation layer 32 is aluminum oxide.

[0062] Optionally, the thickness of the second passivation layer 32 formed in this embodiment is 6nm-10nm, and the refractive index is 1.60-1.65. For example, the thickness can be 6nm, 7nm, 8nm, 9nm, or 10nm, etc., and can be determined according to actual conditions, without limitation. In this embodiment, the thickness of the second passivation layer 32 is preferably 8nm. The refractive index can be 1.60, 1.61, 1.62, 1.63, 1.64, or 1.65, etc., and can be determined according to actual conditions, without limitation.

[0063] S240. Using a third deposition process, under third preset conditions, a third passivation layer is formed on the surface of the second passivation layer away from the N-type silicon substrate.

[0064] The third preset condition is to introduce a mixed gas of silane and ammonia with a flow ratio of 1:8 to 1:12 into the third deposition process, with a deposition temperature of 300℃ to 380℃, a chamber pressure of 200Pa to 400Pa, and a radio frequency power of 300W to 500W.

[0065] The third passivation layer 33 is a dielectric film located on the outermost side of the second passivation layer 32. It has both passivation and anti-reflection functions. It can diffuse to the silicon interface during subsequent heat treatment to further repair defects. At the same time, its refractive index can be adjusted to the optimal anti-reflection range to reduce frontal reflection loss and protect the underlying film from external environmental corrosion.

[0066] Specifically, after the formation of the second passivation layer 32, a third passivation layer 33 is formed on the surface of the second passivation layer 32 away from the N-type silicon substrate 1. Specifically, a third deposition process is employed, preferably plasma-enhanced chemical vapor deposition (PECVD). This involves introducing a mixed gas of silane (SiH4) and ammonia (NH3) at a flow ratio of 1:8 to 1:12 into the third deposition process. Under the third preset conditions of a deposition temperature of 300℃-380℃, a chamber pressure of 200Pa-400Pa, and a radio frequency power of 300W-500W, a third passivation layer 33 of a certain thickness is deposited on the surface of the second passivation layer 32 on the front side away from the N-type silicon substrate 1. This third passivation layer serves as the core optical antireflection layer. The three-layer film system works synergistically to control the front reflectivity to an extremely low level, enhancing light absorption. Furthermore, the film contains hydrogen, which can diffuse into the N-type silicon substrate 1, passivating internal defects and grain boundaries. Additionally, the dense film provides mechanical protection and moisture barrier functions, resisting outdoor environmental corrosion. In this embodiment, the material of the third passivation layer 33 is silicon nitride (SiN). x :H).

[0067] Optionally, the thickness of the third passivation layer 33 formed in this embodiment is 60nm-80nm, and the refractive index is 2.05-2.15. For example, the thickness can be 60nm, 63nm, 65nm, 68nm, 70nm, 72nm, 75nm, 78nm, or 80nm, etc., and can be determined according to actual conditions, without limitation. In this embodiment, the thickness of the third passivation layer 33 is preferably 70nm. The refractive index can be 2.05, 2.06, 2.07, 2.08, 2.09, 2.10, 2.11, 2.12, 2.13, 2.14, or 2.15, etc., and can be determined according to actual conditions, without limitation.

[0068] S250. Using the fourth deposition process, under the fourth preset conditions, a first tunneling oxide layer is formed in the first region.

[0069] The fourth preset condition is to introduce a mixed gas of silane and oxygen into the fourth deposition process, with a deposition temperature of 580℃-620℃ and a chamber pressure of 80Pa-120Pa.

[0070] Specifically, before depositing the tunneling oxide layer on the back side, laser etching can be used to etch the back side to distinguish the first region and the second region, forming an interdigitated structure. The laser power in the laser etching process is set to 8W-15W, the laser scanning speed is 2000mm / s-4000mm / s, the finger width of the first region and the second region is 40μm-50μm, preferably 45μm, and the distance between the first region and the second region is 110μm-130μm, preferably 120μm, so as to accurately delineate the P-type emission region and N-type field region on the back side, realize the positioning of the interdigitated pattern, and provide pattern definition for selective doping.

[0071] Subsequently, a tunneling oxide layer and a doped layer are prepared in the first and second regions. When the first tunneling oxide layer 41 is prepared in the first region, a fourth deposition process is used, preferably a low-pressure chemical vapor deposition (LPCVD) process. By introducing a mixed gas formed by silane and oxygen into the fourth deposition process, under the fourth preset conditions of a deposition temperature of 580℃-620℃ and a chamber pressure of 80Pa-120Pa, an ultrathin first tunneling oxide layer 41 is formed.

[0072] In this embodiment, the thickness of the first tunneling oxide layer 41 is 1.0 nm-1.4 nm, and the refractive index is 1.45-1.48. For example, the thickness can be 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, or 1.4 nm, etc., and can be determined according to actual conditions, without limitation. In this embodiment, the thickness of the first tunneling oxide layer 41 is preferably 1.2 nm. The refractive index of the first tunneling oxide layer 41 can be 1.45, 1.46, 1.47, or 1.48, etc., and can be determined according to actual conditions, without limitation.

[0073] S260. Using the fifth deposition process, under the fifth preset conditions, a first doped layer is formed on the surface of the first tunneling oxide layer on the side away from the N-type silicon substrate.

[0074] The fifth preset condition is to introduce a mixed gas of silane and diborane into the fifth deposition process, with a deposition temperature of 580℃-620℃ and a chamber pressure of 80Pa-120Pa.

[0075] Specifically, after the first tunneling oxide layer 41 is formed, a first doped layer 42 is formed on the surface of the first tunneling oxide layer 41 facing away from the N-type silicon substrate 1. Specifically, a fifth deposition process is used, preferably a low-pressure chemical vapor deposition (LPCVD) process. A mixed gas formed by silane (SiH4) and diborane (B2H6) is introduced into the fifth deposition process, and a first doped layer 42 is formed under the fifth preset conditions of deposition temperature of 580℃-620℃ and chamber pressure of 80Pa-120Pa.

[0076] In this embodiment, the thickness of the first doped layer 42 is 18nm-22nm, and the sheet resistance is 40Ω / □-70Ω / □. For example, the thickness can be 18nm, 19nm, 20nm, 21nm, or 22nm, etc., and can be determined according to actual conditions, without limitation here. In this embodiment, the thickness of the first doped layer 42 is preferably 20nm. The sheet resistance of the first doped layer 42 can be 40Ω / □, 45Ω / □, 50Ω / □, 55Ω / □, 60Ω / □, 65Ω / □, or 70Ω / □, etc., and can be determined according to actual conditions, without limitation here.

[0077] S270, Prepare a second tunneling oxide layer and a second doped layer in the second region.

[0078] Specifically, after the first tunneling oxide layer 41 and the first doped layer 42 are formed in the first region, a second tunneling oxide layer 51 and a second doped layer 52 are then formed in the second region. In this embodiment, when forming the second tunneling oxide layer 51 in the second region, a low-pressure chemical vapor deposition (LPCVD) process is used. A mixed gas of silane and oxygen is introduced into the reaction chamber of the LPCVD process, and under preset conditions of a deposition temperature of 580℃-620℃ and a chamber pressure of 80Pa-120Pa, an ultrathin second tunneling oxide layer 51 is formed.

[0079] In this embodiment, the thickness of the second tunneling oxide layer 51 is 1.6 nm-2.0 nm, and the refractive index is 1.45-1.48. For example, the thickness can be 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, or 2.0 nm, etc., and can be determined according to actual conditions, without limitation. In this embodiment, the thickness of the second tunneling oxide layer 51 is preferably 1.8 nm. The refractive index of the second tunneling oxide layer 51 can be 1.45, 1.46, 1.47, or 1.48, etc., and can be determined according to actual conditions, without limitation.

[0080] After forming the second tunneling oxide layer 51, a second doped layer 52 is formed on the surface of the second tunneling oxide layer 51 facing away from the N-type silicon substrate 1. Specifically, using low-pressure chemical vapor deposition (LPCVD), a mixed gas of silane and phosphine (PH3) is introduced into the reaction chamber of the LPCVD process. Under preset conditions of deposition temperature of 580℃-620℃ and chamber pressure of 80Pa-120Pa, a second doped layer 52 is formed. This method forms a gradient-partitioned tunneling passivation structure, solving the problems of poor adaptability and high recombination loss of traditional uniform thickness passivation layers, and is a core process for improving open-circuit voltage.

[0081] In this embodiment, the thickness of the second doped layer 52 is 23nm-27nm, and the sheet resistance is 30Ω / □-60Ω / □. For example, the thickness can be 23nm, 24nm, 25nm, 26nm, or 27nm, etc., and can be determined according to actual conditions, without limitation here. In this embodiment, the thickness of the second doped layer 52 is preferably 25nm. The sheet resistance of the second doped layer 52 can be 30Ω / □, 35Ω / □, 40Ω / □, 45Ω / □, 50Ω / □, 55Ω / □, or 60Ω / □, etc., and can be determined according to actual conditions, without limitation here.

[0082] S280. Screen printing and low-temperature sintering are performed on the first region and the second region to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer.

[0083] Specifically, when preparing the first electrode 6 and the second electrode 7, a fully automatic back screen printing machine with a chain sintering furnace is used to place the N-type silicon substrate 1 into the screen printing machine. A layer of silver-copper composite paste with a thickness of 18μm-25μm and a solid content of 85%-92% is printed on the surface of the first doped layer 42 in the first region. After the printing in the first region is completed, a layer of nano-carbon-doped aluminum paste with a thickness of 20μm-28μm is printed on the surface of the second doped layer 52 in the second region. After printing, the N-type silicon substrate 1 is placed in a chain sintering furnace. Under air atmosphere, the temperature of the sintering furnace is raised from room temperature to 200°C to dry the N-type silicon substrate 1. Then, the temperature is raised to 480°C-520°C and held for 30s-60s. The total sintering time is 3min-5min to sinter the paste. After sintering, a first electrode 6 is formed in the first region in contact with the first doped layer 42, and a second electrode 7 is formed in the second region in contact with the second doped layer 52. The edges of the first electrode 6 and the second electrode 7 both have a preset rounded chamfer.

[0084] S290, Prepare a barrier layer in the spacer region between the first region and the second region.

[0085] The barrier layer 8 refers to a phase change temperature-sensitive polymer material coated on the electrode gap area on the back of the battery. This material is solid or gel-like at room temperature and adheres to the back of the battery, providing physical isolation. When the local temperature of the battery rises to a set threshold (e.g., due to abnormal heating caused by hot spot effect), the material undergoes a phase change, transforming into a liquid or elastic state, expanding in volume and flowing towards the surrounding area. The preset threshold can be 80℃-90℃, preferably 85℃.

[0086] Specifically, after the electrodes are fabricated on the back side, a barrier layer 8 needs to be fabricated in the gap area. Specifically, the N-type silicon substrate 1 is placed in a microgravure coating machine or dispensing machine and dried in an air environment at 120℃-150℃ and normal pressure for 5-10 minutes. This creates a barrier layer 8 of a certain thickness in the gap area between the first and second regions, filling the electrode gap and further improving the overall moisture resistance and insulation of the back side. In this embodiment, the thickness of the barrier layer 8 is 10μm-20μm. For example, the thickness can be 10μm, 12μm, 13μm, 15μm, 16μm, 18μm, or 20μm, etc., and can be determined according to the actual situation, without limitation.

[0087] It should be noted that, in another embodiment, when fabricating the textured structure 2 on the front side, a textured structure can also be fabricated sequentially or simultaneously on the back side. Subsequently, during laser etching, the textured structures in the first and second regions can be removed, leaving only the textured structure in the spacer region. Finally, when fabricating the barrier layer 8, the textured structure retained in the spacer region is formed on the surface of the side facing away from the N-type silicon substrate 1. (Refer to...) Figure 2This increases the contact area and mechanical anchoring force between the barrier layer 8 and the back surface, while utilizing the light-trapping properties of the velvety structure to reduce parasitic absorption on the back surface, thereby improving the adhesion reliability of the barrier layer 8 and the light utilization rate of the battery.

[0088] The technical solution of this invention utilizes a first deposition process, under first preset conditions, to form a first passivation layer on the surface of the textured structure on the side facing away from the N-type silicon substrate; utilizes a second deposition process, under second preset conditions, to form a second passivation layer on the surface of the first passivation layer facing away from the N-type silicon substrate; utilizes a third deposition process, under third preset conditions, to form a third passivation layer on the surface of the second passivation layer facing away from the N-type silicon substrate; utilizes a fourth deposition process, under fourth preset conditions, to form a first tunneling oxide layer in a first region; utilizes a fifth deposition process, under fifth preset conditions, to form a first doped layer on the surface of the first tunneling oxide layer facing away from the N-type silicon substrate; and prepares a barrier layer in the spacer region between the first and second regions. Using the above method, precise adaptation to different carrier transport characteristics is achieved, effectively reducing interfacial recombination losses; simultaneously, the amount of silver paste used and contact resistance are significantly reduced, and the risk of electric field concentration and hot spots is also reduced, improving the conversion efficiency, reliability, and cost-effectiveness of the battery.

[0089] Based on the same inventive concept, this invention also provides a BC battery, which is prepared using the above-described BC battery preparation method. Specifically, it shares the same technical features and beneficial effects as the above-described preparation method.

[0090] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0091] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a BC battery, characterized in that, include: Provides N-type silicon substrates; The N-type silicon substrate includes a front side and a back side, and the back side includes a first region and a second region arranged in an alternating interdigitated pattern; A textured structure is prepared on the front side and the back side, and a multilayer passivation layer is formed on the surface of the textured structure on the front side away from the N-type silicon substrate. A first tunneling oxide layer and a first doped layer are prepared in the first region; A second tunneling oxide layer and a second doped layer are prepared in the second region; the thickness of the first tunneling oxide layer is less than the thickness of the second tunneling oxide layer, and the thickness of the first doped layer is less than the thickness of the second doped layer; The first region and the second region are screen printed and sintered at low temperature to form a first electrode in contact with the first doped layer and a second electrode in contact with the second doped layer. The first electrode is made of a different material than the second electrode, and both the first electrode and the second electrode have a pre-set rounded chamfer at their edges.

2. The preparation method according to claim 1, characterized in that, A multilayer passivation layer is formed on the surface of the textured structure on the front side facing away from the N-type silicon substrate, including: Using a first deposition process, under first preset conditions, a first passivation layer is formed on the surface of the textured structure on the front side away from the N-type silicon substrate. Using a second deposition process, under second preset conditions, a second passivation layer is formed on the surface of the first passivation layer on the side opposite to the N-type silicon substrate; Using a third deposition process, under third preset conditions, a third passivation layer is formed on the surface of the second passivation layer on the side opposite to the N-type silicon substrate.

3. The preparation method according to claim 2, characterized in that, The first preset conditions are: introducing a mixed solution of tetraethyl orthosilicate and ozone into the first deposition process; a deposition temperature of 250℃-300℃; a chamber pressure of 50Pa-150Pa; and a deposition rate of 0.08nm / cycle-0.12nm / cycle. The second preset conditions are: introducing a mixed solution of trimethylaluminum and deionized water into the second deposition process; a deposition temperature of 200℃-280℃; a chamber pressure of 60Pa-120Pa; and a deposition rate of 0.1nm / cycle-0.15nm / cycle. The third preset conditions are: introducing a mixed gas of silane and ammonia with a flow ratio of 1:8-1:12 into the third deposition process; a deposition temperature of 300℃-380℃; a chamber pressure of 200Pa-400Pa; and a radio frequency power of 300W-500W.

4. The preparation method according to claim 2, characterized in that, The thickness of the first passivation layer is 1.5nm-2.5nm, and the refractive index is 1.45-1.48; the thickness of the second passivation layer is 6nm-10nm, and the refractive index is 1.60-1.65; the thickness of the third passivation layer is 60nm-80nm, and the refractive index is 2.05-2.

15.

5. The preparation method according to claim 1, characterized in that, The preparation of a first tunneling oxide layer and a first doped layer in the first region includes: Using a fourth deposition process, under fourth preset conditions, the first tunneling oxide layer is formed in the first region; the fourth preset conditions are: a mixed gas of silane and oxygen is introduced into the fourth deposition process, the deposition temperature is 580℃-620℃, and the cavity pressure is 80Pa-120Pa. Using a fifth deposition process, under fifth preset conditions, the first doped layer is formed on the surface of the first tunneling oxide layer facing away from the N-type silicon substrate; the fifth preset conditions are that a mixed gas formed by silane and diborane is introduced into the fifth deposition process, the deposition temperature is 580℃-620℃, and the chamber pressure is 80Pa-120Pa.

6. The preparation method according to claim 1, characterized in that, The thickness of the first tunneling oxide layer is 1.0 nm-1.4 nm, and the refractive index is 1.45-1.48; the thickness of the second tunneling oxide layer is 1.6 nm-2.0 nm, and the refractive index is 1.45-1.48; the thickness of the first doped layer is 18 nm-22 nm, and the sheet resistance is 40 Ω / □-70 Ω / □; the thickness of the second doped layer is 23 nm-27 nm, and the sheet resistance is 30 Ω / □-60 Ω / □.

7. The preparation method according to claim 1, characterized in that, The chamfer radius of the preset circular arc chamfer is 8μm-15μm.

8. The preparation method according to claim 1, characterized in that, The first electrode is made of silver-copper composite paste with a thickness of 18μm-25μm and a solid content of 85%-92%; the second electrode is made of nano-carbon-doped aluminum paste with a thickness of 20μm-28μm.

9. The preparation method according to claim 1, characterized in that, After forming the first electrode in contact with the first doped layer and the second electrode in contact with the second doped layer, the method further includes: A barrier layer is prepared in the spacer region between the first region and the second region.

10. A BC battery, characterized in that, The BC battery is prepared using the method described in any one of claims 1-9.

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