A server low-power memory dynamic energy efficiency control method and system

Abstract

The application discloses a kind of server low-power memory dynamic energy efficiency control method and system, belong to server storage technical field.The application is by collecting the running state data corresponding to each storage unit of server memory, generates the memory load prediction result in the set time range, simultaneously completes the hierarchical processing of memory storage data, based on load prediction result and hierarchical storage data matching and switches memory power supply operating mode, adjusts the refresh cycle of corresponding memory storage unit, again in combination with memory chip temperature data and the current effective power supply operating mode adjusts heat dissipation system operating parameter, completes the collaborative control of memory power consumption and heat dissipation.The application can realize energy efficiency dynamic optimization while guaranteeing the continuity of memory read-write operation, reduce the invalid energy consumption in the whole operation cycle of memory, avoid the performance decline caused by temperature fluctuation, improve the stability and energy efficiency level of memory operation.

Description

Technical Field

[0001] This invention relates to the field of server storage technology, and in particular to a method and system for dynamic energy efficiency control of low-power server memory. Background Technology

[0002] With the rapid development of technologies such as cloud computing, big data processing, and artificial intelligence training and inference, servers, as the core hardware carriers of data centers and edge computing nodes, are experiencing continuous increases in computing density and workload. Memory, as the core component for server data interaction, directly determines the overall performance of the server and the overall operating cost of the data center through its performance, capacity, and energy efficiency. Currently, server memory technology is evolving towards high bandwidth, large capacity, and high-density integration. The implementation of next-generation memory interface standards has further improved the peak read / write performance and single-module storage capacity of server memory. Meanwhile, technologies related to memory energy efficiency optimization have become a key focus of industry research and development. Various technical solutions for memory power consumption control, storage architecture optimization, and improved heat dissipation performance are emerging and widely used in various scenarios such as internet data centers, high-performance computing clusters, and enterprise-level servers, becoming one of the key technologies supporting the stable and efficient operation of digital infrastructure.

[0003] Currently, the application of server memory energy efficiency control technologies still faces multiple technical limitations. Existing memory energy efficiency adjustment solutions mostly adopt a single-stage, independent management model, failing to achieve end-to-end coordinated control of memory operating status perception, load adaptation, power consumption management, and heat dissipation adjustment. This makes it difficult to achieve dynamic adaptation and optimization of memory energy efficiency while ensuring continuous and stable memory read and write operations. Furthermore, existing technologies for adjusting memory power consumption are largely passive responses based on the current load state, lacking proactive prediction and adaptation to changes in memory load trends. They also fail to incorporate tiered scheduling based on memory data access characteristics, making it difficult to accurately match the actual power consumption requirements of memory under different operating scenarios and effectively reduce ineffective energy consumption throughout the entire memory operating cycle. In addition, existing memory power consumption management and heat dissipation adjustment processes are independent, lacking a coordinated linkage mechanism. They cannot synchronously adjust heat dissipation strategies based on real-time memory operating power consumption and working mode, easily leading to significant fluctuations in memory temperature causing read and write performance degradation. It is difficult to simultaneously achieve both energy efficiency and performance stability in memory operation. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and system for dynamic energy efficiency control of low-power memory in servers.

[0005] The objective of this invention is achieved through the following technical solution: A method for dynamic energy efficiency control of low-power memory in servers is provided, the method comprising the following steps: S1. Collect the operating status data corresponding to each storage unit of the server memory. The memory operating status data includes memory access frequency data, memory read and write request data, and memory chip temperature data. S2. Based on the collected memory operating status data, generate memory load prediction results within a set time range. At the same time, classify the memory storage data according to the interval of memory access frequency to obtain the classified storage data corresponding to different access frequency intervals. S3. Based on the generated memory load prediction results and hierarchical storage data, match and switch the working mode of memory power supply, and adjust the refresh cycle of the corresponding memory storage unit; S4. Based on the collected memory chip temperature data and the currently effective memory power supply mode, adjust the operating parameters of the memory heat dissipation system to complete the coordinated control of server memory power consumption and heat dissipation.

[0006] Furthermore, step S1 includes the following sub-steps: S1.1. According to the preset sampling period, memory access frequency data, memory read and write request data and memory chip temperature data are collected in parallel. The collection process is independent of the normal read and write operation execution process of memory and does not interfere with the core read and write scheduling logic of memory controller. S1.2. Preprocess all collected memory running status data. Preprocessing includes data format standardization, abnormal data removal, and data timing alignment. Invalid data that exceeds the pre-set reasonable range is removed to obtain standardized memory running status data. S1.3. Write the standardized memory running status data into a pre-defined cache area. The data in the cache area is sorted and stored according to the collection time sequence for direct retrieval in subsequent steps.

[0007] Furthermore, step S2 includes the following sub-steps: S2.1. Based on the standardized memory operation status data, the data is input into a pre-trained and converged neural network model. The model is used to generate memory load prediction results within a set time window. The memory load prediction results include memory read / write bandwidth requirements and memory access frequency change trends. S2.2. According to the pre-defined memory access frequency intervals, the memory stored data is divided into three levels: hot data, warm data, and cold data. Each level corresponds to a unique access frequency interval, and there is no overlap between the intervals. S2.3. Based on the generated memory load prediction results, determine the storage medium location corresponding to each level of data, and generate corresponding data migration scheduling instructions. The data migration scheduling instructions include the address range of the migrated data and the migration execution sequence.

[0008] Furthermore, step S3 includes the following sub-steps: S3.1. Based on the generated memory load prediction results, match the memory power supply working mode corresponding to the current load demand. The memory power supply working mode includes high performance mode and energy saving mode. After the matching is completed, generate the corresponding voltage adjustment command. S3.2. According to the determined memory power supply working mode and voltage adjustment instructions, adjust the output voltage parameters of the memory power supply circuit to complete the smooth switching of the memory power supply working mode, and maintain the continuous execution of memory read and write operations during the switching process; S3.3. Based on the access frequency range corresponding to the hierarchical storage data, adjust the refresh cycle of the corresponding memory storage unit. At the same time, combined with the result of memory error correction code verification, trigger the local refresh operation of the corresponding memory unit only when a bit error is detected.

[0009] Furthermore, step S4 includes the following sub-steps: S4.1. Read the collected memory chip temperature data and the currently effective memory power supply mode, and combine it with the pre-set temperature-power consumption correspondence to determine the target operating parameters of the memory heat dissipation system. Different power supply modes correspond to independent parameter mapping tables. S4.2. Adjust the operating status of the memory cooling system according to the determined target operating parameters. The adjustment includes the circulation rate of the cooling medium and the output power of the cooling system. S4.3. Acquire the adjusted memory chip temperature data in real time, compare the real-time temperature data with the preset temperature threshold, and correct the operating parameters of the memory heat dissipation system in a closed loop based on the comparison results.

[0010] Furthermore, in step S1, the process of acquiring memory operating status data is executed in parallel with the normal memory read and write operation process. The acquisition operation does not occupy the clock cycle of the memory read and write operation, and the acquisition channel and the memory data read and write channel are independent of each other. During the acquisition process, independent acquisition links are divided according to data type, corresponding to the acquisition of memory access frequency data, memory read and write request data, and memory chip temperature data, respectively. The sampling period of each acquisition link can be adjusted individually based on the memory operating status. The acquired raw data is classified and stored according to the corresponding link identifier. The preprocessing process is executed in parallel according to data classification and link.

[0011] Furthermore, in step S2, hot data is stored in dynamic random access memory, warm data is stored in spin-torque magnetic memory, and cold data is stored in NAND flash memory. The data migration scheduling instruction is updated in real time based on changes in memory load prediction results. The data migration process is executed according to the idle timing window in the memory load prediction results. The migration process does not occupy the peak read / write bandwidth of memory. The storage address range of each level of data is predefined and there is no address overlap between them. After the data migration is completed, the address mapping table of the corresponding data is updated synchronously. The address mapping table is stored in the designated cache area for real-time access by memory read / write operations.

[0012] Furthermore, in step S3, the high-performance mode uses the standard power supply voltage, and the energy-saving mode uses the subthreshold power supply voltage. The adjustment process of the memory power supply voltage is completed synchronously with the execution process of the data migration scheduling instruction. The power supply voltage adjustment process is executed step by step according to the preset step value to avoid voltage sudden changes affecting the memory operating state. The step value of voltage adjustment is determined based on the current memory load prediction result. After the voltage adjustment is completed, the stability of memory read and write operations is checked synchronously. If the check passes, the current power supply voltage parameter is locked. If the check fails, the power supply voltage parameter is restored to the previous state.

[0013] Furthermore, in step S4, when the memory chip temperature exceeds a preset threshold, the memory power supply mode is switched to energy-saving mode simultaneously, and the operating power of the memory cooling system is increased to complete the closed-loop control of memory temperature. The temperature threshold is preset based on different memory power supply modes, and different power supply modes correspond to different temperature threshold ranges. During the temperature adjustment process, the performance parameters of memory read and write operations are monitored simultaneously. When the memory load prediction result shows an increase in read and write demand, the operating parameters of the cooling system and the power supply mode are adjusted simultaneously to ensure the stability of memory read and write performance.

[0014] A server low-power memory dynamic energy efficiency control system is provided. This system includes a data acquisition module, a load prediction and data classification module, a power supply control module, a refresh control module, and a heat dissipation coordination control module. The data acquisition module is connected to the memory hardware unit to collect and preprocess memory operating status data. The load prediction and data classification module communicates with the other modules to generate memory load prediction results and data classification scheduling instructions. The power supply control module is connected to the memory power supply circuit to perform power supply mode switching and voltage adjustment operations. The refresh control module is connected to the memory storage unit to perform refresh cycle adjustment and partial refresh operations. The heat dissipation coordination control module is connected to the memory heat dissipation system to perform heat dissipation parameter adjustment and coordination control operations.

[0015] The beneficial effects of this invention are: (1) By collecting and managing the server memory operation status data in real time and linking the entire process, the coordinated adaptation of memory power supply, refresh and heat dissipation links can be achieved, so as to achieve dynamic optimization of energy efficiency while ensuring the continuity of memory read and write operation. (2) By hierarchically scheduling the access characteristics of memory storage data and predicting the load change trend in advance, it can accurately adapt to the power consumption requirements of different memory operation scenarios and effectively reduce the ineffective energy consumption during the entire memory operation cycle. (3) By combining memory power consumption control with the linkage adjustment of the heat dissipation system, the performance degradation caused by memory temperature fluctuations can be avoided, while improving the stability of memory operation and the reliability of long-term use. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating the steps of a method for dynamic energy efficiency control of low-power memory in servers.

[0017] Figure 2 The following is a flowchart illustrating the specific steps of a server low-power memory dynamic energy efficiency control method provided in this embodiment. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1 See Figure 1 This embodiment provides a method for dynamic energy efficiency control of low-power memory in servers, which includes the following steps: S1. Collect the operating status data corresponding to each storage unit of the server memory. The memory operating status data includes memory access frequency data, memory read and write request data, and memory chip temperature data. S2. Based on the collected memory operating status data, generate memory load prediction results within a set time range. At the same time, classify the memory storage data according to the interval of memory access frequency to obtain the classified storage data corresponding to different access frequency intervals. S3. Based on the generated memory load prediction results and hierarchical storage data, match and switch the working mode of memory power supply, and adjust the refresh cycle of the corresponding memory storage unit; S4. Based on the collected memory chip temperature data and the currently effective memory power supply mode, adjust the operating parameters of the memory heat dissipation system to complete the coordinated control of server memory power consumption and heat dissipation.

[0020] In some embodiments, step S1 includes the following sub-steps: S1.1. According to the preset sampling period, memory access frequency data, memory read and write request data and memory chip temperature data are collected in parallel. The collection process is independent of the normal read and write operation execution process of memory and does not interfere with the core read and write scheduling logic of memory controller. S1.2. Preprocess all collected memory running status data. Preprocessing includes data format standardization, abnormal data removal, and data timing alignment. Invalid data that exceeds the pre-set reasonable range is removed to obtain standardized memory running status data. S1.3. Write the standardized memory running status data into a pre-defined cache area. The data in the cache area is sorted and stored according to the collection time sequence for direct retrieval in subsequent steps.

[0021] In some embodiments, step S2 includes the following sub-steps: S2.1. Based on the standardized memory operation status data, the data is input into a pre-trained and converged neural network model. The model is used to generate memory load prediction results within a set time window. The memory load prediction results include memory read / write bandwidth requirements and memory access frequency change trends. S2.2. According to the pre-defined memory access frequency intervals, the memory stored data is divided into three levels: hot data, warm data, and cold data. Each level corresponds to a unique access frequency interval, and there is no overlap between the intervals. S2.3. Based on the generated memory load prediction results, determine the storage medium location corresponding to each level of data, and generate corresponding data migration scheduling instructions. The data migration scheduling instructions include the address range of the migrated data and the migration execution sequence.

[0022] In some embodiments, step S3 includes the following sub-steps: S3.1. Based on the generated memory load prediction results, match the memory power supply working mode corresponding to the current load demand. The memory power supply working mode includes high performance mode and energy saving mode. After the matching is completed, generate the corresponding voltage adjustment command. S3.2. According to the determined memory power supply working mode and voltage adjustment instructions, adjust the output voltage parameters of the memory power supply circuit to complete the smooth switching of the memory power supply working mode, and maintain the continuous execution of memory read and write operations during the switching process; S3.3. Based on the access frequency range corresponding to the hierarchical storage data, adjust the refresh cycle of the corresponding memory storage unit. At the same time, combined with the result of memory error correction code verification, trigger the local refresh operation of the corresponding memory unit only when a bit error is detected.

[0023] In some embodiments, step S4 includes the following sub-steps: S4.1. Read the collected memory chip temperature data and the currently effective memory power supply mode, and combine it with the pre-set temperature-power consumption correspondence to determine the target operating parameters of the memory heat dissipation system. Different power supply modes correspond to independent parameter mapping tables. S4.2. Adjust the operating status of the memory cooling system according to the determined target operating parameters. The adjustment includes the circulation rate of the cooling medium and the output power of the cooling system. S4.3. Acquire the adjusted memory chip temperature data in real time, compare the real-time temperature data with the preset temperature threshold, and correct the operating parameters of the memory heat dissipation system in a closed loop based on the comparison results.

[0024] In some embodiments, in step S1, the process of acquiring memory operating status data is executed in parallel with the normal memory read and write operation process. The acquisition operation does not occupy the clock cycle of the memory read and write operation, and the acquisition channel and the memory data read and write channel are independent of each other. During the acquisition process, independent acquisition links are divided according to data type, corresponding to the acquisition of memory access frequency data, memory read and write request data and memory chip temperature data, respectively. The sampling period of each acquisition link can be adjusted individually based on the memory operating status. The acquired raw data is classified and stored according to the identifier of the corresponding link. The preprocessing process is executed in parallel according to data classification and link.

[0025] In some embodiments, in step S2, hot data is stored in dynamic random access memory, warm data is stored in spin-torque magnetic memory, and cold data is stored in NAND flash memory. The data migration scheduling instruction is updated in real time based on changes in memory load prediction results. The data migration process is executed according to the idle timing window in the memory load prediction results. The migration process does not occupy the peak read / write bandwidth of memory. The storage address range of each level of data is predefined and there is no address overlap between them. After the data migration is completed, the address mapping table of the corresponding data is updated synchronously. The address mapping table is stored in a designated cache area for real-time access by memory read / write operations.

[0026] In some embodiments, in step S3, the high-performance mode uses the standard power supply voltage, the energy-saving mode uses the subthreshold power supply voltage, and the adjustment process of the memory power supply voltage is completed synchronously with the execution process of the data migration scheduling instruction. The power supply voltage adjustment process is executed step by step according to a preset step value to avoid voltage sudden changes affecting the memory operating state. The step value of voltage adjustment is determined based on the current memory load prediction result. After the voltage adjustment is completed, the stability of memory read and write operations is checked synchronously. If the check passes, the current power supply voltage parameter is locked. If the check fails, the power supply voltage parameter is restored to the previous state.

[0027] In some embodiments, in step S4, when the memory chip temperature data exceeds a preset threshold, the memory power supply mode is switched to energy-saving mode simultaneously, and the operating power of the memory heat dissipation system is increased to complete the closed-loop control of memory temperature. The temperature threshold is preset based on different memory power supply modes, and different power supply modes correspond to different temperature threshold ranges. During the temperature adjustment process, the performance parameters of memory read and write operations are monitored simultaneously. When the memory load prediction result shows an increase in read and write demand, the operating parameters of the heat dissipation system and the power supply mode are adjusted simultaneously to ensure the stability of memory read and write performance.

[0028] A server low-power memory dynamic energy efficiency control system is provided. This system includes a data acquisition module, a load prediction and data classification module, a power supply control module, a refresh control module, and a heat dissipation coordination control module. The data acquisition module is connected to the memory hardware unit to collect and preprocess memory operating status data. The load prediction and data classification module communicates with the other modules to generate memory load prediction results and data classification scheduling instructions. The power supply control module is connected to the memory power supply circuit to perform power supply mode switching and voltage adjustment operations. The refresh control module is connected to the memory storage unit to perform refresh cycle adjustment and partial refresh operations. The heat dissipation coordination control module is connected to the memory heat dissipation system to perform heat dissipation parameter adjustment and coordination control operations.

[0029] Example 2 This embodiment provides a specific implementation process of a dynamic energy efficiency control method for low-power memory in servers. This process achieves coordinated adaptation between memory power consumption and operating performance through full-process management of the memory's operating state, while simultaneously coordinating the control of memory power consumption and heat dissipation, ensuring energy efficiency optimization and stable operation during memory operation. Figure 2 As shown, the specific implementation process is as follows: S1. Memory running status data acquisition and processing: S1.1. Parallel acquisition of memory running status data: Parallel acquisition refers to using independent acquisition links to simultaneously perform data capture operations for multiple types of memory operating status data. In this embodiment, this method is used to avoid data timing deviations caused by single-link acquisition, while ensuring that the acquisition process does not affect normal memory read and write operations. Memory access frequency data, memory read and write request data, and memory chip temperature data are acquired in parallel according to a pre-set sampling period. The acquisition process is independent of the normal memory read and write operation execution process and does not interfere with the core read and write scheduling logic of the memory controller.

[0030] The data acquisition process runs in parallel with normal memory read / write operations. The acquisition operation does not occupy the clock cycles of memory read / write operations, and the acquisition channel and memory data read / write channel are independent of each other. During the acquisition process, independent acquisition links are divided according to data type, corresponding to the acquisition of memory access frequency data, memory read / write request data, and memory chip temperature data, respectively. The sampling period of each acquisition link can be adjusted individually based on the memory operating status, and the acquired raw data is classified and stored according to the corresponding link's identifier.

[0031] S1.2. Standardization preprocessing of collected data: Preprocessing refers to the operation of standardizing and filtering the collected raw data, removing invalid data, and standardizing the data format. In this embodiment, this operation is used to ensure the consistency and validity of input data in subsequent data operations and to avoid abnormal data interfering with the operation results. Preprocessing is performed on all collected memory runtime data, including data format standardization, abnormal data removal, and data timing alignment. Invalid data exceeding a pre-defined reasonable range is removed to obtain standardized memory runtime data. The preprocessing process is executed in parallel according to data classification and links. The raw data corresponding to different acquisition links undergoes corresponding preprocessing operations, and the preprocessing processes of each link do not interfere with each other and can be completed synchronously.

[0032] S1.3. Cache storage of processed data: A cache region refers to an address range pre-defined in high-speed memory storage media for temporary storage of standardized operational status data. In this embodiment, this region provides a fast data retrieval channel for subsequent steps, reducing data retrieval latency. The standardized memory operational status data is written into the pre-defined cache region. The data within the cache region is sorted and stored according to the acquisition sequence for direct retrieval by subsequent steps. Data within the cache region is subject to corresponding access permissions; only the energy efficiency control process corresponding to this embodiment can read and modify the data within this region, preventing other processes from accidentally altering the data and ensuring data security and accuracy.

[0033] In some embodiments, the collected memory operating status data may also include memory power supply voltage data and memory error correction code verification result data. Data acquisition links may be added according to the newly added data types. The sampling period of each link may be set uniformly or separately according to different data types.

[0034] In some specific implementations, during the acquisition of memory operating status data, the sampling period of each acquisition link is uniformly set to 100 microseconds, which corresponds to 10,000 full data acquisitions per second. Among them, the acquisition links for memory access frequency data and memory read / write request data can dynamically adjust the sampling period to 50 microseconds based on memory load fluctuations, which corresponds to 20,000 data acquisitions per second. The acquisition link for memory chip temperature data maintains a fixed sampling period to ensure the continuity and stability of temperature data acquisition.

[0035] During data acquisition, each acquisition link is allocated an independent 2GB / s bandwidth acquisition channel. These acquisition channels are physically isolated from the main memory read / write channel, ensuring that acquisition operations do not consume any clock cycles of the main memory read / write channel. Simultaneously, each acquisition link is configured with an independent 128KB L1 cache for temporary storage of the acquired raw data, preventing congestion and data loss during multi-link data acquisition. In preprocessing, a 1-millisecond time window is set for data timing alignment. Multiple data types within the same time window are timestamped and aligned. Upper and lower thresholds are set for reasonable data ranges; abnormal data exceeding these thresholds is directly discarded. The remaining data, after format standardization, is written to a pre-defined 2MB L2 cache area. Data within the cache is arranged in ascending order of timestamps, providing continuous and uniformly formatted input data for subsequent load prediction steps. This addresses the issue of inaccurate load prediction results caused by data acquisition lag and timing deviations in high-burst load scenarios.

[0036] S2. Memory Load Prediction and Data Classification Processing: S2.1. Generation of memory load prediction results: Long Short-Term Memory (LSTM) networks are recurrent neural networks capable of learning from and predicting time-series data. They can predict data change trends in future time periods based on historical time-series data. In this embodiment, the network is used to generate memory load changes in subsequent time periods based on historical memory operation status data. The LSM network used in this embodiment includes an input layer, a hidden layer, and an output layer. The input layer receives standardized time-series memory operation status data. The hidden layer has a forget gate, an input gate, and an output gate connected in sequence. The forget gate filters out historical data that is not valuable for load prediction. The input gate updates the weight parameters corresponding to the current input data. The output gate outputs the final load prediction result.

[0037] The model training process includes acquiring pre-collected historical memory runtime data, dividing the data into training and validation sets, iteratively updating the model's weight parameters using the training set data, and validating the model's prediction accuracy using the validation set data. The trained and converged model can then be directly used for load prediction computation. Based on standardized memory runtime data, the data is input into the pre-trained and converged Long Short-Term Memory (LSTM) network model. The model then generates memory load prediction results within a set time window, including memory read / write bandwidth requirements and memory access frequency trends. The generated load prediction results are synchronously written to a cache area and stored in association with the corresponding memory runtime data for subsequent steps.

[0038] In some specific implementations, the Long Short-Term Memory (LSTM) network model used for load prediction is configured with a 3-layer hidden layer structure, with 128 neurons in each hidden layer. The input layer dimension is set to 3, corresponding to standardized memory access frequency data, memory read / write request data, and memory chip temperature data, respectively. The time series length of the input data is set to 36,000, corresponding to historical data collected within one hour. The output layer dimension is set to 2, corresponding to memory read / write bandwidth requirements and memory access frequency change trends within the next 10 milliseconds. During model training, 30 consecutive days of historical server memory runtime data are collected, with 80% of the data allocated to the training set and 20% to the validation set. The Adam optimizer is used during training, with an initial learning rate of 0.001, a batch size of 64, and 100 training iterations. After each training iteration, the model's prediction accuracy is verified using the validation set. When the model's prediction accuracy stabilizes above 92% and the loss function value no longer decreases, the model is considered to have converged, and training is stopped.

[0039] The trained model is deployed in the built-in processing unit of the memory controller. Each time a full data acquisition is completed, the input model completes a load prediction calculation. The calculation process takes no more than 1 microsecond, ensuring the real-time performance of the load prediction results and solving the problems of high response latency and inability to adapt to high burst load scenarios in traditional load prediction methods.

[0040] S2.2. Hierarchical division of data stored in memory: Data tiering refers to dividing memory-stored data into different tiers based on data access frequency, and matching different tiers with corresponding storage media. In this embodiment, this operation is used to reduce the overall power consumption of the memory while ensuring data read / write performance. Based on pre-defined memory access frequency ranges, the memory-stored data is divided into three tiers: hot data, warm data, and cold data. Each tier corresponds to a unique access frequency range, and there is no overlap between ranges.

[0041] Hot data refers to frequently accessed memory storage data, warm data refers to periodically accessed memory storage data, and cold data refers to infrequently accessed memory storage data. The data hierarchy is associated with the storage address and access frequency information of the corresponding data and is synchronously updated to the cache area for subsequent data migration operations.

[0042] S2.3. Generation of data migration scheduling instructions: Data migration scheduling instructions are control instructions used to manage the location transfer of data at different levels between corresponding storage media. In this embodiment, the instructions are used to ensure that data at different levels are stored in matching storage media, thereby adapting data storage and access requirements.

[0043] Based on the generated memory load prediction results, the storage medium location corresponding to each level of data is determined, and corresponding data migration scheduling instructions are generated. These instructions include the address range of the migrated data and the migration execution sequence. Hot data is stored in Dynamic Random Access Memory (DRAM), a volatile memory with high read / write speeds, which in this embodiment provides full-speed read / write support for frequently accessed hot data. Warm data is stored in Spin Torque Memory, a non-volatile magnetic memory with lower power consumption, which in this embodiment provides read / write support for periodically accessed warm data while reducing storage power consumption. Cold data is stored in NAND flash memory, a non-volatile memory with large storage capacity, which in this embodiment provides long-term storage support for infrequently accessed cold data, further reducing memory usage.

[0044] Data migration scheduling instructions are updated in real time based on changes in memory load prediction results. The data migration process is executed according to the idle time window in the memory load prediction results. The migration process does not consume peak memory read / write bandwidth. The storage address ranges of data at each level are pre-defined, and there is no address overlap between them. After the data migration is completed, the address mapping table of the corresponding data is updated synchronously. The address mapping table is stored in a designated high-speed cache area for real-time access by memory read / write operations. The address mapping table records the current storage address, data level, and access frequency information of each data block. When a memory read / write operation is executed, the storage address of the corresponding data is first looked up through the address mapping table, and then the corresponding read / write operation is executed.

[0045] In some specific implementations, during the hierarchical classification of memory storage data, three access frequency ranges are pre-defined. The access frequency range for hot data is no less than 1000 accesses per hour; the access frequency range for warm data is between 10 and 1000 accesses per hour; and the access frequency range for cold data is less than 10 accesses per hour. These three ranges do not overlap. The access count for each data block is updated every 100 milliseconds, synchronously re-determining the data hierarchy. After data classification, hot data is stored in 3D stacked DRAM chips, with a single chip capacity of 16Gb, and a total of 8 chips configured, supporting a full-speed read / write rate of 6400MT / s. Warm data is stored in STT-MRAM chips in the same package, with a single chip capacity of 8Gb, and a total of 4 chips configured, reducing read / write power consumption by 50% compared to DRAM chips. Cold data, after compression, is stored in NAND flash memory chips in the same package, with a single chip capacity of 64Gb, and a total of 2 chips configured.

[0046] During the data migration process, the migration operation is performed based on the idle time window in the load prediction results. The migration bandwidth is set to 800GB / s, and the latency of a single batch of data migration does not exceed 5 microseconds. After the migration is completed, the address mapping table is updated synchronously. The address mapping table is fully updated every 50 microseconds to ensure that memory read and write operations can quickly locate the data storage address, thus solving the problems of low efficiency of cold and hot data migration and excessive memory read and write bandwidth in traditional hybrid storage architectures.

[0047] In some embodiments, the memory storage data can be divided into two levels: high-frequency access data and low-frequency access data. The data in the two levels correspond to the matching storage media, and the data migration scheduling instructions can be adjusted accordingly based on the division of the two levels.

[0048] S3. Memory power supply mode switching and refresh cycle adjustment: S3.1. Memory power supply mode matching: The memory power supply operating mode refers to the different voltage output schemes set by the memory power supply circuit according to the memory load demand. Different operating modes correspond to different memory operating speeds and power consumption levels. In this embodiment, this mode is used to adapt the memory power supply to the load demand, reducing operating power consumption while ensuring performance. Based on the generated memory load prediction results, the memory power supply operating mode corresponding to the current load demand is matched. The memory power supply operating modes include high-performance mode and energy-saving mode. After matching, the corresponding voltage adjustment command is generated.

[0049] The high-performance mode uses the standard supply voltage to provide full-speed read and write power support for the memory; the energy-saving mode uses a subthreshold supply voltage, which is a supply voltage lower than the standard turn-on voltage of the transistor. In this embodiment, this voltage is used to reduce the static power consumption of the memory in standby mode while ensuring the normal execution of basic memory read and write operations. The matching result of the working mode and the voltage adjustment instruction are synchronously written to the cache area and stored in association with the corresponding load prediction result for subsequent switching operations.

[0050] S3.2. Smooth switching of power supply operating modes: Smooth switching refers to a switching method where the power supply voltage is gradually adjusted according to a set step value to avoid abnormal memory operation caused by sudden voltage changes. In this embodiment, this method is used to ensure the continuous execution of memory read and write operations during the power supply mode switching process, without data read and write interruptions. According to the determined memory power supply operating mode and voltage adjustment instructions, the output voltage parameters of the memory power supply circuit are adjusted to complete the smooth switching of the memory power supply operating mode, maintaining the continuous execution of memory read and write operations during the switching process.

[0051] The adjustment of the memory power supply voltage is completed synchronously with the execution of data migration scheduling instructions. The voltage adjustment process is executed step by step according to a pre-set step value to avoid voltage sudden changes affecting the memory's operating status. The voltage adjustment step value is determined based on the current memory load prediction result. After the voltage adjustment is completed, the stability of memory read and write operations is checked simultaneously. If the check passes, the current power supply voltage parameters are locked; if the check fails, the power supply voltage parameters are restored to the previous state. After the power supply mode switch is completed, the currently effective memory power supply mode information is synchronously written to the cache area for subsequent thermal management control steps.

[0052] In some specific implementations, during the matching and switching of memory power supply modes, the standard power supply voltage for high-performance mode is pre-set to 1.1V. In this mode, the memory can support a peak read / write bandwidth of 6400MT / s, meeting the read / write requirements under high load scenarios. The subthreshold power supply voltage for energy-saving mode is 0.6V. In this mode, the memory read / write speed is reduced to 3200MT / s, and the static power consumption is reduced by 65% ​​compared to the standard voltage mode, adapting to the energy efficiency requirements of low load or standby scenarios. During the power supply mode matching process, based on the memory read / write bandwidth requirements in the next 10 milliseconds from the load prediction results, when the predicted bandwidth requirement exceeds 50% of the peak bandwidth, high-performance mode is matched; when the predicted bandwidth requirement is less than 30% of the peak bandwidth, energy-saving mode is matched; in the intermediate range, the current operating mode remains unchanged to avoid operational instability caused by frequent switching.

[0053] During power supply mode switching, the voltage adjustment step value is set to 10mV per step, and the interval time for each voltage adjustment step is set to 100 nanoseconds. The total delay for completing the full voltage switch does not exceed 2 microseconds. During the switching process, memory read and write stability verification is performed simultaneously. If 1000 read and write operations are completed consecutively and the bit error rate is lower than 1E-18, the switch is considered successful and the current power supply voltage parameters are locked. If the verification fails, the power supply voltage is restored to the previous state according to the corresponding step value. This solves the problems of high response delay and easy read and write errors during the switching process of traditional voltage regulation technology.

[0054] S3.3. Memory refresh cycle adjustment and partial refresh control: Memory refresh operations refer to the process of replenishing charge to the storage cells of dynamic random access memory (DRAM) to prevent data loss. The frequency of refresh operations directly affects the power consumption of memory refresh. In this embodiment, by adjusting the refresh cycle and partial refresh control, invalid refresh operations are reduced, thereby lowering memory refresh power consumption. Error correction codes are a coding technique used to detect and correct bit errors that occur during memory data read and write operations. In this embodiment, this technique is used to ensure the accuracy of memory data read and write operations and to provide a triggering basis for partial refresh operations.

[0055] Based on the access frequency range corresponding to the tiered storage data, the refresh cycle of the corresponding memory storage unit is adjusted. Simultaneously, considering the results of memory error correction code verification, a partial refresh operation is triggered only when a bit error is detected. Storage units with higher access frequencies correspond to shorter refresh cycles, while those with lower access frequencies correspond to longer refresh cycles. This differentiated adjustment of refresh cycles reduces invalid refresh operations on low-frequency access storage units, thereby lowering refresh power consumption.

[0056] Partial refresh operations are performed only on memory cells where bit errors are detected, eliminating the need for a full refresh of all memory cells and further reducing the number of invalid refresh operations.

[0057] In some specific implementations, during memory refresh cycle adjustment and partial refresh control, the adjustable range of the refresh cycle is preset to 64ms to 512ms. Specifically, the refresh cycle for DRAM memory cells corresponding to hot data is set to 64ms to ensure the storage stability of frequently accessed data; the refresh cycle for STT-MRAM memory cells corresponding to warm data is set to 256ms to reduce power consumption from periodic refreshes; and the refresh cycle for NAND flash memory cells corresponding to cold data is set to 512ms to minimize invalid refresh operations. The refresh cycle adjustment is performed synchronously with the data hierarchy division. Each time a data hierarchy update is completed, the refresh cycle of the corresponding memory cell is adjusted synchronously. Through differentiated refresh cycle settings, the overall memory refresh power consumption can be reduced by 40%.

[0058] During partial refresh control, after each memory read / write operation, bit error detection is performed on the read / write data through the ECC check mechanism. ECC check can correct single-bit errors and detect double-bit errors. Only when an uncorrectable bit error is detected during the check is a partial refresh operation triggered on the memory cell at the corresponding address. This eliminates the need to perform a full refresh on the entire memory bank, further reducing the number of invalid refresh operations and keeping the bit error rate during memory operation below 1E-18. This solves the problems of high power consumption and numerous invalid refresh operations associated with traditional full refresh memory operations.

[0059] In some embodiments, an intermediate mode can be added to the memory power supply operating mode. The power supply voltage corresponding to the intermediate mode is between the high-performance mode and the energy-saving mode. It can be matched according to the intermediate range of the memory load prediction results to further refine the degree of adaptation between power supply and load.

[0060] S4. Coordinated control of memory power consumption and heat dissipation: S4.1. Determination of target operating parameters for the heat dissipation system: The temperature-power consumption correspondence refers to a pre-defined mapping relationship between memory chip temperature and memory operating power consumption. Different memory power supply modes correspond to different mapping relationships. In this embodiment, this relationship is used to provide a basis for adjusting the operating parameters of the heat dissipation system, achieving coordinated control of power consumption and heat dissipation. The collected memory chip temperature data and the currently effective memory power supply mode are read, and combined with the pre-defined temperature-power consumption correspondence, the target operating parameters of the memory heat dissipation system are determined. Different power supply modes correspond to independent parameter mapping tables.

[0061] The process of determining the target operating parameters also takes into account the current memory load prediction results. When the load prediction results show that the subsequent memory read and write demand will increase, the corresponding adjustment margin of the heat dissipation system is reserved to ensure the stability of the memory chip temperature when the load increases.

[0062] S4.2. Adjustment of the operating status of the heat dissipation system: A heat dissipation system refers to a hardware system that provides heat dissipation and temperature control for memory chips. In this embodiment, the system can adjust its heat dissipation capacity by changing the circulation rate and operating power of the heat dissipation medium to adapt to the temperature control requirements of the memory chips. According to the determined target operating parameters, the operating state of the memory heat dissipation system is adjusted, including the circulation rate of the heat dissipation medium and the output power of the system. The adjustment process of the heat dissipation system is executed synchronously with the switching process of the memory power supply operating mode, achieving coordinated adaptation between changes in power consumption and changes in heat dissipation capacity, and avoiding large fluctuations in the temperature of the memory chips.

[0063] S4.3. Closed-loop correction of heat dissipation parameters: Closed-loop correction refers to a control method that continuously adjusts the operating parameters of the heat dissipation system based on the adjusted actual temperature feedback to maintain the memory chip temperature within a set range. In this embodiment, this method is used to ensure the stability of memory temperature control and avoid the impact of temperature fluctuations on memory operation. The adjusted memory chip temperature data is acquired in real time, compared with a pre-set temperature threshold, and the operating parameters of the memory heat dissipation system are corrected in a closed-loop manner based on the comparison results.

[0064] When the memory chip temperature exceeds a preset threshold, the memory power supply mode is switched to energy-saving mode, and the operating power of the memory cooling system is increased to complete closed-loop control of memory temperature. The temperature threshold is preset based on different memory power supply modes, and different power supply modes correspond to different temperature threshold ranges. During the temperature adjustment process, the performance parameters of memory read and write operations are monitored simultaneously. When the memory load prediction results show an increase in read and write demand, the operating parameters of the cooling system and the power supply mode are adjusted simultaneously to ensure the stability of memory read and write performance.

[0065] In some specific implementations, during the coordinated control of memory power consumption and heat dissipation, a 0.2mm thick gallium-based liquid metal phase change material thermal conductive layer is coated on the surface of the memory module. This thermal conductive layer has a thermal conductivity of no less than 30W / m·K. The thermal conductive layer is directly attached to the cold plate of the server's liquid cooling system, forming a complete heat dissipation path. A pre-set parameter mapping table for temperature-power consumption correspondence is used, where the temperature threshold for high-performance mode is set to 65℃, and the temperature threshold for energy-saving mode is set to 75℃. When the memory chip temperature exceeds the temperature threshold for the corresponding mode, a linkage control operation is triggered.

[0066] During the adjustment of the heat dissipation system's operating parameters, the liquid cooling system's pump speed is adjustable from 3000rpm to 8000rpm. When the memory chip temperature exceeds the threshold, the liquid cooling pump speed is increased by 2000rpm, and the memory power supply mode is simultaneously switched to energy-saving mode to reduce memory power consumption. This two-dimensional collaborative approach achieves memory temperature control, with a response time of no more than 1 microsecond. After adjustment, real-time temperature data of the memory chip is collected every 100 microseconds and compared with the set threshold. When the temperature drops below 10°C below the threshold, the liquid cooling pump speed and power supply mode are gradually adjusted back. Through closed-loop control, the chip temperature under full load is stabilized at around 63°C, which is about 15°C lower than traditional air-cooling solutions. This solves the problem of passive adjustment and passive memory frequency reduction caused by temperature rise in traditional heat dissipation systems.

[0067] In some embodiments, the adjustment of the operating parameters of the heat dissipation system can be performed synchronously with the adjustment of the memory refresh cycle. When the temperature of the memory chip exceeds a set threshold, the refresh cycle of the corresponding memory storage unit is extended synchronously to further reduce the power consumption of memory operation and assist in temperature control.

[0068] In some embodiments, closed-loop control of memory chip temperature can be enhanced by adding a temperature warning range. When the memory chip temperature enters the warning range, the operating parameters of the heat dissipation system are adjusted in advance, and a preparatory instruction for power supply mode switching is generated in advance to prevent the temperature from exceeding the threshold.

[0069] This embodiment also provides a server low-power memory dynamic energy efficiency control system. This system executes the aforementioned server low-power memory dynamic energy efficiency control method. The system includes a data acquisition module, a load prediction and data classification module, a power supply control module, a refresh control module, and a heat dissipation coordination control module. The data acquisition module is connected to the memory hardware unit to collect and preprocess memory operating status data. The load prediction and data classification module communicates with the other modules to generate memory load prediction results and data classification scheduling instructions. The power supply control module is connected to the memory power supply circuit to perform power supply mode switching and voltage adjustment operations. The refresh control module is connected to the memory storage unit to perform refresh cycle adjustment and partial refresh operations. The heat dissipation coordination control module is connected to the memory heat dissipation system to perform heat dissipation parameter adjustment and coordination control operations.

[0070] The modules interact with each other through a pre-defined communication link. The operation of all modules does not interfere with the core read and write scheduling logic of the memory controller, ensuring the continuous execution of normal memory read and write operations.

[0071] This embodiment achieves energy efficiency optimization during server memory operation through a comprehensive technical solution encompassing end-to-end memory operation status management, load prediction and data grading, power supply and refresh adaptation, and power consumption and heat dissipation coordination, while ensuring stable memory read and write performance. By parallel acquisition and standardized processing of memory operation status data, this embodiment obtains accurate and time-aligned memory operation data, providing a reliable data foundation for subsequent energy efficiency management operations. This effect can be directly achieved through the basic process of memory operation status data acquisition and processing.

[0072] This embodiment achieves advance adaptation of memory power supply mode through load prediction, avoiding the response latency issues of traditional energy efficiency adjustment methods. Simultaneously, through tiered data storage, it reduces overall memory power consumption while ensuring high-frequency data access read / write performance. This embodiment avoids passive frequency throttling caused by rising memory temperature through coordinated power consumption and heat dissipation management. Furthermore, by using differentiated refresh and partial refresh control, it reduces ineffective refresh power consumption, further improving memory energy efficiency. The technical solution of this embodiment can adapt to different memory load scenarios, achieving continuous optimization of memory energy efficiency while ensuring memory operational stability, demonstrating good scenario adaptability and operational reliability.

[0073] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for dynamic energy efficiency control of low-power memory in servers, characterized in that, Includes the following steps: S1. Collect the operating status data corresponding to each storage unit of the server memory. The memory operating status data includes memory access frequency data, memory read and write request data, and memory chip temperature data. S2. Based on the collected memory operating status data, generate memory load prediction results within a set time range. At the same time, classify the memory storage data according to the interval of memory access frequency to obtain the classified storage data corresponding to different access frequency intervals. S3. Based on the generated memory load prediction results and hierarchical storage data, match and switch the working mode of memory power supply, and adjust the refresh cycle of the corresponding memory storage unit; S4. Based on the collected memory chip temperature data and the currently effective memory power supply mode, adjust the operating parameters of the memory heat dissipation system to complete the coordinated control of server memory power consumption and heat dissipation.

2. The method according to claim 1, characterized in that, Step S1 includes the following sub-steps: S1.

1. According to the preset sampling period, memory access frequency data, memory read and write request data and memory chip temperature data are collected in parallel. The collection process is independent of the normal read and write operation execution process of memory and does not interfere with the core read and write scheduling logic of memory controller. S1.

2. Preprocess all collected memory running status data. Preprocessing includes data format standardization, abnormal data removal, and data timing alignment. Invalid data that exceeds the pre-set reasonable range is removed to obtain standardized memory running status data. S1.

3. Write the standardized memory running status data into a pre-defined cache area. The data in the cache area is sorted and stored according to the collection time sequence for direct retrieval in subsequent steps.

3. The method according to claim 1, characterized in that, Step S2 includes the following sub-steps: S2.

1. Based on the standardized memory operation status data, the data is input into a pre-trained and converged neural network model. The model is used to generate memory load prediction results within a set time window. The memory load prediction results include memory read / write bandwidth requirements and memory access frequency change trends. S2.

2. According to the pre-defined memory access frequency intervals, the memory stored data is divided into three levels: hot data, warm data, and cold data. Each level corresponds to a unique access frequency interval, and there is no overlap between the intervals. S2.

3. Based on the generated memory load prediction results, determine the storage medium location corresponding to each level of data, and generate corresponding data migration scheduling instructions. The data migration scheduling instructions include the address range of the migrated data and the migration execution sequence.

4. The method according to claim 1, characterized in that, Step S3 includes the following sub-steps: S3.

1. Based on the generated memory load prediction results, match the memory power supply working mode corresponding to the current load demand. The memory power supply working mode includes high performance mode and energy saving mode. After the matching is completed, generate the corresponding voltage adjustment command. S3.

2. According to the determined memory power supply working mode and voltage adjustment instructions, adjust the output voltage parameters of the memory power supply circuit to complete the smooth switching of the memory power supply working mode, and maintain the continuous execution of memory read and write operations during the switching process; S3.

3. Based on the access frequency range corresponding to the hierarchical storage data, adjust the refresh cycle of the corresponding memory storage unit. At the same time, combined with the result of memory error correction code verification, trigger the local refresh operation of the corresponding memory unit only when a bit error is detected.

5. The method according to claim 1, characterized in that, Step S4 includes the following sub-steps: S4.

1. Read the collected memory chip temperature data and the currently effective memory power supply mode, and combine it with the pre-set temperature-power consumption correspondence to determine the target operating parameters of the memory heat dissipation system. Different power supply modes correspond to independent parameter mapping tables. S4.

2. Adjust the operating status of the memory cooling system according to the determined target operating parameters. The adjustment includes the circulation rate of the cooling medium and the output power of the cooling system. S4.

3. Acquire the adjusted memory chip temperature data in real time, compare the real-time temperature data with the preset temperature threshold, and correct the operating parameters of the memory heat dissipation system in a closed loop based on the comparison results.

6. The method according to claim 2, characterized in that, In step S1, the process of acquiring memory operating status data is executed in parallel with the normal memory read and write operation process. The acquisition operation does not occupy the clock cycle of the memory read and write operation, and the acquisition channel and the memory data read and write channel are independent of each other. During the acquisition process, independent acquisition links are divided according to data type, corresponding to the acquisition of memory access frequency data, memory read and write request data, and memory chip temperature data, respectively. The sampling period of each acquisition link can be adjusted individually based on the memory operating status. The acquired raw data is classified and stored according to the corresponding link identifier. The preprocessing process is executed in parallel according to data classification and link.

7. The method according to claim 3, characterized in that, In step S2, hot data is stored in dynamic random access memory, warm data is stored in spin-torque magnetic memory, and cold data is stored in NAND flash memory. The data migration scheduling instruction is updated in real time based on changes in memory load prediction results. The data migration process is executed according to the idle timing window in the memory load prediction results. The migration process does not occupy the peak read / write bandwidth of memory. The storage address range of each level of data is predefined and there is no address overlap between them. After the data migration is completed, the address mapping table of the corresponding data is updated synchronously. The address mapping table is stored in the designated cache area for real-time access by memory read / write operations.

8. The method according to claim 4, characterized in that, In step S3, the high-performance mode uses the standard power supply voltage, and the energy-saving mode uses the subthreshold power supply voltage. The adjustment process of the memory power supply voltage is completed synchronously with the execution process of the data migration scheduling instruction. The power supply voltage adjustment process is executed step by step according to the preset step value to avoid voltage sudden changes affecting the memory operating state. The step value of voltage adjustment is determined based on the current memory load prediction result. After the voltage adjustment is completed, the stability of memory read and write operations is checked synchronously. If the check passes, the current power supply voltage parameter is locked. If the check fails, the power supply voltage parameter is restored to the previous state.

9. The method according to claim 5, characterized in that, In step S4, when the memory chip temperature exceeds a preset threshold, the memory power supply mode is switched to energy-saving mode, and the operating power of the memory heat dissipation system is increased to complete the closed-loop control of memory temperature. Temperature thresholds are preset based on different memory power supply modes. Different power supply modes correspond to different temperature threshold ranges. During temperature adjustment, the performance parameters of memory read and write operations are monitored simultaneously. When the memory load prediction results show an increase in read and write demand, the operating parameters of the heat dissipation system and the power supply mode are adjusted simultaneously to ensure the stability of memory read and write performance.

10. A server low-power memory dynamic energy efficiency control system, used to execute the method as described in any one of claims 1-9, characterized in that, It includes a data acquisition module, a load prediction and data classification module, a power supply control module, a refresh control module, and a heat dissipation coordination control module. The data acquisition module is connected to the memory hardware unit to complete the acquisition and preprocessing of memory operating status data. The load prediction and data classification module communicates with the other modules to generate memory load prediction results and data classification scheduling instructions. The power supply control module is connected to the memory power supply circuit to perform power supply working mode switching and voltage adjustment operations. The refresh control module is connected to the memory storage unit to perform refresh cycle adjustment and partial refresh operations. The heat dissipation coordination control module is connected to the memory heat dissipation system to perform heat dissipation parameter adjustment and coordination control operations.

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