A signal delay control method and system based on carry4 delay chain

Abstract

This application proposes a signal delay control method and system based on a carry4 delay chain. The method includes: configuring a target delay time and dividing the target delay time into a coarse delay and a fine delay; using a clock counter based on the FPGA system clock to count and output the coarse delay, obtaining a coarse delay pulse signal; inputting the coarse delay pulse signal into a delay chain combination composed of multiple cascaded carry4 units within the FPGA, and using the delay chain combination to output the fine delay, obtaining multiple initial delay trigger signals; and eliminating delay jitter errors by voting calibration of the multiple initial delay trigger signals to obtain a final delay trigger signal to control the signal delay. This application employs a two-level architecture of clock counter to implement the coarse delay and carry4 chain to implement the fine delay, which can break through the limitation of the FPGA system clock cycle in terms of delay step accuracy, achieving fine delay control much smaller than the clock cycle, and solving the problem of insufficient accuracy in traditional delay methods.

Description

Technical Field

[0001] This application relates to the field of signal delay control, specifically to a signal delay control method and system based on the Carry4 delay chain. Background Technology

[0002] In many applications in radio frequency communication, radar, and electronic warfare, a precisely controllable time delay is often required to be added to signals or other devices, and the accuracy of this delay control is directly related to system performance. In radar, the precision of delay control between different elements in a phased array radar affects the radar's search and tracking accuracy. In electronic warfare, the success rate of signal deception in signal relay systems often depends on the system's ability to precisely control the relay delay. In the time and frequency domain, systems such as two-way time and frequency relay also require precise time delay control capabilities.

[0003] Typically, signal delays are generated using an internal clock counter built into the FPGA. This involves counting the internal clock signal, and once the count reaches a certain value, a delay signal is generated, thus delaying the input signal. However, the delay control step accuracy achieved by this method depends on the system clock cycle, which is generally in the nanosecond range in FPGAs. To improve the time delay step control accuracy to within the system clock cycle, this invention proposes a method of adding a delay chain after the clock counter. This delay chain is implemented based on the FPGA's internal carry4 carry unit, which can improve the delay control step accuracy to 50 picoseconds. Summary of the Invention

[0004] To address the problem of low step accuracy in delay control in practical applications of existing technologies, this application provides a signal delay control method and system based on the Carry4 delay chain.

[0005] The first aspect of this application provides a signal delay control method based on a Carry4 delay chain, the method comprising: Configure a target delay time, and divide the target delay time into coarse delay and fine delay; A time counter based on the FPGA system clock is used to complete the counting output of the coarse delay, thereby obtaining a coarse delay pulse signal; The coarse delay pulse signal is input into a delay chain combination composed of multiple cascaded carry4 units within the FPGA. The fine delay is output through the delay chain combination to obtain multiple initial delay trigger signals. The multiple initial delay trigger signals are calibrated by voting to eliminate delay jitter error, resulting in the final delay trigger signal, which controls the signal delay.

[0006] Optionally, dividing the target delay time into coarse delay and fine delay includes: Using the FPGA system clock cycle as the coarse delay step unit, extract the portion of the target delay time that is an integer multiple of the clock cycle as the coarse delay. Using the carry4 carry unit single-level carry delay as the fine delay step unit, the portion of the target delay time that is less than one clock cycle is extracted as the fine delay.

[0007] Optionally, a clock counter based on the FPGA system clock is used to complete the counting output of the coarse delay, resulting in a coarse delay pulse signal including: Input the delay start signal into the clock counter; The clock counter counts cycles based on the FPGA system clock until the count value matches the number of clock cycles corresponding to the coarse delay. After counting is completed, a coarse delay pulse signal is output, which serves as the carry initial trigger signal for the delay chain combination.

[0008] Optionally, the input of the coarse delay pulse signal into a delay chain combination consisting of multiple cascaded carry4 units within the FPGA includes: Connect the CINT terminal of the first-stage carry4 unit to the coarse delay pulse signal; The DI terminal of each carry4 unit is fixed to input binary 0000, and the S terminal is fixed to input binary 1111. The COUT[3] terminal of the previous carry4 unit is connected to the CIN terminal of the next carry4 unit to form a continuous carry delay chain.

[0009] Optionally, the step of achieving the fine delay output through the delay chain combination to obtain multiple initial delay trigger signals includes: A coarse-delayed pulse signal triggers a multi-level carry4 unit to carry in step by step, and the COUT terminal of each carry4 unit outputs a carry signal synchronously. Based on the carry4 carry level corresponding to the fine delay, the COUT signal of the corresponding level is selected by the encoder selector as the initial delay trigger signal of a single delay chain. Multiple identical carry4 delay chains run in parallel, and multiple initial delay trigger signals are output synchronously.

[0010] Optionally, the step of selecting the COUT signal of the corresponding level as the initial delay trigger signal for a single delay chain through an encoder selector based on the carry4 carry level corresponding to the fine delay includes: The delay step is set to 50ps for a single-level carry4 carry unit in the preset FPGA series. Divide the fine delay time by 50ps to get the target round number; The encoder selector selects the COUT signal corresponding to the target carry level and outputs the initial delay trigger signal corresponding to the fine delay.

[0011] Optionally, eliminating delay jitter error by calibrating the multiple initial delay trigger signals through voting includes: Multiple initial delay trigger signals are input into a preset voting circuit; When most of the initial delay trigger signals are high, the voting circuit outputs a high level; otherwise, it outputs a low level as the final delay trigger signal.

[0012] Optionally, the step of inputting multiple initial delayed trigger signals into a 3-to-2 voting circuit includes: The three initial delay trigger signals are denoted as the first signal, the second signal, and the third signal, and the calibration output signal is denoted as the voting output signal. If at least two of the first, second, and third signals are output at a high level, then the voting output signal is high; otherwise, it is low.

[0013] Optionally, the method further includes: The number of delay chains in the delay chain combination is expanded to 5, and the mean is calibrated by a five-to-three voting logic to obtain the final delay trigger signal.

[0014] A second aspect of this application provides a signal delay control system based on a Carry4 delay chain, the system comprising: The configuration module is used to configure the target delay time, and to divide the target delay time into coarse delay and fine delay; The coarse delay pulse signal module is used to use a time counter based on the FPGA system clock to complete the counting output of the coarse delay and obtain the coarse delay pulse signal; The output module is used to input the coarse delay pulse signal into a delay chain combination composed of multiple cascaded carry4 units inside the FPGA, and to achieve the fine delay output through the delay chain combination to obtain multiple initial delay trigger signals. The calibration module is used to eliminate delay jitter error by voting calibration of the multiple initial delay trigger signals to obtain the final delay trigger signal, so as to control the signal delay.

[0015] As can be seen from the above technical solution, this application adopts a two-level architecture of clock counter to achieve coarse delay and carry4 carry chain to achieve fine delay. This can break through the clock cycle limitation of FPGA system to achieve fine delay control much smaller than the clock cycle, solving the problem of insufficient accuracy of traditional delay methods. This application also utilizes the physical delay characteristics of carry4 carry unit's step-by-step transmission. The delay magnitude has a strict linear relationship with the carry level. Accurate configuration of arbitrary fine delay can be achieved through the encoder selector. The delay output is stable, without jumps or distortion, and the control method is simple and direct. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a signal delay control method based on a carry4 delay chain in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the specific structure of a carry in an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the structure of a delay chain composed of multiple carry4s in an embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the mean calibration circuit structure in the embodiments of this application.

[0021] Figure 5 This is a schematic diagram of a signal delay control system based on a Carry4 delay chain in an embodiment of this application.

[0022] Figure 6 This is a schematic diagram of a signal delay control device based on a carry4 delay chain in an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Based on this, this application provides an implementation method for a signal delay control method based on a Carry4 delay chain, such as... Figure 1 As shown, the method includes: S101, Configure the target delay time, and divide the target delay time into coarse delay and fine delay; S102, a time counter is used to complete the counting output of the coarse delay based on the FPGA system clock, so as to obtain the coarse delay pulse signal; S103, the coarse delay pulse signal is input into a delay chain combination composed of multiple cascaded carry4 units inside the FPGA, and the fine delay is output through the delay chain combination to obtain multiple initial delay trigger signals; S104, the multiple initial delay trigger signals are calibrated by voting to eliminate delay jitter error, and the final delay trigger signal is obtained to control the signal delay.

[0025] It should be noted that the target delay time refers to the total delay duration of the desired signal sent by the user or host computer to the delay control system according to the actual application scenario requirements. Its value is dynamically configured to adapt to the delay requirements under different scenarios. In the embodiments of this application, a single delay quantity is decomposed into coarse and fine delays. This retains the advantages of clock counting to achieve large-span, highly stable coarse delays, while using carry4 carry chain to achieve picosecond-level fine delays within the clock cycle. After the two delays are superimposed, the accuracy bottleneck of traditional delay schemes can be overcome.

[0026] It should be noted that coarse delay refers to the delay component with the FPGA system clock cycle as the smallest step unit, responsible for achieving delay outputs of large durations and integer multiples of clock cycles; fine delay refers to the fine delay component, smaller than a single system clock cycle, implemented based on the inherent propagation delay of the carry4 unit. The two levels of delay work together to cover the high-precision delay requirements across the entire range. In this embodiment, the clock counter serves as the coarse delay implementation unit, relying on the native clock resources within the FPGA to complete the counting logic without the need for additional complex hardware circuits, ensuring the stability and reliability of the coarse delay output. Its output coarse delay pulse signal serves as the trigger reference for subsequent fine delay units, providing the timing start point for the entire delay link. It should also be noted that the carry4 unit is the core hardware carrier of this application, a dedicated addition carry logic unit integrated within FPGAs such as the Xilinx7 series. This application does not use it for addition operations, but rather utilizes its inherent propagation delay characteristics at the transistor level to construct a passive delay link, achieving clock-independent fine-grained delay control. In this embodiment, multiple carry4 carry units are cascaded to form a delay chain combination. Precise output of fine delays is achieved through the step-by-step transmission of carry signals. A single delay chain can output a fixed, fine delay, while multiple delay chains operating in parallel provide a data foundation for subsequent error calibration. It should be noted that the initial delay trigger signal refers to the pulse signal output by a single carry4 delay chain carrying fine delay information. Due to non-ideal factors such as temperature, power supply, and wiring, the initial delay trigger signal output by a single delay chain exhibits timing jitter and cannot be directly used in high-precision scenarios. In this embodiment, voting calibration is used to eliminate delay jitter errors. By logically judging the timing states of multiple initial delay trigger signals, effective timing features are extracted, random jitter interference is filtered out, and a stable and accurate final delay trigger signal is finally output, completing the entire process of signal delay control.

[0027] For example, in a radar phased array element delay control scenario, the target delay time is issued by the radar beam pointing algorithm. After coarse and fine delay division, the clock counter completes large-span coarse delay matching between array elements, the carry4 delay chain combination achieves picosecond-level fine delay compensation, and voting calibration eliminates delay fluctuations caused by environmental factors, ultimately ensuring the signal synchronization of each array element and improving radar search and tracking accuracy. This application is not limited to this; the method is also applicable to scenarios such as relay-type time deception, satellite navigation time synchronization, and two-way time and frequency transmission in the field of electronic countermeasures. Only the target delay time configuration parameters need to be adjusted according to the scenario requirements, without modifying the core hardware and logic architecture. It should be noted that in the embodiments of this application, the core value of signal delay control lies in breaking through the delay step accuracy to below the system clock cycle, achieving picosecond-level control capability that traditional solutions cannot achieve, while taking into account a large delay range and high stability, meeting the stringent timing requirements of high-end electronic systems.

[0028] It should be noted that carry4 is a basic carry unit used for addition calculations. One carry contains four carry units, each corresponding to one of the four carry outputs, as shown in the structure below. Figure 2 As shown, CIN is the carry input and COUT is the carry output. The cout[3] of the previous carry4 is connected to the CIN of the next stage to form a delay chain. CINT is the carry initial signal. The CINT of the first carry4 is connected to the pulse signal as the trigger. In addition, in order to meet the carry requirements, the input data DI and the XOR S of the input data are input as binary 0000 and 1111 respectively. It should be noted that each bit of the carry output COUT is connected to the encoder selector in sequence.

[0029] Due to the switching characteristics of the transistors inside the carry4 stage, each stage generates the same delay when performing consecutive carry operations. Depending on the FPGA chip manufacturing process, the delay of each carry stage varies; for example, in a Xilinx 7 series FPGA, the delay of each carry stage is approximately 50 ps. Since a carry4 stage has four carry stages, constructing a carry delay chain of 50 stages can cover the delay of one cycle of a 100MHz clock.

[0030] This application, through multiple parallel delay chains combined with voting mean calibration, can significantly eliminate delay fluctuations caused by environmental factors and hardware differences, greatly improving the stability and consistency of delay output and meeting the requirements of high-precision timing systems. Furthermore, this application is based on the native carry4 carry unit and general logic implementation within the FPGA, requiring no external devices, no high-frequency clock, and no complex algorithms, resulting in high resource utilization, compatibility with various FPGA platforms, and strong portability. In addition, it features a wide delay range, balancing coarse and fine adjustment. The coarse delay enables large-span, long-delay outputs, while the fine delay enables high-precision compensation within a clock cycle. The combination of these two features ensures both a large delay range and extremely high delay resolution, simultaneously meeting the needs of multiple scenarios such as radar, electronic countermeasures, and time synchronization.

[0031] In one embodiment that can be implemented in this application, dividing the target delay time into coarse delay and fine delay includes: S201 uses the FPGA system clock cycle as the coarse delay step unit and extracts the part of the target delay time that is an integer multiple of the clock cycle as the coarse delay. S202 uses the carry delay of the carry4 unit as the fine delay step unit and extracts the part of the target delay time that is less than one clock cycle as the fine delay.

[0032] It should be noted that the FPGA system clock cycle is jointly determined by the external crystal oscillator and the internal clock management unit, and is the basic timing unit of the FPGA's internal timing logic. Traditional delay schemes can only use this as the smallest step. This application uses it as the coarse delay step unit to ensure the compatibility and stability of the coarse delay implementation. In the embodiments of this application, the coarse delay extraction logic is as follows: divide the target delay time by the system clock cycle, and take the duration corresponding to the integer quotient as the coarse delay. This part of the delay can be implemented entirely through clock counting, without relying on the carry4 delay chain, thus reducing the load on the core delay unit.

[0033] For example, when the target delay time includes multiple system clock cycles, the integer multiples are all classified as coarse delays to ensure efficient implementation of large-span delays. This application is not limited to this; the partitioning logic can be adapted to FPGA system clocks of any frequency without modifying the algorithm for a specific clock frequency. It should be noted that the single-level carry delay of the carry4 unit is an inherent physical delay within the FPGA hardware, determined by the physical characteristics of transistor conduction and signal transmission, and does not depend on the clock signal. This application uses it as a fine delay step unit to achieve continuous and fine delay control within a clock cycle. In this embodiment, the fine delay extraction logic is as follows: the target delay time is divided by the system clock cycle, and the remainder is taken as the fine delay. This portion of the delay is less than a single system clock cycle and cannot be achieved through clock counting; it needs to be output using carry4 delay chain combinations.

[0034] It should be noted that the division of coarse and fine delays is non-overlapping and non-overlapping, and their sum strictly equals the target delay time. This ensures the accuracy of the total delay control duration, which is the fundamental premise for achieving high-precision delay control in this application. In this embodiment, the division process is automatically completed by the internal logic unit of the FPGA without manual intervention. After configuring the target delay time, the division logic performs real-time calculations and outputs coarse and fine delay configuration parameters, which are transmitted to the clock counter and delay chain combination, respectively, to achieve coordinated configuration of the two-level delay. For example, in time and frequency transmission scenarios, the system has extremely high requirements for the accuracy of the total delay duration. The division method of this application can ensure that the coarse delay covers long-term delay requirements, and the fine delay compensates for small deviations within the clock cycle, so that the overall delay error can be controlled within the stringent industry standards. This application is not limited to this; the division logic can support real-time adjustment of the dynamic target delay time. When the application scenario requirements change, the coarse and fine delays can be quickly re-divided to ensure the real-time response capability of the delay control system. It should be noted that in this embodiment, the maximum range of fine delay does not exceed a single system clock cycle. Therefore, only a suitable number of carry4 units are needed to cover the full range of fine delay requirements, avoiding waste of hardware resources and improving FPGA resource utilization.

[0035] In one embodiment of this application, a clock counter is used to complete the counting output of the coarse delay based on the FPGA system clock, resulting in a coarse delay pulse signal including: S301 inputs the delay start signal to the clock counter; S302, the clock counter counts the cycles based on the FPGA system clock until the count value matches the number of clock cycles corresponding to the coarse delay; S303, after the counting is completed, a coarse delay pulse signal is output, which serves as the carry initial trigger signal for the delay chain combination.

[0036] It should be noted that the delay start signal refers to the pulse signal input from the external system that marks the start of the delay timing. It is the start instruction for the entire delay control process, and the clock counter only starts counting after receiving this signal. In this embodiment, the clock counter is a general-purpose sequential logic unit inside the FPGA, requiring no additional dedicated hardware instantiation. It can be implemented using the FPGA's native registers and counting logic, featuring low resource consumption, high stability, and strong compatibility. It should be noted that the clock counter's counting reference is strictly synchronized with the FPGA system clock. Each counting cycle corresponds to a duration equal to one system clock cycle, and the count value is completely consistent with the number of clock cycles corresponding to the coarse delay, ensuring accurate matching of the coarse delay duration. In this embodiment, the counting process is a closed-loop logic: after the delay start signal is input, the counter is cleared and starts counting. Each time a rising edge of the system clock is detected, the count value increments by 1. When the count value reaches a preset threshold (the number of cycles corresponding to the coarse delay), counting stops and a pulse output is triggered.

[0037] For example, in an electronic countermeasures relay-based deception scenario, the delay start signal is triggered by the RF signal receiving unit, marking the reception time of the signal to be relayed. The clock counter completes counting according to the coarse delay parameters, and the output coarse delay pulse signal marks the end of the coarse delay stage and the entry into the fine delay stage. It should be noted that the carry initial trigger signal is the functional definition of the coarse delay pulse signal in the delay chain combination. Its rising edge serves as the start signal of the carry4 delay chain combination, triggering the step-by-step transmission of the carry signal and acting as the timing connection point between the coarse and fine delay units. In this embodiment, the pulse width and level standard of the coarse delay pulse signal are compatible with the FPGA's internal logic level and can be directly input to the trigger port of the carry4 delay chain combination without the need for a level conversion circuit, simplifying the hardware architecture. This application is not limited to this; the clock counter can support dynamic modification of pre-designed values ​​to adapt to different coarse delay requirements. The counting accuracy is not affected by the external environment, ensuring the long-term stability of the coarse delay output. It should be noted that in this embodiment, the clock counter is only responsible for the coarse delay counting output and does not participate in fine delay control. This clearly defined architecture reduces logic complexity and improves the overall system reliability.

[0038] In one embodiment of this application, inputting the coarse delay pulse signal into a delay chain combination consisting of multiple cascaded carry4 units within an FPGA includes: S401 connects the CINT terminal of the first-stage carry4 unit to a coarse delay pulse signal; S402, the DI terminal of each carry4 unit has a fixed input of binary 0000, and the S terminal has a fixed input of binary 1111; S403, the COUT[3] terminal of the previous carry4 unit is connected to the CIN terminal of the next carry4 unit to form a continuous carry delay chain.

[0039] For example, such as Figure 3 As shown, this application uses multiple carry4 stages to form a delay chain. When a pulse signal arrives, carry4 stages carry up sequentially and output a carry signal COUT. All carry signals are connected to an encoder selector. Depending on the required delay, the encoder selector selects the corresponding carry output signal as the delay trigger signal. For example, when a 400ps delay is required, the encoder selector will select the carry signal of the 8th COUT stage in the delay chain as the delay trigger signal. When a pulse signal is generated, the carry4 delay chain carries up sequentially. After the carry is completed by the 8th stage carry, the delay trigger signal output by the encoder selector will be set high. At this time, compared with the input pulse signal, the output delay trigger signal lags by exactly 400ps. This method achieves precise experimental control with a step size of 50ps. This application is not limited to this.

[0040] It should be noted that the CINT, DI, S, CIN, and COUT terminals are all native hardware ports of the carry4 unit. This application uses fixed configurations for each port based on delay control requirements, rather than following the conventional addition operation. In this embodiment, the CINT terminal of the first-stage carry4 unit is the carry initial signal input port. After receiving the coarse delay pulse signal, this signal serves as the carry start signal for the entire delay chain, triggering the first-stage unit to begin carry transmission. It should also be noted that the DI and S terminals are the data input ports of the carry4 unit. In this embodiment, the DI terminal is fixed to all 0s and the S terminal is fixed to all 1s to force the carry4 unit into a continuous carry transmission state, disabling the addition operation function and retaining only the physical delay characteristics of signal transmission. This application is not limited to this; the configuration logic of the DI and S terminals can be fine-tuned according to the FPGA model and carry4 unit architecture. The core objective is to ensure continuous carry without logical interruption. This embodiment is merely an exemplary configuration. In this embodiment, the cascading rule of the multi-level carry4 units is as follows: the highest carry output terminal COUT[3] of the previous level unit is directly connected to the carry input terminal CIN of the next level unit to form a serial carry transmission link, ensuring that the signal is transmitted step by step without branches or delay abrupt changes. It should be noted that the continuous carry delay chain provides a physical carrier for the realization of fine delay. The transmission time of the signal on the link is linearly related to the number of transmission levels. Each transmission of a carry4 unit corresponds to a fixed physical delay, which is the core hardware foundation for precise and controllable fine delay. For example, in the scenario of radio frequency communication signal delay control, the delay chain formed by the cascading of multi-level carry4 units ensures the linearity of signal transmission delay and avoids nonlinear distortion of delay caused by improper cascading method. In this embodiment, the number of delay chain levels can be flexibly configured according to the maximum range requirement of fine delay. The more levels, the larger the fine delay range that can be covered. This application is not limited to this and can be adapted to scenarios with different accuracy and range requirements. It should be noted that in this embodiment, the cascading of the carry4 unit uses dedicated carry routing resources inside the FPGA, rather than general programmable routing. Dedicated routing resources have higher delay consistency and further improve the control accuracy of fine delays.

[0041] In one embodiment of this application, the step of achieving the fine delay output through the delay chain combination to obtain multiple initial delay trigger signals includes: S501, a coarse delay pulse signal triggers multi-level carry4 units to carry step by step, and the COUT terminal of each carry4 unit outputs the carry signal synchronously; S502, based on the carry4 carry level corresponding to the fine delay, selects the COUT signal of the corresponding level as the initial delay trigger signal of a single delay chain through the encoder selector; The S503 runs multiple identical carry4 delay chains in parallel and synchronously outputs multiple initial delay trigger signals.

[0042] It should be noted that the encoder selector is a custom logic unit in this application and is the core component connecting the carry4 delay chain and the subsequent calibration module. It is responsible for selecting the carry signal of the target level from the multi-level COUT signals based on the fine delay parameters. In this embodiment, after the coarse delay pulse signal is triggered, the carry signal passes through the carry4 unit level by level with a fixed physical delay. The COUT terminal of each level unit synchronously outputs the carry status of the current level, forming a multi-level carry signal sequence with sequential timing delays. It should be noted that the carry4 carry level corresponding to the fine delay is determined by the ratio of the fine delay duration to the transmission delay of a single carry4 unit. The encoder selector completes signal selection based on this level, ensuring that the lag duration of the selected signal is strictly equal to the fine delay duration. In this embodiment, the initial delay trigger signal of a single delay chain is the target level COUT signal selected by the encoder selector. This signal carries precise fine delay information and is the basic data for subsequent calibration. For example, in a phased array radar fine delay compensation scenario, the encoder selector quickly selects the corresponding level of COUT signal according to the fine delay parameters required by the array element, achieving picosecond-level delay compensation and improving beam pointing accuracy. It should be noted that multiple structurally identical carry4 delay chains refer to a delay chain combination containing multiple parallel carry4 delay links with identical hardware configurations and cascading rules. Parallel operation ensures that each link receives the same trigger signal and configuration parameters. In this embodiment, multiple delay chains synchronously output initial delay trigger signals, with ideal timing sequences completely consistent. Actual timing sequences exhibit slight jitter due to environmental interference, providing multiple sets of redundant data for voting calibration. This application is not limited to this; the number of delay chains can be flexibly adjusted according to calibration accuracy requirements. In this embodiment, three and five chains are typical configurations to adapt to different levels of jitter suppression requirements. It should be noted that the encoder selector's selection logic is real-time responsive. After a change in fine delay parameters, the encoder selector can immediately switch the selection level, ensuring the real-time nature of the fine delay output and meeting the requirements of dynamic delay control scenarios. In this embodiment, the level standard of the initial delay trigger signal is compatible with the internal logic of the FPGA and can be directly input to the mean calibration module without the need for additional signal conditioning circuitry, thus simplifying the system architecture.

[0043] In one embodiment of this application, selecting the COUT signal of the corresponding level as the initial delay trigger signal for a single delay chain via an encoder selector, based on the carry4 carry level corresponding to the fine delay, includes: S601 uses a preset series FPGA single-level carry4 carry unit with a delay step of 50ps; S602, the target carry level is obtained by dividing the fine delay time by 50ps; S603, the encoder selector selects the COUT signal corresponding to the target carry level and outputs the initial delay trigger signal corresponding to the fine delay.

[0044] It should be noted that the Xilinx 7 series FPGA is used as a typical hardware carrier in this application embodiment. The carry4 carry unit of this series of chips has mature hardware characteristics and stable physical delay, making it a preferred implementation platform for the technical solution of this application. This application is not limited to this; this technical solution can be extended to other FPGA platforms that integrate similar carry units. Only the level calculation logic needs to be adjusted according to the single-level carry unit delay parameters of the target platform, and the core architecture does not need to be modified. In this application embodiment, the delay step is determined by the physical delay of the single-level carry4 carry unit. This step is an inherent parameter of the FPGA hardware and is not affected by clock frequency or logic configuration, ensuring the stability of fine delay step. It should be noted that the calculation of the target carry level is a linear operation. The ratio of the fine delay duration to the single-level delay directly corresponds to the number of carry4 unit levels to be transmitted. There is no complex algorithm, the operation efficiency is high, and it can be completed in real time. In this application embodiment, the encoder selector directly selects the corresponding level's COUT signal according to the calculated target carry level. The selection process has no logic conversion and no additional delay, ensuring the timing accuracy of the initial delay trigger signal. For example, in high-precision time synchronization scenarios, linear calculation and direct gating methods can ensure that fine-delay outputs have no calculation errors and no gating delays, thus meeting the stringent timing requirements of time synchronization systems.

[0045] It should be noted that the number of selection channels in the encoder selector matches the number of carry4 unit stages in the delay chain, ensuring that the COUT signal of all stages can be selected, covering the fine delay requirements across the entire range. In this embodiment, the delay of a single carry4 unit is a fixed hardware parameter, thus the calculation result of the target carry stage is unique, avoiding selection errors caused by multiple solutions and improving system reliability. This application is not limited to this; when the application scenario requires higher fine delay accuracy, the single-stage delay can be reduced by optimizing the FPGA hardware configuration or using carry4 units with more advanced technology, thereby improving the delay step accuracy.

[0046] In one embodiment of this application, eliminating delay jitter error by voting calibration of the plurality of initial delay trigger signals includes: S701 inputs three initial delayed trigger signals into a 3-to-2 voting circuit; S702: When at least two initial delay trigger signals are high, the voting circuit outputs a high level; otherwise, it outputs a low level to obtain the final delay trigger signal.

[0047] It should be noted that delay jitter error refers to the slight random deviation in the timing of multiple initial delay trigger signals caused by non-ideal factors such as temperature changes, power supply fluctuations, and differences in FPGA internal wiring. This error reduces the accuracy of delay control and needs to be eliminated through calibration. In this embodiment, the 3-to-2 voting circuit is the core unit of the mean calibration module. It adopts a digital logic decision method, requiring no analog circuits or complex algorithms, resulting in simple hardware implementation, low resource consumption, and fast response speed. It should be noted that selecting three delay chains as inputs to the 3-to-2 voting circuit is an optimal solution that balances calibration accuracy, hardware resources, and response speed, effectively filtering out random jitter from a single link. In this embodiment, the decision logic of the voting circuit is as follows: real-time monitoring of the level status of the three initial delay trigger signals; when at least two signals are synchronously high, it is determined that the timing is valid, and a high level is output; if only one signal or no signal is high, it is determined to be jitter interference, and a low level is output.

[0048] For example, when a delay chain experiences timing lead or lag due to environmental interference, its level state becomes inconsistent with the other two. The voting circuit ignores this abnormal signal, ensuring the stability of the output timing. It should be noted that the essence of voting calibration is to perform timing averaging on multiple initial delay trigger signals, extracting consistent timing characteristics from most links and filtering out random errors from a few links, thus achieving passive suppression of delay jitter. In this embodiment, the output signal of the voting circuit is the calibrated final delay trigger signal, whose timing jitter is much smaller than that of a single initial delay trigger signal, significantly improving delay control accuracy. This application is not limited to this; the three-to-two voting logic can adapt to most high-precision delay control scenarios. If the scenario has higher requirements for jitter suppression, the number of voting links can be expanded, and more gating rules can be adopted. It should be noted that in this embodiment, the voting calibration process has no additional timing delay; the decision and output are completed synchronously, ensuring the real-time performance of the entire delay control system and meeting the needs of high-speed signal processing scenarios.

[0049] In one embodiment of this application, inputting three initial delayed trigger signals into a three-to-two voting circuit includes: S801, the three initial delay trigger signals are recorded as the first signal, the second signal, and the third signal, and the calibration output signal is recorded as the voting output signal; S802, if at least two of the first, second, and third signals are output at a high level, then the voting output signal is high; otherwise, it is low.

[0050] For example, S1, S2, and S3 are the initial delay trigger signals output by the three delay chains, and S_out is the final delay trigger signal after voting calibration. All three are digital level signals, conforming to the FPGA internal logic level specifications. In this embodiment, the core expression of the three-to-two voting logic is S_out=(S1&S2)|(S1&S3)|(S2&S3), which fully covers the decision rule that outputs high when at least two signals are high. It should be noted that directly using AND and OR gates to implement the above logic would increase FPGA resource consumption and result in poor timing performance. Therefore, this application uses De Morgan's Law for logic transformation to optimize the circuit implementation. In this embodiment, based on De Morgan's Law, the original logic expression is transformed into NAND gate form. NAND gates are the most basic, resource-efficient, and fastest logic units within the FPGA, maximizing circuit performance. For example, after logic transformation, the voting circuit can be implemented with only a small number of NAND gates, eliminating the need for multi-level logic cascading, reducing the circuit's own transmission delay, and further improving calibration accuracy. This application is not limited to this; the logic conversion rules can be flexibly adjusted according to the type of logic unit inside the FPGA. The core objective is to reduce resource consumption and improve timing performance. The embodiments in this application are merely preferred implementations. It should be noted that FPGA instantiation refers to writing the converted NAND gate logic into the FPGA using a hardware description language, solidifying it as a hardware circuit. No software intervention is required during runtime, resulting in fast logic decision speed and high stability. In the embodiments of this application, the instantiation process of the voting circuit is standardized, adaptable to different models of Xilinx 7 series FPGAs, without requiring modification of the logic code for specific chips, thus improving the versatility of the solution. It should be noted that in the embodiments of this application, the logic implementation of the voting circuit has no feedback and no timing dependency; it is a combinational logic circuit that can respond to changes in input signals in real time, ensuring a delay-free response during the calibration process.

[0051] In one embodiment that can be implemented in this application, the method further includes: The number of delay chains in the delay chain combination is expanded to 5, and the mean is calibrated by a five-to-three voting logic to obtain the final delay trigger signal.

[0052] It should be noted that the five-to-three voting logic is an upgraded form of the three-to-two logic. By increasing the number of redundant delay chains, more sets of initial delay trigger signals are obtained, improving the accuracy of timing average extraction. In this embodiment, the number of delay chains is expanded to five, with the five chains running in parallel and triggering synchronously, outputting five sets of initial delay trigger signals. The voting circuit's decision rule is: when at least three signals are high, a high level is output; otherwise, a low level is output.

[0053] For example, in ultra-precise time and frequency transfer scenarios, five delay chains can effectively suppress more random jitter and environmental interference, resulting in higher timing stability of the final delayed trigger signal after calibration and further reduction in delay error. This application is not limited to this; the number of delay chains can be expanded to more based on actual needs, and the voting logic can be adjusted to an N-to-M format. In this embodiment, five chains are the preferred expansion scheme, balancing accuracy and resource consumption. It should be noted that the number of delay chains should not be excessive, as too many chains will increase FPGA logic resource consumption and introduce additional wiring delays, thus reducing system performance. This embodiment has balanced accuracy and resource requirements. In this embodiment, after expanding the number of delay chains, the architecture of the encoder selector and voting circuit does not need significant modification; only the input channel and decision logic need to be added, maintaining compatibility with the original core technology solution and improving the scalability of the solution. It should be noted that in this embodiment, the expanded calibration scheme and the original calibration scheme can be dynamically switched, selecting either a 3-chain or 5-chain mode according to the scenario's accuracy requirements, improving the system's scenario adaptability.

[0054] For example, taking the mean calibration using three delay chains as an example, the voting circuit will be designed in a three-to-two manner. That is, when two of the delay trigger signals of the three delay chains are high, the calibrated delay trigger signal is the high bit, and the rest are low bits. This achieves the purpose of taking the average of the three delay trigger signals.

[0055] The design of the mean calibration circuit is as follows, assuming the calibrated delayed trigger signal is... The delayed trigger signals for the three chains are respectively , and Based on the three-choice-two voting method, its logical expression is:

[0056] Based on De Morgan's law, it can be transformed into a NAND gate form that is easier to implement on FPGAs:

[0057]

[0058] Based on the above design concept, the following is obtained: Figure 4 The mean calibration circuit diagram shown below, when the three chains are delayed trigger signals , and Two of them are outputs of the high-time calibration circuit. It is considered high, and therefore... , and The output delay control signal is averaged to achieve the purpose of calibrating jitter error.

[0059] The second aspect of this application provides a signal delay control system based on a Carry4 delay chain, such as... Figure 5 As shown, the system includes: Configuration module 901 is used to configure the target delay time and divide the target delay time into coarse delay and fine delay; The coarse delay pulse signal module 902 is used to complete the counting output of the coarse delay based on the FPGA system clock using a time counter to obtain the coarse delay pulse signal; Output module 903 is used to input the coarse delay pulse signal into a delay chain combination composed of multiple cascaded carry4 units inside the FPGA, and to achieve the fine delay output through the delay chain combination to obtain multiple initial delay trigger signals; The calibration module 904 is used to eliminate delay jitter error by voting calibration of the multiple initial delay trigger signals to obtain the final delay trigger signal, so as to control the signal delay.

[0060] A third aspect of this application provides a signal delay control device based on a Carry4 delay chain, such as... Figure 6 As shown, it includes: a clock counter, a delay chain assembly, and a mean calibration module. The clock counter generates a coarse delay with a step accuracy of 1 clock cycle. The delay chain assembly generates a fine delay with a step accuracy of 50ps. The mean calibration module is used to calibrate the jitter error of the delay chain.

[0061] Specific embodiments have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A signal delay control method based on a Carry4 delay chain, characterized in that, The method includes: Configure a target delay time, and divide the target delay time into coarse delay and fine delay; A time counter based on the FPGA system clock is used to complete the counting output of the coarse delay, thereby obtaining a coarse delay pulse signal; The coarse delay pulse signal is input into a delay chain combination composed of multiple cascaded carry4 units within the FPGA. The fine delay is output through the delay chain combination to obtain multiple initial delay trigger signals. The multiple initial delay trigger signals are calibrated by voting to eliminate delay jitter error, resulting in the final delay trigger signal, which controls the signal delay.

2. The method according to claim 1, characterized in that, Dividing the target delay time into coarse delay and fine delay includes: Using the FPGA system clock cycle as the coarse delay step unit, extract the portion of the target delay time that is an integer multiple of the clock cycle as the coarse delay. Using the carry4 carry unit single-level carry delay as the fine delay step unit, the portion of the target delay time that is less than one clock cycle is extracted as the fine delay.

3. The method according to claim 1, characterized in that, The coarse delay is counted and output using a clock counter based on the FPGA system clock, resulting in a coarse delay pulse signal including: Input the delay start signal into the clock counter; The clock counter counts cycles based on the FPGA system clock until the count value matches the number of clock cycles corresponding to the coarse delay. After counting is completed, a coarse delay pulse signal is output, which serves as the carry initial trigger signal for the delay chain combination.

4. The method according to claim 1, characterized in that, The input of the coarse delay pulse signal into a delay chain combination consisting of multiple cascaded carry4 units within the FPGA includes: Connect the CINT terminal of the first-stage carry4 unit to the coarse delay pulse signal; The DI terminal of each carry4 unit is fixed to input binary 0000, and the S terminal is fixed to input binary 1111. The COUT[3] terminal of the previous carry4 unit is connected to the CIN terminal of the next carry4 unit to form a continuous carry delay chain.

5. The method according to claim 1, characterized in that, The process of achieving the fine delay output through the combination of the delay chains to obtain multiple initial delay trigger signals includes: A coarse-delayed pulse signal triggers a multi-level carry4 unit to carry in step by step, and the COUT terminal of each carry4 unit outputs a carry signal synchronously. Based on the carry4 carry level corresponding to the fine delay, the COUT signal of the corresponding level is selected by the encoder selector as the initial delay trigger signal of a single delay chain. Multiple identical carry4 delay chains run in parallel, and multiple initial delay trigger signals are output synchronously.

6. The method according to claim 5, characterized in that, The step of selecting the COUT signal of the corresponding level as the initial delay trigger signal for a single delay chain based on the carry4 carry level corresponding to the fine delay includes: The delay step is set to 50ps for a single-level carry4 carry unit in the preset FPGA series. Divide the fine delay time by 50ps to obtain the target carry level; The encoder selector selects the COUT signal corresponding to the target carry level and outputs the initial delay trigger signal corresponding to the fine delay.

7. The method according to claim 1, characterized in that, The step of eliminating delay jitter error by calibrating the multiple initial delay trigger signals through voting includes: Multiple initial delay trigger signals are input into a preset voting circuit; When most of the initial delay trigger signals are high, the voting circuit outputs a high level; otherwise, it outputs a low level as the final delay trigger signal.

8. The method according to claim 7, characterized in that, The voting circuit that inputs multiple initial delayed trigger signals includes: The three initial delay trigger signals are denoted as the first signal, the second signal, and the third signal, and the calibration output signal is denoted as the voting output signal. If at least two of the first, second, and third signals are output at a high level, then the voting output signal is high; otherwise, it is low.

9. The method according to claim 1, characterized in that, The method further includes: The number of delay chains in the delay chain combination is expanded to 5, and the mean is calibrated by a five-to-three voting logic to obtain the final delay trigger signal.

10. A signal delay control system based on a Carry4 delay chain, characterized in that, The system includes: The configuration module is used to configure the target delay time, and to divide the target delay time into coarse delay and fine delay; The coarse delay pulse signal module is used to use a time counter based on the FPGA system clock to complete the counting output of the coarse delay and obtain the coarse delay pulse signal; The output module is used to input the coarse delay pulse signal into a delay chain combination composed of multiple cascaded carry4 units inside the FPGA, and to achieve the fine delay output through the delay chain combination to obtain multiple initial delay trigger signals. The calibration module is used to eliminate delay jitter error by voting calibration of the multiple initial delay trigger signals to obtain the final delay trigger signal, so as to control the signal delay.

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