Heterojunction bipolar transistor and method of forming the same

Abstract

This invention provides a heterojunction bipolar transistor and its formation method, comprising a base, a heterojunction interlayer dielectric layer, an emitter, and a collector. The base is located on a substrate, covered by the heterojunction interlayer dielectric layer, the emitter is located on the heterojunction interlayer dielectric layer, and the collector is located on the side of the substrate away from the base. By forming a heterojunction interlayer dielectric layer between the base and the emitter, electrons emitted from the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer. Electrons that meet the preset threshold and enter the base are transported to the collector when a reverse voltage is applied to the collector, thereby improving electron transport efficiency. Furthermore, by controlling the properties of the heterojunction interlayer dielectric layer, the current amplification coefficients of the collector and base are precisely controlled, significantly improving the stability of the current amplification coefficients of the collector and base, and ensuring stable high-frequency radio frequency performance of the heterojunction device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a heterojunction bipolar transistor and a method for forming the same. Background Technology

[0002] A heterojunction bipolar transistor (HBT) is a transistor in which the emitter, base, and collector are made of semiconductor materials with different bandgap widths (Eg). It has excellent high-frequency characteristics and is commonly used in high-frequency and high-speed circuits such as microwave and radio frequency communications and radar.

[0003] The collector and base current amplification factor Beta (Ic / Ib) of an HBT is an important parameter characterizing the HBT's ability to selectively emit injected carriers from the emitter and efficiently collect them from the collector, and is extremely critical for high-frequency applications.

[0004] During the manufacturing process of HBTs, the processing technology at the base-emitter interface can greatly affect the stability of the base current, which in turn leads to instability in the collector-base current amplification factor Beta, ultimately affecting the characteristic frequency of the HBT and causing chip failure. Summary of the Invention

[0005] The purpose of this invention is to provide a heterojunction bipolar transistor and its formation method to solve the problem that the processing technology at the base and emitter interface affects the stability of the base current, thereby causing instability of the collector and base current amplification factor Beta, which ultimately affects the characteristic frequency of the HBT and leads to chip failure.

[0006] To solve the above-mentioned technical problems, the present invention provides a heterojunction bipolar transistor, comprising:

[0007] Substrate;

[0008] Base electrode, the base electrode being located on the substrate;

[0009] A heterojunction interlayer dielectric layer, wherein the heterojunction interlayer dielectric layer covers the base electrode;

[0010] The emitter is located on the heterojunction interlayer dielectric layer. Electrons emitted by the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer into the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer.

[0011] The collector is located on the side of the substrate away from the base. Electrons that enter the base and meet a preset threshold are transported to the collector under reverse voltage, and the relationship between the thickness of the heterojunction interlayer dielectric layer and the current amplification factor of the collector and base is obtained.

[0012] Optionally, the thickness of the heterojunction interlayer dielectric layer ranges from 20 angstroms to 30 angstroms.

[0013] Optionally, the material of the heterojunction interlayer dielectric layer is silicon oxide.

[0014] Optionally, it may also include an insulating layer and an opening through the insulating layer, the insulating layer covering the base, the opening exposing a portion of the top surface of the base.

[0015] Optionally, the substrate may also have vertically stacked buried layers and sidewall critical dimension control layers.

[0016] Optionally, the substrate is doped with a first doping type, and the buried layer is doped with a second doping type.

[0017] Optionally, the width of the opening is smaller than the width of the sidewall critical dimension control layer.

[0018] Based on the same inventive concept, the present invention also provides a method for forming a heterojunction bipolar transistor, for forming the heterojunction bipolar transistor described in any of the above claims, comprising:

[0019] Provide a substrate;

[0020] A base electrode is formed, the base electrode being located on the substrate;

[0021] A heterojunction interlayer dielectric layer is formed, which covers the base electrode;

[0022] An emitter is formed, which is located on the heterojunction interlayer dielectric layer, so that electrons emitted by the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer.

[0023] A collector is formed, which is located on the side of the substrate away from the base. Electrons that enter the base and meet a preset threshold are transported to the collector under a reverse voltage to obtain the correspondence between the thickness of the heterojunction interlayer dielectric layer and the current amplification factor of the collector and base.

[0024] Optionally, the heterojunction interlayer dielectric layer is formed using a thermal oxidation process or a chemical vapor deposition process.

[0025] Optionally, between the step of forming the heterojunction interlayer dielectric layer and the step of forming the base, the following method is further included:

[0026] An insulating layer is formed, which covers the base electrode;

[0027] A portion of the insulating layer is etched to form an opening that penetrates the insulating layer and exposes a portion of the top surface of the base.

[0028] In a heterojunction bipolar transistor provided by this invention, there are a base, a heterojunction interlayer dielectric layer, an emitter, and a collector. The base is located on a substrate, and the heterojunction interlayer dielectric layer covers the base. The emitter is located on the heterojunction interlayer dielectric layer, and the collector is located on the side of the substrate away from the base. By forming a heterojunction interlayer dielectric layer between the base and the emitter, electrons emitted from the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked from entering the base by the heterojunction interlayer dielectric layer. Electrons that meet the preset threshold and enter the base are transported to the collector when a reverse voltage is applied to the collector, thereby improving the electron transport efficiency. Furthermore, by controlling the properties of the heterojunction interlayer dielectric layer, the current amplification coefficients of the collector and base are precisely controlled, significantly improving the stability of the current amplification coefficients of the collector and base, and ensuring stable high-frequency radio frequency performance of the heterojunction device. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of a heterojunction bipolar transistor according to an embodiment of the present invention.

[0030] Figure 2 This is a flowchart of a method for forming a heterojunction bipolar transistor according to an embodiment of the present invention.

[0031] Figure 3 This is a schematic diagram of the heterojunction bipolar transistor structure after the formation of the sidewall critical dimension control layer in an embodiment of the present invention.

[0032] Figure 4 This is a schematic diagram of the heterojunction bipolar transistor after the base is formed according to an embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of the heterojunction bipolar transistor after the formation of the insulating layer according to an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of the heterojunction bipolar transistor after the opening is formed according to an embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the heterojunction bipolar transistor structure after the formation of the heterojunction interlayer dielectric layer according to an embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of the heterojunction bipolar transistor structure after the emitter is formed according to an embodiment of the present invention.

[0037] Figure 9 This is a schematic diagram of the heterojunction bipolar transistor structure after the collector electrode is formed according to an embodiment of the present invention.

[0038] Figure 10 This is a schematic diagram showing the relationship between the thickness of the interlayer dielectric layer and BETA in a heterojunction according to an embodiment of the present invention.

[0039] In the picture,

[0040] 10-Substrate; 11-Buried layer; 12-Shallow trench isolation structure; 13-Sidewall critical dimension control layer; 14-Base; 15-Insulating layer; 15a-First insulating layer; 15b-Second insulating layer; 16-Opening; 17-Heterojunction interlayer dielectric layer; 18-Emitter; 19-Collector. Detailed Implementation

[0041] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.

[0042] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "over" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.

[0043] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.

[0044] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values ​​that vary within, for example, 10% of the value. It is understood that for numerical values ​​not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values ​​described in the embodiments are merely exemplary.

[0045] Figure 1This is a schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a heterojunction bipolar transistor, including:

[0046] Substrate 10;

[0047] Base 14, the base 14 being located on the substrate 10;

[0048] A heterojunction interlayer dielectric layer 17 covers the base 14;

[0049] Emitter 18, located on the heterojunction interlayer dielectric layer 17, electrons emitted by emitter 18 that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer 17 into the base 14, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer 17.

[0050] Collector 19 is located on the side of the substrate 10 away from the base. Electrons that enter the base 14 and meet a preset threshold are transported to the collector 19 under reverse voltage, and the relationship between the thickness of the heterojunction interlayer dielectric layer 17 and the current amplification factor of the collector and base is obtained.

[0051] Please continue to refer to this. Figure 1 In this embodiment, the material of the heterojunction interlayer dielectric layer 17 is, for example, silicon oxide. The thickness of the heterojunction interlayer dielectric layer 17 ranges from 20 angstroms to 30 angstroms.

[0052] Please continue to refer to this. Figure 1 An insulating layer 15 and an opening 16 penetrating the insulating layer 15 are also disposed on the substrate 10. The insulating layer 15 covers the base 14, and the opening 16 exposes a portion of the top surface of the base 14. The insulating layer 15 includes a first insulating layer 15a and a second insulating layer 15b, the second insulating layer 15b covering the first insulating layer 15a, and the first insulating layer 15a covering the base 14. The material of the first insulating layer 15a is, for example, silicon oxide, and the material of the second insulating layer 15b is, for example, silicon nitride.

[0053] Please continue to refer to this. Figure 1 The substrate 10 also has a vertically stacked buried layer 11 and a sidewall critical dimension control layer 13. The width of the opening 16 is smaller than the width of the sidewall critical dimension control layer 13. The substrate 10 is doped with a first doping type, and the buried layer 11 is doped with a second doping type. For example, the first doping type is P-type, i.e., a P-type substrate. Then the buried layer 11 is an N-type buried layer. The N-type buried layer is used to isolate the substrate 10 from the device above it, prevent carrier leakage, and enable the device to "levitate" and operate.

[0054] Figure 2 This is a flowchart illustrating a method for forming a heterojunction bipolar transistor according to an embodiment of the present invention. Figure 2 As shown, this embodiment also provides a method for forming a heterojunction bipolar transistor, used to form the heterojunction bipolar transistor described in any of the above claims, comprising:

[0055] Step S10: Provide a substrate;

[0056] Step S20: Forming a base electrode, wherein the base electrode is located on the substrate;

[0057] Step S30: A heterojunction interlayer dielectric layer is formed, wherein the heterojunction interlayer dielectric layer covers the base electrode;

[0058] Step S40: An emitter is formed, which is located on the heterojunction interlayer dielectric layer, so that electrons emitted by the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer.

[0059] Step S50: Form a collector electrode, which is located on the side of the substrate away from the base electrode. Electrons that enter the base electrode and meet a preset threshold are transported to the collector electrode under reverse voltage to obtain the correspondence between the thickness of the heterojunction interlayer dielectric layer and the current amplification coefficient of the collector electrode and the base electrode.

[0060] Figures 3 to 9 This is a schematic diagram showing the structural steps corresponding to the formation method of a heterojunction bipolar transistor according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 3 to 9 Specific embodiments of the present invention will be described in detail below.

[0061] Figure 3 This is a schematic diagram of the heterojunction bipolar transistor structure after forming the sidewall critical dimension control layer according to an embodiment of the present invention. Figure 3As shown, a substrate 10 is provided. In some embodiments, the substrate 10 can be a semiconductor substrate, made of any semiconductor material suitable for semiconductor devices (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate 10 can also be various composite substrates such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI). The electron mobility of the silicon-germanium layer is higher than that of pure silicon. This high electron mobility not only reduces noise, bias current, and feed power, but also increases the operating frequency. Compared to pure silicon, silicon-germanium can also achieve stable operating characteristics over a very wide temperature range. Therefore, silicon-germanium is widely used in bipolar and advanced CMOS devices. Those skilled in the art will understand that the substrate is not limited in any way, but can be selected according to the actual application. The doping type of the substrate 10 is, for example, a first doping type, such as P-type; that is, in this embodiment, the substrate 10 is a P-type substrate.

[0062] Please continue to refer to this. Figure 3 A vertically stacked buried layer 11 and a sidewall critical dimension control layer 13 are formed on the substrate 10. The buried layer 11 is doped with a second doping type, such as N-type, i.e., an N-type buried layer. The N-type buried layer (NBL) is a heavily doped N-type region formed on the silicon substrate 10 by a high-concentration ion implantation process. It is used to withstand the longitudinal electric field under high-voltage devices and prevent the devices from undergoing punch-through breakdown under high voltage. The sidewall critical dimension control layer (spacer critical) is formed before the emitter window is formed by forming precise sidewalls (spacers) on the sidewalls of the window and using them as hard masks to define the intrinsic base region window in a self-aligned manner. Shallow trench isolation structures 12 are formed on both sides of the sidewall critical dimension control layer 13 to isolate the sidewall critical dimension control layer 13 from the devices on both sides.

[0063] Figure 4 This is a schematic diagram of the heterojunction bipolar transistor structure after the base is formed according to an embodiment of the present invention. Figure 4 As shown, a base 14 is formed on the substrate 10. The base 14 covers a sidewall critical dimension control layer 13 and a shallow trench isolation structure 12. The base 14 is made of, for example, a SiGe epitaxial layer and is formed using an epitaxial growth process.

[0064] Figure 5 This is a schematic diagram of the heterojunction bipolar transistor structure after the formation of the insulating layer according to an embodiment of the present invention. Figure 5As shown, an insulating layer 15 is formed, which covers the base 14. The insulating layer 15 includes a first insulating layer 15a and a second insulating layer 15b, with the second insulating layer 15b covering the first insulating layer 15a, and the first insulating layer 15a covering the base 14. The material of the first insulating layer 15a is, for example, silicon oxide, and the material of the second insulating layer 15b is, for example, silicon nitride. The first insulating layer 15a and the second insulating layer 15b can be formed using a chemical vapor deposition process.

[0065] Figure 6 This is a schematic diagram of the heterojunction bipolar transistor structure after the opening is formed according to an embodiment of the present invention. Figure 6 As shown, a portion of the insulating layer 15 is etched to form an opening 16 that penetrates the insulating layer 15 and exposes a portion of the top surface of the base 14. The width of the opening 16 is smaller than the width of the sidewall critical dimension control layer 13. The etching process for the portion of the insulating layer 15 is, for example, a dry etching process.

[0066] Figure 7 This is a schematic diagram of the heterojunction bipolar transistor structure after forming the heterojunction interlayer dielectric layer according to an embodiment of the present invention. Figure 7 As shown, a heterojunction interlayer dielectric layer 17 is formed, which covers the base 14. The material of the heterojunction interlayer dielectric layer 17 is, for example, silicon oxide. The thickness of the heterojunction interlayer dielectric layer 17 ranges from 20 angstroms to 30 angstroms. The heterojunction interlayer dielectric layer 17 can be formed by thermal oxidation or chemical vapor deposition. If formed by thermal oxidation, the heterojunction interlayer dielectric layer 17 is formed only on the top surface of the base exposed within the opening 16. If formed by chemical vapor deposition, the heterojunction interlayer dielectric layer 17 is formed not only on the top surface of the base exposed within the opening 16, but also on the sidewalls of the opening 16 and the top surface of the second insulating layer 15b.

[0067] Figure 8 This is a schematic diagram of the heterojunction bipolar transistor structure after the emitter is formed according to an embodiment of the present invention. Figure 8As shown, an emitter 18 is formed, located on the heterojunction interlayer dielectric layer 17 and extending to the insulating layer 15. This allows electrons emitted from the emitter 18 that meet a preset threshold to tunnel through the heterojunction interlayer dielectric layer 17 into the base 14, while electrons and holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer 17. The emitter 18 is made of polycrystalline silicon and formed using a chemical vapor deposition process. Electrons meeting the preset threshold include those with low effective mass and low barrier height. The specific range of effective mass and barrier height depends on the specific requirements of the heterojunction bipolar transistor. Holes blocked by the heterojunction interlayer dielectric layer 17 from entering the base have a high effective mass or a high barrier height, thereby improving transmission efficiency.

[0068] Figure 9 This is a schematic diagram of the heterojunction bipolar transistor structure after the collector electrode is formed according to an embodiment of the present invention. Figure 9 As shown, a collector 19 is formed, located on the side of the substrate 10 away from the base 14. Electrons that enter the base 14 and meet a preset threshold are transported to the collector 19 under a reverse voltage applied to the collector, thus obtaining the correspondence between the thickness of the heterojunction interlayer dielectric layer 17 and the collector and base current amplification factors (Beta). The collector 19 is made of polycrystalline silicon and is formed using a chemical vapor deposition process. By controlling the properties of the heterojunction interlayer dielectric layer 17, the collector and base current amplification factors are precisely controlled, significantly improving their stability and ensuring stable high-frequency radio frequency performance of the heterojunction device.

[0069] Figure 10 This is a schematic diagram illustrating the relationship between the thickness of the interlayer dielectric layer and BETA in a heterojunction according to an embodiment of the present invention. Figure 10 As shown, the applicant conducted experimental research and obtained the collector and base current amplification factors (BETA) of heterojunction bipolar transistors with different thicknesses of the interlayer dielectric layer. Figure 10 In the figure, the horizontal axis represents the thickness of the heterojunction interlayer dielectric layer, in angstroms; the vertical axis represents BETA, which is the collector and base current amplification factor. Those skilled in the art can select the thickness range of the heterojunction interlayer dielectric layer according to the required collector and base current amplification factor of the heterojunction bipolar transistor. In this embodiment, the thickness range of the heterojunction interlayer dielectric layer is, for example, 20 angstroms to 30 angstroms.

[0070] In summary, the heterojunction bipolar transistor provided in this embodiment of the invention includes a base, a heterojunction interlayer dielectric layer, an emitter, and a collector. The base is located on a substrate, covered by the heterojunction interlayer dielectric layer, the emitter is located on the heterojunction interlayer dielectric layer, and the collector is located on the side of the substrate away from the base. By forming a heterojunction interlayer dielectric layer between the base and the emitter, electrons emitted from the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked from entering the base by the heterojunction interlayer dielectric layer. Electrons that meet the preset threshold and enter the base are transported to the collector when a reverse voltage is applied to the collector, thereby improving the electron transport efficiency. Furthermore, by controlling the properties of the heterojunction interlayer dielectric layer, the current amplification coefficients of the collector and base are precisely controlled, significantly improving the stability of the current amplification coefficients of the collector and base, and ensuring stable high-frequency radio frequency performance of the heterojunction device.

[0071] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A heterojunction bipolar transistor, characterized in that, include: Substrate; Base electrode, the base electrode being located on the substrate; A heterojunction interlayer dielectric layer, wherein the heterojunction interlayer dielectric layer covers the base electrode; The emitter is located on the heterojunction interlayer dielectric layer. Electrons emitted by the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer into the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer. The collector is located on the side of the substrate away from the base. Electrons that enter the base and meet a preset threshold are transported to the collector under reverse voltage, and the relationship between the thickness of the heterojunction interlayer dielectric layer and the current amplification factor of the collector and base is obtained.

2. The heterojunction bipolar transistor as described in claim 1, characterized in that, The thickness of the heterojunction interlayer dielectric layer ranges from 20 angstroms to 30 angstroms.

3. The heterojunction bipolar transistor as described in claim 1, characterized in that, The material of the interlayer dielectric layer of the heterojunction is silicon oxide.

4. The heterojunction bipolar transistor as described in claim 1, characterized in that, It also includes an insulating layer and an opening through the insulating layer, the insulating layer covering the base, and the opening exposing a portion of the top surface of the base.

5. The heterojunction bipolar transistor as described in claim 4, characterized in that, The substrate also has vertically stacked buried layers and sidewall critical dimension control layers.

6. The heterojunction bipolar transistor as described in claim 5, characterized in that, The substrate is doped with a first doping type, and the buried layer is doped with a second doping type.

7. The heterojunction bipolar transistor as described in claim 5, characterized in that, The width of the opening is less than the width of the critical dimension control layer of the sidewall.

8. A method for forming a heterojunction bipolar transistor, characterized in that, For forming a heterojunction bipolar transistor as described in any one of claims 1 to 7, comprising: Provide a substrate; A base electrode is formed, the base electrode being located on the substrate; A heterojunction interlayer dielectric layer is formed, which covers the base electrode; An emitter is formed, which is located on the heterojunction interlayer dielectric layer, so that electrons emitted by the emitter that meet a preset threshold tunnel through the heterojunction interlayer dielectric layer to enter the base, while electrons or holes that do not meet the preset threshold are blocked by the heterojunction interlayer dielectric layer. A collector is formed, which is located on the side of the substrate away from the base. Electrons that enter the base and meet a preset threshold are transported to the collector under a reverse voltage to obtain the correspondence between the thickness of the heterojunction interlayer dielectric layer and the current amplification factor of the collector and base.

9. The method for forming a heterojunction bipolar transistor as described in claim 8, characterized in that, The heterojunction interlayer dielectric layer is formed using a thermal oxidation process or a chemical vapor deposition process.

10. The method for forming a heterojunction bipolar transistor as described in claim 8, characterized in that, Between the step of forming the heterojunction interlayer dielectric layer and the step of forming the base, the following is also included: An insulating layer is formed, the insulating layer covering the base electrode; A portion of the insulating layer is etched to form an opening that penetrates the insulating layer and exposes a portion of the top surface of the base.

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