High-frequency semiconductor device with improved voltage resistance and method for manufacturing the same
By introducing additional polysilicon field plates within the unit cell trench and precisely controlling the gate polysilicon size, the problem of uneven electric field distribution in traditional shielded gate MOSFET devices is solved, thereby improving voltage withstand and frequency.
Patent Information
- Application Number
- CN202610770402.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-01
- Publication Date
- 2026-08-25
AI Technical Summary
Traditional shielded gate MOSFET devices have uneven electric field distribution under reverse bias, which leads to a decrease in device withstand voltage and an inability to increase operating frequency.
An additional polysilicon field plate is introduced within the single-cell trench, and the polysilicon field plate is formed to smooth the electric field distribution by precisely controlling the size of the gate polysilicon and the thickness of the field oxide layer.
This improved the device's withstand voltage performance, increased the operating frequency, and reduced the gate charge, achieving a dual improvement in both withstand voltage and frequency.
Smart Images
Figure CN122641055A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a high-frequency semiconductor device with improved withstand voltage and its fabrication method. Background Technology
[0002] In traditional shielded gate MOSFET devices, the polysilicon field plate within the unit cell trench is typically a single, integral structure. When the device operates under reverse bias, the electric field distribution in the Y direction (the depth direction of the unit cell trench) is concentrated in the upper part of the unit cell trench. Figure 1 The two circled locations show a phenomenon where the electric field is relatively low, such as... Figure 21 As shown in curve a, this will cause the device's withstand voltage to decrease.
[0003] In traditional shielded gate structures, the formation of gate trenches is mostly achieved by wet etching of the field oxide layer inside the single-cell trench. The size of the gate polysilicon is approximately equal to the thickness of the field oxide layer, and the thickness of the field oxide layer determines the voltage withstand capability of the device. In higher voltage devices, a thicker field oxide layer is required. Therefore, as the voltage withstand level increases, the gate charge of the device will increase significantly, making it impossible to increase the device operating frequency. Summary of the Invention
[0004] To address at least one technical problem in the prior art, embodiments of the present invention provide a high-frequency semiconductor device with improved withstand voltage and a method for fabricating the same, which can improve both the withstand voltage performance and the operating frequency of the device. To achieve the above technical objectives, the technical solution adopted by embodiments of the present invention is as follows: In a first aspect, embodiments of the present invention provide a high-frequency semiconductor device with improved withstand voltage, including a first conductivity type substrate, on which a first conductivity type epitaxial layer is disposed; the surface of the first conductivity type epitaxial layer facing away from the first conductivity type substrate is a first main surface, and the surface of the first conductivity type substrate facing away from the first conductivity type epitaxial layer is a second main surface; A single-cell trench is provided in the first conductivity type epitaxial layer; the single-cell trench is located in the active region of the device and is arranged in parallel at intervals; a second conductivity type well region and a heavily doped first conductivity type implantation region are provided from bottom to top in the first conductivity type epitaxial layer on both sides of the single-cell trench in the active region; the single-cell trench extends from the first main surface to below the second conductivity type well region. A top space is provided within a single-cell trench; a field oxide layer is provided on the inner wall below the top space within the single-cell trench; a gate oxide layer is provided on the side wall of the top space within the single-cell trench; a first polysilicon field plate is provided in the middle of the single-cell trench; a second polysilicon field plate and a third polysilicon field plate are provided on the top two sides of the first polysilicon field plate within the single-cell trench; the first polysilicon field plate, the second polysilicon field plate, and the third polysilicon field plate are all located below the top space of the single-cell trench and are isolated from each other by the field oxide layer; A first gate polysilicon and a second gate polysilicon are respectively provided on both sides of the top space within the unit cell trench; the first gate polysilicon and the second gate polysilicon are insulated from the first conductivity type implantation region and the second conductivity type well region through gate oxide layers respectively; the inner surfaces and top surfaces of the first gate polysilicon and the second gate polysilicon are covered with isolation oxide layers; in the lateral direction, a second polysilicon field plate is located between the first gate polysilicon and the first polysilicon field plate, and a third polysilicon field plate is located between the second gate polysilicon and the first polysilicon field plate; An insulating dielectric layer is provided in the top space of the first main surface and the unit cell trench; a source metal and a gate metal are provided on the insulating dielectric layer; The source metal is connected to the first polysilicon field plate in the unit cell trench through the source contact hole penetrating the insulating dielectric layer, and is also connected to the second polysilicon field plate and the third polysilicon field plate on both sides of the top of the first polysilicon field plate through the source contact hole penetrating the insulating dielectric layer, respectively. The source metal is connected to the first conductivity type injection region and the second conductivity type well region on both sides of the top of the unit cell trench through the source contact hole that penetrates the insulating dielectric layer and the first conductivity type injection region. The gate metal is connected to the first gate polysilicon and the second gate polysilicon through gate contact holes that penetrate the insulating dielectric layer, respectively. A drain metal is provided on the second main surface.
[0005] Furthermore, the widths of the first gate polysilicon and the second gate polysilicon are the same and less than half the thickness of the field oxide layer.
[0006] Furthermore, the widths of the first gate polysilicon and the second gate polysilicon are 0.1 μm to 0.3 μm.
[0007] Furthermore, the widths of the second and third polycrystalline silicon field plates are 0.1 μm to 0.4 μm.
[0008] Furthermore, the depths of the second and third polycrystalline silicon field plates are 0.5 μm to 5 μm.
[0009] Secondly, embodiments of the present invention also provide a method for fabricating a high-frequency semiconductor device with improved withstand voltage, used to fabricate the high-frequency semiconductor device with improved withstand voltage as described above, comprising the following steps: Step S1: Provide a first conductivity type substrate, and grow a first conductivity type epitaxial layer on the first conductivity type substrate; the surface of the first conductivity type epitaxial layer facing away from the first conductivity type substrate is the first main surface, and the surface of the first conductivity type substrate facing away from the first conductivity type epitaxial layer is the second main surface; Step S2: Etch the epitaxial layer of the first conductivity type to form a unit cell trench; the unit cell trenches are located in the active region of the device and are arranged in parallel at intervals; Step S3: Deposit or grow a field oxide layer in the first master surface and unit cell trench; Step S4: Deposit the first conductive polycrystalline silicon in the first main surface and the unit cell trench; Step S5: Etch the first conductive polysilicon to form a first polysilicon field plate in the unit cell trench; the top of the first polysilicon field plate is lower than the top of the unit cell trench. Step S6: CMP removes the field oxide layer on the first master surface; Step S7: Dry etch the field oxide layer at the top of the unit cell trench so that the top of the field oxide layer is approximately flush with the top of the first polysilicon field plate or higher than the top of the first polysilicon field plate by the thickness of the gate oxide layer. Step S8: A gate oxide layer is grown on the first main surface, the top space sidewall of the single-cell trench, and the top of the first polysilicon field plate. Step S9: Deposit a second conductive polysilicon in the top space of the first main surface and the unit cell trench; Step S10: Etch the second conductive polysilicon to form the first gate polysilicon intermediate and the second gate polysilicon intermediate on both sides of the top space in the single cell trench, respectively. Step S11: Selectively dry etch the first gate polysilicon intermediate and the second gate polysilicon intermediate to form the first gate polysilicon and the second gate polysilicon on both sides of the top space in the single cell trench, respectively. The widths of the first gate polysilicon and the second gate polysilicon are smaller than the widths of the first gate polysilicon intermediate and the second gate polysilicon intermediate, respectively. Step S12: Inject a second type of conductivity impurity into the first main surface and push it into a well, forming a second type of conductivity well region at the top inside the first type of conductivity epitaxial layer; Step S13: Selectively etch the field oxide layer in the unit cell trench; form a first field plate trench and a second field plate trench on the top of the field oxide layer in the unit cell trench, respectively. The first field plate trench is located between the first gate polysilicon and the first polysilicon field plate, and the second field plate trench is located between the second gate polysilicon and the first polysilicon field plate. Step S14: An isolation oxide layer is grown on the first main surface, such that the inner and top surfaces of the first gate polysilicon and the second gate polysilicon are covered with the isolation oxide layer. Step S15: Deposit third conductive polysilicon in the top space of the first main surface, the unit cell trench, the first field plate trench, and the second field plate trench. Step S16: Etch the third conductive polysilicon to form a second polysilicon field plate in the first field plate trench and a third polysilicon field plate in the second field plate trench. Step S17: Selectively implant first conductivity type impurities and anneal to form a heavily doped first conductivity type implantation region at the top of the second conductivity type well region on both sides of the active region unit cell trench; Step S18: Deposit an insulating dielectric layer in the top space of the first main surface, within the unit cell trench; Step S19: Selectively etch the insulating dielectric layer to form source contact holes and gate contact holes; Step S20: Deposit metal on the first main surface and selectively etch it to form source metal and gate metal; The source metal is connected to the first polysilicon field plate in the unit cell trench through the source contact hole penetrating the insulating dielectric layer, and is also connected to the second polysilicon field plate and the third polysilicon field plate on both sides of the top of the first polysilicon field plate through the source contact hole penetrating the insulating dielectric layer, respectively. The source metal is connected to the first conductivity type injection region and the second conductivity type well region on both sides of the top of the unit cell trench through the source contact hole that penetrates the insulating dielectric layer and the first conductivity type injection region. The gate metal is connected to the first gate polysilicon and the second gate polysilicon through gate contact holes that penetrate the insulating dielectric layer, respectively. Step S21: Deposit drain metal on the second main surface.
[0010] Furthermore, the widths of the first gate polysilicon and the second gate polysilicon are the same and less than half the thickness of the field oxide layer.
[0011] Furthermore, the widths of the first gate polysilicon and the second gate polysilicon are 0.1 μm to 0.3 μm.
[0012] Furthermore, the widths of the second and third polycrystalline silicon field plates are 0.1 μm to 0.4 μm.
[0013] Furthermore, the depths of the second and third polycrystalline silicon field plates are 0.5 μm to 5 μm.
[0014] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: 1) Introducing additional polysilicon field plates (i.e., second and third polysilicon field plates) at the top of the unit cell trench makes the electric field smoother when the device is reverse biased, thus increasing the device's withstand voltage.
[0015] 2) It can reduce the size (width) of the gate polysilicon, thereby achieving precise control of the gate charge and reducing the gate charge. This allows for the reduction of the gate charge while using a thicker field oxide layer, which can improve both the device's breakdown voltage and its operating frequency. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of a shielded gate MOSFET device in the prior art.
[0017] Figure 2 This is a schematic diagram of the growth of an epitaxial layer of the first conductivity type in an embodiment of the present invention.
[0018] Figure 3 This is a schematic diagram of etching a first conductivity type epitaxial layer to form a single-cell trench in an embodiment of the present invention.
[0019] Figure 4 This is a schematic diagram of the growth field oxide layer in an embodiment of the present invention.
[0020] Figure 5 This is a schematic diagram of the deposition of the first conductive polycrystalline silicon in an embodiment of the present invention.
[0021] Figure 6 This is a schematic diagram of etching a first conductive polysilicon to form a first polysilicon field plate in an embodiment of the present invention.
[0022] Figure 7 This is a schematic diagram of CMP removal of the field oxide layer on the first main surface in an embodiment of the present invention.
[0023] Figure 8 This is a schematic diagram of the field oxide layer at the top of the dry-etched unit cell trench in an embodiment of the present invention.
[0024] Figure 9 This is a schematic diagram of the growth of the gate oxide layer in an embodiment of the present invention.
[0025] Figure 10 This is a schematic diagram of the deposition of the second conductive polycrystalline silicon in an embodiment of the present invention.
[0026] Figure 11 This is a schematic diagram illustrating the etching process for forming the first gate polysilicon intermediate and the second gate polysilicon intermediate in an embodiment of the present invention.
[0027] Figure 12 This is a schematic diagram of selective dry etching of the first gate polysilicon intermediate and the second gate polysilicon intermediate in an embodiment of the present invention.
[0028] Figure 13 This is a schematic diagram of the formation of a second conductivity type well region in an embodiment of the present invention.
[0029] Figure 14 This is a schematic diagram illustrating the formation of the first field plate groove and the second field plate groove in an embodiment of the present invention.
[0030] Figure 15 This is a schematic diagram of the growth isolation oxide layer in an embodiment of the present invention.
[0031] Figure 16This is a schematic diagram of the deposition of the third conductive polycrystalline silicon in an embodiment of the present invention.
[0032] Figure 17 This is a schematic diagram of etching a third conductive polysilicon to form a second polysilicon field plate and a third polysilicon field plate in an embodiment of the present invention.
[0033] Figure 18 This is a schematic diagram of the formation of a heavily doped first conductivity type implantation region in an embodiment of the present invention.
[0034] Figure 19 This is a schematic diagram of the deposited insulating dielectric layer in an embodiment of the present invention.
[0035] Figure 20 This is a schematic diagram illustrating the etching process used in this embodiment of the invention to form source contact holes and deposit and selectively etch source metal.
[0036] Figure 21 This is a comparison diagram of the electric fields of the embodiments of the present invention and the prior art. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0038] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0039] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.
[0040] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0041] In the following embodiments, the first conductivity type is N-type and the second conductivity type is P-type; one of the high-frequency semiconductor devices with improved withstand voltage in the following embodiments is a shielded gate MOSFET device.
[0042] like Figure 20 As shown, Embodiment 1 of the present invention proposes a high-frequency semiconductor device with improved withstand voltage, including a first conductivity type substrate 1, on which a first conductivity type epitaxial layer 2 is provided; the surface of the first conductivity type epitaxial layer 2 facing away from the first conductivity type substrate 1 is a first main surface, and the surface of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2 is a second main surface. A single-cell trench 3 is provided in the first conductivity type epitaxial layer 2; the single-cell trench 3 is located in the active region of the device and is arranged in parallel at intervals; a second conductivity type well region 8 and a heavily doped first conductivity type implantation region 11 are provided from bottom to top in the first conductivity type epitaxial layer 2 on both sides of the single-cell trench 3 in the active region; the single-cell trench 3 extends from the first main surface to below the second conductivity type well region 8. A top space is provided within a single-cell trench 3; a field oxide layer 4 is provided on the inner wall (including sidewalls and bottom wall) below the top space within the single-cell trench 3; a gate oxide layer 6 is provided on the sidewall of the top space within the single-cell trench 3; a first polysilicon field plate 501 is provided in the middle of the single-cell trench 3; a second polysilicon field plate 1001 and a third polysilicon field plate 1002 are provided on both sides of the top of the first polysilicon field plate 501 in the single-cell trench 3; the first polysilicon field plate 501, the second polysilicon field plate 1001 and the third polysilicon field plate 1002 are all located below the top space of the single-cell trench 3 and are isolated from each other by the field oxide layer 4; A first gate polysilicon 703 and a second gate polysilicon 704 are respectively provided on both sides of the top space within the unit cell trench 3; the first gate polysilicon 703 and the second gate polysilicon 704 are insulated from the first conductivity type implantation region 11 and the second conductivity type well region 8 through the gate oxide layer 6 respectively; the inner surface and top surface of the first gate polysilicon 703 and the second gate polysilicon 704 are covered with an isolation oxide layer 9; in the lateral direction, the second polysilicon field plate 1001 is located between the first gate polysilicon 703 and the first polysilicon field plate 501, and the third polysilicon field plate 1002 is located between the second gate polysilicon 704 and the first polysilicon field plate 501; An insulating dielectric layer 12 is provided in the top space of the first main surface and the unit cell trench 3; a source metal 14 and a gate metal are provided on the insulating dielectric layer 12; The source metal 14 is connected to the first polysilicon field plate 501 in the unit cell trench 3 through the source contact hole 1301 penetrating the insulating dielectric layer 12, and is also connected to the second polysilicon field plate 1001 and the third polysilicon field plate 1002 on both sides of the top of the first polysilicon field plate 501 through the source contact hole 1301 penetrating the insulating dielectric layer 12, respectively. The source metal 14 is connected to the first conductive type injection region 11 and the second conductive type well region 8 on both sides of the top of the unit cell trench 3 through the source contact hole 1301 penetrating the insulating dielectric layer 12 and the first conductive type injection region 11. The gate metal is connected to the first gate polysilicon 703 and the second gate polysilicon 704 through gate contact holes penetrating the insulating dielectric layer 12, respectively. A drain metal is provided on the second main surface.
[0043] Furthermore, the widths of the first gate polysilicon 703 and the second gate polysilicon 704 are the same and less than half the thickness of the field oxide layer 4.
[0044] Furthermore, the widths of the first gate polysilicon 703 and the second gate polysilicon 704 are preferably 0.1 μm to 0.3 μm, for example, 0.1 μm, 0.2 μm, or 0.3 μm.
[0045] Furthermore, the widths of the second polysilicon field plate 1001 and the third polysilicon field plate 1002 are 0.1 μm to 0.4 μm.
[0046] Furthermore, the depths of the second polysilicon field plate 1001 and the third polysilicon field plate 1002 are 0.5 μm to 5 μm.
[0047] This application introduces additional polysilicon field plates (i.e., a second polysilicon field plate 1001 and a third polysilicon field plate 1002) at the top of the unit cell trench. The second polysilicon field plate 1001 and the third polysilicon field plate 1002 are at zero potential during operation, and their electric field tends to smooth out when the device is reverse biased. Figure 21 As shown in curve b, this increases the device's withstand voltage.
[0048] Embodiment 2 of the present invention proposes a method for fabricating a high-frequency semiconductor device with improved withstand voltage, comprising the following steps: Step S1, as follows Figure 2 As shown, a first conductivity type substrate 1 is provided, and a first conductivity type epitaxial layer 2 is grown on the first conductivity type substrate 1; the surface of the first conductivity type epitaxial layer 2 facing away from the first conductivity type substrate 1 is a first main surface, and the surface of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2 is a second main surface; Step S2, as follows Figure 3As shown, the first conductivity type epitaxial layer 2 is etched to form a unit cell trench 3; the unit cell trench 3 is located in the active region of the device and is arranged in parallel at intervals; Step S3, as follows Figure 4 As shown, a field oxide layer 4 is deposited or grown in the first main surface, unit cell groove 3; Step S4, as follows Figure 5 As shown, a first conductive polycrystalline silicon 5 is deposited in the first main surface, the unit cell trench 3; Step S5, as follows Figure 6 As shown, the first conductive polysilicon 5 is etched to form a first polysilicon field plate 501 in the unit cell trench 3; the top of the first polysilicon field plate 501 is lower than the top of the unit cell trench 3. In this step, the etching of the first conductive polysilicon 5 is performed using a conventional etching method; Step S6, as follows Figure 7 As shown, CMP removes the field oxide layer 4 on the first master surface; Step S7, as follows Figure 8 As shown, the field oxide layer 4 at the top of the unit cell trench 3 is dry etched so that the top of the field oxide layer 4 is approximately flush with the top of the first polysilicon field plate 501 or higher than the top of the first polysilicon field plate 501 by the thickness of a gate oxide layer. Step S8, as follows Figure 9 As shown, a gate oxide layer 6 is grown on the first main surface, the top space sidewall of the unit cell trench 3, and the top of the first polysilicon field plate 501. It should be noted that when the gate oxide layer 6 is formed by growth, it is only formed on the surface that is in contact with the epitaxial layer 2 of the first conductivity type and the conductive polysilicon. Step S9, as follows Figure 10 As shown, a second conductive polysilicon 7 is deposited in the top space of the first main surface, within the unit cell trench 3; Step S10, as follows Figure 11 As shown, the second conductive polysilicon 7 is etched to form a first gate polysilicon intermediate 701 and a second gate polysilicon intermediate 702 on both sides of the top space in the single cell trench 3. In this step, the etching of the second conductive polysilicon 7 is performed using a conventional etching method; Step S11, as follows Figure 12 As shown, selective dry etching is used to form the first gate polysilicon intermediate 701 and the second gate polysilicon intermediate 702, and the first gate polysilicon 703 and the second gate polysilicon 704 are formed on both sides of the top space in the unit cell trench 3, respectively. The widths of the first gate polysilicon 703 and the second gate polysilicon 704 are smaller than the widths of the first gate polysilicon intermediate 701 and the second gate polysilicon intermediate 702, respectively. The widths of the first gate polysilicon 703 and the second gate polysilicon 704 are the same and less than half the thickness of the field oxide layer 4. The widths of the first gate polysilicon 703 and the second gate polysilicon 704 are preferably 0.1 μm to 0.3 μm; This application reduces the size (width) of the gate polysilicon through an additional dry etching step, and can precisely control the size (width) of the gate polysilicon to achieve precise control of the gate charge, thereby reducing the gate charge. This allows for the reduction of the gate charge while using a thicker field oxide layer, and can improve both the device's breakdown voltage and its operating frequency. Step S12, as follows Figure 13 As shown, a second conductivity type impurity is injected into the first main surface and pushed into a well, forming a second conductivity type well region 8 at the top inside the first conductivity type epitaxial layer 2; Step S13, as follows Figure 14 As shown, the field oxide layer 4 in the unit cell trench 3 is selectively etched; a first field plate trench 401 and a second field plate trench 402 are formed on the top of the field oxide layer 4 in the unit cell trench 3, respectively. The first field plate trench 401 is located between the first gate polysilicon 703 and the first polysilicon field plate 501, and the second field plate trench 402 is located between the second gate polysilicon 704 and the first polysilicon field plate 501. Step S14, as follows Figure 15 As shown, an isolation oxide layer 9 is grown on the first main surface, such that the inner surface and top surface of the first gate polysilicon 703 and the second gate polysilicon 704 are covered by the isolation oxide layer 9. In this step, a very thin isolation oxide layer is also formed on the gate oxide layer 6 of the first main surface, which is not shown in the figure. Step S15, as follows Figure 16 As shown, a third conductive polysilicon 10 is deposited in the top space of the first main surface, the unit cell trench 3, the first field plate trench 401, and the second field plate trench 402. Step S16, as follows Figure 17 As shown, the third conductive polysilicon 10 is etched, a second polysilicon field plate 1001 is formed in the first field plate trench 401, and a third polysilicon field plate 1002 is formed in the second field plate trench 402. In this step, the etching of the third conductive polysilicon 10 is performed using a conventional etching method; Furthermore, the widths of the second polysilicon field plate 1001 and the third polysilicon field plate 1002 are 0.1 μm to 0.4 μm; Furthermore, the depths of the second polysilicon field plate 1001 and the third polysilicon field plate 1002 are 0.5 μm to 5 μm; Step S17, as follows Figure 18As shown, selective implantation of first conductivity type impurities followed by annealing forms a heavily doped first conductivity type implantation region 11 at the top of the second conductivity type well region 8 on both sides of the active region unit cell trench 3. Step S18, as follows Figure 19 As shown, an insulating dielectric layer 12 is deposited in the top space of the first main surface, the unit cell trench 3; Step S19, as follows Figure 20 As shown, the insulating dielectric layer 12 is selectively etched to form the source contact hole 1301 and the gate contact hole; The gate contact hole is not shown in the figure; this is hereby noted. Step S20, as follows Figure 20 As shown, metal is deposited on the first main surface and selectively etched to form source metal 14 and gate metal; The source metal 14 is connected to the first polysilicon field plate 501 in the unit cell trench 3 through the source contact hole 1301 penetrating the insulating dielectric layer 12, and is also connected to the second polysilicon field plate 1001 and the third polysilicon field plate 1002 on both sides of the top of the first polysilicon field plate 501 through the source contact hole 1301 penetrating the insulating dielectric layer 12, respectively. The source metal 14 is connected to the first conductive type injection region 11 and the second conductive type well region 8 on both sides of the top of the unit cell trench 3 through the source contact hole 1301 penetrating the insulating dielectric layer 12 and the first conductive type injection region 11. The gate metal is connected to the first gate polysilicon 703 and the second gate polysilicon 704 through gate contact holes penetrating the insulating dielectric layer 12, respectively. The connection method between gate metal and gate polysilicon is relatively mature. For example, a gate lead-out trench is set on the periphery of the single cell trench, and a gate polysilicon is also set in the gate lead-out trench. The gate polysilicon in the gate lead-out trench is connected to the gate polysilicon in the single cell trench. The gate metal is connected to the gate polysilicon in the gate lead-out trench through the gate contact hole that penetrates the insulating dielectric layer, thereby connecting the gate polysilicon in the single cell trench. Step S21: Deposit drain metal on the second main surface; The drain metal is not shown in the diagram.
[0049] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A high-frequency semiconductor device with improved withstand voltage, comprising a first conductivity type substrate (1), wherein a first conductivity type epitaxial layer (2) is disposed on the first conductivity type substrate (1); the surface of the first conductivity type epitaxial layer (2) facing away from the first conductivity type substrate (1) is a first main surface, and the surface of the first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is a second main surface; characterized in that, A single-cell trench (3) is provided in the first conductivity type epitaxial layer (2); the single-cell trench (3) is located in the active region of the device and is arranged in parallel at intervals; a second conductivity type well region (8) and a heavily doped first conductivity type implantation region (11) are provided from bottom to top in the first conductivity type epitaxial layer (2) on both sides of the single-cell trench (3) in the active region; the single-cell trench (3) extends from the first main surface into the second conductivity type well region (8); A top space is provided in the unit cell trench (3); a field oxide layer (4) is provided on the inner wall below the top space in the unit cell trench (3); a gate oxide layer (6) is provided on the side wall of the top space in the unit cell trench (3); a first polysilicon field plate (501) is provided in the middle of the unit cell trench (3); a second polysilicon field plate (1001) and a third polysilicon field plate (1002) are provided on the top two sides of the first polysilicon field plate (501) in the unit cell trench (3); the first polysilicon field plate (501), the second polysilicon field plate (1001) and the third polysilicon field plate (1002) are all located below the top space of the unit cell trench (3) and are isolated from each other by the field oxide layer (4); A first gate polysilicon (703) and a second gate polysilicon (704) are respectively provided on both sides of the top space inside the unit cell trench (3); the first gate polysilicon (703) and the second gate polysilicon (704) are respectively insulated from the first conductivity type implantation region (11) and the second conductivity type well region (8) through the gate oxide layer (6); the inner surface and top surface of the first gate polysilicon (703) and the second gate polysilicon (704) are covered with an isolation oxide layer (9); in the lateral direction, the second polysilicon field plate (1001) is located between the first gate polysilicon (703) and the first polysilicon field plate (501), and the third polysilicon field plate (1002) is located between the second gate polysilicon (704) and the first polysilicon field plate (501); An insulating dielectric layer (12) is provided in the top space of the first main surface and the unit cell trench (3); a source metal (14) and a gate metal are provided on the insulating dielectric layer (12); The source metal (14) is connected to the first polysilicon field plate (501) in the unit cell trench (3) through the source contact hole (1301) penetrating the insulating dielectric layer (12), and is also connected to the second polysilicon field plate (1001) and the third polysilicon field plate (1002) on both sides of the top of the first polysilicon field plate (501) through the source contact hole (1301) penetrating the insulating dielectric layer (12); The source metal (14) is connected to the first conductive type injection region (11) and the second conductive type well region (8) on both sides of the top of the unit cell trench (3) through the source contact hole (1301) that penetrates the insulating dielectric layer (12) and the first conductive type injection region (11); The gate metal is connected to the first gate polysilicon (703) and the second gate polysilicon (704) through gate contact holes penetrating the insulating dielectric layer (12); A drain metal is provided on the second main surface.
2. The high-frequency semiconductor device with improved withstand voltage as described in claim 1, characterized in that, The first gate polysilicon (703) and the second gate polysilicon (704) have the same width and are less than half the thickness of the field oxide layer (4).
3. The high-frequency semiconductor device with improved withstand voltage as described in claim 1, characterized in that, The widths of the first gate polysilicon (703) and the second gate polysilicon (704) are 0.1 μm to 0.3 μm.
4. The high-frequency semiconductor device with improved withstand voltage as described in claim 1, characterized in that, The widths of the second polycrystalline silicon field plate (1001) and the third polycrystalline silicon field plate (1002) are 0.1 μm to 0.4 μm.
5. The high-frequency semiconductor device with improved withstand voltage as described in claim 1, characterized in that, The depths of the second polycrystalline silicon field plate (1001) and the third polycrystalline silicon field plate (1002) are 0.5 μm to 5 μm.
6. A method for fabricating a high-frequency semiconductor device with improved withstand voltage, used to fabricate a high-frequency semiconductor device with improved withstand voltage as described in any one of claims 1 to 5, characterized in that, Includes the following steps: Step S1: Provide a first conductivity type substrate (1), and grow a first conductivity type epitaxial layer (2) on the first conductivity type substrate (1); the surface of the first conductivity type epitaxial layer (2) facing away from the first conductivity type substrate (1) is the first main surface, and the surface of the first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is the second main surface; Step S2, etching the first conductivity type epitaxial layer (2) to form a unit cell trench (3); the unit cell trench (3) is located in the active region of the device and is arranged in parallel at intervals; Step S3: Deposit or grow a field oxide layer (4) in the first main surface, unit cell trench (3); Step S4: Deposit first conductive polysilicon (5) in the first main surface, unit cell trench (3); Step S5, etch the first conductive polysilicon (5) to form a first polysilicon field plate (501) in the unit cell trench (3); the top of the first polysilicon field plate (501) is lower than the top of the unit cell trench (3); Step S6, CMP removes the field oxide layer (4) on the first master surface; Step S7, dry etching the field oxide layer (4) at the top of the unit cell trench (3) so that the top of the field oxide layer (4) is approximately flush with the top of the first polysilicon field plate (501) or higher than the top of the first polysilicon field plate (501) by the thickness of a gate oxide layer. Step S8: A gate oxide layer (6) is grown on the first main surface, the top space sidewall of the unit cell trench (3) and the top of the first polysilicon field plate (501); Step S9: Deposit a second conductive polysilicon (7) in the top space of the first main surface, unit cell trench (3); Step S10: Etch the second conductive polysilicon (7) to form the first gate polysilicon intermediate (701) and the second gate polysilicon intermediate (702) on both sides of the top space in the unit cell trench (3); Step S11: Selectively dry etch the first gate polysilicon intermediate (701) and the second gate polysilicon intermediate (702) to form the first gate polysilicon (703) and the second gate polysilicon (704) on both sides of the top space in the unit cell trench (3). The widths of the first gate polysilicon (703) and the second gate polysilicon (704) are smaller than the widths of the first gate polysilicon intermediate (701) and the second gate polysilicon intermediate (702), respectively. Step S12: Inject a second type of conductivity impurity into the first main surface and push it into a well, forming a second type of conductivity well region (8) at the top inside the first type of conductivity epitaxial layer (2); Step S13: Selectively etch the field oxide layer (4) in the unit cell trench (3); form a first field plate trench (401) and a second field plate trench (402) on the top of the field oxide layer (4) in the unit cell trench (3); The first field plate trench (401) is located between the first gate polysilicon (703) and the first polysilicon field plate (501), and the second field plate trench (402) is located between the second gate polysilicon (704) and the first polysilicon field plate (501); Step S14: An isolation oxide layer (9) is grown on the first main surface, so that the inner surface and top surface of the first gate polysilicon (703) and the second gate polysilicon (704) are covered with the isolation oxide layer (9); Step S15: Deposit third conductive polysilicon (10) in the top space of the first main surface, the unit cell trench (3), and the first field plate trench (401) and the second field plate trench (402); Step S16: Etch the third conductive polysilicon (10), form the second polysilicon field plate (1001) in the first field plate trench (401), and form the third polysilicon field plate (1002) in the second field plate trench (402). Step S17: Selectively implant first conductivity type impurities and anneal to form a heavily doped first conductivity type implantation region (11) at the top of the second conductivity type well region (8) on both sides of the active region unit cell trench (3); Step S18: Deposit an insulating dielectric layer (12) in the top space of the first main surface, unit cell trench (3); Step S19: Selectively etch the insulating dielectric layer (12) to form the source contact hole (1301) and the gate contact hole; Step S20: Deposit metal on the first main surface and selectively etch it to form source metal (14) and gate metal; The source metal (14) is connected to the first polysilicon field plate (501) in the unit cell trench (3) through the source contact hole (1301) penetrating the insulating dielectric layer (12), and is also connected to the second polysilicon field plate (1001) and the third polysilicon field plate (1002) on both sides of the top of the first polysilicon field plate (501) through the source contact hole (1301) penetrating the insulating dielectric layer (12); The source metal (14) is connected to the first conductive type injection region (11) and the second conductive type well region (8) on both sides of the top of the unit cell trench (3) through the source contact hole (1301) that penetrates the insulating dielectric layer (12) and the first conductive type injection region (11); The gate metal is connected to the first gate polysilicon (703) and the second gate polysilicon (704) through gate contact holes penetrating the insulating dielectric layer (12); Step S21: Deposit drain metal on the second main surface.
7. The method for fabricating a high-frequency semiconductor device with improved withstand voltage as described in claim 6, characterized in that, The first gate polysilicon (703) and the second gate polysilicon (704) have the same width and are less than half the thickness of the field oxide layer (4).
8. The method for fabricating a high-frequency semiconductor device with improved withstand voltage as described in claim 6, characterized in that, The widths of the first gate polysilicon (703) and the second gate polysilicon (704) are 0.1 μm to 0.3 μm.
9. The method for fabricating a high-frequency semiconductor device with improved withstand voltage as described in claim 6, characterized in that, The widths of the second polycrystalline silicon field plate (1001) and the third polycrystalline silicon field plate (1002) are 0.1 μm to 0.4 μm.
10. The method for fabricating a high-frequency semiconductor device with improved withstand voltage as described in claim 6, characterized in that, The depths of the second polycrystalline silicon field plate (1001) and the third polycrystalline silicon field plate (1002) are 0.5 μm to 5 μm.