Silicon heterojunction solar cell with less indium and less silver

Abstract

The application discloses a kind of little indium little silver silicon heterojunction solar cell, comprising: silicon substrate, intrinsic hydrogenated amorphous silicon a-Si:H (i) sequentially arranged in substrate front surface from inside to outside, phosphorus-doped nanometer silicon oxide film nc-SiO x :H (n), front transparent conductive oxide three-layer, reflection-reducing layer SiN x :H and front electrode, intrinsic hydrogenated amorphous silicon a-Si:H (i) sequentially arranged in substrate back surface from inside to outside, boron-doped nanometer silicon film nc-Si:H (p), back transparent conductive layer AZO and back electrode.The application overcomes the optical loss of ultra-thin ITO and reduces the use of indium, through the design of light-electricity cooperation, while significantly reducing the consumption of rare metal indium and noble metal silver, high conversion efficiency is maintained.

Description

Technical Field

[0001] This invention relates to a technology in the field of solar photovoltaic cells, specifically a low-indium, low-silver silicon heterojunction solar cell. Background Technology

[0002] Silicon heterojunction (SHJ) solar cells have attracted widespread attention due to their high efficiency potential, but they face constraints due to the scarcity of indium and silver. Existing technologies attempt to replace tin-doped indium oxide (ITO) with aluminum-doped zinc oxide (AZO), but its poor interface passivation and high resistivity result in a fill factor (FF) of less than 80%. Typical tandem transparent conductive oxide (TCO) structures (such as ITO / AZO / ITO) cannot overcome the optical losses associated with ITO below the critical thickness (<12 nm). Copper electrodes suffer from poor conductivity and copper diffusion contamination. Overcoming the critical thickness of ITO and achieving a reduction in precious metal content are key challenges for industrialization. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes a low-indium, low-silver silicon heterojunction solar cell that overcomes the optical losses of ultrathin ITO and reduces the amount of indium used. Through photoelectric synergistic design, it maintains high conversion efficiency while significantly reducing the consumption of rare metal indium and precious metal silver.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a low-indium, low-silver silicon heterojunction solar cell, comprising: a crystalline silicon substrate, intrinsic hydrogenated amorphous silicon a-Si:H(i) and a phosphorus-doped nano-silicon oxide thin film nc-SiO2 sequentially disposed on the front surface of the substrate from the inside out. x H(n), front transparent conductive oxide triple layer, antireflection layer SiN x The intrinsic hydrogenated amorphous silicon a-Si:H(i), boron-doped nano-silicon thin film nc-Si:H(p), back transparent conductive layer AZO and back electrode are sequentially disposed on the back surface of the substrate from the inside to the outside.

[0006] The crystalline silicon substrate is n-type crystalline silicon c-Si(n) with a thickness of 60-150 nm, and its surface is prepared with a pyramidal textured surface structure with a size of 0.5-2 μm.

[0007] The thickness of the intrinsic hydrogenated amorphous silicon a-Si:H(i) disposed on the front surface and the back surface of the substrate is 3-10 nm, and the thickness of both is the same.

[0008] The phosphorus-doped nano-silicon oxide thin film nc-SiOx:H(n) has a thickness of 10-20 nm and a phosphorus atom doping concentration of 1×10⁻⁶. 19 / cm 3 -2×1020 / cm 3 .

[0009] The boron-doped nano-silicon thin film nc-Si:H(p) has a thickness of 10-20 nm and a boron atom doping concentration of 5 × 10⁻⁶. 18 / cm 3 -1×10 20 / cm 3 .

[0010] The total thickness of the aforementioned transparent conductive oxide triple layer is 60-80 nm, specifically comprising: an ITO seed layer for optimizing interfacial carrier transport and stabilizing the interface, an AZO intermediate layer for providing bulk conductivity, and a top SiN layer. x The H anti-reflective layer forms an optically synergistic ITO surface layer.

[0011] The deposition conditions for the ITO surface layer should be: magnetron sputtering PVD deposition with a power density of 3.0-4.5 W / cm³. 2 The oxygen concentration is 2.4-3.0% (Ar and O2 mixture), which serves to ensure lateral conductivity and adjust the optical constant to maximize overall transmittance and minimize resistance loss.

[0012] The deposition conditions for the ITO seed layer should be: magnetron sputtering PVD deposition with a power density of 2.0-3.0 W / cm³. 2 The oxygen concentration is 1.8-2.4% (Ar and O2 mixture), which serves to protect the underlying phosphorus-doped nano-silicon oxide film and optimize interfacial carrier transport during sputtering.

[0013] The ITO surface layer and the ITO seed layer have the same thickness, both ranging from 5 to 35 nm.

[0014] The thickness of the AZO layer is 70-10 nm.

[0015] The thickness of the back transparent conductive layer AZO is 70 nm.

[0016] Both the front and back electrodes are silver-coated copper metal electrodes with a linewidth of 25 μm and a copper content of 80%.

[0017] The silver-coated copper metal electrode is preferably prepared by screen printing.

[0018] The antireflection layer SiN x The thickness of H is 80-120nm, used to compensate for optical defects caused by ultrathin ITO layers (<12nm)—especially when sufficient antireflection is not provided in the short-wavelength range (300-500nm), while the antireflection layer SiN... xHydrogen diffusion in H helps passivate deep defects in ITO and activate Sn dopants, thereby increasing carrier concentration. This process occurs after screen printing the electrodes and curing.

[0019] This invention relates to a method for fabricating the above-mentioned low-indium, low-silver silicon heterojunction solar cell, comprising:

[0020] Step 1: Cleaning the flocking process, specifically including:

[0021] 1.1 Select n-type single crystal silicon wafers with resistivity between 0.5-20 Ω·cm and thickness between 60-150 μm as substrates, and remove the wire-cut damage layer on the substrate surface with NaOH solution;

[0022] 1.2 The substrate obtained in step 1.1 is etched with KOH alkaline solution to form a pyramidal textured surface with a height of 0.5-2 μm on the front and back surfaces of the substrate.

[0023] Step 2, depositing intrinsic hydrogenated amorphous silicon a-Si:H(i), specifically includes: placing the substrate obtained in step 1.2 into a PECVD device, introducing SiH4 and H2 gases, and depositing intrinsic hydrogenated amorphous silicon a-Si:H(i) on the front and back surfaces of the substrate.

[0024] The deposition of intrinsic hydrogenated amorphous silicon a-Si:H(i) involves a process pressure of 50-200 Pa, a substrate temperature of 150-250 °C, and a gas flow ratio of SiH4:H2 = 0.01-0.05.

[0025] The thickness of the intrinsic hydrogenated amorphous silicon a-Si:H(i) on both the front and back surfaces is 3-10 nm, and the thicknesses are the same.

[0026] Step 3: Deposit phosphorus-doped nano-silicon oxide thin film nc-SiO x H(n), specifically includes: placing the substrate obtained in step 2 into a PECVD apparatus, introducing SiH4, PH3 and H2 gases, and simultaneously introducing CO2 gas, to deposit a phosphorus-doped nano-silicon oxide thin film nc-SiO on the front surface of the substrate. x :H(n).

[0027] The deposited phosphorus-doped nano-silicon oxide thin film nc-SiO x The process pressure is 50-200 Pa, the substrate temperature is 150-250 ℃, and the gas flow ratio is SiH4:H2=0.01-0.05, PH3:H2=0.005-0.01, CO2:H2=0.01-0.1.

[0028] The phosphorus-doped nano-silicon oxide thin film nc-SiO xH(n) has a thickness of 10-20 nm and a phosphorus doping concentration of 1 × 10⁻⁶. 19 / cm 3 -2×10 20 / cm 3 .

[0029] Step 4: Deposit boron-doped nano-silicon thin film nc-Si:H(p), specifically including: flipping the substrate obtained in step 3, placing it in a PECVD device, introducing SiH4, B2H6 and H2 gases, and depositing boron-doped nano-silicon thin film nc-Si:H(p) on the back surface of the substrate.

[0030] The process pressure for depositing boron-doped nano-silicon thin films nc-Si:H(p) is 50-200 Pa, the substrate temperature is 150-250 °C, and the gas flow ratio is SiH4:H2=0.01-0.05, B2H6:H2=0.005-0.01.

[0031] Step 5: Deposition of a pre-deposited transparent conductive oxide triple layer, specifically including:

[0032] 5.1 Place the substrate obtained in step 4 into a PVD apparatus, attach an ITO target, and apply the PVD at a power density of 2.0-3.0 W / cm². 2 An oxygen concentration of 1.8-2.4% (Ar and O2 mixture) is used to deposit an ITO seed layer.

[0033] 5.2 Place the substrate obtained in step 5.1 into a magnetron sputtering PVD apparatus, attach an AZO target, and perform sputtering at a power density of 2.0-4.0 W / cm². 2 An oxygen concentration of 1.8-2.4% (Ar and O2 mixture) was used to deposit an AZO intermediate layer.

[0034] 5.3 Place the substrate obtained in step 5.2 into a PVD apparatus, attach an ITO target, and apply the PVD at a power density of 3.0-4.5 W / cm². 2 An oxygen concentration of 2.4-3.0% (Ar and O2 mixture) is used to deposit an ITO surface layer.

[0035] Step 6: Deposit a transparent conductive layer (AZO), specifically including: flipping the substrate obtained in step 5.3, placing it in a PVD apparatus, connecting the AZO target, and depositing the AZO at a power density of 2.0-4.0 W / cm². 2 An oxygen concentration of 1.8-2.4% (Ar and O2 mixture) is used to deposit a transparent conductive layer AZO.

[0036] Step 7: Screen printing silver-coated copper electrodes, specifically including: screen printing grid-shaped silver-coated copper paste on the front and back surfaces of the silicon wafer obtained in step 6, and then curing it to form silver-coated copper electrodes.

[0037] The copper content of the silver-coated copper paste is 10-80%, and the curing temperature is 150-250℃.

[0038] Step 8: Deposit SiN antireflection layer x Specifically, this includes: placing the silicon wafer obtained in step 7 into a PECVD environment, introducing SiH4 and NH3 gases, and depositing SiN on the front surface. x :H.

[0039] The deposited antireflective layer SiN x The deposition temperature of SiH4 is 150-300℃, and the gas flow ratio is SiH4:NH3=0.1-0.2.

[0040] Technical effect

[0041] This invention utilizes an ultrathin ITO layer in a front transparent conductive oxide triple-layer structure (ITO / AZO / ITO) and a back transparent conductive layer (AZO) in a silicon heterojunction solar cell, while simultaneously employing an anti-reflection layer (SiN). x The invention compensates for the reduced anti-reflection capability of the ultrathin ITO layer and passivates deep defects in ITO. Compared with conventional heterojunction cells, this invention achieves a significant reduction of more than 90% in the amount of indium and 80% in the amount of silver used in silicon heterojunction cells while maintaining the performance of silicon heterojunction cells. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the structure of the present invention;

[0043] In the figure: 1 is an n-type silicon wafer; 2 is the front surface intrinsic hydrogenated amorphous silicon a-Si:H(i); 3 is a phosphorus-doped nano-silicon oxide thin film nc-SiOx:H(n); 4 is the ITO seed layer in the front transparent conductive oxide tri-layer ITO / AZO / ITO; 5 is the AZO intermediate layer in the front transparent conductive oxide tri-layer ITO / AZO / ITO; 6 is the ITO surface layer in the front transparent conductive oxide tri-layer ITO / AZO / ITO; 7 is the anti-reflection layer SiN. x H and 8 are intrinsic hydrogenated amorphous silicon a-Si:H(i) on the back surface, 9 is boron-doped nano-silicon thin film nc-Si:H(p), 10 is the back transparent conductive layer AZO, 11 is the front electrode, and 12 is the back electrode.

[0044] Figure 2 This is a flowchart of an implementation example;

[0045] Figure 3 The following is a schematic diagram of the simulated IV characteristic curve and performance parameters for an example. Detailed Implementation

[0046] like Figure 2The image shows a method for fabricating a low-indium, low-silver silicon heterojunction solar cell according to this embodiment, comprising:

[0047] Step 1: Select a 135μm thick n-type single crystal silicon as a substrate, and clean and texturize it to form a pyramid textured surface of about 1μm in size;

[0048] Step 2: The front and back surfaces are 6 nm intrinsic hydrogenated amorphous silicon: the front surface is a 20 nm phosphorus-doped nano-silicon oxide film with a phosphorus atom concentration of approximately 1 × 10⁻⁶. 20 / cm 3 The back surface is a 20nm boron-doped silicon nanofilm with a boron atom concentration of approximately 1×10⁻⁶. 19 / cm 3 ;

[0049] Step 3: Seed layer in the pre-deposition transparent conductive oxide triple layer, i.e., ITO, with a mobility of 40 cm⁻¹. 2 / Vs, carrier concentration 2.4×10 20 / cm 3 The thickness is 5nm;

[0050] Step 4: Deposit the intermediate layer of the transparent conductive stack before surface deposition, namely AZO, with a mobility of 10 cm⁻¹. 2 / Vs, carrier concentration 5.7×10 20 / cm 3 The thickness is 50nm;

[0051] Step 5: Deposit the surface layer of the transparent conductive stack before deposition, i.e., ITO, with a mobility of 160 cm⁻¹. 2 / Vs, carrier concentration 1.3×10 20 / cm 3 The thickness is 5nm;

[0052] Step 6: Deposit a transparent conductive layer, AZO, on the back surface with a mobility of 10 cm⁻¹. 2 / Vs, carrier concentration 5.7×10 20 / cm 3 The thickness is 70nm;

[0053] Step 7: The front and back surfaces of the screen printing are grid-shaped silver-coated copper metal electrodes, with copper accounting for 80% of the silver-coated copper and the electrode line width being 25μm;

[0054] Step 8: Deposit the antireflection layer on the pre-deposited surface, i.e., SiN. x :H, with a thickness of 110nm.

[0055] like Figure 1As shown, this embodiment relates to a low-indium, low-silver silicon heterojunction solar cell, comprising: a 5nm ITO / 50nm AZO / 5nm ITO and 110nm SiN triple-layer structure with transparent conductive oxide on the front surface of the substrate. x :H anti-reflective layer and silver-plated copper metal electrodes on the front and back surfaces.

[0056] Verified by Sentaurus TCAD simulation, the efficiency of the indium- and silver-free silicon heterojunction solar cell of this invention can reach 26.76% (open-circuit voltage V). oc =754.1mV, short-circuit current density J sc =42mA / cm², fill factor FF =84.49%). Its IV curve and performance parameters are as follows: Figure 3 As shown. In this embodiment, the total ITO thickness of the low-indium, low-silver silicon heterojunction solar cell is 10 nm. Compared with the conventional silicon heterojunction solar cell ITO scheme (70 nm on the front and 70 nm on the back), it achieves a 92.8% (1-10 / 140) reduction in indium usage and an 80% reduction in silver usage (compared to pure silver electrodes). The described silicon heterojunction solar cell meets the requirements of low indium and low silver usage while maintaining high conversion efficiency.

[0057] Compared with existing technologies, this invention utilizes a TCO stack (ITO ultrathin transport window / AZO conductive body / SiN) x The integration of optical optimization and hydrogen passivation with engineered silver-clad copper electrodes achieves stable ohmic transport with low contact resistance and low light-shielding loss. AZO as the host layer effectively reduces indium usage, while the silver-clad copper electrodes effectively reduce silver consumption. This provides a comprehensive technical solution for the industrialization of high-efficiency, low-cost silicon heterojunction solar cells, balancing the reduction of rare metal usage with performance optimization.

[0058] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A low-indium, low-silver silicon heterojunction solar cell, characterized in that, include: A crystalline silicon substrate, intrinsic hydrogenated amorphous silicon a-Si:H(i) and a phosphorus-doped nano-silicon oxide thin film nc-SiO2 are sequentially disposed on the front surface of the substrate from the inside out. x H(n), front transparent conductive oxide triple layer, antireflective layer SiN x The intrinsic hydrogenated amorphous silicon a-Si:H(i), boron-doped nano-silicon thin film nc-Si:H(p), back transparent conductive layer AZO and back electrode are sequentially disposed on the back surface of the substrate from the inside to the outside.

2. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The crystalline silicon substrate is n-type crystalline silicon c-Si(n) with a thickness of 60-150 nm, and its surface is prepared with a pyramidal textured surface structure with a size of 0.5-2 μm.

3. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The intrinsic hydrogenated amorphous silicon a-Si:H(i) disposed on the front surface and the back surface of the substrate has a thickness of 3-10 nm, and the thickness of both is the same.

4. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The phosphorus-doped nano-silicon oxide thin film nc-SiOx:H(n) has a thickness of 10-20 nm and a phosphorus atom doping concentration of 1×10⁻⁶. 19 / cm 3 -2×10 20 / cm 3 .

5. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The boron-doped nano-silicon thin film nc-Si:H(p) has a thickness of 10-20 nm and a boron atom doping concentration of 5 × 10⁻⁶. 18 / cm 3 -1×10 20 / cm 3 .

6. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The total thickness of the aforementioned transparent conductive oxide triple layer is 60-80 nm, specifically comprising: an ITO seed layer for optimizing interfacial carrier transport and stabilizing the interface, an AZO intermediate layer for providing bulk conductivity, and a top SiN layer. x The H-layer antireflective coating forms an optically synergistic ITO surface layer.

7. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The deposition conditions for the ITO surface layer should be: magnetron sputtering PVD deposition with a power density of 3.0-4.5 W / cm³. 2 The oxygen concentration is 2.4-3.0% (Ar and O2 mixture), which serves to ensure lateral conductivity and adjust the optical constant to maximize overall transmittance and minimize resistance loss. The deposition conditions for the ITO seed layer should be: magnetron sputtering PVD deposition with a power density of 2.0-3.0 W / cm³. 2 The oxygen concentration is 1.8-2.4% (Ar and O2 mixture), which serves to protect the underlying phosphorus-doped nano-silicon oxide film and optimize interfacial carrier transport during sputtering.

8. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The ITO surface layer and the ITO seed layer have the same thickness, both ranging from 5 to 35 nm; the AZO layer has a thickness of 70 to 10 nm; and the back transparent conductive layer AZO has a thickness of 70 nm.

9. The low-indium, low-silver silicon heterojunction solar cell according to claim 1, characterized in that, The antireflection layer SiN x The thickness of H is 80-120 nm, used to compensate for optical defects caused by ultrathin ITO layers (<12 nm)—especially when sufficient antireflection is not provided in the short-wavelength range (300-500 nm), while the antireflection layer SiN... x Hydrogen diffusion in H helps passivate deep defects in ITO and activate Sn dopants, thereby increasing carrier concentration. This process occurs after screen printing the electrodes and curing.

10. A method for preparing a low-indium, low-silver silicon heterojunction solar cell according to any one of claims 1-9, characterized in that, include: Step 1: Cleaning the flocking process, specifically including: 1.1 Select n-type single crystal silicon wafers with resistivity between 0.5-20 Ω·cm and thickness between 60-150 μm as substrates, and remove the wire-cut damage layer on the substrate surface with NaOH solution; 1.2 The substrate obtained in step 1.1 is etched with KOH alkaline solution to form a pyramid textured surface with a height of 0.5-2 μm on the front and back surfaces of the substrate; Step 2, depositing intrinsic hydrogenated amorphous silicon a-Si:H(i), specifically includes: placing the substrate obtained in step 1.2 into a PECVD device, introducing SiH4 and H2 gases, and depositing intrinsic hydrogenated amorphous silicon a-Si:H(i) on the front and back surfaces of the substrate. The deposition of intrinsic hydrogenated amorphous silicon a-Si:H(i) involves a process pressure of 50-200 Pa, a substrate temperature of 150-250 °C, and a gas flow ratio of SiH4:H2 = 0.01-0.

05. The thickness of the intrinsic hydrogenated amorphous silicon a-Si:H(i) on both the front and back surfaces is 3-10 nm, and the thickness of both is the same. Step 3: Deposit phosphorus-doped nano-silicon oxide thin film nc-SiO x H(n), specifically includes: placing the substrate obtained in step 2 into a PECVD apparatus, introducing SiH4, PH3 and H2 gases, and simultaneously introducing CO2 gas, to deposit a phosphorus-doped nano-silicon oxide thin film nc-SiO on the front surface of the substrate. x :H(n); The deposited phosphorus-doped nano-silicon oxide thin film nc-SiO x :H(n), with a process pressure of 50-200Pa, a substrate temperature of 150-250℃, and a gas flow ratio of SiH4:H2=0.01-0.05, PH3:H2=0.005-0.01, and CO2:H2=0.01-0.1; The phosphorus-doped nano-silicon oxide thin film nc-SiO x H(n) has a thickness of 10-20 nm and a phosphorus doping concentration of 1 × 10⁻⁶. 19 / cm 3 -2×10 20 / cm 3 ; Step 4: Deposit boron-doped nano-silicon thin film nc-Si:H(p), specifically including: flipping the substrate obtained in step 3, placing it in a PECVD device, introducing SiH4, B2H6 and H2 gases, and depositing boron-doped nano-silicon thin film nc-Si:H(p) on the back surface of the substrate. The process pressure for depositing boron-doped nano-silicon thin films nc-Si:H(p) is 50-200 Pa, the substrate temperature is 150-250 °C, and the gas flow ratio is SiH4:H2=0.01-0.05, B2H6:H2=0.005-0.

01. Step 5: Deposition of a pre-deposited transparent conductive oxide triple layer, specifically including: 5.1 Place the substrate obtained in step 4 into a PVD apparatus, attach an ITO target, and apply the PVD at a power density of 2.0-3.0 W / cm². 2 An oxygen concentration of 1.8-2.4% (Ar and O2 mixture) is used to deposit an ITO seed layer. 5.2 Place the substrate obtained in step 5.1 into a magnetron sputtering PVD apparatus, attach an AZO target, and perform sputtering at a power density of 2.0-4.0 W / cm². 2 An oxygen concentration of 1.8-2.4% (Ar and O2 mixture) was used to deposit an AZO intermediate layer. 5.3 Place the substrate obtained in step 5.2 into a PVD apparatus, attach an ITO target, and apply the PVD at a power density of 3.0-4.5 W / cm². 2 An oxygen concentration of 2.4-3.0% (Ar and O2 mixture) is used to deposit an ITO surface layer. Step 6: Deposit a transparent conductive layer (AZO), specifically including: flipping the substrate obtained in step 5.3, placing it in a PVD apparatus, connecting the AZO target, and depositing the AZO at a power density of 2.0-4.0 W / cm². 2 An oxygen concentration of 1.8-2.4% (Ar and O2 mixture) is used to deposit a transparent conductive layer (AZO). Step 7: Screen printing silver-coated copper electrodes, specifically including: screen printing grid-shaped silver-coated copper paste on the front and back surfaces of the silicon wafer obtained in step 6, and then curing it to form silver-coated copper electrodes; The copper content of the silver-coated copper paste is 10-80%, and the curing temperature is 150-250℃. Step 8: Deposit SiN antireflection layer x Specifically, this includes: placing the silicon wafer obtained in step 7 into a PECVD environment, introducing SiH4 and NH3 gases, and depositing SiN on the front surface. x :H; The deposited antireflection layer SiN x The deposition temperature of SiH4 is 150-300℃, and the gas flow ratio is SiH4:NH3=0.1-0.2.

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