Ac coupling wideband signal acquisition method based on FPGA time-to-digital converter

Abstract

The application discloses an AC coupling wideband signal acquisition method based on an FPGA time-to-digital converter, and mainly has the following technical points: an FPGA chip generates two same-frequency clock signals clk0 and clk180 with a phase difference of 180 degrees and an integer R frequency division clock signal clkDivR through clock management primitives or IP cores; the clk0 is output through a special clock pin, is filtered through an external series resistor, a capacitor and an internal capacitor, and then is input into a differential input buffer in the FPGA together with a reference signal REF formed by the resistor voltage division circuit after adding a DC bias; a wideband input signal to be sampled is input into the differential input buffer in the FPGA together with the reference signal REF after being filtered through a capacitor; a comparison output signal STA is divided into two branches after time delay adjustment, is propagated through a delay chain, and is driven by the clk0, the clk180 and the clkDivR to complete data latching, decoding and serial-parallel conversion; and the method supports wideband bipolar signal sampling, simplifies time-to-digital conversion logic, and reduces the clock frequency of the back-end signal processing.

Description

Technical Field

[0001] This invention relates to the field of electronic information technology, and in particular to an AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter. Background Technology

[0002] Time-to-digital converter (TDC) technology converts time information into digital code values ​​by measuring the time interval between the signal under test and a reference signal. It can convert analog signals into digital signals represented by time and has been widely used in communication systems, laser ranging, medical imaging, particle physics, and other fields. With the continuous development of Field-Programmable Gate Array (FPGA) technology, FPGA-based TDC implementations have gradually become a research hotspot in related fields due to their advantages such as short development cycle, controllable cost, and strong reconfigurability.

[0003] In their 2015 paper, "200 MS / s ADC implemented in a FPGA employing TDCs," Homulle et al. constructed tapped delay line (TDCs) using a CARRY4 carry chain on a Xilinx Spartan-6 FPGA. They used two TDCs to measure the rising and falling edges of the comparator output, achieving a 200 MS / s sampling rate through dual-edge measurement. In their 2021 paper, "An FPGA-based 7-ENOB 600 MSample / s ADC without any external components," Leuenberger et al. constructed a TDC using a CARRY8 carry chain on a Xilinx UltraScale+ FPGA, utilizing an internally adjustable output impedance to generate a ramp, achieving a 1.2 GS / s sampling rate. In their 2022 paper, "Design and Implementation of a High-Performance ADC Based on FPGA," Tong Lei et al. constructed a TDC using a CARRY8 carry chain on a Xilinx UltraScale FPGA, achieving an 800 MS / s sampling rate through alternating sampling by two TDCs.

[0004] Existing signal acquisition methods based on FPGA TDC mostly employ a unipolar DC-coupled architecture. In this type of method, the signal under test is directly connected to the FPGA's input buffer, and the time interval between the signal edge and the reference clock is measured by the TDC to achieve digital reconstruction of the signal waveform. The core advantage of this sampling method lies in its simple structure and low resource consumption, but it has two inherent limitations:

[0005] First, DC-coupled architectures require the signal under test to be unipolar, meaning the signal's voltage range must be entirely within the effective level range of the FPGA input buffer. This method cannot be directly applied to bipolar signals with positive and negative swings (such as most AC-coupled sensor signals and RF detection signals). Forcing this connection could result in the negative voltage portion exceeding the FPGA input port's operating range, causing signal distortion or even device damage. Therefore, in engineering practice, it is usually necessary to add an additional level shifting circuit at the FPGA front end to convert the bipolar signal into a unipolar signal before acquisition. This not only increases hardware cost and design complexity but also introduces additional noise and offset errors.

[0006] Secondly, regarding the generation of the reference signal, traditional methods often employ RC charging and discharging circuits to generate a reference signal with an exponential waveform. The exponential characteristic of the RC circuit causes the rising / falling edges of the reference signal to exhibit significant nonlinear features, which introduces a systematic nonlinear error into the time measurement of TDC. To correct this error, complex calibration measures are required, which significantly increases the system's calibration overhead and implementation difficulty.

[0007] Furthermore, existing methods generally use the sampling clock to directly output sampled data during the data readout stage. As the sampling rate increases, the operating clock frequency faced by the back-end signal processing module continues to rise, posing a severe challenge to the timing convergence and resource utilization of the FPGA. Especially in multi-channel, highly integrated TDC array applications, high-frequency clock-driven back-end processing often becomes a bottleneck for system performance.

[0008] Therefore, exploring a novel acquisition method that can directly process AC-coupled bipolar signals, reduce calibration complexity, and optimize back-end timing performance has significant practical engineering value. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention provides an AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter.

[0010] The technical solution of this invention to solve the above-mentioned technical problems is: an AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter, comprising the following steps:

[0011] S1: The FPGA chip generates two clock signals clk0 and clk180 with a phase difference of 180°, and one integer R-divided clock signal clkDivR, through clock management primitives or IP cores.

[0012] S2: clk0 is output through a dedicated clock pin. It is filtered by an external series resistor and capacitor and an internal capacitor for DC blocking. After the DC bias is increased by a resistor voltage divider circuit, it forms a unipolar reference signal REF with an approximate triangular waveform.

[0013] S3: The bipolar broadband input signal to be sampled is blocked by a capacitor and biased to generate a unipolar SIG signal, which is sent to the FPGA internal differential input buffer together with the reference signal REF.

[0014] S4: The differential input buffer compares the output signal STA, which is then delayed and adjusted before being split into two branches. After propagation through the delay chain, the signal is latched, decoded, and converted from serial to parallel under the drive of clk0, clk180, and clkDivR.

[0015] In the above-mentioned AC-coupled broadband signal acquisition method based on FPGA time-to-digital converter, in step S1, the FPGA integrated development software uses clock management primitives or IP cores with clock multiplication and division functions to multiply or divide the externally input high-precision reference clock to generate two high-frequency clock signals clk0 and clk180 with the same frequency and a phase difference of 180°, as well as an integer R-division signal clkDivR, whose frequency is one-R of clk0. These signals are cascaded with global clock buffers to drive the on-chip time data conversion logic. In addition, clk0, after being buffered globally, drives a dedicated clock pin to output the CLK signal.

[0016] In the above-described AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter, in step S2, the FPGA output CLK signal is connected to an RC circuit via an external series resistor and capacitor, and an internal parasitic capacitor. Since the external capacitor is relatively large and mainly used to isolate the DC component of the CLK signal, the charging and discharging time of the RC circuit is mainly determined by the external resistor and the internal parasitic capacitor. By increasing the resistance value of the external series resistor, the voltage waveform of the internal parasitic capacitor to ground is made approximately triangular. The FPGA IO voltage or BANK voltage is combined with a resistor divider circuit to add a DC bias to the bipolar triangular wave signal output by the external series capacitor, ultimately generating the reference signal REF.

[0017] In the above-described AC-coupled broadband signal acquisition method based on FPGA time-to-digital converter, in step S3, the broadband input signal to be sampled is DC-blocked by another external series capacitor, and then a DC bias voltage consistent with the reference signal REF is added to the DC-blocked signal using another resistor voltage divider circuit as described in step S2 to obtain a unipolar broadband signal to be sampled, SIG; subsequently, the REF signal and SIG signal generated in step S2 are regarded as differential signals and input to the FPGA through differential traces.

[0018] In the above-mentioned AC-coupled broadband signal acquisition method based on FPGA time-to-digital converter, in step S4, the REF signal and SIG signal are input to the internal differential input buffer via the FPGA differential pair pins. This buffer acts as a voltage comparator and outputs a binary digital signal STA. The phase relationship between the STA signal and clk0 or clk180 is adjusted by the delay adjustment module to obtain the optimal sampling time. The delayed STA signal is split into two branches and propagated through the corresponding N-bit delay chains. The corresponding delay chain data is latched under the drive of clock signals clk0 and clk180, respectively. The decoding is completed by calculating the number of "1"s in the latched data to obtain two parallel M-bit sampled data. Finally, under the drive of clock signals clk0 and clkDivR, the serial-to-parallel conversion of the two sampled data to 2R parallel sampled data is completed, reducing the data reading clock frequency.

[0019] The beneficial effects of this invention are as follows:

[0020] First, this invention, by adding an off-chip DC-blocking capacitor and a resistor-divider network, enables the sampling architecture, which originally only supported unipolar DC-coupled signals, to effectively process broadband bipolar signals. Traditional methods, limited by the DC-coupled structure, cannot directly handle AC-coupled bipolar signals. This invention utilizes the DC-blocking and AC-passing characteristics of the DC-blocking capacitor to process only the AC component of the signal. It does not require changes to the FPGA's internal TDC core circuitry and can achieve signal type expansion with only a few off-chip passive components, significantly improving the versatility and hardware multiplexing efficiency of the sampling system.

[0021] Second, this invention uses an approximate triangular wave as the reference signal, replacing the exponential waveform reference signal generated by the charging and discharging of an RC circuit in traditional methods. Traditional exponential waveforms have poor linearity and require complex calibration measures to ensure time measurement accuracy; while the approximate triangular wave has a flatter slope characteristic, which simplifies the design of time-to-digital conversion logic, reduces dependence on calibration algorithms, and improves measurement consistency and reliability while reducing logic resource consumption.

[0022] Third, this invention introduces a serial-to-parallel conversion module to process the sampled data in parallel. Traditional methods do not perform serial-to-parallel conversion when reading sampled data, requiring the back-end logic to run at a high clock frequency, which puts pressure on timing convergence. This invention, through serial-to-parallel conversion, effectively reduces the clock frequency of the back-end signal processing, improves the system timing margin, and is beneficial for implementing TDC arrays with higher channel counts on resource-constrained FPGA platforms.

[0023] In summary, compared with traditional methods, this invention has better signal compatibility, lower calibration complexity, and better timing performance in AC-coupled bipolar signal sampling scenarios. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating the overall process of the present invention.

[0025] Figure 2 This is a block diagram of the FPGA-based TDC AC-coupled broadband signal acquisition method proposed in this invention.

[0026] Figure 3 This invention presents a timing diagram illustrating the working principle of the FPGA TDC logic.

[0027] Figure 4 This is a spectral analysis diagram of broadband OFDM signal sampling data in an embodiment of the present invention.

[0028] Figure 5 This is a 16QAM constellation diagram recovered after demodulation of the sampled broadband OFDM signal in an embodiment of the present invention. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0030] like Figure 1 As shown, the AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter includes the following steps:

[0031] S1: The FPGA chip generates two clock signals clk0 and clk180 with a phase difference of 180°, and one integer R-divided clock signal clkDivR, through clock management primitives or IP cores.

[0032] In step S1, the FPGA integrated development software uses clock management primitives or IP cores with clock multiplication and division functions to multiply or divide the externally input high-precision reference clock to generate two high-frequency clock signals clk0 and clk180 with the same frequency and a phase difference of 180°, as well as an integer R-division signal clkDivR, whose frequency is one-R of clk0. These signals are cascaded with global clock buffers to drive the on-chip time data conversion logic. In addition, clk0 drives a dedicated clock pin to output the CLK signal after being buffered globally.

[0033] S2: clk0 is output through a dedicated clock pin. It is filtered by an external series resistor and capacitor and an internal capacitor for DC blocking. After the DC bias is increased by a resistor voltage divider circuit, it forms a unipolar reference signal REF with an approximate triangular waveform.

[0034] In step S2, the FPGA output CLK signal is connected to an RC circuit via an external series resistor and capacitor, and an internal parasitic capacitor. Since the external capacitor is relatively large and mainly used to isolate the DC component of the CLK signal, the charging and discharging time of the RC circuit is mainly determined by the external resistor and the internal parasitic capacitor. By increasing the value of the external series resistor, the voltage waveform of the internal parasitic capacitor to ground is made to approximate a triangular wave. The FPGA IO voltage or BANK voltage is used in combination with a resistor divider circuit to add a DC bias to the bipolar triangular wave signal output by the external series capacitor, and finally the reference signal REF is generated.

[0035] S3: The bipolar broadband input signal to be sampled is blocked by a capacitor and biased to generate a unipolar SIG signal, which is sent to the FPGA internal differential input buffer together with the reference signal REF.

[0036] In step S3, the broadband input signal to be sampled is blocked by another external series capacitor and then a DC bias voltage consistent with the reference signal REF is added to the blocked signal using another resistor voltage divider circuit as described in step S2 to obtain a unipolar broadband signal to be sampled SIG; then the REF signal and SIG signal generated in step S2 are regarded as differential signals and input to the FPGA through differential traces.

[0037] S4: The differential input buffer compares the output signal STA, which is then delayed and adjusted before being split into two branches. After propagation through the delay chain, the signal is latched, decoded, and converted from serial to parallel under the drive of clk0, clk180, and clkDivR.

[0038] In step S4, the REF and SIG signals are input to the internal differential input buffer via the FPGA differential pair pins. This buffer acts as a voltage comparator and outputs a binary digital signal STA. The phase relationship between the STA signal and clk0 or clk180 is adjusted by the delay adjustment module to obtain the optimal sampling time. The delayed STA signal is split into two branches and propagated through the corresponding N-bit delay chains. The corresponding delay chain data is latched under the drive of clock signals clk0 and clk180, respectively. The decoding is completed by calculating the number of "1"s in the latched data to obtain two parallel M-bit sampled data. Finally, under the drive of clock signals clk0 and clkDivR, the serial-to-parallel conversion of the two sampled data to 2R parallel sampled data is completed, reducing the data reading clock frequency.

[0039] Figure 2This is a block diagram of the FPGA-based TDC AC-coupled broadband signal acquisition method proposed in this invention. The external reference clock is multiplied or divided by the on-chip clock management module and then passed through a global clock buffer to obtain two clocks clk0 and clk180 with the same frequency but opposite phase, as well as a clock signal clkDivR, whose frequency is 1 / R of clk0. The CLK signal output from clk0 through a dedicated clock pin is DC blocked and filtered by an RC circuit consisting of an external series resistor R0, a capacitor C0, and an internal parasitic capacitor Cin. After passing through a voltage divider circuit composed of resistors R1 and R2, a unipolar reference signal is obtained. By selecting an appropriate resistance value R0, an approximate triangular wave reference signal REF is obtained. The voltage divider circuit adds a DC bias R2 / (R1+R2)×VCCIO to the bipolar reference signal output from C0 by dividing the FPGA IO voltage VCCIO.

[0040] The wideband signal to be sampled is AC-coupled to a voltage divider circuit composed of resistors R3 and R4 via capacitor C1, and its DC bias is kept consistent with that of the reference signal REF to obtain the bias reset input signal SIG. The externally generated reference signal REF and the signal to be sampled SIG are treated as differential signals and input to the on-chip differential input buffer via the FPGA differential pair pins. The comparison output generates a binary digital signal STA, which, after time delay adjustment, is input to the corresponding N-tap delay chains via two branches for propagation. N-bit tap data is latched at the rising edges of clk0 and clk180, respectively. It is important to note that the propagation delay of the N-tap delay chain should be comparable to the clk clock period, and the delay chain resources used by the two branches need to be constrained to ensure that the routing delays of the STA signal traces to the corresponding delay chains are similar. Pipeline addition is performed on the latched data to calculate the number of "1"s in the N-bit data to complete the corresponding decoding function. The two decoders operate in parallel, outputting two M-bit sampled data, A and B. Where M is an integer greater than or equal to log2(N). To reduce the operating frequency of data readout or subsequent signal processing logic, the sampled data can be converted from serial to parallel using an asynchronous clock FIFO. Specifically, clk0, two M-bit data A and B are used as the FIFO write clock and write data; clkDivR is used as the FIFO readout clock, and the readout data can be regarded as one 2RM-bit data or 2R-bit M-bit data.

[0041] Figure 3This is a timing diagram illustrating the working principle of the FPGA TDC logic proposed in this invention, where R=2. Since the REF and SIG signals are input through the differential pair pins P and N respectively, when the REF signal voltage is greater than the SIG signal voltage, the STA signal output by the differential input buffer after comparison is high, and vice versa. Assuming that the highest frequency component of the sampled wideband input signal is lower than the sampling clock clk0 or clk180, the voltage change of the SIG signal is small within the corresponding sampling clock cycle. The duration of the high level of the STA signal is linearly negatively correlated with the voltage of the sampled signal SIG. Therefore, analog-to-digital conversion can be achieved through TDC. In the diagram, the REF signal phase is consistent with clk0. In practice, the reference signal REF and clk0 have the same frequency but a phase difference. A delay adjustment module is needed to calibrate the STA signal to ensure that the optimal sampling time is at the rising edge of clk0 or clk180. After the calibrated STA signal is propagated through an N-bit tapped delay chain, it is latched and decoded at the rising edges of clocks clk0 and clk180 to obtain M-bit sampled data. After serial-to-parallel conversion, 2R parallel sampled data are read per cycle under the drive of the clkDivR clock. Since sampling is performed twice within one clock cycle, the designed equivalent sampling rate is twice the clk0 clock frequency.

[0042] To fully verify the effectiveness of this invention, a TDC AC-coupled broadband signal acquisition device based on a Xilinx / AMD XC7K325T FPGA chip was designed and implemented. Key parameters include: R0 = 47Ω, R1 = R2 = R3 = R4 = 1kΩ, C0 = C1 = 100nF, VCCIO = 2.5V, R = 4, clk0, clk180, and clkDivR frequencies of 400, 400, and 100MHz respectively, N = 200, and M = 8. Simultaneously, a frame of real-valued OFDM signal is generated based on software programming and a signal generation device. This includes a training sequence for timing synchronization and channel estimation, and 100 data 16QAM-OFDM symbols. Specific parameters are as follows: IFFT points, cyclic prefix / suffix, and effective data subcarriers are 1024, 16 / 16, and 480 respectively; the digital-to-analog conversion rate is 400MSa / s; and the OFDM signal bandwidth is 187.5MHz.

[0043] After synthesis, placement and routing, the TDC logic occupies only 1010 lookup tables (LUTs) and 1649 registers, 100 CARRY4s to implement two delay chain modules, and 1 block RAM to implement serial-to-parallel conversion.

[0044] After suppressing high-frequency imagery of the OFDM signal using a 200MHz low-pass filter, the sampled broadband signal is input to the FPGA TDC device designed in this invention for signal conversion. The FPGA debug IP core, combined with the JTAG interface, uploads the sampled data to a computer and saves it as a text file. Finally, the OFDM receiver demodulation algorithm processes the sampled data.

[0045] Figure 4 The amplitude spectrum of the sampled broadband OFDM signal obtained from FFT analysis in this embodiment of the invention is rectangular in shape, with signal bandwidth consistent with theoretical analysis and good in-band flatness.

[0046] Figure 5 The 16QAM constellation diagram recovered after demodulation of the sampled broadband OFDM signal in this embodiment of the invention has good convergence, with a corresponding error vector amplitude of approximately -20 dB and a bit error rate far below 1×10⁻⁶. -3 .

[0047] In summary, this invention not only supports broadband bipolar signal sampling by enabling DC blocking and resistor voltage division, but also reduces the time-to-digital conversion logic design by using an approximate triangular wave reference signal and introduces a serial-to-parallel conversion module to reduce the clock frequency of back-end signal processing.

Claims

1. A method for acquiring AC-coupled broadband signals based on an FPGA time-to-digital converter, characterized in that, Includes the following steps: S1: The FPGA chip generates two clock signals clk0 and clk180 with a phase difference of 180°, and an integer R-divided clock signal clkDivR, through clock management primitives or IP cores. S2: clk0 is output through a dedicated clock pin. It is filtered by an external series resistor and capacitor and an internal capacitor for DC blocking. After the DC bias is increased by a resistor voltage divider circuit, it forms a unipolar reference signal REF with an approximate triangular waveform. S3: The bipolar broadband input signal to be sampled is blocked by a capacitor and biased to generate a unipolar SIG signal, which is sent to the FPGA internal differential input buffer together with the reference signal REF. S4: The differential input buffer compares the output signal STA, which is then delayed and adjusted before being split into two branches. After propagation through the delay chain, the signal is latched, decoded, and converted from serial to parallel under the drive of clk0, clk180, and clkDivR.

2. The AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter according to claim 1, characterized in that, In step S1, the FPGA integrated development software uses clock management primitives or IP cores with clock multiplication and division functions to multiply or divide the externally input high-precision reference clock to generate two high-frequency clock signals clk0 and clk180 with the same frequency and a phase difference of 180°, as well as an integer R-division signal clkDivR, whose frequency is one-R of clk0. These signals are cascaded with global clock buffers to drive the on-chip time data conversion logic. In addition, clk0 drives a dedicated clock pin to output the CLK signal after being buffered globally.

3. The AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter according to claim 1, characterized in that, In step S2, the FPGA output CLK signal is connected to an RC circuit via an external series resistor and capacitor, and an internal parasitic capacitor. Since the external capacitor is relatively large and mainly used to isolate the DC component of the CLK signal, the charging and discharging time of the RC circuit is mainly determined by the external resistor and the internal parasitic capacitor. By increasing the value of the external series resistor, the voltage waveform of the internal parasitic capacitor to ground is made to approximate a triangular wave. The FPGA IO voltage or Bank voltage is used in combination with a resistor divider circuit to add a DC bias to the bipolar triangular wave signal output by the external series capacitor, and finally the reference signal REF is generated.

4. The AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter according to claim 1, characterized in that, In step S3, the broadband input signal to be sampled is blocked by another external series capacitor and then a DC bias voltage consistent with the reference signal REF is added to the blocked signal using another resistor voltage divider circuit as described in step S2 to obtain a unipolar broadband signal to be sampled SIG. The REF and SIG signals generated in step S2 are then treated as differential signals and input to the FPGA via differential traces.

5. The AC-coupled broadband signal acquisition method based on an FPGA time-to-digital converter according to claim 1, characterized in that, In step S4, the REF and SIG signals are input to the internal differential input buffer via the FPGA differential pair pins. This buffer acts as a voltage comparator and outputs a binary digital signal STA. The phase relationship between the STA signal and clk0 or clk180 is adjusted by the delay adjustment module to obtain the optimal sampling time. The delayed STA signal is split into two branches and propagated through the corresponding N-bit delay chains. The corresponding delay chain data is latched under the drive of clock signals clk0 and clk180, respectively. The decoding is completed by calculating the number of "1"s in the latched data to obtain two parallel M-bit sampled data. Finally, under the drive of clock signals clk0 and clkDivR, the serial-to-parallel conversion of the two sampled data to 2R parallel sampled data is completed, reducing the data reading clock frequency.

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