An improved circuit of a PLL phase-locked loop based on a multi-channel feedback loop

Abstract

The application discloses an improved circuit of a PLL phase-locked loop based on a multi-channel feedback loop, and the whole PLL system circuit comprises a low-pass filter, a voltage-controlled oscillator, an improved high-order frequency divider, a multi-channel retiming circuit, a three-way frequency discriminator and a phase discriminator and a charge pump; the improved high-order frequency divider comprises an improved high-order modulator based on a traditional mash1-1-1 and a multi-mode frequency divider. The application multiplies a set fractional frequency division ratio by 4, takes the fractional part of the obtained result as the input of the mash1-1-1, adds the integer part and the output sequence of the mash1-1-1 to obtain a new output sequence, divides the new output sequence by 4, and converts the positive fractional part into a two-bit binary control code s<1:0>. The remaining integer is taken as the output of the modulator and added to the multi-mode frequency divider to control the change of the frequency division ratio. The multi-channel retiming circuit selects CK1 and CK2 generated based on the output clock of the voltage-controlled oscillator according to s<1:0>, the clock periods of the two clocks are different by 1Tvco, and the quantization step is reduced from 1*Tvco to 0.25*Tvco.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an improved PLL phase-locked loop circuit based on a multi-channel feedback loop. Background Technology

[0002] A phase-locked loop (PLL) is a widely used feedback control system whose core function is to enable the frequency or phase of the output signal to accurately track the frequency and phase of the clock of the input reference signal.

[0003] The pursuit of wider locking range and lower phase noise is an inevitable trend in PLL development, and fractional dividers, with their advantages of high resolution, low phase noise, and short locking time, have become mainstream. The core principle of a fractional divider is to cleverly mix different integer division ratios within a relatively long time window to obtain a fractional division ratio on average. This mechanism inevitably introduces a deviation between the actual and ideal division ratios in each clock cycle, resulting in quantization errors, which increase with the modulator order. Summary of the Invention

[0004] The purpose of this invention is to provide an improved PLL phase-locked loop circuit based on a multi-channel feedback loop to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides an improved PLL phase-locked loop circuit based on a multi-channel feedback loop, including: a low-pass filter, a voltage-controlled oscillator, an improved high-order frequency divider, a multi-channel retiming circuit, a three-channel frequency and phase detector, and a charge pump. The outputs of the three-channel frequency and phase detectors and the charge pump are connected to the input of the low-pass filter. The output of the low-pass filter is connected to the input of the voltage-controlled oscillator. The voltage-controlled oscillator outputs the clock CKVCO to the multi-channel retiming circuit. The improved high-order frequency divider outputs two binary codes s<1:0> and a signal CCMMD. The two binary codes s<1:0> serve as the input to the multiplex retiming circuit to select the corresponding clock; the signal CCMMD performs integer frequency division of the voltage-controlled oscillator's clock. The multi-channel retiming circuit outputs clocks CLK0, CLK1, and CLK2 to three frequency and phase detectors and a charge pump, respectively. Depending on the control signal s<1:0>, different outputs can achieve additional fractional frequency division of 0, 0.25, 0.5, or 0.75.

[0006] In one embodiment, the improved high-order frequency divider includes an improved high-order modulator based on the conventional mash1-1-1 and a multimode frequency divider; wherein, The improved high-order modulator includes a ×4 multiplier, a ÷4 divider, a conventional mash1-1-1 circuit, a first adder, and a second adder. The set division ratio is Nf. The fractional part is used as the input to the ×4 multiplier to obtain the output result. The fractional part of this result is used as the input to the conventional mash1-1-1 circuit. The integer part of this result and the output sequence of the conventional mash1-1-1 circuit are used as the two inputs to the first adder. The output of the first adder is used as the input to the ÷4 divider to obtain the output result. The output result is divided into a positive fractional and an integer. The integer is used as the output sequence NDIV of the improved high-order modulator to control the division ratio of the multimode divider. The positive fractional is converted into a two-bit binary code s<1:0> and input to the multi-channel retiming circuit.

[0007] In one embodiment, the multi-channel feedback loop is composed of a multi-channel retiming circuit, three frequency and phase detectors, and a charge pump. The multi-channel retiming circuit includes D flip-flops DFF1~DFF5 and selectors Mux1~Mux3; the clk input terminals of D flip-flops DFF1~DFF5 are all connected to the output clock CKVCO of the voltage-controlled oscillator; the D input terminal of D flip-flop DFF1 is connected to the output signal CGMMD of the multi-mode divider; the Q output terminal of D flip-flop DFF1 is connected to the D input terminal of D flip-flop DFF2 and the first input port of selectors Mux1~Mux3; the Q output terminal of D flip-flop DFF2 is connected to the second input port of the three selectors; the input terminal of D flip-flop DFF3 is connected to the output terminal of selector Mux1, and the output terminal of D flip-flop DFF3 is the output clock CLK0; the input terminal of D flip-flop DFF4 is connected to the output terminal of selector Mux2, and the output terminal of D flip-flop DFF4 is the output clock CLK1; the input terminal of D flip-flop DFF5 is connected to the output terminal of selector Mux3, and the output terminal of D flip-flop DFF5 is the output clock CLK2. The control terminal of selector Mux1 is connected to a fixed control signal 0; the control terminal of selector Mux2 is connected to a strobe signal s. <1> The control terminal of selector Mux3 is connected to the strobe signal s. <0> When the strobe signal is 0, the selected output clock signal is CK1; when the strobe signal is 1, the selected output clock signal is CK2, which is delayed by 1Tvco compared to CK1, where 1Tvco is one clock cycle of the voltage-controlled oscillator.

[0008] In one embodiment, among the three frequency-phase detectors and charge pumps, the output current of the first frequency-phase detector and charge pump is 0.25*Icp, the output current of the second frequency-phase detector and charge pump is 0.25*Icp, and the output current of the third frequency-phase detector and charge pump is 0.5*Icp.

[0009] The present invention provides an improved PLL phase-locked loop circuit based on a multi-channel feedback loop, which can improve the quantization step size accuracy, effectively optimize the quantization noise of the fractional frequency divider, and improve the overall noise performance of the PLL phase-locked loop. Attached Figure Description

[0010] Figure 1 This is a block diagram of a PLL phase-locked loop system provided by the present invention.

[0011] Figure 2 This is a schematic diagram of an improved high-order modulator circuit provided by the present invention.

[0012] Figure 3 This is a schematic diagram of a multi-channel retiming circuit provided by the present invention. Detailed Implementation

[0013] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the improved PLL phase-locked loop circuit based on a multi-channel feedback loop proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0014] like Figure 1 As shown, a novel high-order modulator in a PLL (Phase-Locked Loop) is adapted to improve quantization noise in a multi-channel loop. The entire PLL system circuit includes three independent frequency and phase discriminators and charge pumps (PFD+CP_01, PFD+CP_02, PFD+CP_03), a low-pass filter circuit (LPF), a voltage-controlled oscillator (VCO) circuit, an improved high-order frequency divider, and a multi-channel retiming circuit. The improved frequency divider circuit specifically includes an improved high-order modulator based on the traditional mash1-1-1 and a multi-mode frequency divider (MMD).

[0015] like Figure 2 As shown, the improved high-order modulator includes a ×4 and ÷4 functional circuit, a traditional mash1-1-1 circuit, and two adders (adder 1 and adder 2). The set division ratio is Nf. The fractional part is used as the input to the ×4 multiplier to obtain the output result. The fractional part of this result is used as the input to the traditional mash1-1-1 circuit. The output sequence of the traditional mash1-1-1 circuit and the integer part of the result are then used as the two inputs to adder 1. The output of adder 1 is used as the input to the ÷4 divider to obtain the output result. This output result is divided into a positive fractional and an integer. The integer is used as the output sequence NDIV of the improved high-order modulator to control the division ratio of the multi-mode divider. The fractional part is converted into a two-bit binary code s<1:0>, which is used as the input to the multiplexed retiming circuit to select the appropriate clock.

[0016] A multi-channel retiming circuit, three frequency and phase detectors, and a charge pump together form a multi-channel feedback loop. For example... Figure 3 As shown, the multi-channel retiming circuit includes five D flip-flops (DFF1~DFF5) and three selectors (Mux1~Mux3). The clk inputs of all five D flip-flops are connected to the output clock CKVCO of the VCO. The D input of DFF1 is connected to the output signal CKMMD of the multi-mode divider MMD. The Q output of DFF1 is connected to the D input of DFF2 and input port 1 of the three selectors. The Q output of DFF2 is connected to input port 2 of the three selectors. The input of DFF3 is connected to the output of selector Mux1, and its output is the output clock CLK0. The input of DFF4 is connected to the output of selector Mux2, and its output is the output clock CLK1. The input of DFF5 is connected to the output of selector Mux3, and its output is the output clock CLK2. The control signal for selector Mux1 is connected to a fixed control signal 0; the control signal for selector Mux2 is connected to the strobe signal s. <1> The control signal for selector Mux3 is connected to the strobe signal s. <0> When the strobe signal is 0, the selected output clock signal is CK1; when the strobe signal is 1, the selected output clock signal is CK2, which is delayed by 1Tvco compared to CK1, where 1Tvco is one clock cycle of the voltage-controlled oscillator. CK1 and CK2 are clock signals output from the Q terminals of DFF1 and DFF2, respectively. Among the three frequency and phase discriminators and the charge pump, the output current of the first path PFD+CP_01 is 0.25*Icp, the output current of the second path PFD+CP_02 is 0.25*Icp, and the output current of the third path PFD+CP_03 is 0.5*Icp.

[0017] This invention improves resolution by feeding the fractional part of the fractional frequency division ratio multiplied by 4 into a traditional mash1-1-1 circuit, adding its output sequence to the integer part, and then dividing this output sequence by 4. Correspondingly, by combining a three-channel frequency and phase discriminator and a charge pump circuit, and selecting two CK1 or CK2 signals with a 1Tvco phase difference, and combining different currents, the quantization step size resolution can be effectively reduced from 1Tvco to 0.25Tvco. Compared to traditional DTC circuits, this invention has a simpler circuit structure, lower power consumption, improves quantization accuracy by 75%, reduces cumulative phase error to 25%, and effectively improves the overall noise performance of the PLL.

[0018] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An improved PLL phase-locked loop circuit based on a multi-channel feedback loop, characterized in that, include: Low-pass filter, voltage-controlled oscillator, improved high-order frequency divider, multi-channel retiming circuit, three-channel frequency and phase detector, and charge pump; The outputs of the three-channel frequency and phase detectors and the charge pump are connected to the input of the low-pass filter. The output of the low-pass filter is connected to the input of the voltage-controlled oscillator. The voltage-controlled oscillator outputs the clock CKVCO to the multi-channel retiming circuit. The improved high-order frequency divider outputs two binary codes s<1:0> and a signal CCMMD. The two binary codes s<1:0> serve as the input to the multiplex retiming circuit to select the corresponding clock; the signal CCMMD performs integer frequency division of the voltage-controlled oscillator's clock. The multi-channel retiming circuit outputs clocks CLK0, CLK1, and CLK2 to three frequency and phase detectors and a charge pump, respectively. Depending on the control signal s<1:0>, different outputs can achieve additional fractional frequency division of 0, 0.25, 0.5, or 0.

75.

2. The improved PLL phase-locked loop circuit based on a multi-channel feedback loop as described in claim 1, characterized in that, The improved high-order frequency divider includes an improved high-order modulator based on the traditional mash 1-1-1 and a multimode frequency divider; wherein, The improved high-order modulator includes a ×4 multiplier, a ÷4 divider, a conventional mash1-1-1 circuit, a first adder, and a second adder. The set division ratio is Nf. The fractional part is used as the input to the ×4 multiplier to obtain the output result. The fractional part of this result is used as the input to the conventional mash1-1-1 circuit. The integer part of this result and the output sequence of the conventional mash1-1-1 circuit are used as the two inputs to the first adder. The output of the first adder is used as the input to the ÷4 divider to obtain the output result. The output result is divided into a positive fractional and an integer. The integer is used as the output sequence NDIV of the improved high-order modulator to control the division ratio of the multimode divider. The positive fractional is converted into a two-bit binary code s<1:0> and input to the multi-channel retiming circuit.

3. The improved PLL phase-locked loop circuit based on a multi-channel feedback loop as described in claim 2, characterized in that, The multi-channel feedback loop is composed of a multi-channel retiming circuit, three frequency and phase detectors, and a charge pump. The multi-channel retiming circuit includes D flip-flops DFF1~DFF5 and selectors Mux1~Mux3; the clk input terminals of D flip-flops DFF1~DFF5 are all connected to the output clock CKVCO of the voltage-controlled oscillator; the D input terminal of D flip-flop DFF1 is connected to the output signal CMMMD of the multi-mode divider; the Q output terminal of D flip-flop DFF1 is connected to the D input terminal of D flip-flop DFF2 and the first input port of selectors Mux1~Mux3; the Q output terminal of D flip-flop DFF2 is connected to the second input port of the three selectors; the input terminal of D flip-flop DFF3 is connected to the output terminal of selector Mux1, and the output terminal of D flip-flop DFF3 is the output clock CLK0; The input of D flip-flop DFF4 is connected to the output of selector Mux2, and the output of D flip-flop DFF4 is the output clock CLK1. The input of D flip-flop DFF5 is connected to the output of selector Mux3, and the output of D flip-flop DFF5 is the output clock CLK2. The control terminal of selector Mux1 is connected to a fixed control signal 0; the control terminal of selector Mux2 is connected to a strobe signal s. <1> The control terminal of selector Mux3 is connected to the strobe signal s. <0> ; When the strobe signal is 0, the selected output clock signal is CK1; when the strobe signal is 1, the selected output clock signal is CK2, which is delayed by 1Tvco compared to CK1, where 1Tvco is one clock cycle of the voltage-controlled oscillator.

4. The improved PLL phase-locked loop circuit based on a multi-channel feedback loop as described in claim 3, characterized in that, Of the three frequency and phase detectors and charge pumps, the output current of the first frequency and phase detector and charge pump is 0.25*Icp, the output current of the second frequency and phase detector and charge pump is 0.25*Icp, and the output current of the third frequency and phase detector and charge pump is 0.5*Icp.

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