Direct memory access control system and method for adaptive prefetch arbitration

Abstract

The application provides a direct memory access control system and method for adaptive prefetch arbitration. The system collects data channel running states through a data channel state monitoring module, estimates descriptor cutoff and payload data starvation risks through a descriptor cutoff risk estimation module and a payload data starvation risk estimation module respectively, and generates and adjusts the priority of the linked list item read request according to the two types of risks through an adaptive prefetch strategy controller. The descriptor prefetch timing and read priority are dynamically adjusted according to the load, the timely preparation of the next descriptor and the continuous supply of the payload data are considered, the data block switching air bubbles and the source buffer idle are reduced, the payload data read continuity is guaranteed, the effective bandwidth utilization of the shared storage channel is improved, and the stability of the transport delay is improved.

Description

Technical Field

[0001] This invention relates to the field of memory access control technology, and in particular to a direct memory access control system and method with adaptive prefetch arbitration. Background Technology

[0002] A list-based Direct Memory Access (DMA) controller is a hardware module capable of transferring data between memory and peripherals or between memory modules with minimal processor intervention. In a list-based DMA architecture, the data to be transferred is organized into several data blocks, each corresponding to a descriptor (also called a list entry). The descriptor records the source address, destination address, transfer length, control fields, and a pointer to the next descriptor for that data block. The controller sequentially reads the descriptors and executes the data transfer operations they indicate, achieving continuous transfer of multiple data blocks.

[0003] To ensure pipeline continuity, linked-list direct memory access controllers typically prefetch the next descriptor while moving the payload data of the current data block; this operation is called descriptor prefetching. The prefetched descriptors are temporarily stored in the shadow descriptor register and can be used immediately after the current data block is moved, avoiding pipeline pauses caused by waiting for descriptor reading.

[0004] However, descriptor prefetch requests and payload data read requests share the same read address channel and on-chip interconnect bandwidth. In existing solutions, the triggering timing and priority of descriptor prefetching typically employ a fixed strategy, such as initiating a prefetch request with a fixed priority at the start of the current data block transfer. This approach has the following problems:

[0005] Firstly, when the payload data volume is large or the bus load is high, the fixed-time prefetch request and the payload read request will compete for bandwidth, causing the data volume of the source buffer to continuously decrease, the payload transmission will be interrupted or even starved, and the overall throughput will decrease. Secondly, when the bus load is light and the current data block transmission is about to end, if the prefetch is still executed at a fixed pace or is continuously delayed due to low priority, the next descriptor may not be ready before the current data block transmission is completed, causing the descriptor to miss the deadline and the transmission pipeline to be interrupted. Third, existing solutions lack the ability to jointly perceive the urgency of prefetching and the hunger of the payload. They cannot dynamically adjust the start, stop, priority, and lead time of prefetching according to the runtime state. The prefetching strategy and the actual transmission load are in an open-loop state, making it difficult to simultaneously ensure the timely readiness of descriptors and the bandwidth guarantee of the payload path under different operating conditions.

[0006] Therefore, a new direct memory access control system is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides an adaptive prefetch arbitration direct memory access control system and method, aiming to solve the problem in existing linked list direct memory access controllers where the fixed descriptor prefetch strategy cannot simultaneously ensure timely preparation of the next descriptor and continuous supply of payload data.

[0008] To address the aforementioned technical problems, in a first aspect, the present invention provides an adaptive prefetch arbitration direct memory access control system, comprising a configuration register module, a current working register module, a shadow descriptor register module, a linked list item state machine, a source-end data read state machine, a destination-end write state machine, a data channel state monitoring module, a descriptor cutoff risk estimation module, a payload data starvation risk estimation module, an adaptive prefetch strategy controller, and a read address arbitrator, wherein: The configuration register module is used to acquire and save channel configuration and threshold parameters, and write the channel configuration into the current working register module. The channel configuration includes channel enable, source transmission configuration, destination transmission configuration, data block transmission length, linked list item address and prefetch enable flag. The current working register module is used to store the channel configuration and the description information of the currently executing data block, and to provide the channel configuration and the description information to the linked list item state machine, the source end data read state machine and the destination end write state machine. The description information includes the source address, destination address, current data block transmission length, control field and next linked list item address. The shadow descriptor register module is used to store the next linked list item descriptor obtained by prefetching based on the address of the next linked list item, and to mark whether the next linked list item descriptor has been saved completely by the shadow descriptor valid flag. When the data block being executed is completed and the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved completely, the saved next linked list item descriptor is copied to the current working register module. The linked list item state machine is used to read the first linked list item descriptor from the system memory according to the linked list item address after the channel is enabled, load the first linked list item descriptor into the current working register module, and then generate an original linked list item read request to read the next linked list item descriptor when the prefetch condition is met, and write the next linked list item descriptor into the shadow descriptor register module after the next linked list item descriptor is returned, while setting the shadow descriptor valid flag. The source-side data read state machine is used to initiate a payload data read request for the currently executing data block based on the source address and the current data block transmission length, and to perform flow control based on the space of the source-side first-in-first-out buffer, the count of incomplete read transactions at the source, and the state of the read address buffer. The destination write state machine is used to initiate a write request to write the payload data of the currently executing data block to the destination address according to the destination transmission configuration, and to perform flow control according to the water level, write response and back pressure status of the destination first-in-first-out buffer. The data channel status monitoring module is used to collect the data channel operating status, which includes whether the source end data read status machine is waiting for the arbitration authorization of the read address arbitrator and the number of cycles of waiting for arbitration authorization, the water level of the source end first-in-first-out buffer, the count of the source end incomplete read transactions, whether the destination end write status machine is waiting for data, whether the read address buffer is full, and the read address channel congestion status. The descriptor cutoff risk estimation module is used to estimate the descriptor cutoff risk that the next linked list item descriptor cannot be prepared before the currently executing data block is moved, based on the remaining transmission volume of the currently executing data block, the payload data service rate, the linked list item read history delay, the shadow register copy delay, and the safety margin determined according to the threshold parameter. The payload data starvation risk estimation module is used to estimate the payload data starvation risk of the payload data read request not receiving timely arbitration authorization based on the water level of the source end first-in-first-out buffer, the number of cycles the source end data read state machine waits for arbitration authorization, whether the destination end write state machine is waiting for data, and the congestion status of the read address channel. The adaptive prefetch strategy controller is used to generate control actions based on the descriptor cutoff risk and the payload data starvation risk. The control actions include allowing list item prefetching, pausing list item prefetching, increasing list item read priority, decreasing list item read priority, and updating the safety margin. Based on the control actions, the controller performs gating and priority generation on the original list item read request to obtain the list item read request, thereby controlling whether the list item read request is sent to the read address arbitrator and the list item read priority at the time of sending. The read address arbitrator is used to receive the linked list item read request and the payload data read request, and select one of the linked list item read request and the payload data read request to be sent to the main interface read channel according to their respective dynamic priorities; The adaptive prefetch strategy controller is configured to allow list item prefetching and increase the read priority of the list item when the descriptor cutoff risk is high; and to suspend list item prefetching or reduce the read priority of the list item when the descriptor cutoff risk is low and the payload data starvation risk is high, so that the next list item descriptor is ready before the currently executing data block transfer is completed, and to prevent the list item read request from preempting the arbitration authorization of the payload data read request.

[0009] Furthermore, the adaptive prefetching strategy controller generates the control action by determining the following in the order of the shadow descriptor validity flag, the descriptor cutoff risk, and the payload data starvation risk: When the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved, a control action is generated to prevent linked list item prefetching, and no new linked list item read requests are submitted to the read address arbitrator. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been fully saved and the descriptor cutoff risk is high, a control action is generated to allow the linked list item prefetching, and the priority of reading the linked list item is raised to a higher priority level than the priority level of the payload data reading request. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been fully saved, the descriptor cutoff risk is low, and the payload data starvation risk is high, a control action to pause linked list item prefetching is generated. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been completely saved, the descriptor cutoff risk is low, and the payload data starvation risk is low, a control action that allows linked list item prefetching is generated, and the linked list item read request is submitted with the channel base priority, which is the channel priority saved by the configuration register module.

[0010] Furthermore, the descriptor cutoff risk estimation module estimates the descriptor cutoff risk, specifically as follows: Calculate the remaining transmission time determination value for the current data block. The remaining transmission time determination value for the current data block is the remaining number of time steps of the currently executing data block divided by the service rate determination value and rounded up. The remaining number of time steps is obtained by subtracting the number of time steps completed at the source end from the total number of time steps of the current data block. The number of time steps completed at the source end is counted by the source end completed time step counter. The source end completed time step counter is incremented by 1 every time the main interface returns 1 time step of effective payload read data. The service rate determination value is the number of effective payload read data time steps returned within the statistical window, which is calculated with a preset number of clock cycles as the statistical window. If the remaining transmission time of the current data block is less than or equal to the sum of the descriptor preparation time and the safety margin, the descriptor cutoff risk is determined to be high; otherwise, the descriptor cutoff risk is determined to be low.

[0011] Furthermore, the descriptor preparation time determination value is the sum of the historical maximum number of cycles during which the linked list item read request waits for arbitration authorization from the read address arbitrator, the historical maximum number of cycles from when the linked list item read request is accepted by the main interface until the next linked list item descriptor returns, and the fixed number of cycles during which the shadow descriptor register module writes and copies. The two historical maximum number of cycles are counted by a hardware saturation counter and the maximum value is taken from the most recent N linked list item reads, where N is a positive integer. The update of the linked list item read history delay in the descriptor cutoff risk estimation module is specifically as follows: When the read request for a linked list item does not receive arbitration authorization from the read address arbitrator, or when it has been issued but the next linked list item descriptor has not yet returned, the number of cycles during which the read request waits for arbitration authorization and the descriptor read return delay are updated. The updated historical delay is used to calculate the descriptor preparation time determination value in the next round.

[0012] Furthermore, the payload data starvation risk estimation module estimates the payload data starvation risk, specifically as follows: If the current data volume of the source-side first-in-first-out buffer is less than or equal to a preset low watermark threshold, and the number of cycles during which the payload data read request continuously waits for arbitration authorization from the read address arbitrator is greater than or equal to a preset waiting threshold, the payload data starvation risk is determined to be high; otherwise, the payload data starvation risk is determined to be low. The current data volume of the source-side first-in-first-out buffer is given by a water level counter, and the number of cycles during which the payload data read request continuously waits for arbitration authorization is given by a waiting counter. The waiting counter increments when the payload data read request is valid but has not obtained arbitration authorization from the read address arbitrator, and is cleared when arbitration authorization is obtained or the payload data read request is withdrawn. The preset low water level threshold and the preset waiting threshold are threshold parameters stored in the configuration register module.

[0013] Furthermore, the adaptive prefetching strategy controller performs gating and priority generation on the original linked list item read requests, specifically as follows: The original list item read request is ANDed with the allow prefetch signal to obtain the list item read request. The allow prefetch signal is valid when the control action is to allow list item prefetching, and the list item read priority determined according to the control action is sent to the read address arbitrator.

[0014] Furthermore, the shadow descriptor register module copies the saved next linked list item descriptor to the current working register module, specifically as follows: The source address, destination address, transmission length, control field, and next descriptor address stored in the shadow descriptor register module are copied to the current working register module as the description information for the next data block. After the copying is completed, the shadow descriptor validity flag is cleared or updated.

[0015] Furthermore, the data channel status monitoring module is also used to standardize the collected data channel operating status and send it to the descriptor cutoff risk estimation module and the payload data starvation risk estimation module, respectively.

[0016] Furthermore, the read address arbitrator is also used to receive destination status read requests and select one of them to send to the main interface read channel according to the dynamic priority of the linked list item read request, the payload data read request and the destination status read request.

[0017] Secondly, the present invention also provides an adaptive prefetch arbitration direct memory access control method, implemented based on the adaptive prefetch arbitration direct memory access control system described above, comprising the following steps: S201, the channel configuration and threshold parameters are obtained and saved through the configuration register module, and the channel configuration saved by the configuration register module is written into the current working register module. After the channel enable in the channel configuration takes effect, the first linked list item descriptor is read from the system memory according to the linked list item address in the channel configuration through the linked list item state machine, and the first linked list item descriptor is loaded into the current working register module to obtain the description information of the currently executing data block. The description information includes the source address, destination address, current data block transmission length, control field and next linked list item address. S202, the source end data read state machine initiates a request to read the payload data of the currently executing data block according to the source address and the current data block transmission length. At the same time, the destination end write state machine initiates a write request to write the payload data of the currently executing data block to the destination address according to the destination end transmission configuration, so as to execute the transfer of the currently executing data block. S203, when the prefetch condition is met, the linked list item state machine generates an original linked list item read request to read the next linked list item descriptor, wherein the next linked list item descriptor is a descriptor read from the system memory according to the address of the next linked list item; S204, the data channel operation status is collected through the data channel status monitoring module. The data channel operation status includes whether the source end data read status machine is waiting for arbitration authorization from the read address arbitrator and the number of consecutive cycles of waiting for arbitration authorization, the water level of the source end first-in-first-out buffer, the count of incomplete read transactions at the source end, whether the destination end write status machine is waiting for data, whether the read address buffer is full, and the read address channel congestion status. S205, the descriptor cutoff risk estimation module estimates the descriptor cutoff risk that the next linked list item descriptor cannot be prepared before the currently executing data block is moved, based on the remaining transmission volume of the currently executing data block, the payload data service rate, the linked list item read history delay, the shadow register copy delay, and the safety margin determined by the threshold parameter. S206, the payload data starvation risk estimation module estimates the payload data starvation risk of the payload data read request not receiving timely arbitration authorization based on the water level of the source end first-in-first-out buffer, the number of continuous cycles of the source end data read state machine waiting for arbitration authorization, whether the destination end write state machine is waiting for data, and the congestion status of the read address channel. S207, the adaptive prefetch strategy controller generates control actions based on the descriptor cutoff risk and the payload data starvation risk. Based on these control actions, the original linked list item read requests are gated and prioritized to obtain linked list item read requests. The control actions include allowing linked list item prefetching, pausing linked list item prefetching, increasing linked list item read priority, decreasing linked list item read priority, and updating the safety margin. Specifically, when the descriptor cutoff risk is high, linked list item prefetching is allowed and the linked list item read priority is increased. When the descriptor cutoff risk is low and the payload data starvation risk is high, linked list item prefetching is paused or the linked list item read priority is decreased, so that the next linked list item descriptor is prepared before the currently executing data block transfer is completed, and to prevent the linked list item read request from preempting the arbitration authorization of the payload data read request. S208, the linked list item read request and the payload data read request are received through the read address arbitrator, and one of them is selected and sent to the main interface read channel according to the dynamic priority of the linked list item read request and the payload data read request. S209: After the linked list item read request obtains arbitration authorization from the read address arbitrator and the next linked list item descriptor is returned, the returned next linked list item descriptor is written to the shadow descriptor register module, and the shadow descriptor valid flag is set. The shadow descriptor valid flag is used to mark whether the next linked list item descriptor has been saved completely. When the currently executing data block transfer is completed and the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved completely, the next linked list item descriptor saved in the shadow descriptor register module is copied to the current working register module as the description information of the next data block, and the process returns to step S202 to execute the transfer of the next data block.

[0018] The beneficial effects achieved by this invention lie in providing an adaptive prefetch arbitration direct memory access control system. This system collects the data channel operating status through a data channel status monitoring module, and estimates the descriptor cutoff risk and payload data starvation risk by a descriptor cutoff risk estimation module and a payload data starvation risk estimation module, respectively. The adaptive prefetch strategy controller gates and prioritizes linked list item read requests based on these two risk types. Prefetching is allowed and priority is increased when the descriptor cutoff risk is high, while prefetching is paused or priority is reduced when the payload data starvation risk is high and the descriptor is not urgent. The timing of descriptor prefetching and read priority are dynamically adjusted according to the load, achieving a balance between timely preparation of the next descriptor and continuous payload data supply. This reduces data block switching idling and source buffer idleness, ensures the continuity of payload data reading, improves the effective bandwidth utilization of the shared memory path, and enhances the stability of transport latency. Attached Figure Description

[0019] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings: Figure 1 This is an architecture diagram of the direct memory access control system with adaptive prefetch arbitration provided in an embodiment of the present invention; Figure 2 This is a flowchart of the adaptive prefetch arbitration direct memory access control method provided in an embodiment of the present invention. Detailed Implementation

[0020] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] The specific embodiments / examples described herein are specific implementations of the present invention, used to illustrate the concept of the invention, and are illustrative and exemplary, and should not be construed as limiting the implementation methods or scope of the present invention. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein, all of which are within the protection scope of the present invention.

[0022] Example 1 Please refer to Figure 1 , Figure 1 This is an architecture diagram of the adaptive prefetch arbitration direct memory access control system 100 provided in an embodiment of the present invention. The adaptive prefetch arbitration direct memory access control system 100 includes a configuration register module 101, a current working register module 102, a shadow descriptor register module 103, a linked list item state machine 104, a source data read state machine 105, a destination write state machine 106, a data channel status monitoring module 107, a descriptor cutoff risk estimation module 108, a payload data starvation risk estimation module 109, an adaptive prefetch strategy controller 1010, and a read address arbitrator 1011.

[0023] For ease of understanding, the main terms involved in the embodiments of the present invention are explained as follows: Direct Memory Access (DMA) is used to move data between memory, peripherals, on-chip accelerators, or on-chip interconnects with minimal processor involvement. A Linked List Item (LLI) is a descriptor in a linked list-based DMA controller that describes a data block moving task. Each LLI descriptor typically contains a source address, destination address, transfer length, control field, status field, and the address of the next descriptor.

[0024] A First-In-First-Out (FIFO) buffer is a buffer structure used to temporarily store data between the source end's read data and the destination end's write data. Software can configure the channel through the Advanced Peripheral Bus (APB) or a similar register interface.

[0025] The main interface is the controller's on-chip interconnect interface, which can use common on-chip bus interfaces such as the Advanced Dextensible Interface (AXI). The system memory can be Double Data Rate (DDR) synchronous dynamic random access memory or high-bandwidth memory.

[0026] An incomplete read transaction refers to a read transaction that has been accepted by the main interface but whose read data has not yet been returned. The source-side incomplete read transaction count is used to count the number of such read transactions. Backpressure refers to the pressure exerted on the upstream by the downstream module or peripheral through a handshake signal to pause transmission. A clock cycle refers to the unit of data transmitted in one bus data clock cycle.

[0027] Specifically, the configuration register module 101 is used to acquire and save the channel configuration and threshold parameters, and write the channel configuration into the current working register module 102. The channel configuration includes channel enable, source transmission configuration, destination transmission configuration, data block transmission length, linked list item address and prefetch enable flag.

[0028] In this embodiment of the invention, the software writes the channel configuration into the configuration register module 101 through the advanced peripheral bus or a similar register interface. Various threshold parameters include a preset low water level threshold, a preset waiting threshold, and a safety margin. The configuration register module 101 provides various threshold parameters to the descriptor cutoff risk estimation module 108 and the payload data starvation risk estimation module 109, respectively.

[0029] The current working register module 102 is used to store the channel configuration and the description information of the currently executing data block, and to provide the channel configuration and the description information to the linked list item state machine 104, the source end data read state machine 105 and the destination end write state machine 106. The description information includes the source address, destination address, current data block transmission length, control field and next linked list item address.

[0030] The shadow descriptor register module 103 is used to store the next linked list item descriptor obtained by prefetching the address of the next linked list item, and to mark whether the next linked list item descriptor has been saved completely by the shadow descriptor validity flag. When the data block transfer currently being executed is completed and the shadow descriptor validity flag indicates that the next linked list item descriptor has been saved completely, the saved next linked list item descriptor is copied to the current working register module 102.

[0031] The setting of the shadow descriptor register module 103 allows the linked list item state machine 104 to read the next linked list item descriptor in advance and store it in the shadow descriptor register module 103 before the current data block has been moved. After the current data block is completed, it is immediately copied to the current working register module 102, thereby reducing the waiting caused by reading the next descriptor after the current data block is completed.

[0032] The linked list item state machine 104 is used to read the first linked list item descriptor from the system memory according to the linked list item address after the channel is enabled, and load the first linked list item descriptor into the current working register module 102. Then, when the prefetch condition is met, it generates an original linked list item read request to read the next linked list item descriptor, and writes the next linked list item descriptor into the shadow descriptor register module 103 after the next linked list item descriptor is returned, while setting the shadow descriptor valid flag.

[0033] Once the channel is enabled by software, the controller loads the current descriptor into the current working register module 102. The current descriptor includes the source address, destination address, current data block transmission length, control field, and next descriptor address. After loading, the source data read state machine 105 and the destination write state machine 106 can start executing the current data block transfer based on the current working register module 102.

[0034] The source-side data read state machine 105 is used to initiate a payload data read request for the currently executing data block based on the source address and the current data block transmission length, and to perform flow control based on the space of the source-side first-in-first-out buffer, the count of incomplete read transactions at the source end, and the state of the read address buffer.

[0035] The destination write state machine 106 is used to initiate a write request to write the payload data of the currently executing data block to the destination address according to the destination transmission configuration, and to perform flow control according to the water level, write response and back pressure status of the destination first-in-first-out buffer.

[0036] The data channel status monitoring module 107 is used to collect the data channel operating status, which includes whether the source end data read status machine 105 is waiting for the arbitration authorization of the read address arbitrator 1011 and the number of consecutive cycles of waiting for arbitration authorization, the water level of the source end first-in-first-out buffer, the count of incomplete read transactions at the source end, whether the destination end write status machine 106 is waiting for data, whether the read address buffer is full, and the read address channel congestion status.

[0037] Among them, the descriptor deadline risk, also known as the descriptor missed deadline risk, is used to characterize whether the descriptor of the next linked list item may not be ready before the current data block is completed. The payload data starvation risk is used to characterize whether continuing to issue linked list item prefetch requests or maintaining a high priority for linked list item reads may result in the source payload data read not receiving timely arbitration authorization, thereby causing the data buffer to be low-watered or empty.

[0038] The descriptor cutoff risk estimation module 108 is used to estimate the descriptor cutoff risk that the next linked list item descriptor cannot be prepared before the currently executing data block is moved, based on the remaining transmission volume of the currently executing data block, the payload data service rate, the linked list item read history delay, the shadow register copy delay, and the safety margin determined according to the threshold parameter.

[0039] The payload data starvation risk estimation module 109 is used to estimate the payload data starvation risk of the payload data read request not receiving timely arbitration authorization based on the water level of the source end first-in-first-out buffer, the number of cycles the source end data read state machine 105 waits for arbitration authorization, whether the destination end write state machine 106 is waiting for data, and the congestion status of the read address channel.

[0040] The adaptive prefetch strategy controller 1010 is used to generate control actions based on the descriptor cutoff risk and the payload data starvation risk. The control actions include allowing list item prefetching, pausing list item prefetching, increasing list item read priority, decreasing list item read priority, and updating the safety margin. Based on the control actions, the controller performs gating and priority generation on the original list item read request to obtain the list item read request, thereby controlling whether the list item read request is sent to the read address arbitrator 1011 and the list item read priority at the time of sending.

[0041] In this embodiment of the invention, the signals output by the adaptive prefetch strategy controller 1010 include a linked list item prefetch enable signal, a linked list item prefetch pause signal, a linked list item read priority boost signal, a linked list item read priority debuff signal, and a safety margin update signal. These signals act on the linked list item read request and the linked list item read priority. When resources are sufficient, the adaptive prefetch strategy controller 1010 allows descriptor prefetching and payload reading to proceed in parallel. When resources are insufficient, the adaptive prefetch strategy controller 1010 prioritizes channels with a risk of payload supply shortage. It should be noted that the gating and priority generation functions are implemented by the gating circuit and priority generation circuit inside the adaptive prefetch strategy controller 1010. Figure 1 Gating and priority generation logic between the middle linked list item state machine 104 and the address arbitrator 1011.

[0042] The read address arbitrator 1011 is used to receive the linked list item read request and the payload data read request, and select one of the linked list item read request and the payload data read request to be sent to the main interface read channel according to their respective dynamic priorities.

[0043] The adaptive prefetch strategy controller 1010 is configured to allow list item prefetching and increase the read priority of the list item when the descriptor cutoff risk is high; and to suspend list item prefetching or reduce the read priority of the list item when the descriptor cutoff risk is low and the payload data starvation risk is high, so that the next list item descriptor is ready before the currently executing data block transfer is completed, and to prevent the list item read request from preempting the arbitration authorization of the payload data read request.

[0044] The overall working principle of the adaptive prefetch arbitration direct memory access control system 100 proposed in this embodiment of the invention is as follows: Configuration register module 101 writes the channel configuration to current working register module 102. Current working register module 102 simultaneously provides current data block information to linked list item state machine 104, source data read state machine 105, and destination write state machine 106.

[0045] When the linked list item state machine 104 needs to prefetch the next descriptor, it generates an original linked list item read request. This original linked list item read request is not directly sent to the read address arbitrator 1011, but is gated and prioritized by the adaptive prefetch strategy controller 1010 before being sent to the read address arbitrator 1011.

[0046] The source-end data read state machine 105 and the destination-end write state machine 106 send their own operating states to the data channel state monitoring module 107. The data channel state monitoring module 107 normalizes the states and sends them to the descriptor cutoff risk estimation module 108 and the payload data starvation risk estimation module 109. The outputs of the two risk estimation modules enter the adaptive prefetching strategy controller 1010. The adaptive prefetching strategy controller 1010 enables, suspends, promotes, or demotes the read request of the linked list item according to the two types of risks.

[0047] When a linked list item read request is allowed and authorized by the read address arbitrator 1011, the main interface reads the next linked list item descriptor from the system memory. After the descriptor is returned, it is written to the shadow descriptor register module 103. When the current data block is completed, if the shadow descriptor is valid, the shadow descriptor is copied to the current working register module 102, thus entering the next data block transfer.

[0048] During implementation, the adaptive prefetch arbitration direct memory access control system 100 is divided into three levels according to its functional affiliation in the system architecture. For example... Figure 1As shown, the first level is software and data storage, including configuration register module 101 and system memory (specifically involving the linked list item descriptor chain and payload data area). This level is oriented towards software and system memory. The software writes channel configuration and threshold parameters into the configuration register module through the register interface, and the linked list item descriptors and payload data are stored in the system memory.

[0049] The second level is the internal logic of the direct memory access channel, including the current working register module 102, the shadow descriptor register module 103, the linked list item state machine 104, the source data read state machine 105, the destination write state machine 106, the data channel status monitoring module 107, the descriptor cutoff risk estimation module 108, the payload data starvation risk estimation module 109, and the adaptive prefetch strategy controller 1010. This level is the internal logic of the direct memory access channel, responsible for the execution of current data block transfer, the acquisition of data channel operating status, the estimation of descriptor cutoff risk and payload data starvation risk, and the generation of control actions.

[0050] The third layer is the master interface and arbitration, including the read address arbitrator 1011 and the master interface read channel. This layer is oriented towards the on-chip interconnect and system memory, and is responsible for arbitrating read requests according to dynamic priorities and sending the selected request to the master interface read channel.

[0051] Based on the above hierarchical division, the adaptive prefetch strategy controller 1010 of this embodiment is located inside the direct memory access channel and only acts on the linked list item read request and linked list item read priority of this channel. It does not require changing the software configuration process and descriptor format of the software and data storage hierarchy, nor does it require changing the structure of the main interface and arbitration hierarchy. The hardware modification is small and it has good compatibility and scalability in multi-channel concurrent scenarios.

[0052] Furthermore, the adaptive prefetching strategy controller 1010 generates the control action, specifically by determining the following in the order of the shadow descriptor validity flag, the descriptor cutoff risk, and the payload data starvation risk: When the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved, a control action is generated to prevent linked list item prefetching, and no new linked list item read requests are submitted to the read address arbitrator 1011. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been fully saved and the descriptor cutoff risk is high, a control action is generated to allow the linked list item prefetching, and the priority of reading the linked list item is raised to a higher priority level than the priority level of the payload data reading request. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been fully saved, the descriptor cutoff risk is low, and the payload data starvation risk is high, a control action to pause linked list item prefetching is generated. When the shadow descriptor valid flag indicates that the next linked list item descriptor has not been completely saved, the descriptor cutoff risk is low, and the payload data starvation risk is low, a control action that allows linked list item prefetching is generated, and the linked list item read request is submitted with the channel base priority, which is the channel priority saved by the configuration register module 101.

[0053] Furthermore, the descriptor cutoff risk estimation module 108 estimates the descriptor cutoff risk, specifically as follows: Calculate the remaining transmission time determination value for the current data block. The remaining transmission time determination value for the current data block is the remaining number of time steps of the currently executing data block divided by the service rate determination value and rounded up. The remaining number of time steps is obtained by subtracting the number of time steps completed at the source end from the total number of time steps of the current data block. The number of time steps completed at the source end is counted by the source end completed time step counter. The source end completed time step counter is incremented by 1 every time the main interface returns 1 time step of effective payload read data. The service rate determination value is the number of effective payload read data time steps returned within the statistical window, which is calculated with a preset number of clock cycles as the statistical window. As a specific implementation, the preset number of the statistics window can be 64 clock cycles.

[0054] If the remaining transmission time of the current data block is less than or equal to the sum of the descriptor preparation time and the safety margin, the descriptor cutoff risk is determined to be high; otherwise, the descriptor cutoff risk is determined to be low.

[0055] The descriptor preparation time determination value is the sum of the historical maximum number of cycles during which the linked list item read request waits for the arbitration authorization of the read address arbitrator 1011, the historical maximum number of cycles from when the linked list item read request is accepted by the main interface until the next linked list item descriptor returns, and the fixed number of cycles during which the shadow descriptor register module 103 writes and prepares for copying. The two historical maximum number of cycles are counted by a hardware saturation counter and the maximum value is taken from the most recent N linked list item reads, where N is a positive integer. As a specific implementation, N can be 16, and the fixed number of cycles for writing and copying preparation of the shadow descriptor register module 103 is the number of cycles required for writing and copying control of the shadow descriptor register module 103 in the implementation.

[0056] The update of the linked list item read history delay in the descriptor cutoff risk estimation module 108 is specifically as follows: When the linked list item read request does not receive arbitration authorization from the read address arbitrator 1011, or when it has been issued but the next linked list item descriptor has not yet returned, the number of cycles for the linked list item read request to wait for arbitration authorization and the descriptor read return delay are updated. The updated historical delay is used for the calculation of the descriptor preparation time determination value in the next round.

[0057] The payload data starvation risk estimation module 109 estimates the payload data starvation risk, specifically as follows: If the current data volume of the source-side first-in-first-out buffer is less than or equal to a preset low watermark threshold, and the number of cycles during which the payload data read request continuously waits for the arbitration authorization of the read address arbitrator 1011 is greater than or equal to a preset waiting threshold, the payload data starvation risk is determined to be high; otherwise, the payload data starvation risk is determined to be low. The current data volume of the source-side first-in-first-out buffer is given by a water level counter, and the number of cycles during which the payload data read request continuously waits for arbitration authorization is given by a waiting counter. The waiting counter increments when the payload data read request is valid but does not obtain arbitration authorization from the read address arbitrator 1011, and is cleared when arbitration authorization is obtained or the payload data read request is withdrawn. The preset low water level threshold and the preset waiting threshold are threshold parameters stored in the configuration register module 101.

[0058] The adaptive prefetching strategy controller 1010 performs gating and priority generation on the original linked list item read requests, specifically as follows: The original linked list item read request is ANDed with the allow prefetch signal to obtain the linked list item read request. The allow prefetch signal is valid when the control action is to allow linked list item prefetching, and the linked list item read priority determined according to the control action is sent to the read address arbitrator 1011.

[0059] The shadow descriptor register module 103 copies the saved next linked list item descriptor to the current working register module 102, specifically as follows: The source address, destination address, transmission length, control field, and next descriptor address stored in the shadow descriptor register module 103 are copied to the current working register module 102 as the description information for the next data block. After the copying is completed, the shadow descriptor validity flag is cleared or updated.

[0060] The data channel status monitoring module 107 is further configured to standardize the collected data channel operating status and send it to the descriptor cutoff risk estimation module 108 and the payload data starvation risk estimation module 109 respectively.

[0061] The read address arbitrator 1011 is also used to receive the destination status read request, and select one of the following to be sent to the main interface read channel according to the dynamic priority of the linked list item read request, the payload data read request and the destination status read request.

[0062] The adaptive prefetch arbitration scheme of this invention can be implemented as an enhancement module between the linked list item state machine 104 and the read address arbitrator 1011. It mainly functions to handle linked list item read requests and linked list item read priorities. It does not require changes to the descriptor format, software configuration process, or payload data main path. The hardware modifications are minor, and it has strong compatibility with existing linked list direct memory access controller architectures.

[0063] The beneficial effects achieved by this invention are as follows: it provides an adaptive prefetch arbitration direct memory access control system 100. This system collects the data channel operating status through a data channel status monitoring module 107, and estimates the descriptor cutoff risk and payload data starvation risk by a descriptor cutoff risk estimation module 108 and a payload data starvation risk estimation module 109, respectively. The adaptive prefetch strategy controller 1010 performs gating and priority generation on linked list item read requests based on the two types of risks. When the descriptor cutoff risk is high, prefetching is allowed and the priority is increased. When the payload data starvation risk is high and the descriptor is not urgent, prefetching is paused or the priority is reduced. The timing of descriptor prefetching and the read priority are dynamically adjusted according to the load, realizing a balance between timely preparation of the next descriptor and continuous supply of payload data. This reduces data block switching idling and source buffer idleness, ensures the continuity of payload data reading, improves the effective bandwidth utilization of the shared memory path, and improves the stability of transport latency.

[0064] Example 2 This invention also provides an adaptive prefetch arbitration direct memory access control method, please refer to... Figure 2 , Figure 2 This is a flowchart of an adaptive prefetch arbitration direct memory access control method provided in an embodiment of the present invention. The adaptive prefetch arbitration direct memory access control method is implemented based on the adaptive prefetch arbitration direct memory access control system 100 described in Embodiment 1 above. The adaptive prefetch arbitration direct memory access control method includes the following steps: S201, the channel configuration and threshold parameters are obtained and saved through the configuration register module 101, and the channel configuration saved by the configuration register module 101 is written into the current working register module 102. After the channel enable in the channel configuration takes effect, the first linked list item descriptor is read from the system memory according to the linked list item address in the channel configuration through the linked list item state machine 104, and the first linked list item descriptor is loaded into the current working register module 102 to obtain the description information of the currently executing data block. The description information includes the source address, destination address, current data block transmission length, control field and next linked list item address.

[0065] S202, the source-end data read state machine 105 initiates a request to read the payload data of the currently executing data block according to the source address and the current data block transmission length. At the same time, the destination-end write state machine 106 initiates a write request to write the payload data of the currently executing data block to the destination address according to the destination transmission configuration, so as to execute the transfer of the currently executing data block.

[0066] During the current data block transfer, the return status of the source end payload read data is continuously monitored. Whenever the main interface returns 1 tick of payload read data to the channel, the source end completed tick count counter is incremented by 1. The remaining tick count of the current data block is obtained by subtracting the source end completed tick count from the total number of ticks of the current data block.

[0067] S203, when the prefetch condition is met, the linked list item state machine 104 generates an original linked list item read request to read the next linked list item descriptor, wherein the next linked list item descriptor is a descriptor read from the system memory according to the address of the next linked list item.

[0068] The purpose of this step is to prepare in advance for the request to read the next linked list item descriptor. The original linked list item read request is not directly sent to the read address arbitrator 1011. Whether to send it and the priority when sending it are determined by subsequent steps based on the risk status.

[0069] S204, the data channel operation status is collected by the data channel status monitoring module 107. The data channel operation status includes whether the source end data read status machine 105 is waiting for the arbitration authorization of the read address arbitrator 1011 and the number of consecutive cycles of waiting for arbitration authorization, the water level of the source end first-in-first-out buffer, the count of incomplete read transactions at the source end, whether the destination end write status machine 106 is waiting for data, whether the read address buffer is full, and the read address channel congestion status.

[0070] The current data volume of the source-side first-in-first-out buffer is given by the water level counter, and the number of cycles during which the source-side payload data read request continuously waits for arbitration authorization is given by the waiting counter. The waiting counter increments when the source-side payload data read request is valid but has not been authorized by the read address arbitrator 1011, and is cleared when arbitration authorization is obtained or the request is revoked.

[0071] S205, the descriptor cutoff risk estimation module 108 estimates the descriptor cutoff risk that the next linked list item descriptor cannot be prepared before the currently executing data block is moved, based on the remaining transmission volume of the currently executing data block, the payload data service rate, the linked list item read history delay, the shadow register copy delay, and the safety margin determined by the threshold parameter.

[0072] The purpose of this step is to quantify whether the next linked list item descriptor can be prepared before the current data block is completed. Specifically, using a statistical window of 64 clock cycles, the number of payload read data cycles returned within this window is counted and used as the service rate determination value. The remaining transmission time determination value for the current data block is equal to the remaining number of cycles for the current data block divided by this service rate determination value, rounded up. The descriptor preparation time determination value is the sum of three parts: the historical maximum number of cycles for the linked list item read request to wait for read address arbitration authorization, the historical maximum number of cycles from when the linked list item read request is accepted by the main interface to when the descriptor data is returned, and the fixed number of cycles for writing and copying preparation by the shadow descriptor register module 103. The first two items are counted by a hardware saturation counter, and the maximum value is taken from the last 16 linked list item reads. The third item is fixed as the number of cycles required for writing and copying control of the shadow descriptor register module 103 in the implementation. If the remaining transmission time of the current data block is less than or equal to the sum of the descriptor preparation time determination value and the safety margin, the risk of the descriptor missing the deadline is determined to be high; otherwise, the risk is determined to be low.

[0073] S206, the payload data starvation risk estimation module 109 estimates the payload data starvation risk of the payload data read request not receiving timely arbitration authorization based on the water level of the source end first-in-first-out buffer, the number of cycles the source end data read state machine 105 waits for arbitration authorization, whether the destination end write state machine 106 is waiting for data, and the congestion status of the read address channel.

[0074] The purpose of this step is to quantify whether continuing to issue list item prefetch requests will crowd out payload data reading. Specifically, two conditions are used to determine the risk of payload data starvation: first, the current data volume in the source-side FIFO buffer is less than or equal to a preset low-water mark threshold; second, the number of cycles during which the source-side payload data read requests continuously wait for read address arbitration authorization is greater than or equal to a preset waiting threshold. When both conditions are met, the risk of payload data starvation is determined to be high; otherwise, the risk of payload data starvation is determined to be low.

[0075] S207, the adaptive prefetch strategy controller 1010 generates control actions based on the descriptor cutoff risk and the payload data starvation risk. Based on these control actions, the original linked list item read request is gated and prioritized to obtain a linked list item read request. The control actions include allowing linked list item prefetching, pausing linked list item prefetching, increasing linked list item read priority, decreasing linked list item read priority, and updating the safety margin. Specifically, when the descriptor cutoff risk is high, linked list item prefetching is allowed and the linked list item read priority is increased. When the descriptor cutoff risk is low and the payload data starvation risk is high, linked list item prefetching is paused or the linked list item read priority is decreased, so that the next linked list item descriptor is prepared before the currently executing data block transfer is completed, and to prevent the linked list item read request from preempting the arbitration authorization of the payload data read request.

[0076] Specifically, the descriptor missed deadline risk assessment result, the payload data starvation risk assessment result, and the validity flag of the shadow descriptor register module 103 are jointly input into the adaptive prefetch strategy controller 1010. The controller prioritizes determining whether the shadow descriptor is already valid. If the shadow descriptor is not valid, then determine if the descriptor is close to its deadline. If the descriptor is not close to its deadline, then determine if the risk of payload data starvation is high.

[0077] When the shadow descriptor is already valid, output a signal to disable prefetching, and stop submitting new list item read requests to the read address arbitrator 1011, waiting for the next evaluation cycle.

[0078] When the shadow descriptor is not valid and the descriptor is close to its deadline, output a prefetch enable signal and prioritize the list item read request to a higher priority than the source payload read request.

[0079] When the shadow descriptor is invalid, the descriptor is not nearing its deadline, and the risk of payload data starvation is high, a pause prefetch signal is output, and the list item read request remains in an unissued state, waiting for the next evaluation cycle. When the shadow descriptor is invalid, the descriptor is not nearing its deadline, and the risk of payload data starvation is low, a allow prefetch signal is output, and the list item read request is submitted using the channel-based priority.

[0080] S208, the read address arbitrator 1011 receives the linked list item read request and the payload data read request, and selects one of the linked list item read request and the payload data read request to be sent to the main interface read channel according to their respective dynamic priorities.

[0081] Specifically, the original linked list item read request is ANDed with the allow prefetch signal to generate a linked list item read request. The determined linked list item read priority is then sent to the read address arbitrator 1011, which arbitrates between the linked list item read request and the source payload data read request. If the linked list item read request has not yet been granted arbitration authorization, or has been issued but the descriptor data has not yet been returned, the number of cycles waiting for arbitration authorization and the descriptor read return delay are updated. The updated historical delay is used for the calculation of the descriptor preparation time determination value in the next round. After the update is completed, the process returns to S204 to enter the next evaluation cycle.

[0082] S209: After the linked list item read request obtains arbitration authorization from the read address arbitrator 1011 and the next linked list item descriptor is returned, the returned next linked list item descriptor is written to the shadow descriptor register module 103, and the shadow descriptor valid flag is set. The shadow descriptor valid flag is used to mark whether the next linked list item descriptor has been saved completely. When the currently executing data block transfer is completed and the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved completely, the next linked list item descriptor saved in the shadow descriptor register module 103 is copied to the current working register module 102 as the description information of the next data block, and the process returns to step S202 to execute the transfer of the next data block.

[0083] Specifically, after writing the descriptor of the next linked list item returned to the shadow descriptor register module 103 and setting the shadow descriptor valid flag, the system continues to determine whether the current data block is complete. If the current data block is not yet complete, the system returns to S204 to continue monitoring the execution status of the current data block, and prioritizes identifying the status of the shadow descriptor being valid in subsequent evaluation cycles, thereby preventing repeated prefetching. When the current data block is complete and the shadow descriptor is valid, the source address, destination address, transmission length, control field, and next descriptor address in the shadow descriptor register module 103 are copied to the current working register module 102 as the current descriptor of the next data block. After the copying is completed, the shadow descriptor valid flag is cleared or updated, and the system returns to S202 to begin monitoring the execution status of the next data block.

[0084] The system and method proposed in this invention can be applied to scenarios such as RISC-V (Reduced Instruction Set Computing) high-performance servers, server-level systems-on-a-chip, network interface packet handling, storage input / output data handling, data exchange between processors and on-chip accelerators, data supply for artificial intelligence accelerators, memory-to-memory handling, and chained handling between peripherals and memory or memory and peripherals. In high-bandwidth, low-latency computing systems represented by RISC-V high-performance servers, processor cores, network interfaces, storage controllers, accelerators, and multiple direct memory access channels may concurrently access shared on-chip interconnects and system memory. The solution in this invention helps reduce the interference of descriptor reads on payload data reads under the above-mentioned concurrent access conditions, reduce data block switching waits and data path jitter, improve effective storage bandwidth utilization, and improve data handling latency and tail latency stability. In real-time streaming scenarios involving chained transport of small data blocks, multi-channel concurrency, storage of descriptors in double-rate synchronous dynamic random access memory, limited read transaction capacity at the source end, shallow first-in-first-out buffers for channels, congestion of read address arbitrators, and sensitivity to tail delay, the solution of this invention is more effective.

[0085] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0086] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0087] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A direct memory access control system with adaptive prefetch arbitration, characterized in that, This includes a configuration register module, a current working register module, a shadow descriptor register module, a linked list item state machine, a source data read state machine, a destination write state machine, a data channel status monitoring module, a descriptor cutoff risk estimation module, a payload data starvation risk estimation module, an adaptive prefetch strategy controller, and a read address arbitrator, wherein: The configuration register module is used to acquire and save channel configuration and threshold parameters, and write the channel configuration into the current working register module. The channel configuration includes channel enable, source transmission configuration, destination transmission configuration, data block transmission length, linked list item address and prefetch enable flag. The current working register module is used to store the channel configuration and the description information of the currently executing data block, and to provide the channel configuration and the description information to the linked list item state machine, the source end data read state machine and the destination end write state machine. The description information includes the source address, destination address, current data block transmission length, control field and next linked list item address. The shadow descriptor register module is used to store the next linked list item descriptor obtained by prefetching based on the address of the next linked list item, and to mark whether the next linked list item descriptor has been saved completely by the shadow descriptor valid flag. When the data block being executed is completed and the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved completely, the saved next linked list item descriptor is copied to the current working register module. The linked list item state machine is used to read the first linked list item descriptor from the system memory according to the linked list item address after the channel is enabled, load the first linked list item descriptor into the current working register module, and then generate an original linked list item read request to read the next linked list item descriptor when the prefetch condition is met, and write the next linked list item descriptor into the shadow descriptor register module after the next linked list item descriptor is returned, while setting the shadow descriptor valid flag. The source-side data read state machine is used to initiate a payload data read request for the currently executing data block based on the source address and the current data block transmission length, and to perform flow control based on the space of the source-side first-in-first-out buffer, the count of incomplete read transactions at the source, and the state of the read address buffer. The destination write state machine is used to initiate a write request to write the payload data of the currently executing data block to the destination address according to the destination transmission configuration, and to perform flow control according to the water level, write response and back pressure status of the destination first-in-first-out buffer. The data channel status monitoring module is used to collect the data channel operating status, which includes whether the source end data read status machine is waiting for the arbitration authorization of the read address arbitrator and the number of cycles of waiting for arbitration authorization, the water level of the source end first-in-first-out buffer, the count of the source end incomplete read transactions, whether the destination end write status machine is waiting for data, whether the read address buffer is full, and the read address channel congestion status. The descriptor cutoff risk estimation module is used to estimate the descriptor cutoff risk that the next linked list item descriptor cannot be prepared before the currently executing data block is moved, based on the remaining transmission volume of the currently executing data block, the payload data service rate, the linked list item read history delay, the shadow register copy delay, and the safety margin determined according to the threshold parameter. The payload data starvation risk estimation module is used to estimate the payload data starvation risk of the payload data read request not receiving timely arbitration authorization based on the water level of the source end first-in-first-out buffer, the number of cycles the source end data read state machine waits for arbitration authorization, whether the destination end write state machine is waiting for data, and the congestion status of the read address channel. The adaptive prefetch strategy controller is used to generate control actions based on the descriptor cutoff risk and the payload data starvation risk. The control actions include allowing list item prefetching, pausing list item prefetching, increasing list item read priority, decreasing list item read priority, and updating the safety margin. Based on the control actions, the controller performs gating and priority generation on the original list item read request to obtain the list item read request, thereby controlling whether the list item read request is sent to the read address arbitrator and the list item read priority at the time of sending. The read address arbitrator is used to receive the linked list item read request and the payload data read request, and select one of the linked list item read request and the payload data read request to be sent to the main interface read channel according to their respective dynamic priorities; The adaptive prefetch strategy controller is configured to allow list item prefetching and increase the read priority of the list item when the descriptor cutoff risk is high; and to suspend list item prefetching or reduce the read priority of the list item when the descriptor cutoff risk is low and the payload data starvation risk is high, so that the next list item descriptor is ready before the currently executing data block transfer is completed, and to prevent the list item read request from preempting the arbitration authorization of the payload data read request.

2. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The adaptive prefetching strategy controller generates the control action by determining the following in the order of shadow descriptor validity flag, descriptor cutoff risk, and payload data starvation risk: When the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved, a control action is generated to prevent linked list item prefetching, and no new linked list item read requests are submitted to the read address arbitrator. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been fully saved and the descriptor cutoff risk is high, a control action is generated to allow the linked list item prefetching, and the priority of reading the linked list item is raised to a higher priority level than the priority level of the payload data reading request. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been fully saved, the descriptor cutoff risk is low, and the payload data starvation risk is high, a control action to pause linked list item prefetching is generated. When the shadow descriptor validity flag indicates that the next linked list item descriptor has not been completely saved, the descriptor cutoff risk is low, and the payload data starvation risk is low, a control action that allows linked list item prefetching is generated, and the linked list item read request is submitted with the channel base priority, which is the channel priority saved by the configuration register module.

3. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The descriptor cutoff risk estimation module estimates the descriptor cutoff risk, specifically as follows: Calculate the remaining transmission time determination value for the current data block. The remaining transmission time determination value for the current data block is the remaining number of time steps of the currently executing data block divided by the service rate determination value and rounded up. The remaining number of time steps is obtained by subtracting the number of time steps completed at the source end from the total number of time steps of the current data block. The number of time steps completed at the source end is counted by the source end completed time step counter. The source end completed time step counter is incremented by 1 every time the main interface returns 1 time step of effective payload read data. The service rate determination value is the number of effective payload read data time steps returned within the statistical window, which is calculated with a preset number of clock cycles as the statistical window. If the remaining transmission time of the current data block is less than or equal to the sum of the descriptor preparation time and the safety margin, the descriptor cutoff risk is determined to be high; otherwise, the descriptor cutoff risk is determined to be low.

4. The direct memory access control system with adaptive prefetch arbitration according to claim 3, characterized in that, The descriptor preparation time determination value is the sum of the historical maximum number of cycles during which the linked list item read request waits for arbitration authorization from the read address arbitrator, the historical maximum number of cycles from when the linked list item read request is accepted by the main interface until the next linked list item descriptor returns, and the fixed number of cycles during which the shadow descriptor register module writes and copies. The two historical maximum number of cycles are counted by a hardware saturation counter and the maximum value is taken from the most recent N linked list item reads, where N is a positive integer. The update of the linked list item read history delay in the descriptor cutoff risk estimation module is specifically as follows: When the read request for a linked list item does not receive arbitration authorization from the read address arbitrator, or when it has been issued but the next linked list item descriptor has not yet returned, the number of cycles during which the read request waits for arbitration authorization and the descriptor read return delay are updated. The updated historical delay is used to calculate the descriptor preparation time determination value in the next round.

5. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The payload data starvation risk estimation module estimates the payload data starvation risk, specifically as follows: If the current data volume of the source-side first-in-first-out buffer is less than or equal to a preset low watermark threshold, and the number of cycles during which the payload data read request continuously waits for arbitration authorization from the read address arbitrator is greater than or equal to a preset waiting threshold, the payload data starvation risk is determined to be high; otherwise, the payload data starvation risk is determined to be low. The current data volume of the source-side first-in-first-out buffer is given by a water level counter, and the number of cycles during which the payload data read request continuously waits for arbitration authorization is given by a waiting counter. The waiting counter increments when the payload data read request is valid but has not obtained arbitration authorization from the read address arbitrator, and is cleared when arbitration authorization is obtained or the payload data read request is withdrawn. The preset low water level threshold and the preset waiting threshold are threshold parameters stored in the configuration register module.

6. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The adaptive prefetching strategy controller performs gating and priority generation on the original linked list item read requests, specifically as follows: The original list item read request is ANDed with the allow prefetch signal to obtain the list item read request. The allow prefetch signal is valid when the control action is to allow list item prefetching, and the list item read priority determined according to the control action is sent to the read address arbitrator.

7. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The shadow descriptor register module copies the saved next linked list item descriptor to the current working register module, specifically as follows: The source address, destination address, transmission length, control field, and next descriptor address stored in the shadow descriptor register module are copied to the current working register module as the description information for the next data block. After the copying is completed, the shadow descriptor validity flag is cleared or updated.

8. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The data channel status monitoring module is also used to standardize the collected data channel operating status and send it to the descriptor cutoff risk estimation module and the payload data starvation risk estimation module, respectively.

9. The direct memory access control system with adaptive prefetch arbitration according to claim 1, characterized in that, The read address arbitrator is also used to receive destination status read requests and select one of them to send to the main interface read channel according to the dynamic priority of the linked list item read request, the payload data read request and the destination status read request.

10. A direct memory access control method with adaptive prefetch arbitration, implemented based on the direct memory access control system with adaptive prefetch arbitration as described in any one of claims 1 to 9, characterized in that, Includes the following steps: S201, the channel configuration and threshold parameters are obtained and saved through the configuration register module, and the channel configuration saved by the configuration register module is written into the current working register module. After the channel enable in the channel configuration takes effect, the first linked list item descriptor is read from the system memory according to the linked list item address in the channel configuration through the linked list item state machine, and the first linked list item descriptor is loaded into the current working register module to obtain the description information of the currently executing data block. The description information includes the source address, destination address, current data block transmission length, control field and next linked list item address. S202, the source end data read state machine initiates a request to read the payload data of the currently executing data block according to the source address and the current data block transmission length. At the same time, the destination end write state machine initiates a write request to write the payload data of the currently executing data block to the destination address according to the destination end transmission configuration, so as to execute the transfer of the currently executing data block. S203, when the prefetch condition is met, the linked list item state machine generates an original linked list item read request to read the next linked list item descriptor, wherein the next linked list item descriptor is a descriptor read from the system memory according to the address of the next linked list item; S204, the data channel operation status is collected through the data channel status monitoring module. The data channel operation status includes whether the source end data read status machine is waiting for arbitration authorization from the read address arbitrator and the number of consecutive cycles of waiting for arbitration authorization, the water level of the source end first-in-first-out buffer, the count of incomplete read transactions at the source end, whether the destination end write status machine is waiting for data, whether the read address buffer is full, and the read address channel congestion status. S205, the descriptor cutoff risk estimation module estimates the descriptor cutoff risk that the next linked list item descriptor cannot be prepared before the currently executing data block is moved, based on the remaining transmission volume of the currently executing data block, the payload data service rate, the linked list item read history delay, the shadow register copy delay, and the safety margin determined by the threshold parameter. S206, the payload data starvation risk estimation module estimates the payload data starvation risk of the payload data read request not receiving timely arbitration authorization based on the water level of the source end first-in-first-out buffer, the number of continuous cycles of the source end data read state machine waiting for arbitration authorization, whether the destination end write state machine is waiting for data, and the congestion status of the read address channel. S207, the adaptive prefetch strategy controller generates control actions based on the descriptor cutoff risk and the payload data starvation risk. Based on these control actions, the original linked list item read requests are gated and prioritized to obtain linked list item read requests. The control actions include allowing linked list item prefetching, pausing linked list item prefetching, increasing linked list item read priority, decreasing linked list item read priority, and updating the safety margin. Specifically, when the descriptor cutoff risk is high, linked list item prefetching is allowed and the linked list item read priority is increased. When the descriptor cutoff risk is low and the payload data starvation risk is high, linked list item prefetching is paused or the linked list item read priority is decreased, so that the next linked list item descriptor is prepared before the currently executing data block transfer is completed, and to prevent the linked list item read request from preempting the arbitration authorization of the payload data read request. S208, the linked list item read request and the payload data read request are received through the read address arbitrator, and one of them is selected and sent to the main interface read channel according to the dynamic priority of the linked list item read request and the payload data read request. S209: After the linked list item read request obtains arbitration authorization from the read address arbitrator and the next linked list item descriptor is returned, the returned next linked list item descriptor is written to the shadow descriptor register module, and the shadow descriptor valid flag is set. The shadow descriptor valid flag is used to mark whether the next linked list item descriptor has been saved completely. When the currently executing data block transfer is completed and the shadow descriptor valid flag indicates that the next linked list item descriptor has been saved completely, the next linked list item descriptor saved in the shadow descriptor register module is copied to the current working register module as the description information of the next data block, and the process returns to step S202 to execute the transfer of the next data block.

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