Instruction processing method, processor core, processor and instruction processing device

Abstract

The application provides an instruction processing method, a processor core, a processor, an instruction processing device, a video encoding method, a video decoding method, a video encoding device, a video decoding device, a computer readable storage medium and a computer program product. The instruction processing method comprises the following steps: obtaining a Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate a first matrix to be involved in operation; generating a matrix multiplication instruction for the first matrix and generating a matrix transposition instruction for the operation result of the matrix multiplication instruction according to the Hadamard transform instruction; executing the matrix multiplication instruction and the matrix transposition instruction to obtain a target operation result for the Hadamard transform instruction. Therefore, the scheme provided by the application can reduce the number of operator instructions required to be executed in the Hadamard transform, improve the instruction execution efficiency, reduce the data access delay, and improve the end-to-end frame rate in video encoding.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an instruction processing method, a processor core, a processor, an instruction processing device, a video encoding method, a video decoding method, a video encoding device, a video decoding device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] With the continuous development of the high-definition video industry, video compression methods such as H.264 and H.265 video coding have been widely used in real-time communication, live streaming, and gaming. In H.264 and H.265 video coding scenarios, to eliminate spatial redundancy in images, Hadamard Transform is typically performed to evaluate the similarity of residual signal (the difference matrix between the original pixels and the predicted pixels) blocks. However, in related technologies, the Hadamard Transform (HT) involves too many operator instructions (potentially dozens or more), leading to low instruction execution efficiency and memory access latency. This reduces the number of video frames processed per unit time, lowering the end-to-end frame rate in video coding.

[0003] Therefore, improving the end-to-end frame rate in video encoding has become an urgent technical problem to be solved. Summary of the Invention

[0004] This application provides an instruction processing method, a processor core, a processor, a system-on-a-chip, an instruction device, a video encoding method, a video decoding method, a video encoding device, a video decoding device, an electronic device, a computer-readable storage medium, and a computer program product, which can reduce the number of operator instructions to be processed in Hadamard transform, thereby improving the end-to-end frame rate in video encoding. The specific solution is as follows: In a first aspect, embodiments of this application provide an instruction processing method, the method comprising: Obtain the Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate the first matrix to be involved in the operation. Based on the Hadamard transform instruction, a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the result of the matrix multiplication instruction are generated. Execute the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction.

[0005] Secondly, embodiments of this application provide a processor core, the processor core comprising: The instruction acquisition unit is used to acquire the Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate the first matrix to be involved in the operation. The instruction extension unit is configured to generate a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the result of the matrix multiplication instruction, based on the Hadamard transform instruction. The instruction execution unit is used to execute the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction.

[0006] Thirdly, embodiments of this application provide a processor, the processor including one or more processor cores as described in the second aspect.

[0007] Fourthly, embodiments of this application provide an instruction processing apparatus, the apparatus including components for processing the method as described in the first aspect.

[0008] Fifthly, embodiments of this application provide a video encoding method, the method comprising: Get the residual matrix corresponding to the current block; Multiply the coefficient matrix that matches the residual matrix by the residual matrix to obtain the second matrix; Transpose the second matrix to obtain the third matrix; Multiply the coefficient matrix by the third matrix to obtain the fourth matrix; The fourth matrix is ​​normalized, and the absolute values ​​of the elements of the normalized matrix are summed to obtain the absolute difference of the transformation. The coding parameters of the current block are determined based on the absolute difference of the transform, and the frequency domain coefficients of the current block are determined based on the coding parameters. The encoding parameters and the frequency domain coefficients are added to the video bitstream.

[0009] Sixthly, embodiments of this application provide a video encoding apparatus, the video encoding apparatus comprising: The acquisition unit is used to acquire the residual matrix corresponding to the current block; The first calculation unit is used to multiply the coefficient matrix that matches the residual matrix by the residual matrix to obtain the second matrix; The second calculation unit is used to transpose the second matrix to obtain the third matrix; The third calculation unit is used to multiply the coefficient matrix by the third matrix to obtain the fourth matrix; The normalization unit is used to normalize the fourth matrix and accumulate the absolute values ​​of the elements of the normalized matrix to obtain the sum of the absolute differences of the transformations. The first determining unit is configured to determine the coding parameters of the current block based on the transform absolute difference and to determine the frequency domain coefficients of the current block according to the coding parameters; An incorporation unit is used to add the encoding parameters and the frequency domain coefficients to the video bitstream.

[0010] Seventhly, embodiments of this application provide a video decoding method, the method comprising: Receive video bitstream; Receive coding parameters and frequency domain coefficients related to the current block from the video bitstream; The residual processing method for the current block is determined based on the encoding parameters; Based on the residual processing method, the frequency domain coefficients are dequantized and inversely transformed to obtain the target residual matrix of the current block; The current block is reconstructed based on the target residual matrix.

[0011] Eighthly, embodiments of this application provide a video decoding apparatus, the video decoding apparatus comprising: A receiving unit is configured to receive a video bitstream and receive from the video bitstream encoding parameters associated with the current block and frequency domain coefficients associated with the current block; The second determining unit is used to determine the residual processing method of the current block based on the encoding parameters; The processing unit is used to perform inverse quantization and inverse transformation processing on the frequency domain coefficients based on the residual processing method to obtain the target residual matrix of the current block; A reconstruction unit is used to reconstruct the current block based on the target residual matrix.

[0012] In a ninth aspect, embodiments of this application provide a computer-readable storage medium storing an instruction set and a video bitstream, the instruction set being executable by one or more processors to generate the video bitstream, the method including the method described in the first or fifth aspect.

[0013] In a tenth aspect, embodiments of this application provide a computer program product, including a computer program / instructions, wherein the computer program / instructions, when executed by a processor, implement the method described in the first, fifth, or sixth aspect.

[0014] Eleventhly, embodiments of this application provide a system-on-a-chip, the system-on-a-chip including one or more processors as provided in the third aspect of this application.

[0015] In a twelfth aspect, embodiments of this application also provide an electronic device, including: a processor; and a memory for storing programs related to instruction processing methods, video encoding methods, or video decoding methods. After the electronic device is powered on and runs the program through the processor, it executes the methods described in the first, fifth, or sixth aspects.

[0016] Compared with the prior art, this application has the following advantages: The first embodiment of this application provides an instruction processing method, comprising the following steps: obtaining a Hadamard transform instruction to be processed; the Hadamard transform instruction indicating a first matrix to be involved in the operation; generating a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the operation result of the matrix multiplication instruction based on the Hadamard transform instruction; executing the matrix multiplication instruction and the matrix transpose instruction to obtain a target operation result for the Hadamard transform instruction. It can be seen that in this embodiment, by generating a matrix multiplication instruction and a matrix transpose instruction, the target operation result for the Hadamard transform instruction can be obtained by executing these two instructions. In contrast, in the prior art, Hadamard transform instructions typically need to be implemented using the Hadamard transform formula, which will be broken down into dozens of instructions (e.g., forty or fifty), requiring too many operator instructions to be executed. Therefore, the instruction processing method provided in this embodiment reduces the number of operator instructions required to be executed in the Hadamard transform. This improves instruction execution efficiency, reduces data memory access latency, thereby increasing the number of video frames processed per unit time and improving the end-to-end frame rate in video encoding. Attached Figure Description

[0017] Figure 1 This is a flowchart of the instruction processing method provided in the first embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the matrix multiplication instruction in the instruction processing method provided in the first embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the matrix transpose instruction in the instruction processing method provided in the first embodiment of this application.

[0020] Figure 4 This is a schematic diagram of the processor core provided in the second embodiment of this application.

[0021] Figure 5 This is a flowchart of the video encoding method provided in the embodiments of this application.

[0022] Figure 6 This is a flowchart of the video decoding method provided in the embodiments of this application.

[0023] Figure 7This is a structural block diagram of an example of an electronic device for instruction processing, video encoding, or video decoding provided in the eighth embodiment of this application. Detailed Implementation

[0024] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0025] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0026] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0027] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0028] Based on the reasons mentioned in the background art, the first embodiment of this application provides an instruction processing method to reduce the number of operator instructions to be processed in the Hadamard transform, thereby improving the end-to-end frame rate in video encoding. This method can, for example, be applied to a processor (central processing unit, or CPU).

[0029] The instruction processing method provided in this application embodiment can be used to calculate the SATD (Sum of Absolute Transformed Difference) of residual signals in video coding scenarios. Specifically, in video coding scenarios such as H.264 and H.265, SATD is a metric used by the encoder to evaluate the accuracy of intra-frame prediction and inter-frame motion compensation, and its calculation relies on Hadamard transform. For example, after the encoder thread reads an original image frame, it generates predicted pixel blocks for the original pixel blocks in the original image frame, and performs a difference operation between the original pixel blocks and the predicted pixel blocks to obtain a residual matrix, which is the first matrix in this application embodiment. Then, if it is determined that SATD is needed to estimate distortion, the SATD calculation function is called. This function will trigger the Hadamard transform calculation logic and generate the Hadamard transform instruction to be processed in this application embodiment. After that, the instruction processing method provided in this application embodiment can be executed, thereby obtaining the target operation result for the Hadamard transform instruction with a small number of operator instructions such as matrix multiplication instructions and matrix transpose instructions. Because fewer instructions are executed, this will improve instruction execution efficiency, reduce data memory access latency, thereby increasing the number of video frames processed per unit time and improving the end-to-end frame rate in video encoding.

[0030] It should be noted that the application scenarios given above are merely examples. Those skilled in the art can apply the instruction processing methods provided in the embodiments of this application to other scenarios according to actual needs. This application will not provide detailed examples of each scenario.

[0031] like Figure 1 The diagram shown is a flowchart of the instruction processing method provided in the first embodiment of this application, including the following steps S101 to S103.

[0032] Step S101: Obtain the Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate the first matrix to be involved in the operation.

[0033] The first matrix refers to the residual matrix between the original pixel blocks and the predicted pixel blocks during video encoding. During video encoding, after the encoder thread calculates the residual matrix between the original pixel blocks and the predicted pixel blocks, it uses this residual matrix as the first matrix and determines a first register from the CPU's register file to store the first matrix. The matrix elements included in the first matrix are then stored in the first register of the CPU's register file. The CPU's register file refers to a storage array composed of multiple registers within the CPU.

[0034] If rate-distortion optimization evaluation is required, the SATD calculation function can be invoked. At this time, the Hadamard transform instruction generated during the program compilation phase can be retrieved from memory. This Hadamard transform instruction can be used to indicate the first matrix to be involved in the calculation, specifically its storage location. For example, the Hadamard transform instruction can carry the first register identifier information corresponding to the first register. This register identifier information is used to uniquely locate the register. In the CPU's register file, different registers correspond to different register identifier information. The register identifier information can be, for example, a register number; for instance, the first matrix is ​​stored in register number 008.

[0035] Step S102: Based on the Hadamard transform instruction, generate a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the result of the matrix multiplication instruction.

[0036] This step transforms the Hadamard transform instruction into two instructions: a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the result of the matrix multiplication instruction. This step can be understood as a modification of the Hadamard transform formula used to implement the Hadamard transform instruction.

[0037] In one specific implementation, matrix multiplication instructions for the first matrix can be generated in the following way: Obtain the first register identifier information corresponding to the first register used to store the matrix elements included in the first matrix; Determine the second register from the register file to store the result of the matrix multiplication instruction, and obtain the second register identifier information corresponding to the second register; The first register identifier information is used as the source operand of the matrix multiplication instruction, and the second register identifier information is used as the destination operand of the matrix multiplication instruction to generate a matrix multiplication instruction for the first matrix.

[0038] In this implementation, the Hadamard transform instruction can be decoded to obtain the first register identifier information corresponding to the first register used to store the matrix elements included in the first matrix. The first register may include one or more; in some specific examples, the number of first registers is four. If the total bit width of the registers is 128 bits (i.e., the physical width of the registers is 128 bits), and the bit width of the matrix elements is 16 bits, then four registers can store 32 matrix elements, i.e., two 4x4 matrices. In this case, the second matrix obtained by executing the matrix multiplication instruction on the first matrix and the third matrix obtained by executing the matrix transpose instruction on the result of the matrix multiplication instruction are both two 4x4 matrices. If the total width of the registers is 256 bits (that is, the physical width of the registers is 256 bits), and the width of the matrix elements is 16 bits, then the four registers can store 64 matrix elements, which is four 4x4 matrices. In this case, the second matrix obtained by executing the matrix multiplication instruction on the first matrix and the third matrix obtained by executing the matrix transpose instruction on the result of the matrix multiplication instruction are both four 4x4 matrices.

[0039] While acquiring the first register identifier information corresponding to the first register used to store the matrix elements included in the first matrix, or before acquiring the first register identifier information corresponding to the first register used to store the matrix elements included in the first matrix, or after acquiring the first register identifier information corresponding to the first register used to store the matrix elements included in the first matrix, a second register used to store the operation result of the matrix multiplication instruction can be determined from the register file. Specifically, the currently free register can be determined from the register file, and the second register used to store the operation result of the matrix multiplication instruction can be determined from the currently free register, and the second register identifier information corresponding to the second register can be acquired.

[0040] The number of the second registers can be one or more, and can be determined based on the result of the matrix multiplication instruction (i.e., the second matrix).

[0041] Then, the first register identifier information can be used as the source operand of the matrix multiplication instruction, and the second register identifier information can be used as the destination operand of the matrix multiplication instruction to generate a matrix multiplication instruction for the first matrix. For example, the matrix multiplication instruction for the first matrix could be: vhardama4x4.vv vd1, vs1, where vd1 is the destination operand of the instruction and vs1 is the source operand of the instruction.

[0042] When the matrix multiplication instruction is executed subsequently, the first matrix can be read from the first register corresponding to the first register identifier information, and the matrix multiplication operation represented by the matrix multiplication instruction can be performed on the first matrix to obtain the second matrix; then, the matrix elements included in the second matrix can be written into the second register corresponding to the second register identifier information.

[0043] For example, such as Figure 2 The diagram shown is a schematic of a matrix multiplication instruction in the instruction processing method provided in this application embodiment. Assuming the total bit width (vlen, Vector Length) of the register is 128 bits (i.e., the physical width of the register is 128 bits), the bit width of the matrix element is 16 bits, each register contains 8 matrix elements, and four consecutive registers form two 4x4 matrices. Therefore, when the register's vlen is 128, a matrix multiplication instruction can be performed... 4x4 matrix multiplication. Figure 2In the matrix multiplication instruction, the destination operands v(d1+0), v(d1+1), v(d1+2), and v(d1+3) point to four registers, which store the matrix elements in the second matrix obtained by the matrix multiplication instruction. The second matrix includes matrix 101 and matrix 102; wherein, the matrix element in the first row and first column of matrix 101 is Y100, the matrix element in the first row and second column of matrix 101 is Y101, and the matrix element in the first row and second column of matrix 101 is Y102. The matrix element in the third column of the first row is Y102, the matrix element in the fourth column of the first row of matrix 101 is Y103, ... the matrix element in the fourth column of the fourth row of matrix 101 is Y133; the matrix element in the first column of the first row of matrix 102 is Y000, the matrix element in the second column of the first row of matrix 102 is Y001, the matrix element in the third column of the first row of matrix 102 is Y002, the matrix element in the fourth column of the first row of matrix 102 is Y003, ... the matrix element in the fourth column of the fourth row of matrix 102 is Y033. The source operands v(s1+0), v(s1+1), v(s1+2), and v(s1+3) of the matrix multiplication instruction point to four registers, which store the matrix elements included in the first matrix. The first matrix includes matrix 104 and matrix 105. Specifically, the matrix element in the first row and first column of matrix 104 is X100, the matrix element in the first row and second column of matrix 104 is X101, and the matrix element in the first row and third column of matrix 105 is X102. The element is X102. The element in the first row and fourth column of matrix 104 is X103, ..., the element in the fourth row and fourth column of matrix 104 is X133; the element in the first row and first column of matrix 105 is X000, the element in the first row and second column of matrix 105 is X001, the element in the first row and third column of matrix 105 is X002, the element in the first row and fourth column of matrix 105 is X003, ..., the element in the fourth row and fourth column of matrix 105 is X033. Multiplying the first matrix by the coefficient matrix 103 that matches the first matrix yields the second matrix, which includes matrices 101 and 102.

[0044] In one alternative implementation, a matrix transpose instruction for the result of the matrix multiplication instruction can be generated in the following way: Determine the third register from the register file that is used to store the operation result of the matrix transpose instruction, and obtain the third register identifier information corresponding to the third register; The second register identifier information is used as the source operand of the matrix transpose instruction, and the third register identifier information is used as the destination operand of the matrix transpose instruction to generate a matrix transpose instruction for the operation result of the matrix multiplication instruction.

[0045] In this implementation, a third register for storing the result of the matrix transpose instruction can be determined from the register file. Specifically, a currently free register can be determined from the register file, and a third register for storing the result of the matrix transpose instruction can be determined from the currently free register, and the third register identifier information corresponding to the third register can be obtained.

[0046] Then, the second register identifier information can be used as the source operand of the matrix transpose instruction, and the third register identifier information can be used as the destination operand of the matrix transpose instruction to generate a matrix transpose instruction for the result of the matrix multiplication instruction. For example, the matrix transpose instruction for the first matrix can be: vtransp4x4.vv vd2, vs2, where vd2 is the destination operand of the instruction and vs2 is the source operand of the instruction.

[0047] When the matrix transpose instruction is executed subsequently, the second matrix can be read from the second register corresponding to the second register identifier information, and the second matrix can be transposed to obtain the third matrix; then, the matrix elements included in the third matrix can be written into the third register corresponding to the third register identifier information.

[0048] For example, such as Figure 3The diagram shown is a schematic of the matrix transpose instruction in the instruction processing method provided in this application embodiment. The destination operands v(d2+0), v(d2+1), v(d2+2), and v(d2+3) of the matrix transpose instruction point to four registers, which are used to store the matrix elements included in the third matrix obtained by the matrix transpose instruction. The third matrix includes matrix 201 and matrix 202; wherein, the matrix element in the first row and first column of matrix 201 is Y100, the matrix element in the first row and second column of matrix 201 is Y110, and the matrix element in the first row and second column of matrix 201 is Y110. The matrix element in the third column of the first row is Y120; the matrix element in the fourth column of the first row of matrix 201 is Y130; ..., the matrix element in the fourth column of the fourth row of matrix 201 is Y133; the matrix element in the first column of the first row of matrix 202 is Y000; the matrix element in the second column of the first row of matrix 202 is Y010; the matrix element in the third column of the first row of matrix 202 is Y020; the matrix element in the fourth column of the first row of matrix 202 is Y030; ..., the matrix element in the fourth column of the fourth row of matrix 202 is Y033. The source operands v(s2+0), v(s2+1), v(s2+2), and v(s2+3) of the matrix transpose instruction point to four registers, which store the matrix elements included in the second matrix, which includes matrix 101 and matrix 102. By transposing the two matrices included in the second matrix, we can obtain matrices 201 and 202 included in the third matrix.

[0049] Figure 2 and Figure 3 This example uses a register with a total bit width of 128 bits, but this application is not limited to this. For example, the total bit width of the register can also be 256 bits. In this case, the first matrix involved in the matrix multiplication instruction is a matrix of four rows and four columns, and the second matrix involved in the matrix transpose instruction is also a matrix of four rows and four columns.

[0050] Step S103: Execute the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction.

[0051] After generating the matrix multiplication instruction and the matrix transpose instruction, the matrix multiplication instruction and the matrix transpose instruction can be executed respectively to obtain the target operation result for the Hadamard transform instruction. Specifically, the first matrix can be used as the input data of the matrix multiplication instruction to execute the matrix multiplication instruction, resulting in a second matrix; the second matrix can be used as the input data of the matrix transpose instruction to execute the matrix transpose instruction, resulting in a third matrix; and the target operation result for the Hadamard transform instruction can be obtained based on the third matrix.

[0052] In a specific implementation, the process of executing the matrix multiplication instruction is as follows: A first matrix is ​​read from the first register corresponding to the first register identifier information, and the matrix multiplication operation represented by the matrix multiplication instruction is performed on the first matrix to obtain a second matrix; the matrix elements included in the second matrix are written into the second register corresponding to the second register identifier information. Specifically, performing the matrix multiplication operation represented by the matrix multiplication instruction on the first matrix to obtain the second matrix includes: multiplying the coefficient matrix that matches the first matrix by the first matrix to obtain the second matrix.

[0053] The specific process of executing the matrix transpose instruction is as follows: read the second matrix from the second register corresponding to the second register identifier information, transpose the second matrix to obtain the third matrix; write the matrix elements included in the third matrix into the third register corresponding to the third register identifier information.

[0054] In this embodiment, the matrix multiplication instruction and the matrix transpose instruction are essentially instructions designed by modifying the Hadamard transformation formula used to implement the Hadamard transformation instruction.

[0055] For example, the Hadamard transform formula for implementing the Hadamard transform instruction is shown in the following formula (1): Formula (1) In the above formula (1), This is the matrix representing the result of the operation corresponding to the Hadamard transformation formula. For the first matrix, The coefficient matrix that matches the first matrix. These are the normalization coefficients. The normalization coefficients are used to cancel out signal amplitude amplification in the Hadamard transform, ensuring that the total energy of the residual signal is equal before and after the transform.

[0056] The above formula (1) can be divided into two parts. The first part is the coefficient matrix that matches the first matrix multiplied by the first matrix to obtain the second matrix. The second part is the second matrix multiplied by the coefficient matrix that matches the first matrix to obtain the sixth matrix. Then, the sixth matrix is ​​multiplied by the normalized coefficients to obtain the operation result matrix corresponding to the Hadamard transform formula.

[0057] As shown in the following formula (2), this is the calculation formula for the first part of the Hadamard transformation formula: Formula (2) In the above formula (2), For the second matrix, For the first matrix, This is the coefficient matrix that matches the first matrix.

[0058] The following can be calculated using formula (2): As shown in the following formula (3), this is the calculation formula for the second part of the Hadamard transformation formula: Formula (3) In the above formula (3), This is the sixth matrix. For the second matrix, This is the coefficient matrix that matches the first matrix. The result matrix of the Hadamard transform formula is the normalized coefficients (1 / 4 in this example) and the sixth matrix. The product of.

[0059] Assumption The above formula can be used to calculate: ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; .

[0060] In this embodiment of the application, two extended instructions can be generated based on the Hadamard transform instruction.

[0061] An extended instruction is a matrix multiplication instruction for the first matrix, used to implement the first part of the Hadamard transformation formula described above. In other words, the specific calculation method of the matrix multiplication instruction in this embodiment is: the coefficient matrix that matches the first matrix is ​​multiplied by the first matrix to obtain the second matrix.

[0062] Another extended instruction is a matrix transpose instruction for the result of the matrix multiplication instruction. This matrix transpose instruction is obtained by transforming the second part of the Hadamard transformation formula described above. In this embodiment, the second part of the Hadamard transformation formula can be transformed to obtain a matrix transpose instruction for the result of the matrix multiplication instruction. The specific calculation method for the matrix transpose instruction for the result of the matrix multiplication instruction is as follows: transpose the second matrix to obtain the third matrix.

[0063] As shown in the following formula (4), this is the second matrix mentioned above. The third matrix obtained after transposition : Formula (4) Then, the coefficient matrix that matches the first matrix can be multiplied by the third matrix to obtain the fourth matrix. The formula for calculating the fourth matrix is ​​shown in formula (5) below: Formula (5) In the above formula (5), This is the fourth matrix. The coefficient matrix that matches the first matrix. This is the third matrix.

[0064] Assumption The above formula can be used to calculate: ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; .

[0065] Therefore, the fourth matrix With the aforementioned sixth matrix They are transposes of each other.

[0066] After executing the matrix transpose instruction to obtain the third matrix, the target operation result for the Hadamard transform instruction can be obtained based on the third matrix. Specifically, the coefficient matrix matching the first matrix can be multiplied by the third matrix to obtain the fourth matrix, and then the target operation result for the Hadamard transform instruction can be obtained based on the fourth matrix.

[0067] In this embodiment of the application, the target operation result for the Hadamard transform instruction can be the sum of absolute transformed differences (SATD), which measures the degree of residual distortion between the original pixel block and the predicted pixel block during video encoding, or it can be the operation result matrix corresponding to the Hadamard transform formula used to implement the Hadamard transform instruction.

[0068] In one optional implementation, the target computation result for the Hadamard transform instruction is the Sum of Absolute Transformed Differences (SATD), which measures the residual distortion between the original pixel block and the predicted pixel block during video encoding. In this implementation, obtaining the target computation result of the Hadamard transform formula based on the fourth matrix may include the following steps: multiplying the fourth matrix by the normalization coefficients to obtain a fifth matrix; and summing the absolute values ​​of the matrix elements included in the fifth matrix to obtain the Sum of Absolute Transformed Differences.

[0069] In the prior art, when obtaining the result matrix of the Hadamard transform formula, the absolute values ​​of each matrix element included in the result matrix are usually added together to obtain the absolute difference of the transform, which is used to measure the degree of residual distortion between the original pixel block and the predicted pixel block.

[0070] In this embodiment, since the fourth and sixth matrices are transposes of each other, the result matrix of the Hadamard transform formula is the product of the normalization coefficients and the sixth matrix. Therefore, after multiplying the fourth matrix by the normalization coefficients, the resulting fifth matrix is ​​also a transpose of the result matrix of the Hadamard transform formula. Thus, the sum of the absolute values ​​of the matrix elements in the fifth matrix is ​​the same as the sum of the absolute values ​​of the matrix elements in the result matrix of the Hadamard transform formula; both are the sum of the absolute differences of the transform, used to measure the degree of residual distortion between the original pixel block and the predicted pixel block.

[0071] In another optional implementation, the target computation result for the Hadamard transform instruction is the computation result matrix corresponding to the Hadamard transform formula used to implement the Hadamard transform instruction; in this implementation, obtaining the target computation result of the Hadamard transform formula based on the fourth matrix may include the following steps: Multiplying the fourth matrix by the normalization coefficients yields the fifth matrix; transposing the fifth matrix yields the result matrix corresponding to the Hadamard transform formula used to implement the Hadamard transform instruction; or The fourth matrix is ​​transposed to obtain the seventh matrix; the seventh matrix is ​​multiplied by the normalization coefficient to obtain the operation result matrix corresponding to the Hadamard transform formula used to implement the Hadamard transform instruction.

[0072] In this embodiment, the operation result matrix corresponding to the Hadamard transform formula used to implement the Hadamard transform instruction can be determined based on the obtained fourth matrix. Specifically, the fourth matrix can be multiplied by the normalization coefficients to obtain the fifth matrix, and then the fifth matrix can be transposed to obtain the operation result matrix corresponding to the Hadamard transform formula; alternatively, the fourth matrix can be transposed to obtain the seventh matrix, and then the seventh matrix can be multiplied by the normalization coefficients to obtain the operation result matrix corresponding to the Hadamard transform formula.

[0073] The first embodiment of this application provides an instruction processing method, comprising the following steps: obtaining a Hadamard transform instruction to be processed; the Hadamard transform instruction indicating a first matrix to be involved in the operation; generating a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the operation result of the matrix multiplication instruction based on the Hadamard transform instruction; executing the matrix multiplication instruction and the matrix transpose instruction to obtain a target operation result for the Hadamard transform instruction. It can be seen that in this embodiment, by generating a matrix multiplication instruction and a matrix transpose instruction, the target operation result for the Hadamard transform instruction can be obtained by executing these two instructions. In contrast, in the prior art, Hadamard transform instructions typically need to be implemented using the Hadamard transform formula, which will be broken down into dozens of instructions (e.g., forty or fifty), requiring too many operator instructions to be executed. Therefore, the instruction processing method provided in this embodiment reduces the number of operator instructions required to be executed in the Hadamard transform. This improves instruction execution efficiency, reduces data memory access latency, thereby increasing the number of video frames processed per unit time and improving the end-to-end frame rate in video encoding.

[0074] like Figure 4 The diagram shown is a schematic of a processor core 300 provided in the second embodiment of this application, including an instruction fetching unit 301, an instruction expansion unit 302, and an instruction execution unit 303.

[0075] The instruction acquisition unit 301 is used to acquire the Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate the first matrix to be involved in the operation; the instruction expansion unit 302 is used to generate a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the operation result of the matrix multiplication instruction according to the Hadamard transform instruction; the instruction execution unit 303 is used to execute the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transform instruction.

[0076] Optionally, the instruction execution unit 303 is specifically used to: execute the matrix multiplication instruction to multiply the coefficient matrix matching the first matrix by the first matrix to obtain a second matrix; execute the matrix transpose instruction to transpose the second matrix to obtain a third matrix; and obtain the target operation result for the Hadamard transformation instruction based on the third matrix.

[0077] Optionally, the instruction extension unit 302 is specifically configured to: obtain first register identification information corresponding to a first register used to store matrix elements included in the first matrix; determine a second register used to store the operation result of the matrix multiplication instruction from the register file, and obtain second register identification information corresponding to the second register; use the first register identification information as the source operand of the matrix multiplication instruction, and use the second register identification information as the destination operand of the matrix multiplication instruction, to generate a matrix multiplication instruction for the first matrix.

[0078] Optionally, the instruction extension unit 302 is specifically used to: determine a third register from the register file for storing the operation result of the matrix transpose instruction, and obtain the third register identification information corresponding to the third register; use the second register identification information as the source operand of the matrix transpose instruction, and use the third register identification information as the destination operand of the matrix transpose instruction, to generate a matrix transpose instruction for the operation result of the matrix multiplication instruction.

[0079] Optionally, the instruction execution unit 303 is specifically configured to: read the first matrix from the first register corresponding to the first register identification information, and perform matrix multiplication operation represented by the matrix multiplication instruction on the first matrix to obtain the second matrix; and execute the matrix transpose instruction on the second matrix to obtain the target operation result for the Hadamard transform instruction.

[0080] Optionally, the instruction execution unit 303 is further configured to: write the matrix elements included in the second matrix into the second register corresponding to the second register identification information; read the second matrix from the second register corresponding to the second register identification information and transpose the second matrix to obtain a third matrix; and obtain the target operation result for the Hadamard transform instruction based on the third matrix.

[0081] Optionally, the instruction execution unit 303 is further configured to: write the matrix elements included in the third matrix into the third register corresponding to the third register identification information.

[0082] Optionally, the instruction execution unit 303 is further configured to: multiply the coefficient matrix that matches the first matrix by the third matrix to obtain a fourth matrix; and obtain the target operation result for the Hadamard transform instruction based on the fourth matrix.

[0083] Optionally, the target computation result for the Hadamard transform instruction is the sum of absolute transform differences, which is used to measure the degree of residual distortion between the original pixel block and the predicted pixel block during video encoding; the instruction execution unit 303 is further specifically used to: multiply the fourth matrix by the normalization coefficient to obtain the fifth matrix; and add the absolute values ​​of the matrix elements included in the fifth matrix to obtain the sum of absolute transform differences.

[0084] The third embodiment of this application provides a processor, which includes one or more processor cores as provided in the second embodiment of this application.

[0085] The fourth embodiment of this application provides an instruction processing apparatus, the apparatus including components for processing the instruction processing method provided in the first embodiment of this application.

[0086] The fifth embodiment of this application provides a video encoding method, which can be applied to the encoding end. For example... Figure 5 As shown, the video encoding method includes the following steps S201 to S207: Step S201: Obtain the residual matrix corresponding to the current block.

[0087] The current block refers to the image pixel unit participating in video encoding at the current moment, which is the original pixel block in the first embodiment of this application. The residual matrix refers to the residual matrix between the current block and the predicted pixel block generated for the current block (the predicted pixel block generated in multiple candidate prediction modes), which is the first matrix in the first embodiment of this application.

[0088] Step S202: Multiply the coefficient matrix that matches the residual matrix by the residual matrix to obtain the second matrix.

[0089] Step S203: Transpose the second matrix to obtain the third matrix.

[0090] Step S204: Multiply the coefficient matrix by the third matrix to obtain the fourth matrix.

[0091] The coefficient matrix that matches the residual matrix is ​​also the coefficient matrix that matches the first matrix in the first embodiment of this application. The second, third, and fourth matrices in this step can be referred to the relevant descriptions of the second, third, and fourth matrices in the first embodiment of this application, respectively, and will not be repeated here.

[0092] Step S205: Normalize the fourth matrix and sum the absolute values ​​of the elements of the normalized matrix to obtain the transformation absolute difference sum.

[0093] In a specific implementation, the fourth matrix can be multiplied by the normalization coefficients to obtain the fifth matrix, and the absolute values ​​of the matrix elements included in the fifth matrix can be added together to obtain the sum of absolute transformation errors (SATD).

[0094] Step S206: Determine the coding parameters of the current block based on the transform absolute difference, and determine the frequency domain coefficients of the current block according to the coding parameters.

[0095] The encoding parameters are used to reconstruct the residual matrix in the time domain during the decoding stage. Specifically, the encoding parameters may include, but are not limited to, prediction mode information, quantization parameter information, and transform type information of the target prediction mode selected from multiple candidate modes. The prediction mode information of the target prediction mode is used to generate target prediction pixel blocks; the quantization parameter information is used to provide the quantization step size to restore the amplitude of the frequency domain coefficients; and the transform type information is used to indicate the inverse transform method used to restore the frequency domain coefficients to the residual matrix in the time domain.

[0096] The frequency domain coefficients of the current block refer to the amplitudes corresponding to different frequency components obtained by transforming and decomposing the residual matrix in the time domain, and are used to represent the energy distribution of the current block in the frequency domain.

[0097] In a specific implementation, after obtaining the sum of absolute transformation errors, a target prediction pixel block can be generated based on the prediction mode information of the target prediction mode in the sum of absolute transformation errors. The target residual matrix is ​​obtained based on the target prediction pixel block and the current block. Then, the target residual matrix is ​​transformed and quantized to obtain the quantized frequency domain coefficients.

[0098] Step S207: Add the encoding parameters and the frequency domain coefficients to the video bitstream.

[0099] After obtaining the encoding parameters and the frequency domain coefficients, they can be written into the video bitstream and sent to the decoding end. In this way, during the subsequent decoding stage, the target residual matrix can be reconstructed based on the encoding parameters and the frequency domain coefficients, thereby reconstructing the current block.

[0100] Corresponding to the video encoding method provided in the fifth embodiment of this application, the sixth embodiment of this application provides a video encoding apparatus, which includes: The acquisition unit is used to acquire the residual matrix corresponding to the current block; The first calculation unit is used to multiply the coefficient matrix that matches the residual matrix by the residual matrix to obtain the second matrix; The second calculation unit is used to transpose the second matrix to obtain the third matrix; The third calculation unit is used to multiply the coefficient matrix by the third matrix to obtain the fourth matrix; The normalization unit is used to normalize the fourth matrix and accumulate the absolute values ​​of the elements of the normalized matrix to obtain the sum of the absolute differences of the transformations. The first determining unit is configured to determine the coding parameters of the current block based on the transform absolute difference and to determine the frequency domain coefficients of the current block according to the coding parameters; An incorporation unit is used to add the encoding parameters and the frequency domain coefficients to the video bitstream.

[0101] Corresponding to the video encoding method provided in the fifth embodiment of this application, the seventh embodiment of this application provides a video decoding method, which can be applied to the decoding end. For example... Figure 6 As shown, the video encoding method includes the following steps S301 to S305: Step S301: Receive video bitstream.

[0102] Step S302: Receive the coding parameters associated with the current block and the frequency domain coefficients associated with the current block from the video bitstream.

[0103] Step S303: Determine the residual processing method for the current block based on the encoding parameters.

[0104] At the decoding end, after receiving the video bitstream, the encoding parameters and frequency domain coefficients associated with the current block can be obtained from the video bitstream. Thus, based on the encoding parameters, a residual processing method can be determined to represent how to transform the frequency domain coefficients.

[0105] Step S304: Perform inverse quantization and inverse transformation on the frequency domain coefficients based on the residual processing method to obtain the target residual matrix of the current block.

[0106] In a specific implementation, the residual processing method may include quantization parameter information and transformation type information. In this way, the frequency domain coefficients can be dequantized based on the quantization parameter information in the residual processing method to recover the amplitude of the frequency domain coefficients. Then, the frequency domain coefficients can be inversely transformed based on the transformation type information in the residual processing method to reconstruct the target residual matrix in the time domain.

[0107] Step S305: Reconstruct the current block based on the target residual matrix.

[0108] In this embodiment, at the decoding end, a target prediction pixel block can be generated based on the prediction mode information of the target prediction mode in the encoding parameters. Then, the target prediction pixel block and the target residual matrix are fused to reconstruct the current block. Corresponding to the video decoding method provided in the seventh embodiment of this application, the eighth embodiment of this application provides a video decoding apparatus, which includes: A receiving unit is configured to receive a video bitstream and receive from the video bitstream encoding parameters associated with the current block and frequency domain coefficients associated with the current block; The second determining unit is used to determine the residual processing method of the current block based on the encoding parameters; The processing unit is used to perform inverse quantization and inverse transformation processing on the frequency domain coefficients based on the residual processing method to obtain the target residual matrix of the current block; A reconstruction unit is used to reconstruct the current block based on the target residual matrix.

[0109] Corresponding to the instruction processing method provided in the first embodiment of this application or the video encoding method provided in the second embodiment of this application, the ninth embodiment of this application provides a computer-readable storage medium storing an instruction set and a video bitstream. The instruction set can be executed by one or more processors to generate the video bitstream, the method including the instruction processing method provided in the first embodiment of this application or the video encoding method provided in the fifth embodiment of this application.

[0110] Corresponding to the instruction processing method provided in the first embodiment of this application, the tenth embodiment of this application provides a computer program product, including a computer program / instruction with an instruction processing method, a video encoding method, or a video decoding method. When the computer program / instruction is executed by a processor, it implements the instruction processing method provided in the first embodiment of this application, the video encoding method provided in the fifth embodiment of this application, or the video decoding method provided in the sixth embodiment of this application.

[0111] The eleventh embodiment of this application also provides a system-on-a-chip, which includes one or more processors as provided in the third embodiment of this application.

[0112] Corresponding to the instruction processing method provided in the first embodiment of this application, the video encoding method provided in the fifth embodiment of this application, or the video decoding method provided in the sixth embodiment of this application, the twelfth embodiment of this application also provides an electronic device for the instruction processing method.

[0113] like Figure 7The diagram shown is a structural block diagram of an example of an electronic device for instruction processing, video encoding, or video decoding provided in an embodiment of this application. In this embodiment, an optional hardware structure of the electronic device 400 may be as follows: Figure 7 As shown, the device includes: at least one processor 401, at least one memory 402, and at least one communication bus 405; the memory 402 contains a program 403 and data 404. The bus 405 can be a communication device for transmitting data between components within the electronic device 400, such as an internal bus (e.g., a CPU-memory bus, where the processor is the central processing unit, or CPU for short) or an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect (PCI) port). Additionally, the electronic device also includes: at least one network interface 406 and at least one peripheral interface 407. Network interface 406 provides wired or wireless communication with an external network 408 (e.g., the Internet, intranet, local area network, mobile communication network, etc.). In some embodiments, network interface 406 may include any number of network interface controllers (NICs), radio frequency (RF) modules, repeaters, transceivers, modems, routers, gateways, any combination of wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication (NFC) adapters, cellular network chips, etc. Peripheral interface 407 is used to connect to peripherals, such as peripheral 1 in the figure. Figure 7 409 in the middle), peripheral 2 ( Figure 7 410 in the middle) and peripheral 3 ( Figure 7(411 in the original text). Peripherals are peripheral devices, which may include, but are not limited to, cursor control devices (e.g., mouse, touchpad, or touchscreen), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays), displays or light-emitting diode displays, video input devices (e.g., cameras or input interfaces coupled to video files), etc. Processor 401 may be a CPU, or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. Memory 402 may include high-speed RAM (Random Access Memory) memory, and may also include non-volatile memory, such as at least one disk storage device. Processor 401 calls the programs and data stored in memory 402 to execute the video encoding method provided in the fifth embodiment of this application or the video decoding method provided in the sixth embodiment of this application.

[0114] It should be noted that for detailed descriptions of the processor core, processor, instruction processing device, video encoding method, video encoding device, computer-readable storage medium, computer program product, system-on-a-chip, and electronic device provided in the embodiments of this application, please refer to the relevant description of the first embodiment of this application, which will not be repeated here.

[0115] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0116] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0117] 1. Computer-readable media includes both permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined in this application, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0118] 2. Those skilled in the art will understand that embodiments of this application can provide methods, systems, or computer program products. Therefore, embodiments of this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0119] 3. This application embodiment may involve the use of user data. In practical applications, user-specific personal data may be used within the scope permitted by applicable laws and regulations of the country in which the application is located (e.g., with the user's explicit consent and effective notification to the user, etc.). Furthermore, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. The collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0120] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. An instruction processing method, characterized in that, The method includes: Obtain the Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate the first matrix to be involved in the operation. Based on the Hadamard transform instruction, a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the result of the matrix multiplication instruction are generated. Execute the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction.

2. The method according to claim 1, characterized in that, The execution of the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction includes: Execute the matrix multiplication instruction to multiply the coefficient matrix that matches the first matrix by the first matrix to obtain the second matrix; Execute the matrix transpose instruction to transpose the second matrix to obtain the third matrix; Based on the third matrix, the target operation result for the Hadamard transformation instruction is obtained.

3. The method according to claim 1, characterized in that, The generation of matrix multiplication instructions for the first matrix includes: Obtain the first register identifier information corresponding to the first register used to store the matrix elements included in the first matrix; Determine the second register from the register file to store the result of the matrix multiplication instruction, and obtain the second register identifier information corresponding to the second register; The first register identifier information is used as the source operand of the matrix multiplication instruction, and the second register identifier information is used as the destination operand of the matrix multiplication instruction to generate a matrix multiplication instruction for the first matrix.

4. The method according to claim 3, characterized in that, The matrix transpose instruction that generates the result of the matrix multiplication instruction includes: Determine the third register from the register file that is used to store the operation result of the matrix transpose instruction, and obtain the third register identifier information corresponding to the third register; The second register identifier information is used as the source operand of the matrix transpose instruction, and the third register identifier information is used as the destination operand of the matrix transpose instruction to generate a matrix transpose instruction for the operation result of the matrix multiplication instruction.

5. The method according to claim 4, characterized in that, The execution of the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction includes: The first matrix is ​​read from the first register corresponding to the first register identification information, and the matrix multiplication operation represented by the matrix multiplication instruction is performed on the first matrix to obtain the second matrix; The matrix transpose instruction is executed on the second matrix to obtain the target operation result for the Hadamard transformation instruction.

6. The method according to claim 5, characterized in that, The method further includes: Write the matrix elements included in the second matrix into the second register corresponding to the second register identifier information; The step of executing the matrix transpose instruction on the second matrix to obtain the target operation result for the Hadamard transformation instruction includes: The second matrix is ​​read from the second register corresponding to the second register identifier information, and the second matrix is ​​transposed to obtain the third matrix; Based on the third matrix, the target operation result for the Hadamard transformation instruction is obtained.

7. The method according to claim 6, characterized in that, The method further includes: Write the matrix elements included in the third matrix into the third register corresponding to the third register identifier information.

8. The method according to claim 2 or 6, characterized in that, The step of obtaining the target operation result for the Hadamard transform instruction based on the third matrix includes: Multiply the coefficient matrix that matches the first matrix by the third matrix to obtain the fourth matrix; Based on the fourth matrix, the target operation result for the Hadamard transformation instruction is obtained.

9. The method according to claim 8, characterized in that, The target computation result for the Hadamard transform instruction is the sum of the absolute differences of the transform, which is used to measure the degree of residual distortion between the original pixel block and the predicted pixel block during the video encoding process. The step of obtaining the target calculation result of the Hadamard transformation formula based on the fourth matrix includes: Multiply the fourth matrix by the normalization coefficient to obtain the fifth matrix; The absolute values ​​of the matrix elements included in the fifth matrix are added together to obtain the absolute difference of the transformation.

10. A processor core, characterized in that, The processor core includes: The instruction acquisition unit is used to acquire the Hadamard transform instruction to be processed; the Hadamard transform instruction is used to indicate the first matrix to be involved in the operation. The instruction extension unit is configured to generate a matrix multiplication instruction for the first matrix and a matrix transpose instruction for the result of the matrix multiplication instruction, based on the Hadamard transform instruction. The instruction execution unit is used to execute the matrix multiplication instruction and the matrix transpose instruction to obtain the target operation result for the Hadamard transformation instruction.

11. A processor, characterized in that, The processor includes one or more processor cores as described in claim 10.

12. An instruction processing apparatus, characterized in that, The apparatus includes components for processing the method as described in any one of claims 1 to 9.

13. A video encoding method, characterized in that, include: Get the residual matrix corresponding to the current block; Multiply the coefficient matrix that matches the residual matrix by the residual matrix to obtain the second matrix; Transpose the second matrix to obtain the third matrix; Multiply the coefficient matrix by the third matrix to obtain the fourth matrix; The fourth matrix is ​​normalized, and the absolute values ​​of the elements of the normalized matrix are summed to obtain the absolute difference of the transformation. The coding parameters of the current block are determined based on the absolute difference of the transform, and the frequency domain coefficients of the current block are determined based on the coding parameters. The encoding parameters and the frequency domain coefficients are added to the video bitstream.

14. A video decoding method, characterized in that, include: Receive video bitstream; Receive coding parameters and frequency domain coefficients related to the current block from the video bitstream; The residual processing method for the current block is determined based on the encoding parameters; Based on the residual processing method, the frequency domain coefficients are dequantized and inversely transformed to obtain the target residual matrix of the current block; The current block is reconstructed based on the target residual matrix.

15. A computer-readable storage medium storing an instruction set and a video bitstream, the instruction set being executable by one or more processors to generate the video bitstream, the method comprising any one of claims 1 to 9 or claim 13.

16. A computer program product, characterized in that, Includes a computer program / instruction, wherein when executed by a processor, the computer program / instruction implements the method described in any one of claims 1 to 9, or claim 13 or claim 14.

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