An anti-single-particle irradiation SGT MOS device with a deep-buried heavily doped P-type body region cell structure and a preparation method thereof

Abstract

The application discloses a kind of SGT MOS devices with deep heavy P-type body area cell structure and preparation method of anti single particle irradiation, belong to the field of semiconductor power device.The device is provided with deep injection high concentration P-type mass region in the center of body area between adjacent grooves, the region penetrates source region and goes deep into body area inside, and its bottom terminates in body area inside and does not contact with drift region.The P-type mass region is as high-efficiency hole collection and discharge channel, can quickly lead out hole when single particle is incident, effectively suppresses parasitic BJT base region potential lifting, prevents single particle burnout.The region avoids channel region, and has little effect on on-resistance.The preparation method forms the P-type mass region by multiple implantation and is annealed with source region implantation, and process compatibility is strong.The application significantly improves the anti single particle irradiation reliability of device without sacrificing electrical performance, and is suitable for wide voltage range of 60V to 300V.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and relates to a single-particle irradiation resistant SGT MOS device with a deeply buried heavily doped P-type bulk region cell structure and its fabrication method. Background Technology

[0002] Shielded Gate Trench (SGT) MOSFETs are widely used in high-reliability fields such as aerospace, avionics, and nuclear industry due to their low on-resistance and high switching speed. However, in the space radiation environment, high-energy particles incident on the device generate a large number of electron-hole pairs along their trajectory. For N-channel SGT MOSFETs, these charges separate under the influence of an electric field, and holes flow to the bulk region, which may cause parasitic bipolar junction transistors (BJTs) to turn on, triggering single-event burn-out (SET) effects and seriously threatening the safety of spacecraft electronic systems. Traditional hardening methods, such as increasing the doping concentration in the bulk region, can suppress parasitic BJT turn-on to some extent, but they significantly increase the device's on-resistance, sacrificing electrical performance. Therefore, there is an urgent need for a structure and method that can effectively improve the SGT MOSFET's resistance to single-event effects without significantly affecting electrical performance. Summary of the Invention

[0003] The purpose of this invention is to solve the above-mentioned problems and provide a single-particle irradiation resistant SGT MOS device with a deeply buried, heavily doped P-type bulk cell structure.

[0004] To achieve the above objectives, the present invention provides a single-event irradiation resistant SGT MOS device with a deeply buried, heavily doped P-type bulk cell structure. include: First conductivity type substrate; A first conductivity type drift region located on the substrate; The second conductivity type body region is located above the drift region; The first conductivity type source region is located above the body region; Multiple trenches extend downwards from the upper surface of the device through the source region and the body region and into the drift region; Each of the trenches is provided with a shielding grid structure, which includes a shielding electrode and a shielding dielectric layer located at the lower part of the trench, and a grid electrode and a grid dielectric layer located at the upper part of the trench. The grid electrode and the shielding electrode are mutually insulated and isolated. The device also includes a deeply injected high-concentration cluster region of a second conductivity type, the cluster region being located at the center between two adjacent trenches, penetrating the source region from the upper surface and extending into the body region, with the bottom of the cluster region terminating inside the body region and not contacting the drift region.

[0005] The peak doping concentration of the high-concentration clustered regions of the second conductivity type ranges from 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 between.

[0006] The depth of the high-concentration clustered region of the second conductivity type is 1 / 2 to 4 / 5 of the depth of the bulk junction.

[0007] The device is an N-channel device, the first conductivity type is N-type, and the second conductivity type is P-type.

[0008] This invention also provides a method for fabricating a single-particle irradiation resistant SGT MOS device with a deeply buried, heavily doped P-type bulk cell structure, comprising the following steps: (1) Provide a semiconductor substrate of a first conductivity type; (2) Grow a drift region of the first conductivity type on the substrate; (3) Etch a deep trench; (4) Grow a shielding gate oxide layer in the deep trench; (5) Deposit a shielding gate polycrystalline layer in the deep trench; (6) Dry etch the shielding gate polycrystalline layer to a suitable depth, and anneal the shielding gate polycrystalline layer; (7) Wet etch the shielding gate oxide layer dielectric to a suitable depth to form a region of the control gate; (8) Grow the control gate oxide layer dielectric layer; (9) Deposit the control gate polycrystalline layer and etch it to a suitable depth, and anneal the control gate polycrystalline layer; (10) Form a second conductivity type body region above the drift region by implantation and anneal; (11) By implantation (12) After forming the source region, a second type of impurity is vertically implanted from the upper surface at the center position between adjacent trenches by photolithography and ion implantation process to form a second type of high-concentration clumped region with a depth exceeding the source region but not penetrating the body region; In order to accurately control the junction depth and junction width of the heavily doped P-type clumped region, the implantation is divided into multiple implantations and annealed together with the implantation of the source region; (13) Deposit dielectric layer; (14) Etch contact hole and form ohmic contact; (15) Deposit tungsten metal in contact hole; (16) Deposit metal layer and etch to form source metal and drain metal.

[0009] The beneficial effects of this invention are as follows: 1. Excellent resistance to single-particle radiation By introducing a deeply injected P-type high-concentration cluster region in the adjacent trench interbody region, a highly efficient "hole collection trap" is formed, which can quickly export transient holes generated by single-particle incident, effectively suppress the base region potential rise, prevent parasitic BJT from turning on, and significantly improve the device's resistance to single-particle burn-out.

[0010] 2. Without sacrificing on-resistance and other electrical properties. The clustered region is located in the central body region between the trenches, avoiding the main current channel region. Therefore, it has minimal impact on the threshold voltage and on-resistance of the device, achieving a balance between radiation hardening and electrical performance.

[0011] 3. The process is extremely simple and the cost is controllable. The deeply buried heavily doped P-type body region cell structure of the present invention only requires the addition of a photolithography layer for ion implantation, which is highly compatible with the traditional SGT MOSFET fabrication process. It does not require additional high-temperature annealing or complex epitaxial processes, and the manufacturing cost is controllable.

[0012] 4. Suitable for a wide voltage range of 60V to 300V. The deeply buried, heavily doped P-type body region cell structure of the present invention is adapted to SGT MOS devices with different voltage ratings, covering a wide voltage range from 60V to 300V. Attached Figure Description

[0013] Figure 1 This schematic diagram illustrates the structure of a single-particle irradiation resistant SGT MOS device with a deeply buried, heavily doped P-type bulk cell structure according to one embodiment of the present invention. Figure 2 The schematic diagram illustrates a method for fabricating a single-particle irradiation resistant SGT MOS device with a deeply buried, heavily doped P-type bulk region cell structure according to an embodiment of the present invention.

[0014] In the picture: 1- Drain region of the first conductivity type (N+ substrate); 2- Drift region of the first conductivity type (N- epitaxial layer); 3- Shielding gate oxide layer; 4- Shielding gate polycrystalline layer; 5- Control gate oxide layer; 6- Control gate polycrystalline layer; 7- Body region of the second conductivity type (P-body region / main junction); 8- Source region of the first conductivity type (N+ source region); 9- Cluster structure of deeply buried heavily doped P-type body region; 10- Dielectric layer ILD NSG; 11- Dielectric layer ILD BPSG; 12- Contact hole; 13- Ohmic contact at the bottom of the contact hole; 14- Source region metal layer. Detailed Implementation

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0016] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. The embodiments cannot be described in detail here, but the embodiments of the present invention are not limited to the following embodiments.

[0017] As shown in the figure, this invention provides a single-particle irradiation resistant SGTMOS device with a deeply buried, heavily doped P-type bulk cell structure, comprising: The first conductivity type drain region 1 (N+ substrate) is located at the bottom of the device and is a heavily doped N-type semiconductor substrate.

[0018] The first conductivity type drift region 2 (N-epitaxial layer) is located above the first conductivity type drain region 1 and is a lightly doped N-type epitaxial layer. The resistivity and thickness of the epitaxial layer are determined according to the breakdown voltage of the device design and are suitable for a wide voltage range of 60V to 300V.

[0019] The shielding gate oxide layer 3 is located inside the deep trench, which penetrates the body region to the underlying epitaxial layer. Taking a 100V withstand voltage device as an example, the trench depth is approximately 5μm to 5.5μm, and the shielding gate oxide layer thickness is approximately 550nm.

[0020] The shielding gate polycrystalline 4 is located inside the shielding gate oxide layer at the bottom of the deep trench, forming the shielding electrode.

[0021] The control gate oxide layer 5 is located above the shielding gate polycrystalline layer 4 and has a thickness of approximately 80 nm.

[0022] The control gate polycrystalline 6 is located inside the control gate oxide layer 5, is wrapped by the gate oxide layer, and forms the gate electrode with a depth of approximately 1.3 μm.

[0023] The second conductivity type body region 7 (P-body region) is located above the drift region 2 and constitutes the active region of the device, with a junction depth of 1.1 μm.

[0024] The first conductivity type source region 8 (N+ source region) is located above and inside the second conductivity type body region 7.

[0025] The deeply buried, heavily doped second conductivity type clumped region 9 is located inside the second conductivity type body region 7, extending from the upper surface of the device through the source region 8 and into the body region 7, terminating at its bottom inside the body region without contacting the drift region 2. This clumped region is located at the center between two adjacent trenches, with a junction depth of 1 / 2 to 4 / 5 of the body region junction depth, and a peak doping concentration of 1 × 10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 .

[0026] The dielectric layer NSG 10, located above the trench and the first conductivity type source region 8, is generally formed of silicon dioxide.

[0027] The dielectric layer BPSG 11, located on the upper side of the dielectric layer 10, is generally formed of boron-phosphorus-doped silicon dioxide.

[0028] The contact hole 12 penetrates the source region 8 of the first conductivity type and extends into the body region 7 of the second conductivity type, with a depth of approximately 0.4 μm.

[0029] Ohmic contact 13 is located at the bottom of the contact hole.

[0030] The source region metal layer 14 is located above the insulating dielectric layer 11.

[0031] The principle of single-particle irradiation resistance of the deeply buried, heavily doped P-type bulk region cellular structure of this invention is as follows: In an SGT MOSFET, the P-type body region, N+ source region, and N- drift region naturally form a parasitic NPN bipolar transistor. When heavy ions are incident, they generate high-density electron-hole pairs along their tracks, forming a conductive "plasma filament." Holes flow to the ohmic contact of the P-type body region, and the voltage drop across the body region's resistance instantaneously raises the potential of the P-type body region below the N+ source region. When this voltage drop exceeds the built-in potential of the PN junction between the N+ source region and the P-body region (approximately 0.7V), the emitter junction becomes forward biased, triggering the parasitic NPN transistor to conduct. The collector current after conduction triggers an avalanche multiplication effect under the high electric field of the depletion region, generating even more electron-hole pairs, forming a strong positive feedback loop, and ultimately leading to single-event burnout.

[0032] This invention creates a highly efficient "hole trap" by introducing a deeply injected, high-concentration P-type cluster region within the inter-trench body region. When a single particle incident generates a large number of electron-hole pairs, this high-concentration region significantly reduces the quasi-Fermi level of holes at that location, making it a powerful and rapid hole discharge channel. This allows transiently generated holes to be quickly discharged away from the center of the parasitic BJT base region, effectively suppressing the rise in base potential and thus preventing the parasitic BJT from turning on. Since this cluster region is located within the central body region between the trenches, avoiding the main current channel region, it has minimal impact on the device's threshold voltage and on-resistance.

[0033] Compared to existing technologies that embed a P+ buried layer beneath the P-type body region, the high-concentration P-type cluster region of this invention is located within and terminates within the body region without contacting the drift region. This avoids the adverse effects of the buried layer on the device breakdown voltage and more effectively forms hole collection and discharge channels within the body region. Compared to existing technologies that extend the P+ body region, the cluster region of this invention is an independent deep-implanted structure that does not change the overall doping distribution of the body region, resulting in less impact on the threshold voltage and on-resistance. Compared to existing technologies that embed a second P-type doped region beneath the P-type well region, the cluster region of this invention is located at the center of the body region, avoiding the channel region and having minimal impact on electrical performance parameters.

[0034] For reference Figure 2As shown, the fabrication process for the above-mentioned SGTMOS device with a deeply buried, heavily doped P-type bulk region cell structure resistant to single-event irradiation includes the following steps: Step (1): Epitaxial layer growth A first conductivity type semiconductor substrate (N+ type Si substrate) is provided, on which a first conductivity type drift region (N- type epitaxial layer) is formed by epitaxial growth. The resistivity and thickness of the epitaxial layer are determined according to the breakdown voltage of the device design, and are suitable for the range of 60V to 300V.

[0035] Step (2): Etching deep grooves After hard mask deposition, trench lithography, hard mask etching, and photoresist removal, trenches are etched and the hard mask is removed to form a deep trench structure.

[0036] Step (3): Grow the shielding gate oxide layer and deposit the shielding gate polycrystalline layer. The shielding gate oxide layer is grown using a thermal oxidation method, with a thickness of approximately 550 nm for a 100V withstand voltage device. Polycrystalline silicon for the shielding gate is then deposited.

[0037] Step (4): Dry etching of the shielding gate polycrystalline layer, wet etching back of the shielding gate oxide layer The polysilicon shielding gate is chemically mechanically polished (CMP) until it is etched back to a depth approximately 100 nm below the silicon plane, followed by polysilicon annealing. Then, polysilicon photolithography is performed to etch the polysilicon to a suitable depth (approximately 1.1 μm). Finally, the shielding gate oxide layer dielectric is wet-etched to a depth of approximately 1.3 μm to remove the photoresist from the polysilicon shielding gate, forming the IPO structure of the control gate.

[0038] Step (5): Grow the control gate oxide layer and deposit the control gate polycrystalline layer. The control gate oxide layer is grown using thermal oxidation, with a thickness of approximately 80 nm. Polysilicon control gate is deposited, and then etched back until the polysilicon is about 100 nm lower than the silicon plane, followed by polysilicon annealing.

[0039] Step (6): Pbody injection and push-out Second conductivity type ion implantation and push junction are performed in the active region to form a second conductivity type body region (P body region) with a junction depth of 1.1 μm.

[0040] Step (7): Nsd injection Nsd lithography and Nsd implantation are performed to form the first conductivity type source region (N+ source region). At this time, the source region has not yet been annealed after implantation.

[0041] Step (8): Injection of the clustered structure of the deeply buried heavily doped P-type body region Photolithography was used to create a clustered structure of a deeply buried, heavily doped P-type body region. A second conductivity type impurity was vertically implanted from the top surface at the center position between adjacent trenches. To precisely control the junction depth and width of this clustered structure, the implantation was performed in multiple stages. After removing the photoresist, Nsd annealing conditions were used for combined activation and junction pushing, forming a high-concentration clustered region of the second conductivity type with a depth exceeding the source region but not penetrating the body region.

[0042] Step (9): Deposition of dielectric layer An ILD NSG layer is deposited, an ILD BPSG layer is deposited, and a BPSG reflow process is performed to form an insulating dielectric layer.

[0043] Step (10): Contact hole etching and tungsten deposition Contact hole photolithography is performed, the ILD dielectric layer is etched, and silicon is etched to a depth of approximately 0.4 μm. After removing the photoresist, the contact hole structure is formed. Low-energy implantation is performed at the bottom of the contact hole, followed by rapid annealing to form an ohmic contact structure at the bottom of the hole. Thin layers of metallic titanium and thin layers of alloyed titanium nitride are deposited, followed by tungsten deposition. The tungsten is then etched back to a depth of approximately 100 nm below the contact hole to form a tungsten plug structure.

[0044] Step (11): Metal layer deposition A thin layer of titanium is deposited, followed by a metal layer (such as an aluminum-copper alloy), and photolithography and etching are performed to define the source and gate electrodes.

[0045] The above description is merely one embodiment of the present invention and is not intended to limit the invention. Those skilled in the art will recognize that the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A single-particle irradiation resistant SGT MOS device with a deeply buried, heavily doped P-type bulk cell structure, characterized in that, include: First conductivity type substrate; A first conductivity type drift region located on the substrate; The second conductivity type body region is located above the drift region; The first conductivity type source region is located above the body region; Multiple trenches extend downwards from the upper surface of the device through the source region and the body region and into the drift region; Each of the trenches is formed with a shielding grid structure; Its features are: The device also includes a deeply injected high-concentration cluster region of a second conductivity type, the cluster region being located at the center between two adjacent trenches, penetrating the source region from the upper surface and extending into the body region, and the bottom of the cluster region terminating inside the body region without contacting the drift region.

2. The device according to claim 1, characterized in that, The peak doping concentration of the high-concentration clustered regions of the second conductivity type ranges from 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 between.

3. The device according to claim 1, characterized in that, The depth of the high-concentration clustered region of the second conductivity type is 1 / 2 to 4 / 5 of the depth of the bulk junction.

4. The device according to claim 1, characterized in that, The shielding grid structure includes a shielding electrode and a shielding dielectric layer located at the lower part of the trench, and a grid electrode and a grid dielectric layer located at the upper part of the trench. The grid electrode and the shielding electrode are mutually insulated and isolated.

5. The device according to claim 1, characterized in that, The device is an N-channel device, the first conductivity type is N-type, and the second conductivity type is P-type.

6. The device according to claim 1, characterized in that, The device has a voltage withstand range of 60V to 300V.

7. A method for manufacturing the device as described in any one of claims 1-6, characterized in that, Includes the following steps: (1) Provide a semiconductor substrate of a first conductivity type; (2) A first conductivity type drift region is grown on the substrate; (3) Etching deep grooves; (4) Growing a shielding grid oxide layer in a deep trench; (5) Deposit the shielding gate polycrystalline material within the deep trench; (6) Dry etch the polycrystalline shielding gate to a suitable depth, and then anneal the polycrystalline shielding gate; (7) Wet etching of the shielding gate oxide layer dielectric to a suitable depth to form the area of ​​the control gate; (8) Growth control gate oxide layer medium; (9) Deposit the control gate polycrystalline material and etch it to a suitable depth, then anneal the control gate polycrystalline material; (10) Form a second conductivity type body region above the drift region by injection and anneal; (11) By injecting a source region of the first conductivity type above the formed region; (12) After the source region is formed, a second type of impurity is vertically implanted from the upper surface at the center position between adjacent trenches through photolithography and ion implantation processes to form a high-concentration clumped region of the second type of conductivity that exceeds the source region but does not penetrate the body region. In order to accurately control the junction depth and junction width of the heavily doped P-type clumped region, the implantation is divided into multiple implantations and annealed together with the implantation of the source region. (13) Deposition medium layer; (14) Etch the contact holes and form ohmic contacts; (15) Deposit tungsten metal inside the contact hole; (16) Deposit a metal layer and etch to form source metal and drain metal.

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