Aging board for screening memory chips

Abstract

The utility model discloses an aging board used for memory chip screening, comprising an aging mother board, the aging mother board is connected with a controller and a plurality of tested chip aging seats, each tested chip aging seat is internally provided with a tested chip, each tested chip is correspondingly connected with a relay unit, and each relay unit is connected with the controller. According to the burn-in board for screening the memory chips disclosed by the utility model, burn-in testing of a plurality of parallel SRAM memories can be realized by using one FPGA chip, and the number of parallel testing is increased; and for a specific number of tested chips, the FPGA with less tube legs and less resources can be used for building the test system, so that the development and construction cost of the test system is reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of integrated circuit chip testing, and in particular relates to an aging board for memory chip screening. Background Art

[0002] Burn-in test for electronic components is often used in screening test of components. The test principle is to apply temperature stress and electrical stress to components within a certain period of time to accelerate their aging, expose chip defects in advance, eliminate early life failures, and make the devices quickly enter the accidental failure period. After entering the accidental failure period, the failure rate of components is low, which can ensure that the final delivered chips have high reliability. Burn-in test is divided into static burn-in and dynamic burn-in. In static burn-in test, temperature stress and rated power supply voltage are applied to the components under test, and the input pins of the components under test are connected to the power supply. At this time, the components under test are in a static working state. In dynamic burn-in, in addition to applying temperature stress and rated power supply voltage to the components under test, specific test vectors are also sent to the input pins of the components under test to flip the internal signals of the circuit. Dynamic burn-in has better test effect and is more commonly used in actual tests.

[0003] In the process of developing memory chips, in order to perform burn-in tests on memory chips, it is necessary to design a corresponding burn-in board to provide mechanical support, electrical connection, and input excitation to the chip under test. At present, the burn-in board design scheme given by the Chinese invention patent "A circuit board and method for memory burn-in test" with publication number CN111462810A is aimed at SDRAM memory chips and can only test one chip at a time; the Chinese invention patent "A MT29F series NAND FLASH test burn-in system with customizable process" with publication number CN106571166A discloses a burn-in test system for parallel port NAND FLASH chips, but its structure is very complex, including a motherboard, a signal board, and a DUT board with a total of three logical levels of boards, and each signal board needs to use an FPGA to control the chip under test. This system has a complex structure, high cost, and low signal transmission speed. In the 2021 issue 2 of the journal Electronic World, author Luo Junjie published "Research and Implementation of Typical Memory Dynamic Burn-in Test Methods", which implements dynamic burn-in of SRAM devices and achieves time-sharing access to the chip under test by switching the chip select signal CE. However, the disadvantage of this method is that every 6 devices use the same digital channel. Therefore, when using CE for chip select, only one-sixth of the chips can be selected at the same time, and the other 5 of the 6 devices are idle, and their test coverage is poor.

[0004] In summary, the existing burn-in board has a complex structure, the number of pins required for the main control FPGA is large, and it is impossible to implement burn-in tests on multiple chips under test through a single FPGA chip. Utility Model Content

[0005] The utility model aims to provide a burn-in board for memory chip screening, which solves the problem in the prior art that a single FPGA chip cannot be used to implement burn-in tests on multiple chips under test.

[0006] The technical solution adopted by the utility model is an burn-in board for memory chip screening, including an burn-in motherboard, on which a controller and a plurality of burn-in sockets for tested chips are connected, each of which is provided with a tested chip, each of which is respectively connected with a relay unit, and each relay unit is respectively connected with the controller.

[0007] The utility model is also characterized in that:

[0008] Each relay unit includes a main relay and multiple sub-relays. The main relay and the multiple sub-relays are connected in series and connected to the controller through a relay control line. The main relay and the multiple sub-relays are respectively connected to the chip under test.

[0009] The controller adopts an FPGA chip, and the port IO[7:0] of the FPGA chip is respectively connected to the main relay in each relay unit through eight signal lines.

[0010] The FPGA chip is Artix XC7A50T, Kintex XC7K70T or Kintex XC7K325T.

[0011] The chip under test uses SRAM memory, and the port IO[7:0] of the SRAM memory is connected to the main relay in each relay unit through eight signal lines. The FPGA chip corresponds to the relay unit connected to the SRAM memory one by one.

[0012] The SRAM memory is model IS61LV25616AL-10TLI.

[0013] The controller is also connected to a power board, and the power board is respectively connected to a plurality of chips under test.

[0014] The chip burn-in socket and the chip under test are connected in a detachable manner.

[0015] The beneficial effects of the utility model are:

[0016] (1) The burn-in board for memory chip screening provided by the utility model places the main control FPGA and the burn-in socket of the chip under test on the same motherboard, avoiding the need for a daughter board and a corresponding converter, improving the signal quality and increasing the system clock frequency.

[0017] (2) The burn-in board for memory chip screening provided by the utility model can implement burn-in tests for multiple parallel port SRAM memories with one FPGA chip, thereby increasing the number of parallel tests.

[0018] (3) The burn-in board for memory chip screening provided by the present invention can use an FPGA with fewer legs and fewer resources to build a test system for a specific number of chips under test, thereby reducing the development and construction costs of the test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the burn-in board used for memory chip screening of the utility model;

[0020] Figure 2 It is a schematic diagram of the structure of the burn-in board used for memory chip screening in Embodiment 2 of the utility model;

[0021] Figure 3 It is a structural schematic diagram of the parallel port SRAM memory burn-in board test system in Example 6 of the utility model. DETAILED DESCRIPTION

[0022] The utility model is described in detail below with reference to the accompanying drawings and specific implementation modes.

[0023] Example 1

[0024] The utility model provides an aging board for memory chip screening, such as Figure 1 As shown, it includes an aging motherboard, a controller and a plurality of tested chip aging sockets are connected to the aging motherboard, each tested chip aging socket is provided with a tested chip, and the tested chip aging socket and the tested chip are detachably connected. Each tested chip is respectively connected to a relay unit, each relay unit includes a main relay and a plurality of sub-relays, the main relay and the plurality of sub-relays are connected in series and connected to the controller through a relay control line, and the main relay and the plurality of sub-relays are respectively connected to the tested chip.

[0025] The controller uses an FPGA chip, and the port IO[7:0] of the FPGA chip is connected to the main relay in each relay unit through eight signal lines. The chip under test uses an SRAM (static) memory, and the port IO[7:0] of the SRAM memory is connected to the main relay in each relay unit through eight signal lines. The relay units connected to the FPGA chip and the SRAM memory correspond one to one.

[0026] In addition, the controller is also connected to a power board, and the power board is respectively connected to a plurality of chips under test.

[0027] The power board features include:

[0028] (1) Provide a separate power supply for each chip under test;

[0029] (2) The power supply on and off of each chip under test can be controlled by the main control FPGA chip;

[0030] (3) When the chip under test fails, the main control FPGA chip can completely cut off its power supply;

[0031] (4) The current monitoring chip on the power board monitors the power supply current of each chip under test in real time;

[0032] (5) FPGA communicates with the current monitoring chip to obtain the current value of each chip under test in real time.

[0033] The working principle of the burn-in board for memory chip screening provided by the utility model is:

[0034] Using temperature as an accelerated stress, integrated circuit products are tested for a long time to predict the life of their chips. For example, if the SRAM memory can work stably and reliably for 1000 hours at 125 degrees Celsius, it is equivalent to how many years of working life it can achieve at room temperature. Specifically: first put the hardware system into a high-temperature incubator, start the incubator, and start heating it up. Wait until the temperature rises to the specified temperature, and the main control FPGA chip starts to perform cyclic erase, write, read and access to multiple SRAM memories, while monitoring the working current of the SRAM memory.

[0035] For each chip under test, the master FPGA chip monitors the consistency of its read / write data. If they are consistent, it is considered that the chip is working normally. If they are inconsistent, it is considered that the chip under test is working incorrectly.

[0036] At the same time, because SRAM memory naturally has some bad blocks, as long as the number of erroneous data does not exceed a specific threshold, the SRAM memory data reading and writing is considered normal. When the current monitoring chip in the power board detects an abnormal current value, or the number of read and write data errors exceeds the threshold, it means that the SRAM memory has failed. The system time at this time is recorded, and the life of the chip under test can be calculated using the time when the system works normally.

[0037] Example 2

[0038] This embodiment provides a burn-in board for memory chip screening, such as Figure 1 As shown, it includes an aging motherboard, on which a controller and multiple aging sockets for chips under test are connected, each aging socket for the chip under test is provided with a chip under test, each chip under test is connected with a relay unit respectively, and each relay unit is connected to the controller respectively; each relay unit includes a main relay and multiple sub-relays, the main relay is connected in series with the multiple sub-relays and is connected to the controller through a relay control line, and the main relay and the multiple sub-relays are connected to the chip under test respectively; the controller adopts Artix XC7A50T model FPGA chip, which includes 250 User IO pins, and the port IO[7:0] of the FPGA chip is connected to the main relay in each relay unit respectively through eight signal lines, and the chip under test uses the ‌IS61LV25616AL-10TLI model SRAM memory; the port IO[7:0] of the SRAM memory is connected to the main relay in each relay unit respectively through eight signal lines, and each pin of the SRAM memory is connected to the sub-relay in each relay unit respectively.

[0039] Example 3

[0040] This embodiment provides a burn-in board for memory chip screening, such as Figure 1As shown, it includes an aging motherboard, on which a controller and multiple chip aging sockets are connected, each chip aging socket is equipped with a chip under test, each chip under test is connected to a relay unit, and each relay unit is connected to the controller; each relay unit includes a main relay and multiple sub-relays, the main relay is connected in series with multiple sub-relays and connected to the controller through a relay control line, and the main relay and multiple sub-relays are connected to the chip under test respectively; the controller adopts KintexXC7K70T model FPGA chip, which contains 300 User IO pins, the port IO[7:0] of the FPGA chip is connected to the main relay in each relay unit through eight signal lines. The chip under test uses the IS61LV25616AL-10TLI model SRAM memory. The port IO[7:0] of the SRAM memory is connected to the main relay in each relay unit through eight signal lines. Each pin of the SRAM memory is connected to the sub-relay in each relay unit. The FPGA chip is also connected to a power supply board, which is connected to multiple chips under test. The chip under test is powered by a power supply board. The power supply board is equipped with a current monitoring chip to monitor the power supply current of each chip under test in real time.

[0041] Example 4

[0042] This embodiment provides a burn-in board for memory chip screening, such as Figure 1 As shown, it includes an aging motherboard, on which a controller and multiple chip aging sockets are connected, each chip aging socket is provided with a chip under test, each chip under test is connected to a relay unit, each relay unit is connected to the controller; each relay unit includes a main relay and multiple sub-relays, the main relay is connected in series with multiple sub-relays and connected to the controller through a relay control line, and the main relay and multiple sub-relays are connected to the chip under test respectively; the controller adopts KintexXC7K325T model FPGA chip, which contains 500 User IO pins, the port IO[7:0] of the FPGA chip is connected to the main relay in each relay unit through eight signal lines. The chip under test uses the IS61LV25616AL-10TLI model SRAM memory. The port IO[7:0] of the SRAM memory is connected to the main relay in each relay unit through eight signal lines. Each pin of the SRAM memory is connected to the sub-relay in each relay unit. The FPGA chip is also connected to a power supply board, which is connected to multiple chips under test. The chip under test is powered by a power supply board. The power supply board is equipped with a current monitoring chip to monitor the power supply current of each chip under test in real time.

[0043] Example 5

[0044] This embodiment takes a burn-in system in which one Kintex XC7K325T FPGA chip controls 60 SRAM chips as an example, and its working process is as follows:

[0045] Step 1, place the hardware system into a high temperature incubator;

[0046] Step 2, start the temperature box, start heating, and wait for the temperature to reach the specified temperature;

[0047] Step 3, the FPGA chip starts to perform cyclic erase and read access to 60 SRAM chips, and monitors the working current of the SRAM chips at the same time;

[0048] Step 4: For each chip, the FPGA chip monitors the consistency of its read / write data. If they are consistent, the chip is considered to be working properly. If they are inconsistent, the chip is considered to be working incorrectly. Because SRAM chips naturally have some bad blocks, as long as the number of erroneous data does not exceed a certain threshold, the SRAM chip data reading and writing is considered normal.

[0049] Step 5: When the current value is found to be abnormal, or the number of read and write data errors exceeds the threshold, it indicates that the SRAM chip has failed, and the system time at this time is recorded;

[0050] Step 6: The chip life can be calculated using the normal working time of the aging system.

[0051] Example 6

[0052] This embodiment provides a parallel port SRAM memory burn-in board test system, such as Figure 3 As shown in FIG. 1 , multiple parallel SRAM memory chips are aged in parallel, and the IO[7:0] of each component under test is independently connected to the main controller, which is typically an FPGA chip. Figure 3 As shown in the figure, the controller and the chip under test are all located on the same motherboard, which avoids the problem of poor signal quality caused by the inter-board converter required by multi-level boards and can achieve a higher test speed. However, the port IO[7:0] of all the tested memories is not connected to the 8 pins of the main control FPGA through relays. Since the IO[7:0] of each chip under test will occupy the 8 User IO pins of the main control FPGA, the number of User IO pins of the FPGA required will increase sharply as the number of chips under test increases. If there are N chips under test, the main control FPGA needs to have User IO pins are used to connect to the IO[7:0] pins of each chip.

[0053] The reason for using relays is that when the chip under test is in the readback state, if there is no relay and the output signal lines of each chip are directly short-circuited together, a signal short circuit will occur. Using relays can avoid the problem of short circuit.

[0054] like Figure 1 As shown in the figure, the on and off of each relay group is controlled by one "relay control line". Therefore, assuming that there are N SRAM parallel port chips under test, the signals related to their IO[7:0] occupy a total of User IO pins. Compared to Figure 3 In The number of FPGA pins required has been greatly reduced and saved.

[0055] The burn-in board for memory chip screening provided by the utility model, the controller and the chip under test are all located on the same motherboard, thus avoiding the problem of signal quality degradation caused by the inter-board converter required for multi-level boards, and achieving a higher test speed. At the same time, the test circuit structure is also simpler, and since only one main control FPGA is used, the cost of system implementation is lower.

Claims

1. A burn-in board for memory chip screening, characterized in that: It includes an aging motherboard, on which a controller and multiple chip aging sockets are connected. Each chip aging socket is equipped with a chip under test, each chip under test is connected to a relay unit, and each relay unit is connected to the controller.

2. The burn-in board for memory chip screening according to claim 1, characterized in that: Each of the relay units includes a main relay and a plurality of sub-relays. The main relay is connected in series with the plurality of sub-relays and is connected to a controller via a relay control line. The main relay and the plurality of sub-relays are respectively connected to the chip under test.

3. The burn-in board for memory chip screening according to claim 2, characterized in that: The controller adopts an FPGA chip, and the port IO[7:0] of the FPGA chip is respectively connected to the main relay in each relay unit through eight signal lines.

4. The burn-in board for memory chip screening according to claim 3, characterized in that: The FPGA chip is selected from Artix XC7A50T, Kintex XC7K70T or Kintex XC7K325T models.

5. The burn-in board for memory chip screening according to claim 3, characterized in that: The chip under test uses an SRAM memory, and the port IO[7:0] of the SRAM memory is respectively connected to the main relay in each relay unit through eight signal lines, and the FPGA chip corresponds to the relay unit connected to the SRAM memory one by one.

6. The burn-in board for memory chip screening according to claim 5, characterized in that: The SRAM memory is of model IS61LV25616AL-10TLI.

7. The burn-in board for memory chip screening according to claim 2, characterized in that: The controller is also connected to a power board, and the power board is respectively connected to a plurality of chips under test.

8. The burn-in board for memory chip screening according to claim 1, characterized in that: The chip-under-test aging seat and the chip-under-test are connected in a detachable manner.

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