A signal enhancement circuit based on LPDDR5 / 5X transmitter

Abstract

The present invention discloses a signal enhancement circuit based on an LPDDR5 / 5X transmitter, the signal enhancement circuit comprising: a parallel-to-serial conversion module for converting parallel low-speed data into serial high-speed data; a driving module for receiving the output of the parallel-to-serial conversion module and performing signal amplification; a signal enhancement module for enhancing the output signal of the driving module; wherein the output of the parallel-to-serial conversion module is connected to the input of the driving module, and the output of the driving module is connected to the output end of the signal enhancement module. The present invention solves the signal attenuation, inter-symbol interference (ISI) and crosstalk problems caused by packaging and PCB in high-speed data transmission by integrating a delay module, a voltage regulation module and fine PMOS and NMOS transistor control technology in the signal enhancement module, and optimizes the signal quality.

Description

Technical Field

[0001] The present invention relates to the field of signal enhancement technology, and in particular to a signal enhancement circuit based on an LPDDR5 / 5X transmitter. Background Art

[0002] With the large-scale application of high-performance computing and artificial intelligence (AI), the demand for transmission bandwidth of high-speed data interfaces is growing. However, this growth in demand is also accompanied by new challenges, especially in terms of the impact of packaging and printed circuit boards (PCBs) on signal transmission. The wiring and material characteristics in the packaging and PCBs can cause signal attenuation and distortion, and these problems become more serious, especially for high-speed signals, seriously affecting the transmission reliability of the signal. The main problems suffered by the signal during transmission include inter-symbol interference (ISI), crosstalk, reflection and attenuation, all of which can lead to a decrease in signal quality and affect the correct interpretation of the data.

[0003] In order to solve the problem of signal quality in high-speed data transmission, transmitter (TX) technology plays a vital role. The transmitter is responsible for converting parallel low-speed data into serial high-speed data and sending it out. Traditional transmitters mainly include parallel-to-serial conversion circuits (P2S), pre-drive circuits, and the final drive circuit. The design of the transmitter can be divided into several modes, such as voltage mode, current mode, and voltage-current mixed mode, each of which has its own characteristics and applicable scenarios. Among them, the voltage mode transmitter is favored for its low power consumption and large swing characteristics, but in high-performance computing and AI applications, the higher requirements for transmitter signal bandwidth, the voltage mode transmitter faces limitations in eliminating ISI and crosstalk.

[0004] However, in the existing technology, although the voltage mode transmitter has the advantages of low power consumption and large swing, it is difficult for the traditional transmitter circuit to effectively deal with the impact of ISI and crosstalk in the context of the increasing demand for signal bandwidth in high-performance computing and AI systems. With the increase in signal speed, inter-symbol interference and crosstalk become the main obstacles to signal transmission, resulting in impaired signal integrity, thus affecting the accuracy and reliability of data. Summary of the invention

[0005] In order to solve at least one of the technical problems mentioned above, the present invention provides a signal enhancement circuit based on the LPDDR5 / 5X transmitter to solve the problem that the existing transmitter technology is difficult to effectively deal with the signal attenuation, inter-symbol interference (ISI) and crosstalk caused by packaging and PCB, resulting in reduced signal transmission reliability.

[0006] The present invention provides a signal enhancement circuit based on an LPDDR5 / 5X transmitter, the signal enhancement circuit comprising:

[0007] A parallel-to-serial conversion module, used for converting parallel low-speed data into serial high-speed data;

[0008] A driving module, used for receiving the output of the parallel-to-serial conversion module and performing signal amplification;

[0009] A signal enhancement module, used for enhancing the output signal of the driving module;

[0010] The output of the parallel-to-serial conversion module is connected to the input of the driving module, and the output of the driving module is connected to the output end of the signal enhancement module.

[0011] Preferably, the signal enhancement module comprises: a plurality of delay units, wherein the delay unit is obtained by connecting a delay sub-unit and a capacitor in series;

[0012] Among them, one end of the first delay unit is connected to the boost signal, and the other end is connected to the output of the driving module. One end of each subsequent delay unit is connected between the delay sub-unit and the capacitor of the previous delay unit, and the other end is connected to the output of the driving module.

[0013] Preferably, the delay time and the number of strobes of the delay unit are adjusted by digital signals.

[0014] Preferably, the signal enhancement module includes a voltage adjustment unit and a duty cycle adjustment unit, the duty cycle adjustment unit includes a plurality of field effect transistor branches, and the field effect transistor branch is composed of two field effect transistors;

[0015] Among them, one end of the voltage adjustment unit is connected to the boost signal, and the other end is connected to the input end of the duty cycle adjustment unit, the two ends of the multiple field effect transistor branches are respectively connected to the boost signal and the VSS power supply, and two of the field effect transistors in the multiple field effect transistor branches are bridged to the output of the driving module.

[0016] Preferably, the field effect transistor includes a PMOS transistor and an NMOS transistor.

[0017] Preferably, the duty cycle adjustment unit adjusts the duty cycle of the output signal by adjusting the ratio of the PMOS transistor to the NMOS transistor.

[0018] Preferably, the voltage adjustment unit adjusts the required boost voltage according to different signal speed requirements.

[0019] Preferably, the driving module comprises a pre-driving unit and a main driving unit;

[0020] The pre-driving unit is used to receive the output of the parallel-to-serial conversion module and perform preliminary driving on the output of the parallel-to-serial conversion module, and the main driving unit is used to receive the output of the pre-driving unit and perform signal amplification.

[0021] Preferably, a matching network is provided between the pre-driving unit and the main driving unit, and the matching network is used to optimize signal transmission efficiency and reduce reflection.

[0022] Preferably, the voltage regulating unit comprises a programmable gain amplifier.

[0023] The beneficial effects of the present invention are:

[0024] (1) The signal enhancement circuit of the LPDDR5 / 5X transmitter of the present invention effectively controls the slew rate by optimizing the rise time and fall time of the signal, significantly reduces the crosstalk in high-speed signal transmission, improves the signal integrity and transmission efficiency, and the dynamically adjusted delay unit ensures the optimal slew rate of the signal under different speed requirements, avoiding signal quality problems caused by too fast slew rate;

[0025] (2) Through the precise control of the voltage regulation module, the boost circuit can adjust the output voltage according to actual needs, optimize the boost strength, effectively improve the signal quality, and reduce the impact of inter-symbol interference (ISI). The fine voltage control capability allows the circuit to provide customized signal enhancement effects under different signal speeds and packaging conditions, ensuring the stability and accuracy of signal transmission;

[0026] (3) The pmos and nmos proportional adjustment mechanism in the present invention allows the circuit to flexibly adjust the duty cycle of the output signal, ensuring that the signal can maintain ideal transmission characteristics under different working conditions.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0029] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to illustrate the technical solutions disclosed in the present invention.

[0030] Figure 1 A schematic diagram of the structure of a signal enhancement circuit based on an LPDDR5 / 5X transmitter provided in an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the structure of a signal enhancement circuit including a delay unit provided in an embodiment of the present invention;

[0032] Figure 3 A schematic structural diagram of a signal enhancement circuit including a voltage adjustment unit and a duty cycle adjustment unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] The terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0035] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0036] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] In addition, in order to better illustrate the present invention, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present invention can be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0038] At present, with the increasing demand for high-speed data interface transmission bandwidth in high-performance computing and AI systems, the negative impact of packaging and PCB on signals has intensified, resulting in reduced signal transmission reliability, especially the limitations of voltage-mode transmitters in eliminating inter-symbol interference (ISI) and crosstalk. Signal enhancement technology is urgently needed to improve signal quality and transmission efficiency.

[0039] The present invention provides a signal enhancement circuit based on LPDDR5 / 5X transmitter, see Figure 1 , the signal enhancement circuit comprises:

[0040] The parallel-to-serial conversion module 100 is used to convert parallel low-speed data into serial high-speed data;

[0041] A driving module 200, used for receiving the output of the parallel-to-serial conversion module and performing signal amplification;

[0042] A signal enhancement module 300, used to enhance the output signal of the driving module;

[0043] The output of the parallel-to-serial conversion module is connected to the input of the driving module, and the output of the driving module is connected to the output end of the signal enhancement module.

[0044] In this embodiment, a signal enhancement circuit for improving the signal quality of the LPDDR5 / 5X interface is provided, which is particularly suitable for high-performance computing. When the signal passes through the package and the PCB, it will suffer from serious signal loss and distortion problems, thereby affecting the transmission reliability of the signal. The signal enhancement circuit mainly includes a parallel-to-serial conversion module 100, a driving module 200 and a signal enhancement module 300.

[0045] The parallel-to-serial conversion module 100 receives parallel low-speed data from a data source and converts it into a serial high-speed data stream in preparation for subsequent signal processing and transmission; the driving module 200 receives the serial high-speed data output by the parallel-to-serial conversion module 100 and performs preliminary signal amplification to ensure that the signal has sufficient driving capability to overcome the signal loss of the package and PCB; the signal enhancement module 300 receives the output signal of the driving module 200 and enhances the signal through a built-in boost circuit to increase the signal slew rate and reduce inter-symbol interference (ISI) and crosstalk.

[0046] In this embodiment, by integrating the signal enhancement module 300, the transmission quality and stability of the signal can be significantly improved. The boost circuit in the signal enhancement module 300 can significantly improve the signal quality, reduce inter-symbol interference and crosstalk, and ensure that the signal maintains good integrity during long-distance transmission on the package and PCB.

[0047] Preferably, see Figure 2 , the signal enhancement module includes: a plurality of delay units, wherein the delay unit is obtained by connecting a delay sub-unit and a capacitor in series;

[0048] Among them, one end of the first delay unit is connected to the boost signal, and the other end is connected to the output of the driving module. One end of each subsequent delay unit is connected between the delay sub-unit and the capacitor of the previous delay unit, and the other end is connected to the output of the driving module.

[0049] In this embodiment, in the signal enhancement circuit, the signal enhancement module 300 further includes a delay unit 310 for finely adjusting the rise time and fall time of the signal to control the slew rate of the signal. By controlling the number of strobes and the delay time of the delay unit 310 through digital signals, it can be adjusted according to the transmission requirements of high-speed signals and the characteristics of the package and PCB, thereby achieving the effect of optimizing signal quality and reducing crosstalk.

[0050] In a possible embodiment, in the signal enhancement circuit, the signal enhancement module 300 is specifically composed of a series of delay units 310, each of which is composed of a delay subunit 311 and a capacitor C in series. This structure allows fine control of the rise time and fall time of the signal, thereby optimizing the slew rate of the signal. One end of the first delay unit is directly connected to the boost signal, and the other end is connected to the output of the driver module 200; the subsequent delay unit is connected across the delay subunit and the capacitor of the previous delay unit, and is finally connected to the output of the driver module.

[0051] The number and configuration of delay units in the signal enhancement module 300 can be dynamically adjusted to meet the requirements of different transmission rates. For example, in high-speed transmission mode, the number of delay units can be increased to further refine the slew rate control of the signal, while in low-speed mode, the number of delay units can be reduced to reduce unnecessary signal delays. This dynamic configuration capability ensures that the circuit can maintain optimal signal transmission performance under various operating conditions.

[0052] In a possible embodiment, in order to cope with the impact of temperature changes on signal transmission, the signal enhancement module 300 integrates a temperature sensor and a compensation circuit. When the temperature sensor detects a change in ambient temperature, the compensation circuit automatically adjusts the delay time of the delay unit to ensure that the rise time and fall time of the signal can be kept within the optimal range even under extreme temperature conditions, thereby maintaining the integrity of the signal and the stability of the system.

[0053] The ability to dynamically adjust the number of delay units in this embodiment enables the circuit to seamlessly adapt to a wide range of data transmission rates from low speed to high speed, ensuring optimal signal transmission performance under any circumstances. By finely controlling the rise time and fall time of the signal, crosstalk and reflections in high-speed signal transmission are effectively reduced, greatly improving signal integrity. Furthermore, the temperature compensation function ensures that the signal enhancement circuit can maintain stable performance in various temperature environments, thereby improving the robustness and reliability of the entire system.

[0054] Preferably, the delay time and the number of strobes of the delay unit are adjusted by digital signals.

[0055] In the signal enhancement circuit, the delay time and the number of strobes of the delay unit are dynamically adjusted by digital signals. Specifically, the circuit contains a digital control module that receives digital signal instructions from a processor or control logic. These instructions can dynamically adjust the number of strobes of the delay unit and the delay time of each delay unit according to the real-time signal quality requirements, transmission speed or package PCB characteristics. When the signal transmission environment changes, such as the increase in signal bandwidth requirements or the increase in signal loss caused by packaging, the circuit can respond quickly and optimize the signal slew rate and reduce crosstalk by adjusting the delay time.

[0056] Furthermore, the adaptive delay configuration function of the signal enhancement circuit allows it to automatically adjust the parameters of the delay unit in different working modes. For example, in low-speed data transmission mode, the circuit can select fewer delay units and shorter delay time to reduce unnecessary signal delay and power consumption, while in high-speed transmission mode, the circuit will enable more delay units and more precise delay time control to ensure signal integrity and reduce inter-symbol interference (ISI), ensuring that the circuit can maintain optimal performance in various application scenarios.

[0057] In one possible embodiment, a fault detection and recovery mechanism is also integrated into the circuit. Once a signal quality degradation or a delay unit failure is detected, the digital control module will automatically reconfigure the number of selections and delay time of the delay unit to bypass the faulty unit and restore normal signal transmission, greatly improving the reliability and robustness of the circuit, especially in applications under long-term continuous operation or harsh environmental conditions.

[0058] The delay adjustment capability of the digital signal control in this embodiment enables the circuit to quickly respond to changes in the signal environment and maintain signal integrity and transmission efficiency. Furthermore, the adaptive delay configuration ensures that the circuit can operate in the most efficient manner in different working modes, avoiding unnecessary waste of resources.

[0059] Preferably, see Figure 3 , the signal enhancement module includes a voltage adjustment unit and a duty cycle adjustment unit, the duty cycle adjustment unit includes a plurality of field effect transistor branches, and the field effect transistor branch is composed of two field effect transistors;

[0060] Among them, one end of the voltage adjustment unit is connected to the boost signal, and the other end is connected to the input end of the duty cycle adjustment unit, the two ends of the multiple field effect transistor branches are respectively connected to the boost signal and the VSS power supply, and two of the field effect transistors in the multiple field effect transistor branches are bridged to the output of the driving module.

[0061] In this embodiment, in the signal enhancement circuit, the signal enhancement module 300 is further subdivided into a voltage adjustment unit 320 and a duty cycle adjustment unit 330. The voltage adjustment unit 320 receives the boost signal as input and adjusts the output voltage according to a preset or dynamically adjusted voltage threshold to adapt to different signal transmission conditions. The duty cycle adjustment unit 330 controls the duty cycle of the output signal through a plurality of branches consisting of two field effect transistors, one end of each branch is connected to the boost signal, the other end is connected to the VSS power supply, and the two field effect transistors are connected across the output end of the driving module 200.

[0062] The voltage regulation unit 320 can automatically adjust the voltage level of the boost signal through an external control signal according to the actual needs of signal transmission. At the same time, the multiple field effect transistor branches in the duty cycle adjustment unit 330 allow the circuit to dynamically adjust the duty cycle of the output signal according to the signal transmission characteristics, ensuring the stability and integrity of the signal during high-speed transmission. This adaptive capability is particularly suitable for high-performance computing and AI systems in the face of ever-changing signal bandwidth requirements.

[0063] In a possible embodiment, the signal enhancement circuit also has the function of maintaining signal quality under different temperature and load conditions. The voltage adjustment unit 320 and the duty cycle adjustment unit 330 can sense the ambient temperature change and load fluctuation, and automatically adjust the voltage and duty cycle of the boost signal to overcome the signal attenuation or distortion caused by temperature or load changes, ensuring that the signal can maintain the best state under various working environments.

[0064] In this embodiment, by dynamically adjusting the voltage and duty cycle of the boost signal, the signal enhancement circuit can significantly improve the signal quality, reduce inter-symbol interference (ISI) and crosstalk, and improve signal integrity and transmission efficiency. Furthermore, the circuit's adaptive voltage and duty cycle adjustment capabilities enable it to automatically adapt to different signal transmission conditions, providing the best signal enhancement effect regardless of high-speed data flow or low-power consumption mode.

[0065] Preferably, the field effect transistor includes a PMOS transistor and an NMOS transistor.

[0066] In this embodiment, in the signal enhancement circuit, the field effect transistor branch of the duty cycle adjustment unit 330 is composed of a PMOS transistor and an NMOS transistor. The combined use of the PMOS transistor and the NMOS transistor can effectively control the high level and low level duration of the output signal, that is, the duty cycle. By adjusting the relative conduction time of the PMOS and NMOS transistors, the duty cycle of the output signal can be optimized to adapt to different signal transmission requirements and working environments.

[0067] The ratio and conduction time of PMOS and NMOS transistors can be dynamically adjusted by external control signals to adapt to various situations in signal transmission. For example, under high-frequency transmission conditions, by shortening the conduction time of PMOS transistors, the high-level duration of the signal can be reduced, thereby reducing the average power consumption of the signal. In the low-frequency transmission or signal recovery stage, by extending the conduction time of NMOS transistors, the low-level duration of the signal can be increased to improve the integrity of the signal.

[0068] The PMOS and NMOS transistors in the duty cycle adjustment unit 330 can also play a role in temperature and voltage compensation. Since the threshold voltage of the PMOS and NMOS transistors changes with temperature, the effect of temperature change on the signal duty cycle can be offset by properly adjusting the ratio of the two transistors. At the same time, the on-resistance of the transistor will also change with the fluctuation of the power supply voltage. The combined use of PMOS and NMOS transistors can provide additional voltage buffering to ensure stable output of the signal under different voltage conditions.

[0069] In this embodiment, by dynamically adjusting the conduction time of the PMOS and NMOS transistors, the circuit can automatically optimize the signal quality according to different signal transmission conditions and working environments, thereby improving the flexibility and applicability of the circuit. Furthermore, the combined use of the PMOS and NMOS transistors enables the circuit to accurately control the duty cycle of the signal, which is very important for reducing inter-symbol interference (ISI) and crosstalk in high-speed signal transmission.

[0070] Preferably, the duty cycle adjustment unit adjusts the duty cycle of the output signal by adjusting the ratio of the PMOS transistor to the NMOS transistor.

[0071] In this embodiment, in the signal enhancement circuit, the duty cycle adjustment unit 330 adjusts the duty cycle of the output signal by controlling the on-time ratio of the PMOS transistor and the NMOS transistor. Specifically, the circuit includes a feedback loop to monitor the duty cycle of the output signal, and dynamically adjusts the on-time ratio of the PMOS and NMOS transistors according to the difference between the target value and the actual value of the required duty cycle, so as to ensure that the duty cycle of the output signal remains within the desired range even when the signal transmission conditions change, thereby optimizing the integrity of the signal. The duty cycle adjustment unit 330 also has the ability to automatically adjust the ratio of the PMOS and NMOS transistors according to the signal environment. For example, in the case of high signal bandwidth requirements, by increasing the on-time ratio of the NMOS transistor, the falling edge of the signal can be accelerated, the falling time of the signal can be reduced, and thus the inter-symbol interference (ISI) and crosstalk can be reduced. Conversely, in low bandwidth or low power consumption mode, by increasing the on-time ratio of the PMOS transistor, the rise time of the signal can be increased, the steepness of the rising edge of the signal can be reduced, and the transient current peak of the signal can be reduced, thereby reducing power consumption.

[0072] Preferably, the voltage adjustment unit adjusts the required boost voltage according to different signal speed requirements.

[0073] In the signal enhancement circuit, the voltage adjustment unit 320 can dynamically adjust the boost voltage according to different requirements of the signal speed. Specifically, when the signal transmission speed is low, the voltage adjustment unit can reduce the boost voltage to reduce power consumption and electromagnetic interference (EMI). On the contrary, when the signal speed requirement increases, the boost voltage will be increased to ensure the integrity of the signal, reduce inter-symbol interference (ISI) and crosstalk, and maintain the clarity and stability of the signal even under high-speed data transmission conditions.

[0074] Preferably, the driving module comprises a pre-driving unit and a main driving unit;

[0075] The pre-driving unit is used to receive the output of the parallel-to-serial conversion module and perform preliminary driving on the output of the parallel-to-serial conversion module, and the main driving unit is used to receive the output of the pre-driving unit and perform signal amplification.

[0076] In the signal enhancement circuit, the driving module 200 is subdivided into a pre-driving unit and a main driving unit. The pre-driving unit first receives the output of the parallel-to-serial conversion module 100, performs preliminary signal driving and shaping on it, so as to enhance the driving force of the signal and reduce the attenuation of the signal in the subsequent circuit. The main driving unit then receives the signal output by the pre-driving unit, and further amplifies the signal to ensure that the signal has sufficient amplitude and energy when it is transmitted to the signal enhancement module 300, so as to overcome the loss caused by the packaging and PCB circuit and maintain the integrity of the signal.

[0077] In this implementation, the hierarchical drive design significantly improves the driving force and transmission efficiency of the signal through the coordinated work of the pre-drive unit and the main drive unit, reduces the signal attenuation in the package and PCB circuit, and maintains the integrity and stability of the signal.

[0078] Preferably, a matching network is provided between the pre-driving unit and the main driving unit, and the matching network is used to optimize signal transmission efficiency and reduce reflection.

[0079] In the signal enhancement circuit, a matching network is set between the pre-driver unit and the main driver unit to ensure a smooth transition of the signal between the two units, optimize the signal transmission efficiency, and reduce reflections. The matching network usually includes a series of inductance, capacitance, and resistance elements, and the configuration of these elements is intended to match the output impedance of the pre-driver unit with the input impedance of the main driver unit, thereby minimizing the reflection of the signal during transmission, maintaining the integrity of the signal, and reducing inter-symbol interference (ISI). By optimizing the matching network between the pre-driver unit and the main driver unit, the signal enhancement circuit significantly improves the transmission efficiency of the signal, reduces the reflection and attenuation of the signal during transmission, and maintains the integrity and stability of the signal.

[0080] Preferably, the voltage regulating unit comprises a programmable gain amplifier.

[0081] In the signal enhancement circuit, the voltage adjustment unit 320 integrates a programmable gain amplifier (PGA) for dynamically adjusting the required boost voltage according to the signal speed requirement. The PGA allows the circuit to adjust its gain through software control. The boost voltage can be accurately set to any required level. When the signal speed requirement increases, the gain of the PGA increases accordingly, thereby providing a higher boost voltage to ensure the quality of the signal during high-speed transmission; conversely, when the signal speed requirement decreases, the PGA reduces its gain and reduces the boost voltage to save power consumption and reduce unnecessary electromagnetic interference (EMI). By integrating a programmable gain amplifier, the voltage adjustment unit 320 can dynamically adjust the boost voltage according to the signal speed requirement and other environmental factors, thereby improving the flexibility and adaptability of the circuit.

[0082] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A signal enhancement circuit based on LPDDR5 / 5X transmitter, characterized in that: The signal enhancement circuit comprises: A parallel-to-serial conversion module, used for converting parallel low-speed data into serial high-speed data; A driving module, used for receiving the output of the parallel-to-serial conversion module and performing signal amplification; A signal enhancement module, used for enhancing the output signal of the driving module; The output of the parallel-to-serial conversion module is connected to the input of the driving module, and the output of the driving module is connected to the output end of the signal enhancement module; The signal enhancement module includes: a plurality of delay units, wherein the delay unit is obtained by connecting a delay sub-unit and a capacitor in series; wherein one end of the first delay unit is connected to the boost signal, and the other end is connected to the output of the driving module, and one end of each subsequent delay unit is connected between the delay sub-unit and the capacitor of the previous delay unit, and the other end is connected to the output of the driving module; Alternatively, the signal enhancement module includes a voltage adjustment unit and a duty cycle adjustment unit, the duty cycle adjustment unit includes multiple field effect transistor branches, and the field effect transistor branch is composed of two field effect transistors; wherein one end of the voltage adjustment unit is connected to the boost signal, and the other end is connected to the input end of the duty cycle adjustment unit, the two ends of the multiple field effect transistor branches are respectively connected to the voltage adjustment unit and the VSS power supply, and two of the field effect transistors in the multiple field effect transistor branches are bridged to the output of the driving module.

2. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 1, characterized in that: The delay time and the number of strobes of the delay unit are adjusted by digital signals.

3. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 1, characterized in that: The field effect transistors include PMOS transistors and NMOS transistors.

4. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 3, characterized in that: The duty cycle adjustment unit adjusts the duty cycle of the output signal by adjusting the ratio of the PMOS transistor to the NMOS transistor.

5. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 1, characterized in that: The voltage adjustment unit adjusts the required boost voltage according to different signal speed requirements.

6. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 1, characterized in that: The driving module includes a pre-driving unit and a main driving unit; The pre-driving unit is used to receive the output of the parallel-to-serial conversion module and perform preliminary driving on the output of the parallel-to-serial conversion module, and the main driving unit is used to receive the output of the pre-driving unit and perform signal amplification.

7. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 6, characterized in that: A matching network is provided between the pre-driving unit and the main driving unit, and the matching network is used to optimize signal transmission efficiency and reduce reflection.

8. The signal enhancement circuit based on LPDDR5 / 5X transmitter according to claim 1, characterized in that: The voltage regulation unit includes a programmable gain amplifier.

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