Clock source device applied to multiple test machines and test equipment

Abstract

The utility model relates to a clock source device and test equipment applied to multiple test machines, the clock source device comprises a clock distribution module and a calibration module, the clock distribution module comprises a clock generator and delay controllers, each delay controller is connected with the clock generator and the corresponding test machine, and the calibration module is connected with the clock generator. The calibration module is connected with each test machine and each delay controller; wherein the clock generator outputs a clock signal to each delay controller; the delay controller outputs a clock signal to a corresponding test machine, and adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is in a set error range; the calibration module receives a calibration clock of the test machine and outputs a phase difference value to the corresponding delay controller. The clock transmitted to the testing machine is adjusted by combining the phase difference value output by the calibration module, so that clock frequency synchronization and phase synchronization of different testing machines are realized, and the synchronization control accuracy is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a clock source device and testing equipment applied to multiple testing machines. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to test various parameters of the device under test (DUT) to eliminate defective products and control the factory quality of semiconductor devices. In automatic testing, the clock source device is used to provide clock signals to different testers so that each tester can work synchronously. However, traditional clock source devices only perform frequency synchronization and cannot achieve phase synchronization, which has the disadvantage of low synchronization control accuracy. Utility Model Content

[0003] Based on this, it is necessary to provide a clock source device and test equipment for multiple test machines that can improve the accuracy of synchronization control in order to address the above problems.

[0004] A first aspect of the present application provides a clock source device applied to multiple test machines, comprising a clock distribution module and a calibration module, wherein the clock distribution module comprises a clock generator and a delay controller, the number of the delay controllers is more than two, and each of the delay controllers is connected to the clock generator and the corresponding test machine, and the calibration module is connected to each of the test machines and each of the delay controllers;

[0005] Among them, the clock generator outputs a clock signal to each of the delay controllers; the delay controller outputs a clock signal to the corresponding test machine, and adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is within a set error range; the calibration module receives the calibration clock of the test machine, and outputs the phase difference value to the corresponding delay controller.

[0006] In one of the embodiments, the clock distribution module further includes a clock end fan-out, and the clock generator is connected to each of the delay controllers via the clock end fan-out.

[0007] In one embodiment, the delay controller is a programmable precision delay controller.

[0008] In one of the embodiments, the calibration module includes a clock multiplexer and a phase measurer, the clock multiplexer is connected to each of the testers and the phase measurer, and the phase measurer is connected to each of the delay controllers.

[0009] In one of the embodiments, the phase measurer is a TDC phase measurer.

[0010] In one of the embodiments, each input end of the clock multiplexer is connected to a corresponding test machine, and the two output ends of the clock multiplexer are connected to the phase measurer; the clock multiplexer selects two calibration clocks from the calibration clocks output by each of the test machines and sends them to the phase measurer; the phase measurer calculates a phase difference value based on the two received calibration clocks, and sends the phase difference value to a delay controller connected to the corresponding test machine.

[0011] In one of the embodiments, each of the delay controllers is connected to a corresponding test machine via a cable; wherein the signal offset between each of the cables is less than or equal to 1 ps / m.

[0012] A second aspect of the present application provides a testing device, including a testing machine and the above-mentioned clock source device.

[0013] In one embodiment, the number of the test machines is more than two, each of the test machines is connected to a corresponding delay controller in the clock source device, and each of the test machines is connected to a calibration module in the clock source device.

[0014] In one of the embodiments, each of the test machines includes a test end fan-out, and each of the test end fan-outs is connected to the calibration module and the corresponding delay controller to provide the calibration clock to the calibration module.

[0015] The clock source device and test equipment applied to multiple test machines are as follows: the clock source device includes a clock distribution module and a calibration module; the clock distribution module includes a clock generator and a delay controller; the number of delay controllers is more than two, and each delay controller is connected to the clock generator and the corresponding test machine; the calibration module is connected to each test machine. The clock generator outputs a clock signal to each delay controller, the delay controller outputs a clock signal to the corresponding test machine, the calibration module receives the calibration clock of the test machine, outputs a phase difference value to the corresponding delay controller, and the delay controller adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is within the set error range. Each delay controller provides a clock for the corresponding test machine according to the clock signal output by the same clock generator, and adjusts the clock transmitted to the test machine in combination with the phase difference value output by the calibration module, so that the phase difference of the clock signal of the test machine is within the set error range, so as to achieve clock frequency synchronization and phase synchronization of different test machines, and improve the accuracy of synchronization control. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A structural frame of a clock source device applied to multiple test machines in one embodiment;

[0017] Figure 2 The schematic diagram is a structural diagram of a clock source device applied to multiple test machines in one embodiment. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0020] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0021] When used herein, the singular forms "a", "an", and "the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0022] Usually, the synchronization between multiple test machines only performs frequency synchronization, but not phase synchronization. The control technology of sampling open loop means that when the clock signal reaches the device to be tested, the accumulated phase error between multiple test machines is close to the ns level, and the phase synchronization accuracy is poor, which is far from the ideal synchronization. Therefore, the present application provides a clock source device to reduce the clock signal offset and improve the phase synchronization accuracy between multiple test machines.

[0023] In one embodiment, Figure 1As shown, a clock source device 100 applied to multiple test machines is provided, including a clock distribution module 110 and a calibration module 120. The clock distribution module 110 includes a clock generator 112 and a delay controller 114. The number of delay controllers 114 is more than two, and each delay controller 114 is connected to the clock generator 112 and the corresponding test machine 200. The calibration module 120 is connected to each test machine 200 and each delay controller 114 (the connection relationship between the calibration module 120 and the delay controller 114 is not shown in the figure). Among them, the clock generator 112 outputs a clock signal to each delay controller 114, and the delay controller 114 outputs a clock signal to the corresponding test machine 200. The calibration module 120 receives the calibration clock of the test machine 200 and outputs a phase difference value to the corresponding delay controller 114. The delay controller 114 adjusts the output clock signal according to the phase difference value output by the calibration module 120, so that the phase difference of the clock signal transmitted to the test machine 200 is within the set error range.

[0024] Specifically, the number of delay controllers 114 is determined according to the number of test machines 200, and the delay controllers 114 and the test machines 200 may correspond one to one. The test machine may include a host computer and a test head, or may not include a host computer. Multiple test heads share one host computer. The test head mentioned above is an integral chassis containing multiple business boards. The clock generator 112 outputs an initial clock signal to each delay controller 114, and each delay controller 114 outputs a clock signal to the corresponding test machine 200. The test machine 200 divides the received clock signal into two paths, one path is transmitted to the device to be tested, and the other path is returned to the calibration module 120 as a calibration clock, that is, the calibration clock is the same as the clock signal transmitted to the device to be tested. After the calibration module 120 receives the calibration clocks returned by each test machine 200, it can select one of the calibration clocks as the reference clock, and compare it with other calibration clocks to determine the phase difference between the other calibration clocks and the reference clock; the calibration module 120 can also compare each calibration clock with a pre-saved reference clock to obtain the phase difference between each calibration clock and the reference clock. The calibration module 120 transmits the calculated phase difference value to the corresponding delay controller 114, and the delay controller 114 then adjusts the phase of the output clock signal according to the received phase difference value, so that the phase difference of the clock signal transmitted to each test machine 200 is finally within the set error range. Among them, the specific value of the error range is not unique and can be set according to actual needs. The delay controller 114 can use a programmable fine delay component (PFDC) with a step accuracy of 10ps to ensure the control accuracy of the clock signal. Each delay controller 114 provides a clock for the corresponding test machine 200 according to the clock signal output by the same clock generator 112, and adjusts the clock transmitted to the test machine 200 in combination with the phase difference value output by the calibration module 120, so that the phase difference of the clock signal of the test machine 200 is within the set error range, thereby realizing clock frequency synchronization and phase synchronization of different test machines.

[0025] In addition, if Figure 2As shown, the clock distribution module 110 may also include a clock end fan-out 116, and the clock generator 112 is connected to each delay controller 114 through the clock end fan-out 116. The clock signal output by the clock generator 112 can be aligned and sent to each delay controller 114 through the clock end fan-out 116. The clock end fan-out 116 can specifically adopt an ultra-low skew clock end fan-out (Ultra-low Skew Clock Buffer), and the output skew is less than 25ps. Furthermore, the delay controller 114 is connected to the corresponding test machine 200 through a cable, and the signal skew between each cable is less than or equal to 1ps / m. By using an ultra-low skew clock end fan-out to transmit the clock signal to each delay controller 114, and each delay controller 114 uses a low-skew cable to transmit the clock signal to the corresponding test machine 200, the signal transmission skew can be effectively reduced to ensure the clock synchronization accuracy.

[0026] In one embodiment, Figure 2 As shown, the calibration module 120 includes a clock multiplexer MUX and a phase measurer 122. The clock multiplexer MUX connects each test machine 200 and the phase measurer 122. The phase measurer 122 connects each delay controller 114. Among them, the clock multiplexer MUX can control the channel to select any two outputs, and the phase measurer 122 can use a TDC (Time To Digital Convertor) phase measurer. Specifically, the clock signal output by the delay controller 114 enters the corresponding test machine 200. The test machine 200 has a test end fan-out 220 inside. The test end fan-out 220 can also use an ultra-low offset clock end fan-out with an output offset of less than 25ps. After receiving the clock signal, the test end fan-out 220 outputs one channel to the device to be tested, such as an ASIC ((Application Specific Integrated Circuit) chip). At the same time, the test end fan-out 220 also sends one channel as a calibration clock to the calibration module 120.

[0027] In the calibration module 120, each input end of the clock multiplexer MUX is connected to the corresponding test machine 200, and the two output ends of the clock multiplexer MUX are connected to the phase measurer 122; the clock multiplexer MUX selects two calibration clocks from the calibration clocks output by each test machine and sends them to the phase measurer 122; the phase measurer 122 calculates the phase difference value based on the received two calibration clocks, and sends the phase difference value to the delay controller 114 connected to the corresponding test machine 200. Specifically, the clock multiplexer MUX selects one calibration clock of a certain test machine 200 as the reference standard and outputs it to the first channel of the phase measurer 122; the clock multiplexer MUX selects one calibration clock of another test machine 200 and sends it to the second channel of the phase measurer 122. The calibration clocks of the two channels are in the phase measurer 122, and the phase difference can be accurately calculated with an accuracy of 10ps. After calculating the phase difference, the delay controller 114 corresponding to the second channel of the phase measurement device 122 can be adjusted so that the phase difference of the clock signal finally transmitted to the tester 200 is reduced to within 20ps (±10ps). According to this principle, the phase difference of each calibration clock relative to the reference clock is calibrated in turn so that the phase difference of the clock signal transmitted to each tester 200 is within the allowable error range.

[0028] The calibration error of the clock synchronization accuracy of the clock source device 100 provided by the present application is: the cable used for calibration (<1ps / m) + the channel error of the clock multiplexer MUX (<5ps) + the accuracy error of the TDC phase measurement device (<10ps), so the calibration error between multiple test machines 200 can be controlled within 20ps. In addition, the resolution of the programmable precision delay controller is 10ps, so the clock synchronization error between multiple test machines 200 can be completely controlled within ±50ps.

[0029] In one embodiment, Figure 2 As shown, a test device is also provided, including a test machine 200 and the above-mentioned clock source device 100. There are more than two test machines 200, each of which is connected to the corresponding delay controller 114 in the clock source device 100, and each of which is connected to the calibration module 120 in the clock source device 100. In addition, each of the test machines 200 includes a test end fan-out 220, each of which is connected to the calibration module 120 and the corresponding delay controller 114, and provides a calibration clock to the calibration module 120.

[0030] The clock source device 100 and the test equipment applied to multiple test machines adopt closed-loop delay control and TDC calibration technology, avoid the phase accumulation error of open-loop clock transmission, realize automatic calibration and automatic phase adjustment, avoid the inefficiency of manual calibration and manual phase adjustment, and avoid the subjective manual operation deviation of manual operation. The clock phase synchronization accuracy between multiple test machines 200 can be controlled within ±50ps, that is, phase synchronization and frequency synchronization are achieved.

[0031] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0032] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A clock source device applied to multiple test machines, characterized in that: It includes a clock distribution module and a calibration module, wherein the clock distribution module includes a clock generator and a delay controller, the number of the delay controllers is more than two, and each of the delay controllers is connected to the clock generator and a corresponding tester, and the calibration module is connected to each of the testers and each of the delay controllers; Among them, the clock generator outputs a clock signal to each of the delay controllers; the delay controller outputs a clock signal to the corresponding test machine, and adjusts the output clock signal according to the phase difference value output by the calibration module, so that the phase difference of the clock signal transmitted to the test machine is within a set error range; the calibration module receives the calibration clock of the test machine, and outputs the phase difference value to the corresponding delay controller.

2. The clock source device according to claim 1, characterized in that: The clock distribution module further includes a clock end fan-out, and the clock generator is connected to each of the delay controllers via the clock end fan-out.

3. The clock source device according to claim 1, characterized in that: The delay controller is a programmable precision delay controller.

4. The clock source device according to claim 1, characterized in that: The calibration module includes a clock multiplexer and a phase measurer, the clock multiplexer is connected to each of the testers and the phase measurer, and the phase measurer is connected to each of the delay controllers.

5. The clock source device according to claim 4, characterized in that: The phase measurer is a TDC phase measurer.

6. The clock source device according to claim 4, characterized in that: Each input end of the clock multiplexer is connected to a corresponding tester, and two output ends of the clock multiplexer are connected to the phase measurer; the clock multiplexer selects two calibration clocks from the calibration clocks output by each tester and sends them to the phase measurer; The phase measurer calculates a phase difference value according to the received two calibration clocks, and sends the phase difference value to a delay controller connected to the corresponding test machine.

7. The clock source device according to any one of claims 1 to 6, characterized in that: Each of the delay controllers is connected to a corresponding test machine via a cable; wherein the signal offset between each of the cables is less than or equal to 1ps / m.

8. A testing device, characterized in that: It comprises a testing machine and a clock source device as described in any one of claims 1-7.

9. The testing device according to claim 8, characterized in that The number of the testers is more than two, each of the testers is connected to a corresponding delay controller in the clock source device, and each of the testers is connected to a calibration module in the clock source device.

10. The testing device according to claim 9, characterized in that Each of the test machines includes a test end fan-out, and each of the test end fan-outs is connected to the calibration module and the corresponding delay controller to provide the calibration clock to the calibration module.

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