Real-time vector detection device based on radio-frequency signal short-wave antenna tuner

Abstract

The utility model discloses a real-time vector detection device based on a radio frequency signal short-wave antenna tuner, which comprises a radio frequency signal sampling module, an AGC, an AD and an FPGA, the sampling input end of the radio frequency signal sampling module is connected with a radio frequency path, and the output end of the radio frequency signal sampling module is provided with a forward signal end and a reverse signal end and is connected to the AGC; the AGC can perform gain attenuation processing on an input forward signal and an input reverse signal, an output end of the AGC is provided with a forward signal end and a reverse signal end which are respectively connected to a sampling input end of the AD, the AD is a dual-channel over-sampling analog-to-digital conversion module, an output end of the AD is connected with the FPGA, an input clock of the FPGA is 100MHz, the DDS is realized by adopting an IP core design, the FPGA can realize sampling, calculation and frequency mixing, and the FPGA is connected with the FPGA. And the matching network is controlled to realize tuning and system protection or alarm according to the calculated impedance value and standing-wave ratio. According to the utility model, the hardware circuit is simplified, the power standing-wave ratio condition of the access can be detected in real time, the detection efficiency is improved, the use is convenient, and the detection is efficient and accurate.

Description

Technical Field

[0001] The utility model relates to the field of short-wave communication equipment, and particularly relates to a real-time vector detection device based on a radio frequency signal short-wave antenna tuner. Background Art

[0002] Short-wave communication is a radio communication method using electromagnetic waves with wavelengths ranging from 100 meters to 10 meters (frequencies from 3 MHz to 30 MHz). It can achieve wireless communication of thousands of kilometers or even tens of thousands of kilometers without relying on or relaying, and is a very important long-distance communication means in military communications of various countries in the world. It is also applicable to emergency, disaster relief communications, and long-distance oversea communications. The short-wave antenna feeder system is an important part of the short-wave communication system, which mainly consists of an antenna, a feeder, and an antenna tuner, etc. The function of the antenna is electromagnetic signal radiation and reception; the function of the feeder is to effectively feed the signal energy between the transmitter and the antenna; the antenna tuner (hereinafter referred to as the antenna tuner) mainly consists of a matching network and a detection module; the function of the matching network is to achieve impedance matching through different network forms and device combinations (referred to as tuning) to ensure the performance of the antenna feeder system; the detection module can detect the impedance characteristics and standing wave ratio of the antenna feeder system to provide a reference for tuning.

[0003] The detection module of the early antenna tuner adopted a scalar detection method. This detection method can only qualitatively detect whether the phase of the antenna feeder system is inductive and whether the standing wave ratio is less than 1.5:1. The antenna tuner control software needs to exhaust as many device combinations and network forms as possible to achieve impedance matching, with a slow tuning speed and unable to guarantee the tuning accuracy. With the development of antenna tuning technology and integrated circuits, vector technology has begun to be applied to the detection method of the short-wave antenna feeder system. The currently used method is to use two DDS chips to generate two paths of radio frequencies. One path is used to simulate a radio frequency signal and send it to the input end of the matching network, and the other path generates I and Q signals in a time-sharing manner. The value generated after mixing with the reflected signal of the radio frequency signal passing through the network and combined with the OSL parameters can quantitatively calculate the impedance characteristics and standing wave ratio value of the network. The antenna tuner control software selects appropriate capacitors, inductors, and network forms according to the impedance characteristics and standing wave ratio value to achieve impedance matching, greatly improving the tuning speed and tuning accuracy. Although the current vector detection module can greatly improve the tuning speed and tuning accuracy, the hardware circuit of this method includes a DDS circuit, a mixing circuit, an amplifying circuit, a Wheatstone bridge, and a multi-path impedance transformation transformer, etc., with a complex composition; the vector detection process and the radio frequency power transmission and reception process cannot work simultaneously, and it is impossible to achieve real-time detection of the power standing wave ratio of the path; each time detection is required, the I and Q signals need to be switched, affecting the detection efficiency. Summary of the Invention

[0004] The technical solution adopted by the utility model to solve the above technical problems is:

[0005] A real-time vector detection device based on a radio frequency signal short-wave antenna tuner, comprising a radio frequency signal sampling module, an AGC gain control module, a high-speed AD module, and an FPGA signal processing module. The sampling input end of the radio frequency signal sampling module is connected to a radio frequency path, and its output end has a forward signal end and a reverse signal end and is connected to the AGC gain control module. The AGC gain control module can perform gain attenuation processing on the input forward signal and reverse signal. The output end of the AGC gain control module has a forward signal end and a reverse signal end respectively connected to the sampling input ends of the high-speed AD module. The high-speed AD module is a dual-channel oversampling analog-to-digital conversion module. The output end of the high-speed AD module is connected to the FPGA signal processing module. The input clock of the FPGA signal processing module is 100 MHz, and DDS is implemented by using an IP core design. The FPGA signal processing module can implement sampling, calculation, and mixing, and control the matching network to achieve tuning and system protection or alarm according to the calculated impedance value and standing wave ratio.

[0006] Further, the radio frequency signal sampling module uses two transformers to achieve directional coupling.

[0007] Further, the AGC gain control module has three paths, namely a direct-through path without attenuation, a -31 dB attenuation path, and a -51 dB attenuation path. When sampling a small signal within 10 dBm, the forward and reverse signals are output to the high-speed AD module by selecting the direct-through path through an electronic switch. When the sampling signal power is less than 100 W, the -31 dB attenuation path is selected through the electronic switch and output to the high-speed AD module. When the sampling signal power is between 100 W and 1000 W, the -51 dB attenuation path is selected through the electronic switch and output to the high-speed AD module.

[0008] Further, the high-speed AD module is a dual-channel high-speed analog-to-digital conversion module of model CS9268-100N, which can simultaneously sample the forward signal and the reverse signal, and the sampling rate is 100 Msps.

[0009] Further, the model of the FPGA signal processing module is EF2M45LG144B. The FPGA signal processing module collects the data converted by the high-speed AD module at a sampling rate of 100 Msps through the data port respectively, and calculates the power values and power ratios of the forward signal and the reverse signal based on 1024 sampling points.

[0010] Further, the FPGA signal processing module uses an IP core design to implement DDS to generate sine and cosine signals with the same working frequency, which are respectively mixed with the input forward signal and reverse signal to obtain the I-channel and Q-channel signal values of the forward and reverse signals, and calculates the phase difference between the forward signal and the reverse signal according to the IQ-channel signal values.

[0011] Furthermore, the FPGA signal processing module can calculate the reflection coefficient of the measured network based on the power ratio and phase difference between the forward signal and the reverse signal, and calculate the impedance value and standing wave ratio based on the reflection coefficient, and send the impedance value and standing wave ratio to the internal processor of the FPGA signal processing module.

[0012] The beneficial effects of the present utility model are as follows: 1. By using the detection device of the present utility model, its hardware circuit is greatly simplified; 2. The designs of AGC, AD, and FPGA enable the detection process and the radio frequency power transceiver process to work simultaneously, and can detect the power standing wave ratio of the path in real time; 3. The FPGA does not need to switch the I-channel and Q-channel signals during detection, greatly improving the detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is the functional structure schematic diagram of the present utility model;

[0014] Figure 2 is the circuit principle schematic diagram of the radio frequency signal sampling module of the present utility model;

[0015] Figure 3 is the circuit principle schematic diagram of the AGC gain control module of the present utility model;

[0016] Figure 4 is the circuit principle schematic diagram of the high-speed AD module of the present utility model;

[0017] Figure 5 is the circuit principle schematic diagram of the FPGA signal processing module of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0019] Such as Figure 1As shown in the figure, the utility model is a real-time vector detection device based on a radio frequency signal short-wave antenna tuner, which includes a radio frequency signal sampling module, an AGC gain control module, a high-speed AD module, and an FPGA signal processing module. The sampling input end of the radio frequency signal sampling module is connected to a radio frequency path, and its output end has a forward signal end and a reverse signal end and is connected to the AGC gain control module. The AGC gain control module can perform gain attenuation processing on the input forward signal and reverse signal. The output end of the AGC gain control module has a forward signal end and a reverse signal end respectively connected to the sampling input end of the high-speed AD module. The high-speed AD module is a dual-channel oversampling analog-to-digital conversion module. The output end of the high-speed AD module is connected to the FPGA signal processing module. The FPGA signal processing module can realize sampling, calculation, and mixing, and control the matching network to achieve tuning according to the impedance value, and achieve system protection or alarm according to the standing wave ratio.

[0020] The radio frequency signal sampling module samples and obtains the forward signal and the reverse signal from the radio frequency path and sends them to the AGC gain control module. The AGC gain control module sends the forward signal and the reverse signal with the power controlled within a proper range to the high-speed AD module. The high-speed AD module realizes analog-to-digital conversion at a speed of 100Msps and sends the result to the FPGA signal processing module. The FPGA signal processing module obtains and calculates the power ratio and phase difference of the forward and reverse signals, thereby calculating the impedance value and the standing wave ratio. Then, the internal processor of the FPGA signal processing module controls the matching network according to the impedance value and the standing wave ratio to achieve tuning functions and system protection or alarm and other functions.

[0021] As Figure 2 shown, the radio frequency signal sampling module uses two transformers to realize the directional coupling function, and obtains the forward signal and the reverse signal from the radio frequency path power signal (range -10dBm to 60dBm) and sends them to the AGC gain control module.

[0022] As Figure 3As shown in the figure, an AGC gain control module is designed in the forward signal and reverse signal paths. The AGC gain control module can perform gain attenuation processing on the forward signal and reverse signal, ensuring that the forward signal and reverse signal of different radio frequency paths at different function levels (micro-power signal 0 dBm to high-power signal up to 60 dBm) are within the effective range of the high-speed AD module. The AGC gain control module has three paths, namely a direct-through path without attenuation, a -31 dB attenuation path, and a -51 dB attenuation path. When sampling a small signal within 10 dBm, the forward and reverse signals are output to the high-speed AD module through the electronic switch to select the direct-through path. When the sampling signal power is less than 100 W, the -31 dB attenuation path is selected through the electronic switch and output to the high-speed AD module. When the sampling signal power is between 100 W and 1000 W, the -51 dB attenuation path is selected through the electronic switch and output to the high-speed AD module.

[0023] As Figure 4 shown, the high-speed AD module uses a CS9268-100N type dual-channel high-speed analog-to-digital conversion circuit to simultaneously sample the forward signal and reverse signal. The sampling rate is 100 Msps. The converted data is sent to the FPGA signal processing module, and its dual channels can sample the forward signal and reverse signal respectively. The high-speed AD module uses an oversampling method.

[0024] As Figure 5 shown, the model of the FPGA signal processing module is EF2M45LG144B, and the input clock is 100 MHz. The FPGA signal processing module collects the data converted by the high-speed AD module through the data port at a sampling rate of 100 Msps respectively, and calculates the power value and power ratio of the forward signal and reverse signal based on 1024 sampling points, which is used as the basis for subsequent calculation of the reflection coefficient.

[0025] The FPGA signal processing module uses IP core design to implement DDS, and generates sine signals and cosine signals with the same working frequency, which are mixed with the input forward signal and reverse signal respectively to obtain the I-channel and Q-channel signal values of the forward and reverse signals. The phase difference between the forward signal and reverse signal is calculated based on the IQ-channel signal values, which is used as the basis for subsequent calculation of the reflection coefficient.

[0026] The FPGA signal processing module calculates the reflection coefficient of the measured network based on the power ratio and phase difference between the forward signal and reverse signal, and calculates the impedance characteristic value and standing wave ratio based on the reflection coefficient, and sends them to the internal processor of the FPGA signal processing module.

[0027] The internal processor of the FPGA signal processing module controls the matching network to achieve the tuning function according to the impedance characteristic value, and performs functions such as system protection or alarm according to the standing wave ratio.

[0028] The utility model is not limited to the above-mentioned optimal implementation mode. Any other product identical or similar to the utility model obtained by anyone under the inspiration of the utility model falls within the protection scope of the utility model.

Claims

1. A real-time vector detection device based on a radio frequency signal shortwave antenna tuner, characterized in that: It includes an RF signal sampling module, an AGC gain control module, a high-speed AD module and an FPGA signal processing module. The sampling input end of the RF signal sampling module is connected to the RF path, and its output end has a forward signal end and a reverse signal end and is connected to the AGC gain control module. The AGC gain control module can perform gain attenuation processing on the input forward signal and reverse signal. The output end of the AGC gain control module has a forward signal end and a reverse signal end respectively connected to the sampling input end of the high-speed AD module. The high-speed AD module is a dual-channel oversampling analog-to-digital conversion module. The output end of the high-speed AD module is connected to the FPGA signal processing module. The input clock of the FPGA signal processing module is 100MHz, and the IP core design is used to implement DDS. The FPGA signal processing module can realize sampling, calculation and mixing, and control the matching network according to the calculated impedance value and standing wave ratio value to achieve tuning and system protection or alarm.

2. The real-time vector detection device based on a radio frequency signal shortwave antenna tuner according to claim 1, characterized in that: The radio frequency signal sampling module uses two transformers to achieve directional coupling.

3. The real-time vector detection device based on a radio frequency signal shortwave antenna tuner according to claim 1, characterized in that: The AGC gain control module has three paths: a direct path with no attenuation, a -31dB attenuation path, and a -51dB attenuation path. When the sampled signal is a small signal within 10dBm, the direct path is selected through an electronic switch to output the forward and reverse signals to the high-speed AD module. When the sampled signal power is less than 100W, the -31dB attenuation path is selected through the electronic switch to output to the high-speed AD module. When the sampled signal power is between 100W and 1000W, the -51dB attenuation path is selected through the electronic switch to output to the high-speed AD module.

4. The real-time vector detection device based on a radio frequency signal shortwave antenna tuner according to claim 1, characterized in that: The high-speed AD module is a dual-channel high-speed analog-to-digital conversion module with the model number CS9268-100N, which can sample the forward signal and the reverse signal at the same time, with a sampling rate of 100Msps.

5. The real-time vector detection device based on a radio frequency signal shortwave antenna tuner according to claim 1, characterized in that: The model used in the FPGA signal processing module is EF2M45LG144B. The FPGA signal processing module collects the data converted by the high-speed AD module at a sampling rate of 100Msps through the data port, and calculates the power value and power ratio of the forward signal and the reverse signal based on 1024 sampling points.

6. The real-time vector detection device based on a radio frequency signal shortwave antenna tuner according to claim 5, characterized in that: The FPGA signal processing module uses an IP core design to implement DDS to generate sine and cosine signals with the same operating frequency, which are mixed with the input forward and reverse signals respectively to obtain the I and Q signal values of the forward and reverse signals, and the phase difference between the forward and reverse signals is calculated based on the I and Q signal values.

7. The real-time vector detection device based on a radio frequency signal shortwave antenna tuner according to claim 6, characterized in that: The FPGA signal processing module can calculate the reflection coefficient of the measured network based on the power ratio and phase difference of the forward signal and the reverse signal, and calculate the impedance value and the standing wave ratio value based on the reflection coefficient, and send the impedance value and the standing wave ratio value to the internal processor of the FPGA signal processing module.

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