Semiconductor structure

Abstract

The utility model relates to a semiconductor structure. The semiconductor structure comprises a substrate; the source electrode, the grid electrode and the drain electrode are stacked on the substrate; the first isolation layer is arranged between the grid electrode and the drain electrode; the second isolation layer is arranged between the first isolation layer and the drain electrode; the channel layer penetrates through the grid electrode, the first isolation layer and the second isolation layer, and the channel layer is arranged on the source electrode; the gate dielectric layer is arranged between the gate and the channel layer; the insulating layer is arranged on the inner side of the channel layer; the contact pad is arranged on the insulating layer; the nitrogen component content of the second isolation layer is greater than the nitrogen component content of the first isolation layer. The second isolation layer protects the first isolation layer in the etching or grinding process, the first isolation layer is prevented from being damaged, the integrity of the semiconductor structure is protected, and the product yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure. Background Art

[0002] With the development of semiconductor technology, integrated circuits are moving towards miniaturization, requiring corresponding integrated circuits to have higher integration density and smaller feature sizes, that is, requiring as many semiconductor devices as possible to be set on a smaller substrate to obtain higher performance.

[0003] However, the miniaturization of semiconductor devices has almost reached its limit. The miniaturization of semiconductor devices increases the difficulty of the manufacturing process and may affect the performance and product yield of semiconductor devices. Utility Model Content

[0004] Based on this, the present disclosure provides a semiconductor structure.

[0005] The present disclosure provides a semiconductor structure, comprising:

[0006] substrate;

[0007] A source electrode, a gate electrode and a drain electrode are stacked on the substrate;

[0008] a first isolation layer, provided between the gate and the drain;

[0009] a second isolation layer, provided between the first isolation layer and the drain electrode;

[0010] a channel layer, passing through the gate, the first isolation layer and the second isolation layer, wherein the channel layer is disposed on the source;

[0011] a gate dielectric layer, disposed between the gate and the channel layer;

[0012] an insulating layer, disposed inside the channel layer;

[0013] a contact pad, disposed on the insulating layer;

[0014] A nitrogen component content of the second isolation layer is greater than a nitrogen component content of the first isolation layer.

[0015] Optionally, a top surface of the second isolation layer is in direct contact with a bottom surface of the drain.

[0016] Optionally, it also includes:

[0017] The third isolation layer is provided between the first isolation layer and the gate, and the material of the third isolation layer is the same as that of the second isolation layer.

[0018] Optionally, it further includes an isolation sidewall located between adjacent drain electrodes, wherein a bottom surface of the isolation sidewall is lower than a bottom surface of the second isolation layer.

[0019] Optionally, a top surface of the insulating layer is lower than a bottom surface of the second isolation layer.

[0020] In the semiconductor structure disclosed herein, a second isolation layer having a higher nitrogen content is disposed between the first isolation layer and the drain electrode. The second isolation layer is used to protect the first isolation layer during the etching or grinding process, thereby preventing the first isolation layer from being damaged and protecting the integrity of the semiconductor structure, which is beneficial to improving the product yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a schematic structural diagram of a semiconductor structure provided in one embodiment;

[0023] Figure 2 is a process flow chart of a method for manufacturing a semiconductor structure provided in one embodiment;

[0024] Figure 3 A schematic diagram of a structure after a source electrode and a gate electrode are formed on a substrate according to an embodiment;

[0025] Figure 4 is a schematic diagram of a structure after forming a third insulating layer, a first insulating layer, and a second insulating layer provided in one embodiment;

[0026] Figure 5 is a schematic diagram of a structure after a first through hole is formed according to an embodiment;

[0027] Figure 6 Schematic diagram of the structure after forming the channel hole and the gate dielectric layer provided in one embodiment;

[0028] Figure 7 is a schematic structural diagram after forming a channel layer provided in one embodiment;

[0029] Figure 8 is a schematic diagram of a structure after forming an insulating layer provided in an embodiment;

[0030] Figure 9 It is a schematic diagram of a structure after the insulating layer and the channel layer on the top surface of the second isolation layer are removed by grinding provided in one embodiment;

[0031] Figure 10 A schematic diagram of the structure after etching the insulating layer until its top surface is lower than the top surface of the channel layer provided in one embodiment;

[0032] Figure 11 is a schematic diagram of a structure after forming a contact pad provided in one embodiment;

[0033] Figure 12 is a schematic diagram of a structure after forming a first metal layer provided in one embodiment;

[0034] Figure 13 A schematic diagram of a structure after an isolation trench is formed to divide the first metal layer into separate drain electrodes according to an embodiment;

[0035] Figure 14 is a schematic diagram of a structure after a nitride layer is formed according to an embodiment;

[0036] Figure 15 FIG. 1 is a schematic structural diagram of a semiconductor structure after an insulating sidewall provided in one embodiment.

[0037] Description of reference numerals:

[0038] 10. Substrate; 11. Source; 111. Source metal layer; 1111. First source barrier layer; 1112. Source conductive layer; 1113. Second source barrier layer; 112. Source contact layer; 12. Gate; 13. Channel layer; 14. Gate dielectric layer; 15. Insulation layer; 161. Contact pad; 162. Drain; 162a. First metal layer; 163. Nitride layer; 21. First isolation layer; 22. Second isolation layer; 23. Third isolation layer; 30. Channel hole; 31. First through hole; 41. First dielectric layer; 42. Second dielectric layer; 43. Isolation sidewall; 44. Isolation trench. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0041] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or being “on” another element, the element may be directly connected or coupled to or “on” the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as being “contacting” or “in contact with” another element, there are no intervening elements at the point of contact. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

[0042] According to an exemplary embodiment, this embodiment provides a semiconductor structure such as Figure 1 As shown, the semiconductor structure includes a substrate 10, a source electrode 11, a gate electrode 12, and a drain electrode 162 stacked on the substrate 10, as well as a first isolation layer 21, a second isolation layer 22, a channel layer 13, an insulating layer 15, and a contact pad 161. The source electrode 11, the gate electrode 12, and the drain electrode 162 are sequentially stacked on the substrate 10 and do not directly contact each other. The first isolation layer 21 is disposed between the gate electrode 12 and the drain electrode 162; the second isolation layer 22 is disposed between the first isolation layer 21 and the drain electrode 162; the channel layer 13 penetrates the gate electrode 12, the first isolation layer 21, and the second isolation layer 22, and is disposed on the source electrode 11; the gate dielectric layer 14 is disposed between the gate electrode 12 and the channel layer 13; the insulating layer 15 is disposed inside the channel layer 13; and the contact pad 161 is disposed on the insulating layer 15. The nitrogen content of the second isolation layer 22 is greater than that of the first isolation layer 21.

[0043] The substrate 10 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited thereto.

[0044] The nitrogen content of the second isolation layer 22 is greater than that of the first isolation layer 21, and the etching resistance of the second isolation layer 22 is greater than that of the first isolation layer 21. The first isolation layer 21 and the second isolation layer 22 are stacked between the gate 12 and the drain 162. The first isolation layer 21 is used to electrically isolate the gate 12 and the drain 162. The second isolation layer 22, which has a higher nitrogen content, is provided between the first isolation layer 21 and the drain 162. The second isolation layer 22 is used to protect the first isolation layer 21 during the etching or polishing process of the semiconductor structure, preventing damage to the first isolation layer 21 and protecting the integrity of the semiconductor structure, thereby improving the product yield of the semiconductor structure.

[0045] In some embodiments, the top surface of the second isolation layer 22 is in direct contact with the bottom surface of the drain electrode 162. The second isolation layer 22 provides better connection stability. The second isolation layer 22 is in contact with the bottom surface of the drain electrode 162, which increases the stability of the semiconductor structure and reduces the risk of damage, delamination, and detachment of the semiconductor structure.

[0046] For example, the material of the second isolation layer 22 may include at least one of nitrogen-doped silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), silicon oxycarbide (SiNC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboronitride (SiOBN), and silicon oxycarbide (SiOC).

[0047] The material of the first isolation layer 21 may include silicon oxide, silicon oxycarbide, or other high density plasma (HDP) oxides.

[0048] In one example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon nitride. In another example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon oxynitride. In yet another example, the material of the first isolation layer 21 includes silicon oxycarbide, and the material of the second isolation layer 22 includes silicon nitride.

[0049] The channel layer 13 passes through the gate 12, the first isolation layer 21 and the second isolation layer 22. The bottom surface of the channel layer 13 is in contact with the source 11. The channel layer 13 has a "U"-shaped opening facing away from the substrate 10. The insulating layer 15 and the contact pad 161 are stacked in sequence in the U"-shaped opening of the channel layer 13 along the direction away from the substrate 10. The insulating layer 15 is arranged between the contact pad 161 and the bottom surface of the channel layer 13 to prevent the contact pad 161 from being short-circuited with the bottom source 11 through the channel layer 13.

[0050] For example, the material of the channel layer 13 may include doped polysilicon.

[0051] In one example, the source 11 includes a source metal layer 111 and a source contact layer 112 sequentially stacked on the substrate 10. For example, the source metal layer 111 includes a first source barrier layer 1111, a source conductive layer 1112, and a second source barrier layer 1113 sequentially stacked between the substrate 10 and the source contact layer 112.

[0052] The insulating layer 15 covers the bottom surface of the channel layer 13 and a portion of the inner sidewall of the channel layer 13 , and the contact pad 161 covers the top surface of the insulating layer 15 and another portion of the inner sidewall of the channel layer 13 .

[0053] In some embodiments, please refer to Figure 1, the top surface of the insulating layer 15 is lower than the bottom surface of the second isolation layer 22 . In other words, the bottom surface of the contact pad 161 is lower than the bottom surface of the second isolation layer 22 .

[0054] The top surface of the contact pad 161 contacts the drain 162, and the drain 162 is in contact with the channel layer 13 through the contact pad 161. The contact area between the contact pad 161 and the channel layer 13 is larger and the contact resistance is smaller, which can reduce the contact resistance between the drain 162 and the channel layer 13, reduce the overall resistance of the semiconductor structure, and improve the electrical performance and response speed of the semiconductor structure.

[0055] The drain electrode 162 includes a first metal layer, and the contact pad 161 includes a doped semiconductor material. For example, the drain electrode 162 includes tungsten or a tungsten compound, tantalum or a tantalum compound, and the contact pad 161 includes doped polysilicon.

[0056] In one example, the material of the drain 162 includes tungsten, and the material of the contact pad 161 includes doped polysilicon.

[0057] The gate 12 continuously surrounds and covers a portion of the outer sidewall of the channel layer 13. The gate 12 is separated from the outer sidewall of the channel layer 13 by a gate dielectric layer 14. The material of the gate 12 includes metal tungsten or a tungsten compound, metal tantalum or a tantalum compound, and the material of the gate dielectric layer 14 includes an oxide, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k material.

[0058] In some embodiments, please refer to Figure 1 The semiconductor structure further includes a third isolation layer 23 disposed between the first isolation layer 21 and the gate 12 . The material of the third isolation layer 23 is the same as that of the second isolation layer 22 .

[0059] In this way, the third isolation layer 23, the first isolation layer 21 and the second isolation layer 22 are stacked in sequence between the gate 12 and the drain 162, and the third isolation layer 23 is in contact with the gate 12. The filling property and connection stability of the third isolation layer 23 are better than those of the first isolation layer 21. The first isolation layer 21 is connected to the gate 12 through the third isolation layer 23, which enhances the connection strength between the first isolation layer 21 and the gate 12, increases the stability of the semiconductor structure, and reduces the risks of damage, delamination, and falling off of the semiconductor structure.

[0060] For example, the material of the first isolation layer 21 includes silicon oxide, the material of the second isolation layer 22 includes silicon nitride, and the material of the third isolation layer 23 includes silicon nitride.

[0061] In some embodiments, please refer to Figure 1 The semiconductor structure further includes an isolation sidewall 43 located between adjacent drain electrodes 162 , and a bottom surface of the isolation sidewall 43 is lower than a bottom surface of the second isolation layer 22 .

[0062] The dielectric constant of the material of the isolation sidewall 43 is lower than the dielectric constant of the material of the second isolation layer 22. For example, the material of the isolation sidewall 43 may include silicon oxide.

[0063] The isolation sidewalls 43 extend toward the substrate 10, penetrate the second isolation layer 22, and extend into the first isolation layer 21. This reduces the proportion of the second isolation layer 22 between devices, lowering the dielectric constant of the isolation medium between devices, thereby reducing the parasitic capacitance of the semiconductor structure and improving product quality and electrical performance.

[0064] In some embodiments, a stacked first isolation layer 21 and a second isolation layer 22 are provided between the gate 12 and the drain 162, the isolation sidewall 43 extends to the first isolation layer 21, and the bottom surface of the isolation sidewall 43 is higher than the bottom surface of the first isolation layer 21, or the bottom surface of the isolation sidewall 43 is at the same horizontal height as the bottom surface of the first isolation layer 21.

[0065] In other embodiments, a third isolation layer 23, a first isolation layer 21, and a second isolation layer 22 are stacked between the gate 12 and the drain 162. The isolation sidewall 43 extends to the first isolation layer 21, and the bottom surface of the isolation sidewall 43 is higher than the bottom surface of the first isolation layer 21.

[0066] According to an exemplary embodiment, this embodiment provides a method for manufacturing a semiconductor structure, such as Figure 2 As shown, the method for manufacturing a semiconductor structure includes the following steps:

[0067] Step S10: providing a substrate 10;

[0068] Step S20: forming a source electrode 11 on the substrate 10;

[0069] Step S30: forming a gate 12 on the source 11;

[0070] Step S40: forming a first isolation layer 21 and a second isolation layer 22 in sequence on the gate 12, wherein the nitrogen content of the second isolation layer 22 is greater than that of the first isolation layer 21;

[0071] Step S50 : forming a channel hole 30 , wherein the channel hole 30 penetrates the gate 12 , the first isolation layer 21 , and the second isolation layer 22 , and the channel hole 30 exposes a portion of the gate 12 ;

[0072] Step S60: forming a gate dielectric layer 14 , the gate dielectric layer 14 covering the gate 12 exposed by the channel hole 30 ;

[0073] Step S70: forming a channel layer 13, wherein the channel layer 13 covers the gate dielectric layer 14;

[0074] Step S80 : forming an insulating layer 15 , the insulating layer 15 covers the channel layer 13 and fills the channel hole 30 , and the top surface of the insulating layer 15 is lower than the top surface of the channel layer 13 ;

[0075] Step S90: forming a contact pad 161 on the insulating layer 15 , wherein the top surface of the contact pad 161 is at the same level as the top surface of the second isolation layer 22 ;

[0076] Step S100 : forming a drain electrode 162 on the contact pad 161 .

[0077] In the manufacturing method of the semiconductor structure of this embodiment, a first isolation layer 21 and a second isolation layer 22 are sequentially formed on the gate 12. The nitrogen content of the second isolation layer 22 is greater than the nitrogen content of the first isolation layer 21. The etching resistance of the second isolation layer 22 is greater than the etching resistance of the first isolation layer 21. The second isolation layer 22 protects the first isolation layer 21 to prevent the first isolation layer 21 from being etched and damaged, or even damaging the gate 12, during the process of forming the channel hole 30, thereby preventing the filled conductive material from short-circuiting with the gate 12, ensuring the structural and performance integrity of the formed semiconductor structure, and being conducive to improving the product yield. It is suitable for the development demand of semiconductor structures towards smaller feature sizes.

[0078] Next, combine Figure 3-Figure 15 Each step of the method for manufacturing the semiconductor structure of this embodiment is described in detail.

[0079] In step S10, refer to Figure 3 As shown, the substrate 10 may be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited thereto.

[0080] In step S20, refer to Figure 3 A source metal layer 111 and a source contact layer 112 are deposited on the substrate 10 using a physical vapor deposition (PVD) process, and the source metal layer 111 and the source contact layer 112 are patterned to form the source 11 .

[0081] In some embodiments, the source metal layer 111 includes a first source barrier layer 1111, a source conductive layer 1112, and a second source barrier layer 1113, which are sequentially stacked between the substrate 10 and the source contact layer 112. For example, the materials of the first source barrier layer 1111 and the second source barrier layer 1113 may include titanium nitride, the material of the source conductive layer 1112 may include metallic tungsten, and the material of the source contact layer 112 may include a semiconductor material, such as doped polysilicon.

[0082] After the source electrodes 11 are formed on the substrate 10 , a first dielectric layer 41 is deposited by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The first dielectric layer 41 covers the source electrodes 11 , the top surface of the substrate 10 exposed by the source electrodes 11 , and the space between the source electrodes 11 .

[0083] In step S30, refer to Figure 3 A gate conductive layer is deposited on the first dielectric layer 41 using PVD, and then the gate conductive layer is patterned and etched to form the gate 12.

[0084] For example, which is not shown in the figure, the gate 12 may include a gate barrier layer and a gate metal layer stacked in sequence from bottom to top, or the gate 12 may also include a gate semiconductor layer and / or a gate metal silicide layer, the gate semiconductor layer may be located on the gate metal layer, and the gate metal silicide layer may be located on the gate semiconductor layer or the gate metal layer.

[0085] In this embodiment, after the gates 12 are formed, a second dielectric layer 42 is deposited using CVD or atomic layer deposition (ALD) to fill the region between the gates 12. For example, the material of the second dielectric layer 42 includes silicon oxide.

[0086] In step S40, refer to Figure 4 The first isolation layer 21 and the second isolation layer 22 may be sequentially deposited on the top surface of the second dielectric layer 42 by using CVD or ALD.

[0087] The nitrogen content of the second isolation layer 22 is greater than the nitrogen content of the first isolation layer 21. For example, the material of the second isolation layer 22 may include at least one of nitrogen-doped silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), silicon oxycarbide (SiNC), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), and silicon oxycarbide (SiOC).

[0088] The material of the first isolation layer 21 may include silicon oxide, silicon oxycarbide, or other high density plasma (HDP) oxides.

[0089] In one example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon nitride. In another example, the material of the first isolation layer 21 includes silicon oxide, and the material of the second isolation layer 22 includes silicon oxynitride. In yet another example, the material of the first isolation layer 21 includes silicon oxycarbide, and the material of the second isolation layer 22 includes silicon nitride.

[0090] In step S50 and step S60, first, refer to Figure 5 , the second isolation layer 22 , the first isolation layer 21 and the gate 12 are etched to form a first through hole 31 , where the first through hole 31 exposes the top surface of the first dielectric layer 41 .

[0091] Then, ALD may be used to deposit a gate dielectric material layer (not shown in the figure), and the gate dielectric material layer covers the gate 12 exposed by the first through hole 31 .

[0092] Next, refer to Figure 6 , the gate dielectric material layer on the bottom wall of the first through hole 31 and the first dielectric layer 41 exposed by the first through hole 31 are etched away until the top surface of the source 11 is exposed, and the first through hole 31 is extended downward to form a channel hole 30.

[0093] The gate dielectric material layer and the first dielectric layer 41 are etched using an anisotropic etching process, wherein the etching rate in a direction perpendicular to the substrate 10 is much greater than the etching rate in a direction parallel to the substrate 10, thereby ensuring that the gate dielectric material layer on the sidewall of the first through hole 31 is completely retained as the gate dielectric layer 14. The material of the gate dielectric layer 14 includes an oxide, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k material.

[0094] For example, the gate dielectric material layer and the first dielectric layer 41 may be etched using a dry process.

[0095] In step S70, if Figure 7 As shown, the channel layer 13 may be deposited by CVD or ALD. The channel layer 13 covers the top surfaces of the gate 12 and the source 11 exposed by the channel hole 30 . The channel layer also covers the top surface of the second isolation layer 22 .

[0096] For example, the material of the channel layer 13 may include doped polysilicon.

[0097] In step S80, Figure 8 As shown, the insulating layer 15 may be deposited by CVD or ALD, and the insulating layer 15 covers the channel layer 13 and fills the unfilled area of the channel hole 30 .

[0098] For example, the material of the insulating layer 15 may include a low-k dielectric material or silicon oxide. The low-k dielectric material may be a material having a lower dielectric constant than silicon oxide. The low-k dielectric material may include one or more of flowable oxide (FOX), toon silazene (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicate glass (FSG), high-density plasma (HDP) oxide, plasma-enhanced oxide (PEOX), or flowable CVD (FCVD) oxide.

[0099] In some embodiments, forming the insulating layer 15 includes the following steps:

[0100] Step S81: grinding and removing the insulating layer 15 and the channel layer 13 on the top surface of the second isolation layer 22, so that the top surface of the remaining insulating layer 15, the top surface of the channel layer 13 and the top surface of the second isolation layer 22 are at the same level;

[0101] like Figure 9 As shown, the top surface of the second isolation layer 22 is used as the polishing end point, and the insulating layer 15 and the channel layer 13 are polished by a chemical mechanical polishing (CMP) process. When the second isolation layer 22 is identified, the etching is stopped, and only the insulating layer 15 and the channel layer 13 in the channel hole 30 are retained to disconnect the channel layer 13 in each channel hole 30 and avoid short circuit between adjacent devices.

[0102] Step S82 : etching the insulating layer 15 until its top surface is lower than the top surface of the channel layer 13 .

[0103] like Figure 10 As shown, the insulating layer 15 is etched back until its top surface is lower than the top surface of the channel layer 13 to expose a portion of the inner sidewall of the top of the channel layer 13 to increase the contact area between the channel layer 13 and the contact pad 161 formed subsequently.

[0104] The manufacturing method of this embodiment, on the one hand, takes advantage of the better etching resistance of the second isolation layer 22, and uses the second isolation layer 22 to protect the first isolation layer 22, so that the first isolation layer 22 is not damaged during the grinding process, thereby avoiding damage to the first isolation layer 22, and further avoiding problems such as short circuits between devices that may be caused by damage to the first isolation layer 22, ensuring the structural and performance integrity of the semiconductor structure, and being conducive to improving product yield, and being suitable for the development demand of semiconductor structures towards smaller feature sizes; on the other hand, this embodiment uses the top surface of the second isolation layer 22 as the grinding end point, and removes the insulating layer 15 and the channel layer 13 on the second isolation layer 22 through a single grinding process, saving process steps, improving manufacturing efficiency, and being conducive to reducing production costs.

[0105] In some embodiments, the top surface of the etched insulating layer 15 is lower than the bottom surface of the second isolation layer 22. This allows the contact area between the channel layer 13 and the subsequently formed contact pad 161 to be sufficiently large, thereby reducing the contact resistance between the channel layer 13 and the contact pad 161.

[0106] Furthermore, the top surface of the etched insulating layer 15 should be higher than the top surface of the gate 12, so as to avoid the gate 12 and the subsequently formed contact pad 161 from having a facing area, which is beneficial to reducing the parasitic capacitance of the semiconductor structure and improving the response speed of the semiconductor structure.

[0107] In step S90 , a contact material layer (not shown in the figure) may be deposited by CVD or ALD. The contact material layer fills the channel hole 30 and covers the top surface of the second isolation layer.

[0108] Then, refer to Figure 10 、 Figure 11 The top surface of the second isolation layer 22 is used as the grinding end point, and the contact material layer on the second isolation layer 22 is removed by CMP grinding, and the contact material layer in the channel hole 30 is retained to form the contact pad 161.

[0109] In this embodiment, the second isolation layer 22 is used to protect the first isolation layer 22 so as to prevent the first isolation layer 22 from being damaged during the process of polishing the contact material layer.

[0110] In step S100, Figure 12 As shown, the first metal layer 162 a may be formed by PVD deposition, and the first metal layer 162 a covers the top surface of the contact pad 161 and the top surface of the second isolation layer 22 .

[0111] Reference Figure 13 The patterned first metal layer 162 a forms a drain electrode 162 , the bottom surface of the drain electrode 162 contacts the top surface of the contact pad 161 , and a portion of the bottom surface of the drain electrode 162 directly contacts the top surface of the second isolation layer 22 around the contact pad 161 .

[0112] In this way, on the one hand, the drain 162 is connected to the channel layer 13 through the contact pad 161, which reduces the contact resistance between the drain 162 and the channel layer 13, which is beneficial to improving the electrical performance and response speed of the semiconductor structure; on the other hand, the connection strength between the second isolation layer 22 and the drain 162 is better, which increases the stability of the semiconductor structure and reduces the risks of damage, delamination, and falling off of the semiconductor structure.

[0113] In some embodiments, reference Figure 4As shown, before the first isolation layer 21 and the second isolation layer 22 are sequentially formed on the gate 12, the following steps are also performed: Step S50-1: forming a third isolation layer 23, the third isolation layer 23 being arranged between the first isolation layer 21 and the gate 12, and the material of the third isolation layer 23 being the same as that of the second isolation layer 22.

[0114] That is, in step S50, a stack of the third isolation layer 23, the first isolation layer 21, and the second isolation layer 22 can be sequentially deposited. The material of the third isolation layer 23 is the same as that of the second isolation layer 22. In this way, the third isolation layer 23 contacts the gate 12. The third isolation layer 23 has better filling performance and connection stability than the first isolation layer 21. The first isolation layer 21 is connected to the gate 12 through the third isolation layer 23, which enhances the connection strength between the first isolation layer 21 and the gate 12, increases the stability of the semiconductor structure, and reduces the risk of damage, delamination, and shedding of the semiconductor structure.

[0115] For example, the material of the first isolation layer 21 includes silicon oxide, the material of the second isolation layer 22 includes silicon nitride, and the material of the third isolation layer 23 includes silicon nitride.

[0116] In some embodiments, the manufacturing method performs: Step S110 : forming an isolation sidewall 43 , the isolation sidewall 43 covers the sidewall of the drain 162 and fills between adjacent drains 162 , and the bottom surface of the isolation sidewall 43 is lower than the bottom surface of the second isolation layer 22 .

[0117] Reference Figure 13 As shown, in the process of patterning the first metal layer 162 a to form the drain electrode 162 in step S100 , a mask is formed on the top surface of the first metal layer 162 a , and the first metal layer 162 a is etched according to the mask to form the independent drain electrode 162 .

[0118] In this embodiment, after etching the first metal layer 162a to expose the top surface of the second isolation layer 22, the second isolation layer 22 and part of the first isolation layer 21 are further etched to form an isolation groove 44. The isolation groove 44 divides the first metal layer 162a into multiple discrete drains 162. The bottom surface of the isolation groove 44 is lower than the bottom surface of the second isolation layer 22, which can avoid the possibility of residual conductive material and thereby reduce the risk of short circuit between devices.

[0119] Then, refer to Figure 14 A nitride layer 163 is formed to cover the sidewalls of the drain 162 exposed by the isolation trench 44. The nitride layer 163 is used to prevent the metal material in the drain 162 from diffusing into other devices or film layers, further reducing the risk of short circuits between devices.

[0120] Illustratively, the material of the nitride layer 163 includes silicon nitride.

[0121] Next, refer to Figure 15 CVD or ALD can be used to deposit insulating material to fill the isolation trench 44 to form an isolation sidewall 43. The isolation sidewall 43 extends toward the substrate 10. The isolation sidewall 43 penetrates the second isolation layer 22 and extends into the first isolation layer 21 to isolate the drain 162.

[0122] The dielectric constant of the material of the isolation sidewall 43 is lower than the dielectric constant of the material of the second isolation layer 22. For example, the material of the isolation sidewall 43 may include silicon oxide. This reduces the proportion of the second isolation layer 22 between devices and lowers the dielectric constant of the isolation medium between devices, thereby reducing the parasitic capacitance of the formed semiconductor structure and improving product quality and electrical performance.

[0123] According to an exemplary embodiment, this embodiment provides an electronic device including a semiconductor structure according to the above embodiment, or a semiconductor structure produced by a method for producing a semiconductor structure according to the above embodiment. The electronic device may be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, or the like.

[0124] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; A source electrode, a gate electrode and a drain electrode are stacked on the substrate; a first isolation layer, provided between the gate and the drain; a second isolation layer, provided between the first isolation layer and the drain electrode; a channel layer, passing through the gate, the first isolation layer and the second isolation layer, wherein the channel layer is disposed on the source; a gate dielectric layer, disposed between the gate and the channel layer; an insulating layer, disposed inside the channel layer; a contact pad, disposed on the insulating layer; A nitrogen component content of the second isolation layer is greater than a nitrogen component content of the first isolation layer.

2. The semiconductor structure according to claim 1, wherein: A top surface of the second isolation layer is in direct contact with a bottom surface of the drain electrode.

3. The semiconductor structure according to claim 1, wherein: Also includes: The third isolation layer is provided between the first isolation layer and the gate, and the material of the third isolation layer is the same as that of the second isolation layer.

4. The semiconductor structure according to claim 1, wherein: It also includes an isolation sidewall located between adjacent drain electrodes, wherein a bottom surface of the isolation sidewall is lower than a bottom surface of the second isolation layer.

5. The semiconductor structure according to claim 1, wherein: A top surface of the insulating layer is lower than a bottom surface of the second isolation layer.

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