Photoelectric co-packaging structure and optical module

Abstract

The utility model provides a photoelectric co-packaging structure and an optical module, and relates to the technical field of optical communication. The photoelectric co-packaging structure comprises a multi-layer circuit board, a photon integrated circuit chip and an anti-warping piece. An optical waveguide and an optical coupling port connected with the optical waveguide are arranged in the photon integrated circuit chip; and the optical coupling port is used for optically coupling with an optical element outside the photonic integrated circuit chip. The photon integrated circuit chip is flip-chip welded on the multilayer circuit board and is electrically connected with the multilayer circuit board. The anti-warping piece is arranged in the multi-layer circuit board; the projection of the photonic integrated circuit chip on the surface of the multilayer circuit board and the projection of the anti-warping piece on the surface of the multilayer circuit board are at least partially overlapped. The multi-layer circuit board is provided with the anti-warping piece, so that the packaging stress can be reduced, the warping deformation of the multi-layer circuit board and the photon integrated circuit chip is reduced, and the packaging quality and reliability are improved.

Description

Technical Field

[0001] The present application relates to the field of optical communication technology, and in particular to an optoelectronic co-packaging structure and an optical module. Background Art

[0002] In existing silicon photonic modules, the silicon photonic chip is glued to a heat sink or printed circuit board (PCB) and then electrically connected to the PCB via bonding wires. A glue buffer exists between the silicon photonic chip and the heat sink or PCB, and there are no specific requirements for the thermal expansion coefficient of the heat sink or PCB.

[0003] As optical module speeds continue to increase, wire bonding electrical connections are unable to meet the high-frequency performance requirements for single-channel, high-speed signal transmission. Therefore, flip-chip soldering of silicon photonic chips directly onto circuit boards (flip-chip) simplifies high-speed links and improves high-frequency performance, enabling single-channel high-speed transmission rates of 100 Gbps, or even 200 Gbps and beyond. Due to the significant difference in the thermal expansion coefficients of silicon photonic chips and circuit boards, the high reflow temperatures during the flip-chip process generate significant stress, causing warping of the circuit board and silicon photonic chip after reheating. This warping also dynamically changes with temperature during optical module production and use. This warping causes the side-by-side optical coupling ports within the silicon photonic chip to deviate from each other and change dynamically, complicating subsequent alignment and coupling with optical components such as fiber arrays, reducing optical coupling efficiency and impacting the stability of the optical module's optical path. Furthermore, circuit board warping can strain the solder joints between the circuit board and the silicon photonic chip, potentially leading to cracking (ball cracking) of the solder joints. This can lead to poor contact or failure of the electrical connection between the silicon photonic chip and circuit board, reducing package reliability. Utility Model Content

[0004] The purpose of this application is to provide an optoelectronic co-packaging structure and an optical module, which can effectively reduce the warping deformation of the multi-layer circuit board and the photonic integrated circuit chip, solve the problem of deviation of the optical coupling port of the photonic integrated circuit chip, improve the stability of the coupled optical path, and reduce the risk of cracking of the flip-chip solder joints, thereby improving the packaging reliability.

[0005] The embodiment of the present application is implemented as follows:

[0006] In a first aspect, the present application provides an optoelectronic co-packaging structure, comprising:

[0007] Multilayer circuit boards;

[0008] A photonic integrated circuit chip, wherein the photonic integrated circuit chip is provided with an optical waveguide and an optical coupling port connected to the optical waveguide; the optical coupling port is used to optically couple with an optical element external to the photonic integrated circuit chip; the photonic integrated circuit chip is flip-chip soldered to the multi-layer circuit board and is electrically connected to the multi-layer circuit board;

[0009] An anti-warping member is provided in the multi-layer circuit board; a projection of the photonic integrated circuit chip on the surface of the multi-layer circuit board and a projection of the anti-warping member on the surface of the multi-layer circuit board at least partially overlap.

[0010] In an optional embodiment, the projection of the anti-warping member on the surface of the multi-layer circuit board covers the projection of the flip-chip soldered region of the photonic integrated circuit chip on the surface of the multi-layer circuit board.

[0011] In an optional embodiment, the multilayer circuit board includes a stacked first outer layer structure, an inner layer structure, and a second outer layer structure, the first outer layer structure includes a first surface of the multilayer circuit board, the second outer layer structure includes a second surface of the multilayer circuit board, and the first surface is opposite to the second surface; the anti-warping component is buried in the inner layer structure.

[0012] In an optional embodiment, the side of the anti-warping member close to the first surface is spaced apart from the first surface by a first distance, and the side of the anti-warping member close to the second surface is spaced apart from the second surface by a second distance, and the first distance and the second distance are equal.

[0013] In an optional embodiment, the thickness of the anti-warping member is 20% to 80% of the thickness of the multi-layer circuit board.

[0014] In an optional embodiment, a groove is provided on a side of the multi-layer circuit board facing away from the photonic integrated circuit chip, and the anti-warping member is provided in the groove.

[0015] In an optional embodiment, the anti-warping member is flush with a surface of the multi-layer circuit board on a side facing away from the photonic integrated circuit chip.

[0016] In an optional embodiment, the thickness of the anti-warping member is 30% to 50% of the thickness of the multi-layer circuit board.

[0017] In an optional embodiment, the optical coupling port is located at an edge of the photonic integrated circuit chip, and the edge of the optical coupling port is extended outside the multi-layer circuit board; or, the optical coupling port is located on a surface of the photonic integrated circuit chip facing away from the multi-layer circuit board.

[0018] In an optional embodiment, the photonic integrated circuit chip has a plurality of optical coupling ports arranged side by side, and the plurality of optical coupling ports are used for optical coupling with an optical element array outside the photonic integrated circuit chip.

[0019] In an optional embodiment, the thermal expansion coefficient of the anti-warping member matches the thermal expansion coefficient of the photonic integrated circuit chip.

[0020] In an optional embodiment, the anti-warping member is one of an aluminum nitride ceramic sheet, a glass sheet, a silicon sheet and a tungsten copper block.

[0021] In an optional embodiment, the surface where the anti-warping member is combined with the multi-layer circuit board is provided with a copper plating layer;

[0022] The thickness of the copper plating layer is less than or equal to 40 microns.

[0023] In a second aspect, the present application provides an optical module, comprising the above-mentioned optoelectronic co-packaging structure.

[0024] The optical module further comprises an optical fiber array, one end of the optical fiber array is optically coupled to the optical coupling port of the photonic integrated circuit chip, and the other end of the optical fiber array has an optical fiber connector, and the optical fiber connector is used to connect to an external optical fiber.

[0025] The beneficial effects of this application include:

[0026] The optoelectronic co-packaging structure provided in the present application is provided with an anti-warping member in the multi-layer circuit board welded to the photonic integrated circuit chip, and the anti-warping member is located inside the multi-layer circuit board in the corresponding welding area, which can effectively reduce the warping deformation of the multi-layer circuit board and the photonic integrated circuit chip caused by thermal stress, thereby solving the problem of deviation of the optical coupling port of the photonic integrated circuit chip, improving the stability of the coupled optical path, reducing the risk of cracking of the flip-chip solder joints, and improving the packaging reliability.

[0027] The present application also provides an optical module, including the above-mentioned optoelectronic co-packaging structure, which can solve the problem of optical coupling port deviation of the photonic integrated circuit chip and the problem of flip-chip solder joint cracking, thereby improving the stability of the coupled optical path and the packaging reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0029] Figure 1A schematic diagram of a structure in which an existing optoelectronic co-packaging structure is warped;

[0030] Figure 2 A schematic diagram of the structure of an optical module provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a first structural embodiment of the optoelectronic co-packaging structure provided in the present application;

[0032] Figure 4 A schematic diagram of a second structure of the optoelectronic co-packaging structure provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of a third structural embodiment of the optoelectronic co-packaging structure provided in the present application;

[0034] Figure 6 for Figure 5 Schematic diagram of the structure of the multi-layer circuit board in the optoelectronic co-packaging structure.

[0035] Icons: 100- optoelectronic co-packaging structure; 10- circuit board; 20- silicon photonic chip; 110- multi-layer circuit board; 111- solder ball; 112- wiring layer; 113- groove; 114- adhesive layer; 101- first outer layer structure; 102- inner layer structure; 103- second outer layer structure; 104- first surface; 105- second surface; 120- photonic integrated circuit chip; 40, 121- optical coupling port; 122- solder joint; 130- anti-warping part; 30, 140- bottom filling glue; 200- optical module; 210- optical fiber array; 220- optical fiber connector; 230- light source. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the utility model product is typically placed when in use. These terms are intended only to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0040] Furthermore, terms such as "horizontal" and "vertical" do not necessarily mean that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0041] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0042] As the speed of optical modules increases to single-channel 100Gbps / 200Gbps and above, the requirements for high-speed links are becoming increasingly simple. Flipping high-speed chips directly onto the circuit board 10 has become an effective solution to increase bandwidth. In the existing solution of mounting the silicon photonic chip 20 on the circuit board 10, the expansion coefficient of the silicon photonic chip 20 is generally below 4ppm, and the expansion coefficient of the circuit board 10 is approximately 9ppm below the Tg (glass transition temperature point), and the expansion coefficient rises sharply above the Tg point, and the Tg point is lower than the furnace temperature of the lead-free reflow soldering. This means that in the reflow soldering process, since the soldering temperature is higher than the Tg point, the expansion of the silicon photonic chip 20 is lower, while the expansion of the circuit board 10 is larger. This trend remains when the temperature drops to the solder curing temperature, that is, the expansion of the silicon photonic chip 20 is lower, while the expansion of the circuit board 10 is larger. Finally, after the temperature drops to room temperature, the side of the circuit board 10 where the silicon photonic chip 20 is soldered shrinks less overall due to the constraint of the silicon photonic chip 20; while the free side of the circuit board 10 (that is, the side of the circuit board 10 facing away from the silicon photonic chip 20) shrinks more, causing the circuit board 10 to be warped as a whole. Figure 1 The warping of the circuit board 10 will pull the solder joints between the circuit board 10 and the silicon photonic chip 20, which may easily cause the solder joints to crack, and then cause poor electrical contact or failure between the silicon photonic chip 20 and the circuit board 10, thereby reducing the reliability of the package.

[0043] Furthermore, when filling the bottom filling glue 30 subsequently, the expansion coefficient of the glue is larger than the expansion coefficient of the silicon photonic chip 20 , and is further deteriorated after high-temperature curing, thereby exacerbating the warping deformation of the circuit board 10 .

[0044] Furthermore, the silicon photonic chip 20 has an array of optical coupling ports that are optically aligned with the outside world, requiring very strict optical alignment. Because the overall structure of the circuit board 10, silicon photonic chip 20, and underfill 30 changes with temperature, the amount of warpage also changes dynamically. This results in the optical coupling ports 40 distributed on the silicon photonic chip 20 having inconsistent heights along the Z axis—that is, they are not on the same horizontal plane and vary dynamically. This increases the difficulty of optical coupling and directly affects the optical coupling efficiency and optical path stability.

[0045] To overcome at least one technical drawback of the prior art, this embodiment proposes an optoelectronic co-packaging structure that reduces warping and deformation of multi-layer circuit boards, thereby lowering the risk of solder joint cracking and improving package reliability. This also helps ensure that all optical coupling ports are aligned at the same height, reducing coupling difficulty and improving optical coupling efficiency and optical path stability.

[0046] Combine Figure 2An embodiment of the present application provides an optical module 200, comprising a multi-layer circuit board 110, a photonic integrated circuit chip 120, a light source 230, and an optical fiber array 210. The photonic integrated circuit chip 120 is flip-chip soldered on the multi-layer circuit board 110 and electrically connected to the multi-layer circuit board 110. The light source 230 may be a laser. The photonic integrated circuit chip 120 has an array of optical coupling ports coupled to the optical fiber array 210 and the light source 230. One end of the optical fiber array 210 is optically coupled to the optical coupling port of the photonic integrated circuit chip 120, and the other end has an optical fiber connector 220, which is used to connect to an external optical fiber. It can be understood that in some embodiments, the light source 230 can also be optically coupled to the photonic integrated circuit chip 120 through the optical fiber array 210.

[0047] Figure 2 The optical module 200 shown adopts a pluggable packaging form, and one end of its multi-layer circuit board 110 has a gold finger, which can realize pluggable electrical connection with external devices such as switches and servers through the gold finger. In some embodiments, the optical module 200 can also adopt a near packaged optics (NPO) form, and can also adopt a co-packaged optics (CPO) form. This application does not limit the external packaging form of the optical module 200. An electrical chip (not shown in the figure) is also flip-chip soldered on the above-mentioned multi-layer circuit board 110, and the electrical chip is electrically connected to the photonic integrated circuit chip 120 through the multi-layer circuit board 110. The optical module 200 adopts an optoelectronic co-packaging structure in which the photonic integrated circuit chip 120 and the electrical chip are flip-chip soldered on the multi-layer circuit board 110, which improves the high-frequency performance of the high-speed link and can achieve a higher transmission rate. The optoelectronic co-packaging structure adopted by the optical module 200 of this application will be described in detail below with reference to the accompanying drawings.

[0048] Please combine Figure 3 This embodiment provides an optoelectronic co-package structure 100, comprising a multi-layer circuit board 110, a photonic integrated circuit chip 120, and an anti-warpage member 130. The photonic integrated circuit chip 120 is provided with an optical waveguide and an optical coupling port 121 connected to the optical waveguide. The optical coupling port 121 is configured to optically couple with an optical element external to the photonic integrated circuit chip 120. The photonic integrated circuit chip 120 is flip-chip soldered to the multi-layer circuit board 110 and electrically connected to the multi-layer circuit board 110.

[0049] The photonic integrated circuit chip 120 in this embodiment is a PIC chip (abbreviated as PIC). PIC chips include, but are not limited to, silicon photonic chips. The PIC chip 120 and the multilayer circuit board 110 are each provided with corresponding fine bump arrays. Through a flip-chip soldering process, the bump arrays of the two are aligned and soldered together, forming solder joints 122 between the PIC chip 120 and the multilayer circuit board 110, thereby achieving an electrical connection between the PIC chip 120 and the multilayer circuit board 110.

[0050] The anti-warping member 130 is disposed within the multilayer circuit board 110. The projection of the photonic integrated circuit chip 120 on the surface of the multilayer circuit board 110 and the projection of the anti-warping member 130 on the surface of the multilayer circuit board 110 at least partially overlap, and may overlap completely or partially. The presence of the anti-warping member 130 in the area of the multilayer circuit board 110 corresponding to the photonic integrated circuit chip 120 reduces warping deformation of the multilayer circuit board 110 and the photonic integrated circuit chip 120 caused by thermal stress, avoids problems such as cracking of the solder joints 122 caused by warping deformation of the multilayer circuit board 110, and improves packaging quality and reliability. This also solves the problem of mutual deviation of the optical coupling ports 121 of the photonic integrated circuit chip 120, reduces coupling difficulty, and meets the strict optical alignment requirements of the optical coupling ports 121, thereby improving optical coupling efficiency and optical path stability.

[0051] In this embodiment, the thermal expansion coefficient of the anti-warping member 130 matches that of the photonic integrated circuit chip 120. "Matching" here can be understood as being identical or similar. The thermal expansion coefficient of the anti-warping member 130 is lower than that of the multi-layer circuit board 110, and the thermal expansion coefficient of the anti-warping member 130 is closer to that of the photonic integrated circuit chip 120. This can solve the problem of uneven shrinkage caused by the large difference in thermal expansion coefficients between the multi-layer circuit board 110 and the photonic integrated circuit chip 120, and reduce the warping deformation of the multi-layer circuit board 110 and the photonic integrated circuit chip 120. Optionally, the anti-warping member 130 can be any one of an aluminum nitride ceramic sheet, a glass sheet, a silicon wafer, and a tungsten copper block. In this embodiment, the anti-warping member 130 is an aluminum nitride ceramic sheet. The thermal expansion coefficient of the aluminum nitride ceramic sheet is approximately 4 ppm, which is slightly different from the thermal expansion coefficient of the photonic integrated circuit chip 120. In addition, the cost of the aluminum nitride ceramic sheet is extremely low, making it more conducive to mass production.

[0052] In this embodiment, the projection of the anti-warpage member 130 on the surface of the multilayer circuit board 110 overlaps the projection of the area on the multilayer circuit board 110 where the photonic integrated circuit chip 120 is flip-chip bonded to the multilayer circuit board 110. In other words, the position of the anti-warpage member 130 on the multilayer circuit board 110 corresponds to the position of the flip-chip bonded area on the multilayer circuit board 110, and the anti-warpage member 130 is larger than the flip-chip bonded area. This effectively utilizes the anti-warpage member 130 to reduce the local thermal expansion coefficient at the location on the multilayer circuit board 110 where the photonic integrated circuit chip 120 is mounted, improve the matching of the thermal expansion coefficients of the flip-chip bonded area of the multilayer circuit board 110 and the photonic integrated circuit chip 120, reduce the warpage deformation of the multilayer circuit board 110 and the photonic integrated circuit chip 120, better resolve the problem of misalignment of the optical coupling port 121 of the photonic integrated circuit chip 120, and reduce the risk of cracking in the flip-chip bonded joints, thereby improving the stability of the coupling optical path and the reliability of the package.

[0053] The anti-warpage member 130 is in the form of a plate or strip. In this embodiment, the anti-warpage member 130 is a flat sheet or block, and the multilayer circuit board 110 is an organic multilayer circuit board 110. Adding the anti-warpage member 130, which has a low thermal expansion coefficient, to the multilayer circuit board 110 reduces warpage during reflow soldering. This approach is more cost-effective than using purely inorganic multilayer ceramic boards, thus saving costs.

[0054] In this embodiment, the anti-warping member 130 is embedded in the multi-layer circuit board 110. For example, the anti-warping member 130 is completely embedded in the multi-layer circuit board 110 by lamination.

[0055] Specifically, multilayer circuit board 110 is a multilayer printed circuit board (PCB) comprising a first outer layer structure 101, an inner layer structure 102, and a second outer layer structure 103 stacked along the thickness direction. First outer layer structure 101 comprises a first surface 104 of multilayer circuit board 110, and second outer layer structure 103 comprises a second surface 105 of multilayer circuit board 110, with first surface 104 and second surface 105 facing away from each other. Anti-warpage member 130 is embedded within inner layer structure 102. During the manufacturing process of the multilayer printed circuit board, after inner layer structure 102 is laminated with first outer layer structure 101 or second outer layer structure 103, grooves may be formed in inner layer structure 102, a flattened anti-warpage member 130 may be added, and the remaining outer layer structure of multilayer circuit board 110 may be laminated thereon, thereby embedding anti-warpage member 130 within multilayer circuit board 110 through lamination. Of course, anti-warpage member 130 may also be embedded within multilayer circuit board 110 through other methods. Optionally, the anti-warpage member 130 can be fixed to the internal layer structure 102 by bonding. In this embodiment, the surface of the anti-warpage member 130 that bonds to the multilayer circuit board 110 is provided with a copper plating layer. Specifically, a thin layer of copper can be plated on both surfaces of the anti-warpage member 130 that face each other in the thickness direction of the multilayer circuit board 110 to better bond the anti-warpage member 130 to the multilayer circuit board 110. The thickness of the copper plating layer is less than or equal to 40 microns to minimize the impact on the overall thermal expansion coefficient of the anti-warpage member 130.

[0056] In this embodiment, along the thickness direction of the multilayer circuit board 110, the side of the anti-warpage member 130 closest to the first surface 104 is spaced apart from the first surface 104 by a first distance, and the side of the anti-warpage member 130 closest to the second surface 105 is spaced apart from the second surface 105 by a second distance, with the first and second distances being equal. This arrangement provides a more even force distribution on both sides of the multilayer circuit board 110, further reducing the overall deformation of the multilayer circuit board 110. Furthermore, during the manufacturing process of the multilayer circuit board 110, positioning the anti-warpage member 130 in the middle of the multilayer circuit board 110 facilitates adjusting the amount of adhesive used to bond the anti-warpage member 130, facilitating the process and improving the bonding strength between the anti-warpage member 130 and the multilayer circuit board 110. Furthermore, positioning the anti-warpage member 130 in the middle of the multilayer circuit board 110 minimizes the impact on the precision of the wiring layer 112 within the multilayer circuit board 110, making the layout of the wiring layer 112 more convenient.

[0057] Optionally, the thickness of the anti-warpage member 130 is 20% to 80% of the thickness of the multilayer circuit board 110. This configuration ensures minimal deformation of the multilayer circuit board 110, providing sufficient bending resistance and achieving a better anti-warpage effect. It also ensures that the anti-warpage member 130 does not occupy excessive internal space within the multilayer circuit board 110, minimizing its impact on the wiring layer 112 within the multilayer circuit board 110. In this embodiment, the thickness of the anti-warpage member 130 is consistent with the thickness of the internal layer structure 102, facilitating the manufacture of the multilayer circuit board 110.

[0058] Combine Figure 4 In some embodiments, the multilayer circuit board 110 can also serve as an interposer, and the wiring layer 112 within the multilayer circuit board 110 can be used to implement fan-out of bumps on the multilayer circuit board 110. For example, solder balls 111 are provided on the side of the multilayer circuit board 110 facing away from the photonic integrated circuit chip 120. The solder balls 111 are used to solder and electrically connect the multilayer circuit board 110 to other substrates.

[0059] Combine Figure 5 and Figure 6 In some other embodiments, the anti-warping member 130 and the multi-layer circuit board 110 may also be combined in the following manner: the anti-warping member 130 is embedded in the side of the multi-layer circuit board 110 facing away from the photonic integrated circuit chip 120 .

[0060] Specifically, a groove 113 is provided on the side of the multi-layer circuit board 110 facing away from the photonic integrated circuit chip 120, and the anti-warping member 130 is provided in the groove 113. Optionally, the anti-warping member 130 is bonded to the multi-layer circuit board 110 using an adhesive layer 114. After the bottom wall and the side wall of the groove 113 are coated with glue respectively, the anti-warping member 130 is bonded to the groove 113. The anti-warping member 130 can be fixed to the multi-layer circuit board 110 when the multi-layer circuit board 110 is manufactured, and can be shipped together after the multi-layer circuit board factory completes the production. It can also be as shown in FIG. Figure 6 As shown, a groove 113 is reserved when the multi-layer circuit board 110 is manufactured, and the anti-warping member 130 is buried in the groove 113 during the module packaging process, which makes the manufacturing more flexible. In this embodiment, the anti-warping member 130 is flush with the surface of the multi-layer circuit board 110 on the side facing away from the photonic integrated circuit chip 120. That is, the depth of the groove 113 is set according to the thickness of the anti-warping member 130. This ensures that the surface of the multi-layer circuit board 110 is flat and has no depressions or protrusions. In this embodiment, a copper plating layer can also be provided on the surface where the anti-warping member 130 is combined with the multi-layer circuit board 110. Specifically, a thin copper layer can be plated on the surface of the anti-warping member 130 opposite to the bottom surface of the groove 113 to better combine the anti-warping member 130 with the multi-layer circuit board 110. The thickness of the copper plating layer is less than or equal to 40 microns to reduce the impact on the overall thermal expansion coefficient of the anti-warping member 130.

[0061] In this embodiment, the thickness of the anti-warpage member 130 is 30% to 50% of the thickness of the multilayer circuit board 110. This ensures that the overall deformation of the multilayer circuit board 110 is minimal, resulting in a better anti-warpage effect. At the same time, the anti-warpage member 130 does not occupy too much space within the multilayer circuit board 110, minimizing the impact on the wiring layers 112 within the multilayer circuit board 110.

[0062] Optionally, underfill 140 is provided in the gaps between the solder joints 122 between the photonic integrated circuit chip 120 and the multi-layer circuit board 110. The underfill 140 protects the electrical connection between the photonic integrated circuit chip 120 and the multi-layer circuit board 110. It also insulates and isolates the multiple solder joints 122 between the photonic integrated circuit chip 120 and the multi-layer circuit board 110, preventing short circuits between the solder joints 122.

[0063] Combine Figure 2 and 3 In the illustrated embodiment, the optical coupling port 121 of the photonic integrated circuit chip 120 is located at an edge of the photonic integrated circuit chip 120, and the edge where the optical coupling port 121 is located extends outside the multilayer circuit board 110. That is, the photonic integrated circuit chip 120 partially extends outside the multilayer circuit board 110, appearing suspended. This ensures that the edge where the optical coupling port 121 is located is not blocked by the multilayer circuit board 110, facilitating alignment, coupling, and fixation with the optical fiber array 210. In this embodiment, the projection of the remaining portion of the photonic integrated circuit chip 120, excluding the edge end extending outside the multilayer circuit board 110, onto the surface of the multilayer circuit board 110 falls within the projection of the anti-warpage member 130 onto the surface of the multilayer circuit board 110.

[0064] In other embodiments, the optical coupling port 121 may also be located on the surface of the photonic integrated circuit chip 120 facing away from the multilayer circuit board 110, such as a grating coupling port or a vertical coupling port. This eliminates the need for the photonic integrated circuit chip 120 to be partially suspended outside the multilayer circuit board 110, improving packaging reliability. In this embodiment, the projection of the photonic integrated circuit chip 120 on the surface of the multilayer circuit board 110 can completely fall within the projection of the anti-warpage member 130 on the surface of the multilayer circuit board 110.

[0065] In the embodiment provided herein, the photonic integrated circuit chip 120 has a plurality of optical coupling ports 121 arranged side by side. The plurality of optical coupling ports 121 are used to optically couple with an optical element array external to the photonic integrated circuit chip 120. The optical element includes, but is not limited to, an optical fiber array 210, such as the optical fiber array 210 in the aforementioned optical module 200, or a light source array.

[0066] In summary, the optoelectronic co-packaging structure 100 and the optical module 200 provided in the embodiments of the present application have the following beneficial effects, including:

[0067] The optoelectronic co-packaging structure 100 provided in the embodiment of the present application has an anti-warping member 130 that matches the photonic integrated circuit chip 120 within the multi-layer circuit board 110 soldered to the photonic integrated circuit chip 120. The anti-warping member 130 is located inside the multi-layer circuit board 110 in the corresponding soldering area, providing sufficient bending resistance for the multi-layer circuit board 110. It can effectively reduce the warping deformation of the multi-layer circuit board 110 and the photonic integrated circuit chip 120 caused by thermal stress, thereby solving the problem of deviation of the optical coupling port 121 of the photonic integrated circuit chip 120, reducing the coupling difficulty, and improving the optical coupling efficiency and the stability of the coupling optical path. It also reduces the risk of cracking of the flip-chip solder joints and improves the packaging reliability. In addition, the multi-layer circuit board 110 adopts a combination of an organic multi-layer circuit board and an anti-warping member 130, which is lower in cost than using a multi-layer ceramic board, which is conducive to cost savings.

[0068] The optical module 200 provided in the embodiments of the present application, comprising a light array 210 and the aforementioned optoelectronic co-packaging structure 100, can effectively address the problem of misalignment of the optical coupling port 121 of the photonic integrated circuit chip 120, reducing coupling difficulty and improving optical coupling efficiency and optical path stability. Furthermore, it can address the problem of cracking in the solder joints 122 between the multilayer circuit board 110 and the photonic integrated circuit chip 120 caused by warping of the multilayer circuit board 110, thereby improving packaging quality and reliability.

[0069] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A photoelectric co-packaging structure, characterized in that: include: Multilayer circuit boards; A photonic integrated circuit chip, wherein the photonic integrated circuit chip is provided with an optical waveguide and an optical coupling port connected to the optical waveguide; the optical coupling port is used to optically couple with an optical element external to the photonic integrated circuit chip; the photonic integrated circuit chip is flip-chip soldered to the multi-layer circuit board and is electrically connected to the multi-layer circuit board; An anti-warping member is provided in the multi-layer circuit board; a projection of the photonic integrated circuit chip on the surface of the multi-layer circuit board and a projection of the anti-warping member on the surface of the multi-layer circuit board at least partially overlap.

2. The optoelectronic co-packaging structure according to claim 1, characterized in that: The projection of the anti-warping member on the surface of the multi-layer circuit board covers the projection of the region where the photonic integrated circuit chip is flip-chip soldered to the multi-layer circuit board on the surface of the multi-layer circuit board.

3. The optoelectronic co-packaging structure according to claim 1, characterized in that: The multilayer circuit board includes a stacked first outer layer structure, an inner layer structure, and a second outer layer structure, wherein the first outer layer structure includes a first surface of the multilayer circuit board, the second outer layer structure includes a second surface of the multilayer circuit board, and the first surface is opposite to the second surface; the anti-warping component is buried in the inner layer structure.

4. The optoelectronic co-packaging structure according to claim 3, characterized in that: The side of the anti-warping member close to the first surface is spaced apart from the first surface by a first distance, and the side of the anti-warping member close to the second surface is spaced apart from the second surface by a second distance, and the first distance and the second distance are equal.

5. The optoelectronic co-packaging structure according to claim 1, characterized in that: The thickness of the anti-warping member is 20% to 80% of the thickness of the multi-layer circuit board.

6. The optoelectronic co-packaging structure according to claim 1, characterized in that: A groove is provided on a side of the multilayer circuit board facing away from the photonic integrated circuit chip, and the anti-warping component is arranged in the groove.

7. The optoelectronic co-packaging structure according to claim 6, characterized in that: The anti-warping member is flush with a surface of the multi-layer circuit board on a side facing away from the photonic integrated circuit chip.

8. The optoelectronic co-packaging structure according to claim 7, characterized in that: The thickness of the anti-warping member is 30% to 50% of the thickness of the multi-layer circuit board.

9. The optoelectronic co-packaging structure according to claim 1, wherein: The optical coupling port is located at an edge of the photonic integrated circuit chip, and the edge of the optical coupling port is arranged to extend outside the multi-layer circuit board; Alternatively, the optical coupling port is located on a surface of the photonic integrated circuit chip facing away from the multi-layer circuit board.

10. The optoelectronic co-packaging structure according to claim 1, wherein: The photonic integrated circuit chip has a plurality of optical coupling ports arranged side by side, and the plurality of optical coupling ports are used for optical coupling with an optical element array outside the photonic integrated circuit chip.

11. The optoelectronic co-packaging structure according to any one of claims 1 to 10, characterized in that: The thermal expansion coefficient of the anti-warping member matches the thermal expansion coefficient of the photonic integrated circuit chip.

12. The optoelectronic co-packaging structure according to claim 11, characterized in that: The anti-warping component is one of an aluminum nitride ceramic sheet, a glass sheet, a silicon sheet and a tungsten copper block.

13. The optoelectronic co-packaging structure according to claim 11, characterized in that: The surface where the anti-warping member is bonded to the multi-layer circuit board is provided with a copper plating layer; The thickness of the copper plating layer is less than or equal to 40 microns.

14. An optical module, characterized in that: The optoelectronic co-packaging structure comprises the optoelectronic co-packaging structure according to any one of claims 1 to 13.

15. The optical module according to claim 14, wherein: The optical module further includes an optical fiber array, one end of which is optically coupled to the optical coupling port of the photonic integrated circuit chip, and the other end of which is provided with an optical fiber connector for connecting to an external optical fiber.

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