SGPIO multipath expansion circuit

Abstract

The SGPIO multi-path expansion circuit provided by the embodiment of the utility model comprises a mainboard management controller BMC and at least two complex programmable logic devices CPLDs connected with the BMC in series, each CPLD comprises an SGPIO slave node Slave and a first multiplexer MUX connected with the SGPIO slave node Slave, an output interface of the BMC is connected with the SGPIO slave node Slave in each CPLD, and an output interface of the BMC is connected with the first multiplexer MUX. Different SGPIO Slaves are configured to analyze signals of preset storage space digits in first signals transmitted by the output interface of the BMC. According to the technical scheme, the SGPIO Slave in the CPLD receives the signals transmitted by the output interface of the BMC, then the SGPIO Slave only analyzes the signals with the preset storage space bits in the first signals, and then the unanalyzed signal data is transmitted to the next CPLD to be analyzed, so that logic resources consumed by the CPLD are reduced, and the real-time performance of data transmission is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a serial general purpose input / output (SGPIO) multi-channel expansion circuit. Background Art

[0002] Currently, the Baseboard Management Controller (BMC) communicates with Complex Programmable Logic Devices (CPLDs) and other devices using SGPIO. Each device requires the BMC to implement an SGPIO function and consumes a group of SGPIO pin resources.

[0003] However, existing BMC solutions for calling multiple SGPIOs to access multiple CPLDs typically connect the BMC's SGPIO master node (English: Master) to the CPLD's SGPIO slave node (English: Slave) in a one-to-one correspondence. Each device occupies a set of BMC SGPIO controllers and four pins. When there are too many devices, the required pin resources are very large, resulting in a shortage of BMC pin resources.

[0004] Therefore, how to design a circuit for transmitting data between CPLD and BMC based on SGPIO multi-channel expansion has become a technical problem that needs to be solved urgently. Utility Model Content

[0005] The embodiment of the present application provides an SGPIO multi-channel expansion circuit to solve the problem in the prior art of how to design a circuit for transmitting data between a CPLD and a BMC based on SGPIO multi-channel expansion.

[0006] In a first aspect, an embodiment of the present application provides an SGPIO multi-channel expansion circuit, the circuit comprising: a mainboard management controller BMC, at least two complex programmable logic devices CPLD connected in series with the BMC;

[0007] For each CPLD, the CPLD includes: an SGPIO slave node Slave, and a first multiplexer MUX connected to the SGPIO Slave;

[0008] The output interface of the BMC is connected to the SGPIO Slave in each CPLD respectively, and different SGPIO Slaves are configured to parse the signal of the preset storage space bit in the first signal transmitted from the output interface of the BMC.

[0009] In one or more embodiments, for each CPLD, the CPLD further includes: a counting unit connected to the SGPIO Slave;

[0010] The counting unit is used to count the number of bits of the first signal parsed by the SGPIO Slave.

[0011] In one or more embodiments, for each CPLD, the CPLD further includes: a register connected to the first MUX via a first line;

[0012] The register is used to store a signal of a preset storage space bit number in the parsed first signal.

[0013] In one or more embodiments, for each CPLD, the register is connected to the SGPIO Slave;

[0014] The SGPIO Slave is used to obtain first data from the register.

[0015] In one or more embodiments, for each CPLD, the CPLD further includes: a second MUX connected to the SGPIO Slave;

[0016] The second MUX is used to obtain the first data of the SGPIO Slave.

[0017] In one or more embodiments, for each CPLD, the second MUX is connected to the counting unit;

[0018] The counting unit is further configured to count the number of bits of the first data sent by the SGPIO Slave.

[0019] In one or more embodiments, for each CPLD, the first MUX is connected to the register via a second line;

[0020] The first MUX is used to store the original data in the register.

[0021] In one or more embodiments, the at least two CPLDs include: a first CPLD, a second MUX in the first CPLD being connected to an input interface of the BMC;

[0022] The second MUX in the first CPLD is used to transmit the acquired first data to the BMC.

[0023] In one or more embodiments, the second MUXs in the respective CPLDs are connected in series;

[0024] For any second MUX, the second MUX is used to obtain first data in a serial CPLD that is not directly connected to the BMC.

[0025] In one or more embodiments, the counting unit is a data byte count DBC.

[0026] The SGPIO multi-channel expansion circuit provided in the embodiment of the present application includes: a BMC, at least two complex programmable logic devices (CPLDs) connected in series with the BMC, and for each CPLD, the CPLD includes: an SGPIO slave node (Slave), a first multiplexer (MUX) connected to the SGPIO Slave, the output interface of the BMC is respectively connected to the SGPIO Slave in each CPLD, and different SGPIO slaves are configured to parse the signal of the preset number of storage space bits in the first signal transmitted from the output interface of the BMC. In this technical solution, the SGPIO Slave in the CPLD receives the signal transmitted from the output interface of the BMC, and then the SGPIO slave only parses the signal of the preset number of storage space bits in the first signal, and then transparently transmits the unparsed signal to the next CPLD for parsing, thereby reducing the logic resources consumed by the CPLD, while reducing the data transmission time from the BMC to the CPLD, and improving the real-time performance of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0028] Figure 1 Schematic diagram of the prior art BMC accessing multiple CPLDs provided in the embodiment of this application Figure 1 ;

[0029] Figure 2 Schematic diagram of the prior art BMC accessing multiple CPLDs provided in the embodiment of this application Figure 2 ;

[0030] Figure 3 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 1 ;

[0031] Figure 4 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 2 ;

[0032] Figure 5 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 3 ;

[0033] Figure 6Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 4 .

[0034] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0035] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] Before introducing the embodiments of the present application, the application background of the embodiments of the present application is first explained:

[0037] Currently, the BMC communicates with the CPLD and other devices using the Serial General Purpose Input / Output (SGPIO) interface. Each device requires the BMC to implement an SGPIO function and consumes a group of SGPIO pin resources to achieve communication. Therefore, pin allocation must be properly configured to ensure that all devices can work properly and effectively improve the communication efficiency between the BMC, CPLD, and other devices.

[0038] However, existing multi-SGPIO device management typically instantiates both the SGPIO Master and SGPIO Slave within the CPLD. The Slave interface connects to the CPLD, and the Master interface connects to the BMC. Multiple CPLDs form a series structure. This approach reduces BMC resources but significantly increases the resources required by the CPLD, thereby increasing the cost of CPLD chip selection. Furthermore, the information obtained by the BMC has a large latency, making real-time performance difficult.

[0039] Figure 1 Schematic diagram of the prior art BMC accessing multiple CPLDs provided in the embodiment of this application Figure 1 , combined with Figure 1 Introduction to existing technologies:

[0040] When the BMC calls multiple SGPIOs to access multiple CPLDs, each device occupies a set of BMC SGPIO controllers. The SGPIO Master interface in the BMC is connected to the SGPIO Slave interface of a CPLD. Each SGPIO interface has four pins. When there are too many devices, the required pin resources are very large, resulting in a shortage of BMC pin resources.

[0041] Figure 2 Schematic diagram of the prior art BMC accessing multiple CPLDs provided in the embodiment of this application Figure 2 , combined with Figure 2 Another existing technology is introduced:

[0042] Each CPLD is connected through a series structure, and information data needs to be transmitted forward one level at a time until it reaches the BMC. For CPLDs that are further back, the time required to transmit data to the BMC will become longer and longer, which will have a greater impact on functions with high real-time requirements.

[0043] In one possible implementation, Figure 2 As shown, each CPLD needs to transmit 256 bytes of data. There are three CPLDs in the series structure mode, and the frequency is calculated at 100 kHz:

[0044] The data length that needs to be transmitted between the BMC and CPLD#1's SGPIO is 256*3*8 bits, and one transmission takes 256*3*8*10us=61440us.

[0045] The data length that needs to be transmitted by the SGPIO of CPLD#1 and CPLD#2 is 256*2*8 bits. One transmission takes 256*2*8*10us=40960us. The time required for the data from CPLD#2 to reach the BMC is between 61440+40960us and 61440*2+40960us, that is, between 102400us and 163840us.

[0046] The data length that needs to be transmitted by the SGPIO of CPLD#2 and CPLD#3 is 256*1*8 bits. One transmission takes 256*1*8*10us=20480us. The time required for the data from CPLD#3 to reach CPLD1 is between 40960+20480us and 40960*2~20480us, that is, between 61440 and 102440us. The time required for the data from CPLD#3 to reach the BMC is between 163840us and 266280us.

[0047] In summary, the more CPLDs there are in the series structure and the longer the transmitted data is, the longer the data delay is and the more logic resources are consumed.

[0048] In response to the technical problems existing in the prior art, the inventors of the present application have the following idea: whereas each CPLD in the prior art receives and parses all data of the signal transmitted by the BMC, the CPLDs of the present application adopt a series structure. If the BMC needs to transmit a signal to multiple CPLDs, each CPLD receives and parses the data from the BMC through the SGPIO Slave interface. The current CPLD1 parses the signal that is less than or equal to the preset memory space for storing data, and the remaining data is transparently transmitted to CPLD2. CPLD2 does not parse the data that has been parsed by CPLD1, but starts to parse the signal from the last bit of the signal parsed by CPLD1, and also parses the signal that is equal to the preset memory space for storing data. The signal is transmitted backward one level at a time until the signal is transmitted to the last CPLD, thereby reducing the data transmission time from the BMC to the CPLD and improving the efficiency of data transmission.

[0049] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0050] Figure 3 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 1 ,like Figure 3 As shown, the circuit may include: a mainboard management controller BMC11, and at least two complex programmable logic devices CPLD connected in series with the BMC;

[0051] It is worth noting that the number of CPLD devices in the actual circuit can be greater than or equal to two. Figure 3 The embodiments of the present application are described using two CPLDs (ie, CPLD1 and CPLD2) as an example. The internal structures of CPLD1 and CPLD2 are the same.

[0052] In actual applications, the number and structure of CPLDs can be adjusted according to the actual application scenarios.

[0053] Optionally, for each CPLD, the CPLD includes: an SGPIO slave node Slave, and a first multiplexer MUX connected to the SGPIO Slave;

[0054] In this implementation, using CPLD 1 as an example, the internal logic structure of CPLD 112 can be configured through programming, supporting multiple input / output voltage standards and adapting to different circuit interface requirements. SGPIO Slave 121 is used to connect and control various external devices, responding to master node requests and performing corresponding operations. MUX 122's main function is to select and output multiple input signals to a single output line.

[0055] Optionally, the output interface of the BMC is connected to the SGPIO Slave in each CPLD respectively, and different SGPIO Slaves are configured to parse the signal of the preset storage space bits in the first signal transmitted from the output interface of the BMC.

[0056] In this implementation, taking CPLD1 as an example, BMC 11 is a microcontroller embedded in the motherboard, which is mainly used to monitor and manage the hardware status of the computer system. Figure 1 SGPIO Master 111 is an interface for controlling and managing device status indications. SGPIO Master 111 of BMC 11 is connected to SGPIO Slave 121 of CPLD 12. SGPIO Slave 121 interprets the first signal output from BMC 11 as a signal corresponding to the number of bits in the preset storage space of CPLD 12.

[0057] The first signal may be an SGPIO clock signal (SGPIO_CLK), an SGPIO control signal (SGPIO_LOAD), and an SGPIO data output signal (SGPIO_DOUT) output by the BMC 11. The preset storage space bit number may be 256 bytes, which can be reduced or increased based on actual application scenarios.

[0058] In one possible implementation, the first signal output by the BMC 11 is 512 bits. The SGPIO Slave 121 in the CPLD 12 receives the 512-bit signal data. The CPLD 112 parses the data from 0 to 255, and the remaining signal data is not parsed and configured as 0. The CPLD 213 receives the 512-bit signal data, but only parses the data from 256 to 512, and the data from 0 to 255 is 0.

[0059] In a possible implementation, there is a situation where only 50 bits of data remain unparsed after the first signal is transmitted to the last CPLD, and then the last CPLD only parses the 50 bits of data.

[0060] The SGPIO multi-channel expansion circuit provided in an embodiment of the present application includes: a mainboard management controller (BMC) and at least two complex programmable logic devices (CPLDs) connected in series with the BMC. For each CPLD, the CPLD includes: an SGPIO slave node (Slave) and a first multiplexer (MUX) connected to the SGPIO Slave. The BMC's output interface is respectively connected to the SGPIO Slave in each CPLD, and different SGPIO Slaves are configured to parse the signal of the preset number of storage space bits in the first signal transmitted from the BMC's output interface. In this technical solution, the SGPIO Slave in the CPLD receives the signal transmitted from the BMC's output interface, and then the SGPIO Slave only parses the signal of the preset number of storage space bits in the first signal, and then transparently transmits the unparsed signal data to the next CPLD for parsing, thereby reducing the logic resources consumed by the CPLD and simultaneously shortening the data transmission time from the BMC to the CPLD, thereby improving the real-time performance of data transmission.

[0061] Based on the above embodiments, Figure 4 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 2 ,like Figure 4 As shown, for each CPLD, the CPLD further includes: a counting unit connected to the SGPIO Slave;

[0062] Optionally, the counting unit is configured to count the number of bits of the first signal parsed by the SGPIO Slave 121 .

[0063] In this implementation, the counting unit counts the number of bits of the first signal outputted by the BMC 11 and received by the SGPIO Slave 121 to ensure that the CPLD receives a signal with a preset number of bits of storage space.

[0064] Furthermore, the counting unit is a data byte count DBC.

[0065] In this implementation, the technical unit is DBC, which is a count value representing the number of data bytes during data transmission or storage. It is used to determine the length of the data stream and ensure that the receiver can correctly receive and process the data.

[0066] In the SGPIO multi-channel expansion circuit provided in an embodiment of the present application, each CPLD further includes a counting unit connected to an SGPIO slave, configured to count the number of bits of the first signal parsed by SGPIO slave 121. In this technical solution, the counting unit is used to ensure that the CPLD can receive signals with a preset number of bits of storage space and store the signals in a register, thereby improving the efficiency of the CPLD in receiving data.

[0067] Based on the above embodiments, Figure 5 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 3 ,like Figure 5 As shown, for each CPLD, the CPLD further includes: a register connected to the first MUX via a first line;

[0068] In this implementation, taking CPLD1 as an example, the first MUX 121 is connected to the register 123 via a first line.

[0069] The data transmission direction of the first line is from the first MUX 121 to the register 123 .

[0070] Optionally, the register is used to store a signal of a preset storage space bit number in the parsed first signal.

[0071] In this implementation, register 123 is a small, high-speed storage unit inside the computer for storing data and instructions, and is used to temporarily store data, addresses, instructions, etc. that need to be quickly accessed during program execution.

[0072] Further, for each CPLD, the first MUX is connected to the register via a second line;

[0073] In this implementation, taking CPLD1 as an example, the first MUX 122 is connected to the register 123 via a second line.

[0074] The data transmission direction of the second line is from the register 123 to the first MUX 122 .

[0075] Optionally, the first MUX is used to store original data in the register.

[0076] In this implementation, taking CPLD1 as an example, the first MUX 122 is used to store the original data in the register 123. The first MUX 122 selects the original data in the register 123 as output, so that the original data in the register will not be changed.

[0077] Furthermore, for each CPLD, the register is connected to the SGPIO Slave;

[0078] In a possible implementation, the register 123 of the CPLD 112 is connected to the SGPIO Slave 121 to ensure data transmission between the master device (ie, the BMC 11 ) and the slave device (ie, the CPLD 112 ).

[0079] Optionally, the SGPIO Slave is used to obtain the first data from the register.

[0080] In this implementation, the first data refers to the data stored in the register itself and the data returned by the register indicating whether the data transmitted by the SGPIO Slave is written successfully.

[0081] In a possible implementation, register 123 transmits its own stored data back to SGPIO Slave 121 , and can also transmit data back to determine whether the data written into the register by SGPIO Slave 121 is successfully written.

[0082] In the SGPIO multi-channel expansion circuit provided in an embodiment of the present application, each CPLD further includes a register connected to the first MUX via a first line, the register being configured to store a signal having a predetermined number of bits of storage space within the parsed first signal. In this technical solution, the MUX and register connection allows for retaining data in the register or updating it with new input data, thereby enabling flexible control of register data.

[0083] Based on the above embodiments, Figure 6 Schematic diagram of the connection of the SGPIO multi-channel expansion circuit provided in the embodiment of the present application Figure 4 ,like Figure 6 As shown, for each CPLD, the CPLD further includes: a second MUX connected to the SGPIO Slave;

[0084] Optionally, the second MUX is used to obtain the first data of the SGPIO Slave.

[0085] In this implementation, taking CPLD1 as an example, the second MUX 124 is used to obtain the first data sent back by the register 123 to the SGPIO Slave 121 .

[0086] The second MUX 124 has the same function as the first MUX 122 , and is used for buffering data and transmitting data.

[0087] Further, for each CPLD, a second MUX is connected to the counting unit;

[0088] In this implementation, taking CPLD1 as an example, the second MUX 124 is connected to the counting unit (ie, DBC 125 ) to complete the functions of data selection, transmission, and counting.

[0089] Optionally, the counting unit is further configured to count the number of bits of the first data sent by the SGPIO Slave.

[0090] In this implementation, the counting unit (ie, DBC 125 ) is used to count the number of bits of the first data sent by SGPIO Slave 121 to ensure that the data received by MUX 124 from SGPIO Slave 121 is equal to the signal of the number of bits of the CPLD preset storage space.

[0091] Furthermore, the at least two CPLDs include: a first CPLD, a second MUX in the first CPLD is connected to an input interface of the BMC;

[0092] In this implementation, the first CPLD is also Figure 6 CPLD 112 in the BMC input interface is also Figure 5 The SGPIOMaster 111 in the CPLD 112 and the second MUX (ie, MUX 124 ) in the CPLD 112 are connected to the SGPIO Master 111 of the BMC 11 .

[0093] Optionally, the second MUX in the first CPLD is used to transmit the acquired first data to the BMC.

[0094] Furthermore, the second MUXs in the respective CPLDs are connected in series in sequence;

[0095] In this implementation, CPLD 112 and CPLD 213 are connected in series, that is, MUX 134 of CPLD 213 is connected to MUX 124 of CPLD 112 .

[0096] Optionally, for any second MUX, the second MUX is used to obtain first data in a serial CPLD that is not directly connected to the BMC.

[0097] In this implementation, the first data refers to the data returned by the register of the CPLD itself.

[0098] In one possible implementation, the MUX 134 of the CPLD 213 receives the return data from the register 133 and transmits the data to the MUX 124 of the CPLD 112. The MUX 124 receives the return data from its own register 123, combines it with the data transmitted by the MUX 134, and then transmits it to the SGPIO Master 111 of the BMC 11.

[0099] The SGPIO multi-channel expansion circuit provided in the present application embodiment includes, for each CPLD, a second MUX connected to the SGPIO slave, configured to retrieve the first data from the SGPIO slave. In this technical solution, the second MUX in the CPLD receives return data from its own register and simultaneously receives return data from other CPLDs in the series structure, forwarding the data one level at a time to the BMC, reducing data transmission latency and improving real-time data availability.

[0100] It is worth noting that, taking the cascade of three CPLDs and SGPIO 100khz as an example, the technical solution of the embodiment of the present application not only saves the logic resources required for calling SGPIO_Master compared to the prior art, but also the time required for the data of the three CPLDs to reach the BMC is 256*3*8*10us=61440us. Compared with the time required for the data of CPLD3 in the above-mentioned prior art to reach the BMC is between 163840us and 266280us, the delay from the CPLD data to the BMC is greatly reduced, and the real-time performance of the data is improved.

[0101] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0102] It should be noted that phrases such as "one embodiment," "an embodiment," "exemplary embodiments," and "some embodiments" in this specification may indicate embodiments that may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A serial general purpose input and output (SGPIO) multi-channel expansion circuit, characterized in that: The circuit includes: a mainboard management controller BMC, and at least two complex programmable logic devices CPLD connected in series with the BMC; For each CPLD, the CPLD includes: an SGPIO slave node Slave, and a first multiplexer MUX connected to the SGPIO Slave; The output interface of the BMC is connected to the SGPIO Slave in each CPLD respectively, and different SGPIO Slaves are configured to parse the signal of the preset storage space bit in the first signal transmitted from the output interface of the BMC.

2. The circuit according to claim 1, wherein: For each CPLD, the CPLD further includes: a counting unit connected to the SGPIO Slave; The counting unit is used to count the number of bits of the first signal parsed by the SGPIO Slave.

3. The circuit according to claim 2, characterized in that For each CPLD, the CPLD further includes: a register connected to the first MUX via a first line; The register is used to store a signal of a preset storage space bit number in the parsed first signal.

4. The circuit according to claim 3, characterized in that For each CPLD, the register is connected to the SGPIOSlave; The SGPIO Slave is used to obtain first data from the register.

5. The circuit according to claim 4, characterized in that For each CPLD, the CPLD further includes: a second MUX connected to the SGPIO Slave; The second MUX is used to obtain the first data of the SGPIO Slave.

6. The circuit according to claim 5, characterized in that For each CPLD, the second MUX is connected to the counting unit; The counting unit is further configured to count the number of bits of the first data sent by the SGPIO Slave.

7. The circuit according to claim 6, characterized in that For each CPLD, the first MUX is connected to the register via a second line; The first MUX is used to store the original data in the register.

8. The circuit according to any one of claims 5 to 7, characterized in that: The at least two CPLDs include: a first CPLD, wherein a second MUX in the first CPLD is connected to an input interface of the BMC; The second MUX in the first CPLD is used to transmit the acquired first data to the BMC.

9. The circuit according to claim 8, characterized in that The second MUX in each CPLD is connected in series in sequence; For any second MUX, the second MUX is used to obtain first data in a serial CPLD that is not directly connected to the BMC.

10. The circuit according to any one of claims 2 to 7, characterized in that: The counting unit is a data byte count DBC.

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