Electrostatic protection circuit suitable for radio frequency port
By constructing an electrostatic protection circuit for ordinary transistors and passive devices at the RF port, various ESD protection problems of the RF port are solved, and efficient and economical ESD protection effects are achieved.
Patent Information
- Application Number
- CN202422768232.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2034-11-13
AI Technical Summary
Existing technologies have difficulty providing reliability protection of multiple ESD protection standards and levels at the RF ports of integrated circuits, and the use of off-chip components or ballast resistors will increase costs or affect performance.
Ordinary transistors and passive components are used to construct an electrostatic protection circuit, including a power clamp circuit, primary, secondary, and tertiary electrostatic protection branches, which provide protection against different ESD models respectively. Large-size diodes and PMOS/NMOS transistors with extended drains are used to improve the ESD protection level.
It provides reliable protection for multiple ESD protection standards and levels without increasing costs or affecting performance, and avoids the use of off-chip components and ballast resistors.
Smart Images
Figure CN223391101U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuits, in particular to an electrostatic protection circuit. Background Art
[0002] During integrated circuit manufacturing, packaging, testing, transportation, and use, static electricity from the human body, the environment, or electronic devices inevitably causes various damages to semiconductor chips. For example, in low-voltage CMOS devices, gate breakdown, internal wiring fusing, and other device damage can lead to pin failures, seriously affecting chip yield. To mitigate the effects of ESD (electrostatic discharge) on chips, the reliability of ESD protection must be considered during chip design.
[0003] There are multiple evaluation standards and models for ESD protection levels, each corresponding to different scenarios, such as the more common Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On the one hand, different standards have different focuses and discharge characteristics, requiring the design of different types of ESD protection circuits to address them. Using a single method for protection is difficult to cover all scenarios. On the other hand, consumer chips typically use ordinary transistors. When designing ESD protection circuits, high-voltage transistors that require special masks are often used to improve the protection level, which undoubtedly leads to a significant increase in chip costs. Therefore, how to develop high-reliability ESD protection circuits that can cope with various scenarios and standards without increasing chip costs has become a hot topic and difficulty in chip design.
[0004] Currently, the commonly used electrostatic protection measures are divided into two types: board level and chip level. At the board level, special TVS tubes or ESD tubes are generally used to protect the pins of the protected device 1. Figure 1 As shown, however, off-chip TVS tubes or ESD tubes will increase the cost and complexity of the solution; the chip level generally uses diodes D1 and D2 combined with a ballast resistor Rin to protect the protected device 1, as shown in the attached Figure 2 As shown, however, the structure of the diode and the ballast resistor is not suitable for RF ports with impedance requirements, such as transceiver antennas. Utility Model Content
[0005] In view of the above problems, the purpose of the present invention is to provide an electrostatic protection circuit suitable for a radio frequency port.
[0006] Electrostatic protection circuit for RF ports, including
[0007] a power clamp circuit comprising a power voltage terminal and a ground terminal;
[0008] a primary electrostatic protection branch, comprising a first diode and a second diode, wherein the anode of the first diode is connected to the RF port, the cathode of the first diode is connected to the power supply voltage terminal, the anode of the second diode is connected to the ground terminal, and the cathode of the second diode is connected to the RF port;
[0009] A three-level electrostatic protection branch includes a first PMOS transistor and a first NMOS transistor, wherein the source of the first PMOS transistor is connected to the power supply voltage terminal, the drain of the first PMOS transistor is connected to the protected device, the drain of the first NMOS transistor is connected to the protected device, and the source of the first NMOS transistor is connected to the ground terminal;
[0010] The secondary electrostatic protection branch is connected between the radio frequency port and the protected device.
[0011] The electrostatic protection circuit of the present invention, the secondary electrostatic protection branch includes:
[0012] a second NMOS transistor, wherein a drain of the second NMOS transistor is connected to the RF port, a source of the second NMOS transistor is connected to a first end of a first inductor, and a second end of the first inductor is connected to the protected device;
[0013] A first capacitor is connected between the second end of the first inductor and the ground end.
[0014] In the electrostatic protection circuit of the present invention, the gate of the first PMOS tube is connected to the source of the first PMOS tube, and the gate of the first NMOS tube is connected to the source of the first NMOS tube.
[0015] In the electrostatic protection circuit of the present invention, the body terminal and the source terminal of the second NMOS tube are short-circuited.
[0016] In the electrostatic protection circuit described in the present invention, the gate, source and body of the first PMOS tube are all connected to the power supply voltage terminal, and the width of the P-doped region of the drain of the first PMOS tube is 5 times the width of the P-doped region of the source.
[0017] In the electrostatic protection circuit of the present invention, the gate, source and body of the first NMOS tube are all connected to the ground terminal, and the width of the N-doped region of the drain of the first NMOS tube is 5 times the width of the N-doped region of the source.
[0018] In the electrostatic protection circuit of the present invention, the P-doped region of the drain of the first PMOS tube is covered with a metal silicide barrier layer.
[0019] In the electrostatic protection circuit of the present invention, the N-doped region of the drain of the first NMOS tube is covered with a metal silicide barrier layer.
[0020] In the electrostatic protection circuit of the present invention, the first-level electrostatic protection branch circuit provides protection for a human body model and a machine model.
[0021] In the electrostatic protection circuit of the present invention, the three-level electrostatic protection branch circuit protects the charging device model.
[0022] Beneficial effects: The utility model provides an electrostatic protection circuit suitable for radio frequency ports. The required components are ordinary transistors and passive devices. There is no need to add special masks, no off-chip components or on-chip series ballast resistors. It can provide reliable ESD protection for multiple protection standards and levels, avoiding the problems of existing technologies such as increasing costs by using off-chip components or affecting radio frequency port performance by using ballast resistors. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a schematic diagram of the prior art using TVS tubes to protect chip pins;
[0024] Figure 2 This is a schematic diagram of the prior art using diodes and ballast resistors to protect chip pins;
[0025] Figure 3 This is a schematic diagram of the principle of the electrostatic protection circuit applicable to the radio frequency port of the utility model;
[0026] Figure 4 It is a cross-sectional schematic diagram of the first diode in the primary electrostatic protection branch of the present utility model;
[0027] Figure 5 It is a cross-sectional schematic diagram of the second diode in the primary electrostatic protection branch of the present utility model;
[0028] Figure 6 This is a schematic cross-sectional view of the second NMOS transistor in the secondary electrostatic protection branch of the present invention;
[0029] Figure 7 This is a schematic cross-sectional view of the first PMOS transistor in the three-level electrostatic protection branch of the present invention;
[0030] Figure 8 It is a schematic cross-sectional view of the first NMOS tube in the three-level electrostatic protection branch of the present invention. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features therein can be combined with each other.
[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.
[0034] Reference Figures 3 to 8 , suitable for electrostatic protection circuits of RF ports, including:
[0035] The power clamp circuit 3 includes a power voltage terminal VCC and a ground terminal VSS;
[0036] A primary electrostatic protection branch 4 includes a first diode D1 and a second diode D2, wherein the anode of the first diode D1 is connected to the RF port 2, the cathode of the first diode D1 is connected to the power supply voltage terminal VCC, the anode of the second diode D2 is connected to the ground terminal VSS, and the cathode of the second diode D2 is connected to the RF port 2;
[0037] The third-level electrostatic protection branch 6 includes a first PMOS transistor PM1 and a first NMOS transistor NM2, wherein the source of the first PMOS transistor PM1 is connected to the power supply voltage terminal VCC, the drain of the first PMOS transistor PM1 is connected to the protected device 1, the drain of the first NMOS transistor NM2 is connected to the protected device 1, and the source of the first NMOS transistor NM2 is connected to the ground terminal VSS;
[0038] The secondary electrostatic protection branch 5 is connected between the RF port 2 and the protected device 1 .
[0039] The utility model provides an electrostatic protection circuit suitable for radio frequency ports. The required components are ordinary transistors and passive devices. No special mask is required, and no off-chip components or on-chip series ballast resistors are required. Reliable ESD protection for multiple protection standards and levels is provided, avoiding the problems of the existing technology of increasing costs by using off-chip components or affecting the performance of radio frequency ports by using ballast resistors.
[0040] See also Figure 4 , the first diode D1 of the P+ / N well of the primary electrostatic protection branch 4 includes a P substrate and an N well, the anode connected to the P+ source and drain region is connected to the RF port 2, and the cathode connected to the N well is connected to the power supply voltage terminal VCC; Figure 5 The anode of the second diode D2 in the N+ / P well, which is connected to the P substrate, is connected to the ground terminal VSS, and the cathode, which is connected to the N+ source and drain region, is connected to the RF port 2; the first diode D1 and the second diode D2 are set close to the RF port, and use large-size diodes with low on-resistance, which can quickly discharge ESD current, mainly for HBM and MM protection.
[0041] Reference Figure 3 , Figure 6 , the electrostatic protection circuit of the utility model, the secondary electrostatic protection branch 5 includes:
[0042] a second NMOS transistor NM1, wherein a drain D of the second NMOS transistor NM1 is connected to the RF port 2, a source S of the second NMOS transistor NM1 is connected to a first end of a first inductor L1, and a second end of the first inductor L1 is connected to the protected device 1;
[0043] The first capacitor C1 is connected between the second end of the first inductor L1 and the ground end VSS.
[0044] The source S and body B of the second NMOS transistor NM1 of the present invention are short-circuited, forming a reverse-biased diode viewed from the RF port 2 toward the internal protected device 1. Since the reverse-biased diode has a very high reverse breakdown voltage, it has a strong blocking effect on ESD current entering from the RF port 2, such as in HBM and MM modes. The short-circuited body B and source S of the second NMOS transistor NM1 are connected to the left port of the first inductor L1, the right port of the first inductor L1 is connected to the upper port of the first capacitor C1, and the lower port of the first capacitor C1 is connected to the ground terminal VSS. The first inductor L1 and the first capacitor C1 form an LC filter. The inductive reactance characteristics of the first inductor L1 can effectively suppress high-frequency ESD current from entering the protected device 1. At the same time, the first capacitor C1 can promptly divert a small amount of high-frequency energy passing through the first inductor L1 to the ground terminal VSS, ensuring that no damage is caused to the internal part of the protected device 1.
[0045] Reference Figure 7 In the electrostatic protection circuit of the present invention, the gate G of the first PMOS transistor PM1, the source S of the first PMOS transistor PM1 (type P-doped region), and the body terminal B of the N-well region are all connected to the power supply voltage terminal VCC. The drain D of the first PMOS transistor PM1 (type P-doped region) is connected to the protected device 1. The drain D is extended, and the width of the P-doped region of the drain D of the first PMOS transistor PM1 is five times the width of the P-doped region of the source S. In addition, the P-doped region of the drain is covered with a metal silicide barrier layer 11, which increases the distance between the drain and the gate and improves the impedance between the drain and the gate, thereby enhancing the ESD protection level.
[0046] Reference Figure 8 In the present electrostatic protection circuit, the gate G, source S, and body B of the first NMOS transistor NM2 are all connected to the ground terminal VSS. The drain D, which is an N-doped region, is connected to the protected device 1. The drain of the first NMOS transistor NM2 is extended, and the width of the N-doped region of the drain D of the first NMOS transistor NM2 is five times the width of the N-doped region of the source S. The N-doped region of the drain D is covered with a metal silicide block 21, which increases the distance between the drain and the gate and improves the drain-to-gate impedance, thereby enhancing the ESD protection level. The third-level electrostatic protection branch mainly targets discharge modes from internal chip devices, such as CDM.
[0047] This application can achieve reliable ESD protection for multiple protection standards and levels such as HBM, MM and CDM through the above-mentioned first-level electrostatic protection branch, second-level electrostatic protection branch and third-level electrostatic protection branch, avoiding the problems of existing technologies such as increasing costs by using off-chip components, or using ballast resistors to affect RF port performance.
[0048] Through the description and drawings, typical embodiments of the specific structure of the specific implementation are given. Based on the spirit of the utility model, other transformations can be made. Although the above utility model proposes existing preferred embodiments, these contents are not intended to be limiting.
[0049] Various changes and modifications will undoubtedly become apparent to those skilled in the art after reading the above description. Therefore, the appended claims should be construed to encompass all changes and modifications within the true intent and scope of the present invention. Any and all equivalents within the scope of the claims should be considered to be within the intent and scope of the present invention.
Claims
1. An electrostatic protection circuit suitable for a radio frequency port, characterized in that: include The power clamp circuit includes a power voltage terminal and a ground terminal; a primary electrostatic protection branch, comprising a first diode and a second diode, wherein the anode of the first diode is connected to the RF port, the cathode of the first diode is connected to the power supply voltage terminal, the anode of the second diode is connected to the ground terminal, and the cathode of the second diode is connected to the RF port; A three-level electrostatic protection branch includes a first PMOS transistor and a first NMOS transistor, wherein the source of the first PMOS transistor is connected to the power supply voltage terminal, the drain of the first PMOS transistor is connected to the protected device, the drain of the first NMOS transistor is connected to the protected device, and the source of the first NMOS transistor is connected to the ground terminal; The secondary electrostatic protection branch is connected between the radio frequency port and the protected device.
2. The electrostatic protection circuit according to claim 1, wherein: The secondary electrostatic protection branch includes: a second NMOS transistor, wherein a drain of the second NMOS transistor is connected to the RF port, a source of the second NMOS transistor is connected to a first end of a first inductor, and a second end of the first inductor is connected to the protected device; A first capacitor is connected between the second end of the first inductor and the ground end.
3. The electrostatic protection circuit according to claim 1, wherein: The gate of the first PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the first NMOS transistor is connected to the source of the first NMOS transistor.
4. The electrostatic protection circuit according to claim 2, wherein: The body terminal and the source terminal of the second NMOS tube are short-circuited.
5. The electrostatic protection circuit according to claim 1, wherein: The gate, source and body of the first PMOS transistor are all connected to the power supply voltage terminal. The width of the P-doped region of the drain of the first PMOS transistor is 5 times the width of the P-doped region of the source.
6. The electrostatic protection circuit according to claim 1, wherein: The gate, source and body of the first NMOS transistor are all connected to the ground terminal, and the width of the N-doped region of the drain of the first NMOS transistor is 5 times the width of the N-doped region of the source.
7. The electrostatic protection circuit according to claim 5, characterized in that: The P-doped region of the drain of the first PMOS tube is covered with a metal silicide barrier layer.
8. The electrostatic protection circuit according to claim 6, wherein: The N-doped region of the drain of the first NMOS tube is covered with a metal silicide barrier layer.
9. The electrostatic protection circuit according to claim 1, wherein: The first-level electrostatic protection branch provides protection for the human body model and the machine model.
10. The electrostatic protection circuit according to claim 1, wherein: The three-level electrostatic protection branch protects the charging device model.