FIN-BASED AND BIPOLAR ELECTROSTATIC DISCHARGE DEVICES

Abstract

Structure comprehensive: a bipolar transistor comprising a collector region (24), an emitter region (28) and a base region (26); and a lateral ballast resistor comprising semiconductor material adjacent to the collector region (24), wherein the collector region (24) comprises a collector fin structure (25) of a first dopant type, the emitter region (28) comprises an emitter fin structure (29) of the first dopant type, the base region (26) comprises a base fin structure (27) of a second dopant type, and the lateral ballast resistor comprises lateral ballast fin structures (23) of the first dopant type adjacent to the collector fin structure (25).

Description

FIELD OF THE INVENTION

[0001] The present disclosure relates to semiconductor structures, and more particularly to fin-based and bipolar electrostatic discharge (ESD) devices and fabrication methods. BACKGROUND

[0002] To protect semiconductor circuits, features are typically provided to guard against electrostatic discharge (ESD), a sudden, transient flow of charge that can cause electrical short circuits or dielectric breakdowns. Indeed, ESD incidents can cause the failure of solid-state electronic components on such integrated circuit chips. For example, ESD incidents can potentially damage core circuits, resulting in gate oxide pinholes, junction damage, metal damage, and surface charge accumulation. Furthermore, ESD incidents can induce latch-up, which can cause permanent circuit damage.

[0003] To prevent such problems, ESD devices can be integrated directly into integrated circuit (IC) chips. Such ESD devices can protect the circuit elements in the IC chips during manufacturing and / or operation of the circuits in the IC chips. For example, the ESD devices can be designed to be triggered—i.e., switched from an 'off' state to an 'on' state—when exposed to an ESD event. During normal operation, the ESD devices are typically in their 'off' state.

[0004] ESD devices can include many different device types. For example, an ESD device may include a lateral bipolar transistor using planar technologies. In this technology, for example, a ballast resistor may be provided by silicide regions. To illustrate, the ballast resistor provided by the silicided regions (e.g., a silicided block) provides added resistance, which in turn adds additional voltage to increase the voltage drop across the pad. Thus, if the ESD device is composed of many parallel fingers, as is often the case, the increased voltage drop helps trigger these parallel fingers into the ON state.

[0005] In FinFET technologies, there is no horizontal ballast resistor, only vertical ballast resistor. When the ballast resistor is designed in ESD devices where a large number of parallel ESD fingers are used, often referred to as a multi-finger trigger arrangement, to handle a large transient current flow, not all of the ESD protection devices turn ON after a small number of the ESD devices initially turn ON. In these cases, inadequate protection is provided due to insufficient ballast resistor in each parallel finger. This occurs when the amount of ballast resistor in the ESD device is insufficient to allow proper triggering to turn all of the multi-finger devices ON after one or some of the devices have been triggered.

[0006] DE 10 2006 022 105 A1 teaches gate-controlled ESD protection elements that can be implemented using FD-SOI technology or MuGFET technology.

[0007] Furthermore, DE 10 2005 039 365 A1 teaches gate-controlled resistance elements that are integrated in a FinFET.

[0008] Furthermore, WO 2001 / 097 358 A1 teaches multi-finger ESD protection devices which have ballast resistance elements made of polysilicon strips or of vias and wiring layers connected in series.

[0009] Furthermore, from US 2014 / 0 354 347 A1 a lateral bipolar transistor on an SOI substrate is known, comprising an emitter region, a collector region and a base region with a control gate and a buffer region adjacent to the collector region, which has the same doping type as the collector region, but with lower doping. BRIEF SUMMARY

[0010] In one aspect of the disclosure, a structure comprises: a bipolar transistor comprising a collector region, an emitter region, and a base region; and a lateral ballast resistor comprising semiconductor material adjacent to the collector region, wherein the collector region comprises a collector fin structure of a first dopant type, the emitter region comprises an emitter fin structure of the first dopant type, the base region comprises a base fin structure of a second dopant type, and the lateral ballast resistor comprises lateral ballast fin structures of the first dopant type adjacent to the collector fin structure.

[0011] In one aspect of the disclosure, a structure comprises: a bipolar transistor comprising a collector region, an emitter region, and a base region; and a lateral ballast resistor comprising semiconductor material adjacent to the collector region, wherein the collector region, the emitter region, and the base region comprise a bulk semiconductor substrate, and the semiconductor material of the lateral ballast resistor comprises a semiconductor-on-insulator, SOI, adjacent to the collector region.

[0012] In one aspect of the disclosure, a structure comprises: a fin-based bipolar electrostatic discharge ESD device comprising: a collector fin structure over a first well of a first dopant type, and ballast resistor fin structures over a second well of a second dopant type contacting the collector fin structure, wherein the collector fin structure and the ballast resistor fin structures are of the second dopant type.

[0013] In one aspect of the disclosure, a method comprises: forming a bipolar transistor comprising a collector region, an emitter region, and a base region; and forming a lateral ballast resistor comprising semiconductor material adjacent to the collector region, wherein the collector region comprises a collector fin structure of a first dopant type, the emitter region comprises an emitter fin structure of the first dopant type, the base region comprises a base fin structure of a second dopant type, and the lateral ballast resistor comprises lateral ballast fin structures of the first dopant type adjacent to the collector fin structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present disclosure is described in the following detailed description with reference to the aforementioned plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. Fig. 1A-1E illustrate a fin-based bipolar electrostatic discharge (ESD) device and respective fabrication processes in accordance with aspects of the present disclosure. Fig. 2A-2D illustrate a fully depleted (or partially depleted) silicon-on-insulator bipolar electrostatic discharge (ESD) device with bulk CMOS regions (hybrid SOI) and respective fabrication processes in accordance with aspects of the present disclosure. Fig. 3 shows a graph comparing ESD devices of the present disclosure with an ESD FinFET device that does not have a lateral ballast resistor. DETAILED DESCRIPTION

[0015] The present disclosure relates to semiconductor structures, and more particularly, to fin-based and bipolar electrostatic discharge (ESD) devices and fabrication methods. More particularly, the present disclosure relates to fin-based bipolar ESD devices and fully depleted silicon-on-insulator (FDSOI) or partially depleted silicon-on-insulator (PDSOI) bipolar devices with lateral ballast resistors. Advantageously, the present disclosure provides ESD performance improvement in FinFET, FDSOI, and PDSOI technologies.

[0016] In embodiments, the ESD device may be a fin-based bipolar transistor with lateral ballast resistance. The lateral ballast resistance may be formed in the fin-based bipolar structures for ESD performance improvement in FinFET technologies. For example, in one implementation described in the present disclosure, a bipolar structure comprises N+ fins in an emitter region, a collector region, and a ballast resistance region, and P+ fins in a base region. The collector, emitter, and base regions may be formed in a P-well region; whereas the ballast resistance region may be formed in an N-well region, with multiple ballast resistance fins providing both vertical ballast resistance through the fins themselves and lateral ballast resistance.In particular, in order to increase the lateral ballast resistance, an epitaxial semiconductor layer may be provided to connect surfaces of the plurality of ballast resistance fins and one or more adjacent collector fins to unite the ballast resistance fins and the collector fins.

[0017] In embodiments, an NPN transistor may be formed in FinFET technology using combined dummy ballast fins to create a ballast resistor to enable multi-finger triggering. A lateral ballasted NPN transistor may be fabricated in FinFET technology, where ballasting may be provided by epitaxially combined ballast fins. Such a lateral bipolar device includes a plurality of adjacent fins, where an innermost fin includes a collector fin located in a P-well, and adjacent fins include ballast fins located in an N-well. In this structure, an epitaxial region over the ballast fins may be silicided and contacted to serve as the collector contact due to the epitaxial region extending via connecting fins between the collector fin and an outermost ballast fin.Furthermore, in this structure, the ballast resistance can be tailored by the number of ballast fins, with the silicide and contact regions located at the epitaxially joined ballast fin regions. In further aspects, lateral ballast resistance can be provided by a fully depleted (FD) or partially depleted (PD) SOI structure.

[0018] In the FDSOI structure or PDSOI structure, for example, a lateral ballast resistor layer can be provided as a thin semiconductor layer over a buried oxide layer fabricated using FDSOI technology, adjacent to, and in contact with, one or both of the collector and emitter of a lateral bipolar transistor device formed in a bulk region of a substrate. In this way, a hybrid ESD device can be formed. For example, a lateral NPN bipolar transistor can be fabricated using FDSOI or PDSOI technologies, where the ballast resistor can be formed, for example, by the thin semiconductor layer in an SOI region, and the NPN transistor can be in an adjacent bulk / hybrid region, where an additional ballast resistor enables the device to operate with finger-to-finger scaling.

[0019] In further examples, a lateral ballasted NPN can be fabricated in fully depleted SOI (FDSOI) or partially depleted SOI (PDSOI) technologies with the ballast resistor at the SOI region and the core portion of the NPN in an adjacent bulk region. Such a lateral bipolar device includes an emitter and a collector formed in a bulk region on a wafer, forming a core NPN transistor where the emitter and collector ballast resistors are provided at FDSOI / PDSOI regions adjacent to the NPN. In such arrangements, bulk NPN and FDSOI / PDSOI ballast regions can be combined / integrated to form a ballasted NPN, where ballasting can be integrated with bulk NPN transistor regions to provide ballasting within the collector and emitter silicon regions.

[0020] The ESD devices of the present disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools are used to form structures with dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, used to fabricate the ESD device of the present disclosure were adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films patterned on top of a wafer using photolithographic processes.In particular, the fabrication of the ESD device uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask to the top of the films by photolithographic imaging, and (iii) etching the films selectively with respect to the mask.

[0021] Fig. 1A shows an initial structure and respective manufacturing processes according to aspects of the present disclosure. In particular, the structure 10 of Fig. 1A, a substrate 12 composed of any suitable semiconductor material, including, but not limited to, Si, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The substrate 12 may comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). The substrate 12 may be a single semiconductor material, such as bulk silicon, or may be composed of semiconductor-on-insulator (SOI) technologies.

[0022] Still referring to Fig. 1A, the substrate 12 includes wells 14, 16. In a lateral NPN bipolar application, well 14 comprises a P-well and well 16 comprises an N-well. In a lateral PNP bipolar application, well 14 may be an N-well and well 16 may be a P-well. The wells 14, 16 may be formed by introducing a different dopant type into the substrate 12, for example, through ion implantation processes. For example, the P-well 14 may be doped with p-type dopants, e.g., boron (B), and the N-well 16 may be doped with n-type dopants, e.g., arsenic (As), phosphorus (P), and antimony (Sb), among other suitable examples.

[0023] In the ion implantation processes, respective patterned implantation masks may be used to define selected areas exposed for the implantations. The implantation mask used to select the exposed area for well 14 is stripped after the implantation, and before the implantation mask for well 16 (or vice versa). Similarly, the implantation mask used to select the selected area for well 16 is stripped after the implantation has been performed. The implantation masks may comprise a layer of a light-sensitive material, such as an organic photoresist, applied by a spin-coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer.Each of the implantation masks has a thickness and stopping power sufficient to block masked areas from receiving a dose of the implanted ions. For example purposes only, N-well 14 and P-well 16 may be on a 10th -17 -level.

[0024] Fig. 1B shows a plurality of fin structures 20 formed by the substrate 12. The plurality of fin structures 20 may be formed before or after the formation of the wells 14, 16. In embodiments, the plurality of fin structures 20 may be formed by conventional lithography and etching processes including a sidewall image technique (SIT). In one example of a SIT technique, a mandrel material, e.g., SiO2, is deposited on the substrate 12 using conventional chemical vapor deposition (CVD) processes. A resist is formed on the mandrel material and exposed to light to form a structure (openings). An etching process, e.g., reactive ion etching (RIE), is performed through the openings to form the mandrels.Spacers are formed on the sidewalls of the mandrels, which are preferably made of a material different from that of the mandrels and can be formed using conventional deposition processes known to those skilled in the art. The mandrels are removed or stripped using a conventional etching process selective with respect to the spacers. Etching can then be performed within the spacing of the spacers to form the sub-lithographic features, e.g., fin structures 20. The sidewall spacers can then be stripped. In embodiments, the height of the fin structures can be between 20-50 nm, although these values ​​are for example purposes only and are not intended to limit the disclosure.

[0025] In embodiments, the fin structures 20 may be used in different regions of the structure forming an ESD device. For example, as shown in Fig. 1B, the different regions include a ballast resistor region 22 having ballast resistor fins 23 (e.g., dummy fins) above the N-well 16, an emitter region 26 having one or more emitter fins 27, a base region 28 having one or more base fins 29 above the P-well 14, and a collector region 24 having one or more collector fins 25 above the P-well 14. Furthermore, in the NPN application, the ballast resistor fin structures 23 in the ballast resistor region 22, the collector fin 25, and the emitter fin 27 may be n-doped fin structures; whereas the base fin 29 may be a p-doped fin structure.In any scenario, the fin structures 20 may be doped by subjecting them to a shallow ion implantation process, preferably after the fin formation process and preferably after the deep ion implantation processes for forming the wells 14, 16, using different masking steps as described above. In embodiments, the fin structures 20 may be doped at a level of approximately 10. -20 be endowed.

[0026] With reference to Fig. 1C, a plurality of shallow trench isolation structures 18a, 18b may be formed in the substrate 12, separating the fins 23, 25, 27, 29. In embodiments, the shallow trench isolation structures 18a extend in the well 14 between (i) the collector region 24 and the emitter region 26 to provide the base width Wb between the collector fin 25 and the emitter fin 27, and (ii) the emitter fin 27 and the base fin 29 to provide a width Wb, as described in more detail with respect to Fig. 1D; whereas the shallow trench isolation structures 18b in the well 16 extend in the ballast resistor region 22 between the ballast resistor fins 23 themselves and between the ballast resistor fins 23 and the collector fin 25.

[0027] The shallow trench isolation structures 18a, 18b, which are Fig. 1C may be formed by conventional etching and deposition techniques known to those skilled in the art. For example, an etching process with a selective chemistry, e.g., RIE, is used to form one or more trenches in the substrate 12. Following the etching process, insulator material may be deposited by any conventional deposition process, e.g., CVD processes, to form the shallow trench isolation structures 18a, 18b, and 18c.

[0028] With reference to Fig. 1D, in embodiments, the fins 23, 25 can be shorted together with an epitaxial semiconductor layer 30 to increase the lateral ballast resistance of the collector fin 25. As described in more detail herein, the growth of the epitaxial semiconductor layer 30 merges over the fins 23, 25, resulting in a short-circuiting of the fins 23, 25 due to the minimal spacing between the fins 23, 25. In this way, a lateral ballast resistance is achieved by the epitaxial semiconductor layer 30, which is formed in direct contact with and merges the ballast resistance fins 23 and the collector fin 25. In contrast, due to the increased distance Wb, the epitaxial semiconductor layer 30 does not merge between the fins 25, 27 and 29. In embodiments, an upper portion of the fins 23, 25 may be recessed before the growth of the epitaxial semiconductor layer 30 takes place.

[0029] In particular, the epitaxial layer 30 may be formed by an epitaxial growth process using the upper surfaces of the ballast resistor fins 23 and the collector fin 25, and continues until the individual epitaxial regions at each of the fins 23, 25 merge and are thus short-circuited by the combined epitaxial semiconductor layer 30. The epitaxial semiconductor layer 30 may be any semiconductor material and may be doped with the same dopant type as the ballast resistor fins 23 and the collector fin 25. For example, the epitaxial semiconductor layer 30 may be silicon germanium or phosphorus-doped silicon at a surface of each fin 23, 25, 27, 29. According to alternative embodiments, the epitaxial layer 30 may be III-V compound semiconductor materials such as GaAs, InP, GaN, InGaAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof.

[0030] In embodiments, the width Wb can be adjusted to ensure that the epitaxial material 30 does not merge the fins 25, 27 or the fins 27, 29. For example, in embodiments, the base width Wb can be greater than the distance between the collector fin 25 and the nearest adjacent ballast resistor fin 23. The base width Wb can also be greater than the distance between the ballast resistor fins 23 themselves. This ensures that the epitaxial growth occurring on the top surfaces of the collector fin 25 does not extend to and merge with the adjacent emitter fin 27 or base fin 29, which would short-circuit the collector and emitter regions 24, 26 or short-circuit the emitter region 26 and the base region 28.

[0031] For example, if the fin pitch between the individual ballast fins 23 and between the collector fin 25 and the next adjacent ballast fin 23 is 14 nm (e.g., in a 14 nm technology), then Wb can be set in a range between 15 nm and 100 nm. In preferred embodiments, Wb can be at least three (3) to four (4) times larger than the pitch between the ballast fins 23 and the collector fin 25 and the next adjacent ballast fin 23 to ensure that the epitaxial layer 30 does not short-circuit the collector fin 25 and emitter fin 27. Also, the height of the epitaxial layer 30 can be determined by the time required for the epitaxial growth process to combine the individual epitaxial regions at each of the ballast resistor fins 23 and the collector fin 25 to form the ballast resistor of the epitaxial layer 30.Typically, in a 14 nm technology, the height of the epitaxial layer 30 may be approximately 25 nm, although this is not intended to be limiting to the disclosure. In other technologies, such as a 7 nm technology, the fin pitch, the base width Wb, and the height of the epitaxial ballast resistor layer 30 could be scaled accordingly.

[0032] Still referring to Fig. 1D, the P-well 14 in the collector region 24 and the N-well 16 in the ballast resistor region 22 may be in contact with each other. Alternatively, in the PNP application, in which the well 16 may be a P-well and the well 14 may be an N-well, the ballast resistor fins 23, the collector fin 25, and the emitter fin 27 may be p-doped fin structures; whereas the base fin 29 in the base region 28 may be an n-doped fin structure. As further shown in Fig. 1D, the ballast resistance fins 23, a base fin 29, a collector fin 25, and an emitter fin 27 are provided; however, it should be understood that a different number of fin structures may be used in each region.

[0033] As should be apparent to those skilled in the art, the ballast resistor fins 23 in the ballast resistor region 22, in combination with the well 16 of a different implant dopant type, e.g., an N-well, can form a lateral ballast resistor at the ballast resistor region 22, e.g., a lateral N-well resistor and vertical dummy fin resistors in the ballast resistor fins 23. The lateral ballast resistor provides stability to the circuit by preventing overcurrent faults. The lateral ballast resistor can also be formed without a silicided block region. In this arrangement, the N-well 16 prevents the ballast resistor fins 23 from acting as collector fins by preventing unwanted avalanche breakdown with the ballast resistor fins 23, thereby rendering the ballast resistor fins 23 dummy fins.

[0034] With reference to Fig. 1E, contacts 32a, 32b, and 32c are provided, respectively, on the epitaxial semiconductor layer 30, the emitter fin 27, and the base fin 29. Since the epitaxial semiconductor layer 30 connects the upper surfaces of the ballast resistor fins 23 and the collector fin 25, the metal contact 32a also serves as a contact for the collector region 24.

[0035] The contacts 32a, 32b, and 32c may be formed using a silicide process. As will be apparent to those skilled in the art, the silicide process begins with a deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over fully formed and patterned semiconductor devices (e.g., a doped or ion-implanted epitaxial ballast resistor layer 30, the emitter fin 27, and the base fin 29 in the Fig. 1E). After deposition of the material, the structure is heated, allowing the transition metal to react with exposed silicon (or another semiconductor material as described herein) in the epitaxial semiconductor layer 30, the emitter fin 27, and the base fin 29, forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, forming silicide contacts 32a, 32b, and 32c in the epitaxial ballast resistor layer 30, the emitter fin 27, and the base fin 29 in the Fig. 1E. Although not shown, metal contacts to the silicided regions may be formed using conventional CMOS processes known to those of ordinary skill in the art, so no further explanation is required herein for a complete understanding of the present disclosure.

[0036] Fig. Figure 2A shows an initial structure of an ESD device and respective manufacturing processes using semiconductor-on-insulator (SOI) substrate technologies. In particular, the ESD device 40 of Fig. 2A, a substrate 42 composed of a silicon layer 44 or any other suitable semiconductor material including, but not limited to, SiGe, SiGeC, SiC, GE alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The substrate 42 may comprise any suitable crystallographic orientation (e.g., a (100), (110), (111), or (001) crystallographic orientation). An insulator layer 45 is provided over the semiconductor layer 44, and a semiconductor layer 47 is provided on the insulator layer 45. The semiconductor layer 47 may be partially or fully depleted SOI technologies. The insulator layer 45 comprises any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. An exemplary insulator layer 45 may be a buried oxide (BOX) layer.The insulator 45 may be formed by any suitable process, such as separation by implantation of oxygen (SIMOX), oxidation, deposition, and / or another suitable process.

[0037] In a lateral NPN bipolar application, the semiconductor layer 44 may comprise a P-well. In a lateral PNP bipolar application, the semiconductor layer 44 may comprise an N-well. The semiconductor layer 44 may be formed by introducing a different dopant type into the semiconductor layer 44, for example, through ion implantation processes as previously described herein.

[0038] With reference to Fig. 2B, the insulator layer 45 and the semiconductor layer 47 in an emitter region 51 and a base region 53 may be removed. The insulator layer 45 and the semiconductor layer 47 may be removed by conventional lithography and etching processes, e.g., RIE, as known in the art, so no further explanation is required for a complete understanding of the present disclosure. In embodiments, the etching process exposes the underlying semiconductor layer 44 such that an epitaxial semiconductor material 43 may be grown in the emitter region 51 and the base region 53 using a conventional epitaxial growth process.In embodiments, the epitaxial semiconductor material 43 may be representative of a bulk region of a substrate composed of any suitable material, including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. Also, the epitaxial semiconductor material 43 may be planarized using, for example, a chemical mechanical planarization (CMP) process, as is known in the art, to form a planar surface.

[0039] As in Fig. 2C, a plurality of shallow trench isolation structures 52 are formed in the emitter region 51 and the base region 53, extending into the epitaxial semiconductor material 43. In embodiments, the shallow trench isolation structures 52 are formed using conventional lithography, etching, and deposition processes, as previously described herein. Thereafter, a collector 46, an emitter 48, and a base 50 are formed in the epitaxial semiconductor material 43 to form a lateral bipolar transistor adjacent to an FDSOI technology composed of a collector-side ballast resistor 47a and an emitter-side ballast resistor 47b formed from the semiconductor layer 47.In this way, a hybrid device is formed with a lateral bipolar transistor structure in the semiconductor layer 44 and a ballast resistor structure formed with an FDSOI technology adjacent to the lateral bipolar transistor structure.

[0040] In embodiments, the collector 46, the emitter 48, and the base 50 may be formed by conventional diffusion or ion implantation processes, as previously described herein. Alternatively, the regions 46, 48, and 50 could be formed by a doped epitaxial deposition for the epitaxial semiconductor material 43. In a lateral NPN bipolar application, the emitter 46 and the collector 48 may be N+ regions, and the base 50 may be a P+ region. In a lateral PNP bipolar application, the emitter 46 and the collector 48 may be P+ regions, and the base 50 may be an N+ region.

[0041] As in Fig. As shown in Figure 2C, the collector-side ballast resistor 47a may be in contact with a side surface of the collector 46, and the emitter-side ballast resistor 47b may be in contact with a side surface of the emitter 48. Also, in lateral NPN bipolar transistor embodiments, both the collector-side ballast resistor 47a and the emitter-side ballast resistor 47b may be N+ doped diffusion regions that may be defined by epitaxial growth. In lateral PNP bipolar transistor embodiments, both the collector-side ballast resistor 47a and the emitter-side ballast resistor 47b may be P+ doped diffusion regions that may be defined by epitaxial growth.

[0042] Due to the use of a thin semiconductor layer 47 in FDSOI / PDSOI technology, e.g., between 3 nm and 15 nm, the collector ballast resistor 47a and the emitter ballast resistor 47b can be of high resistance, e.g., 350 ohms, without the need to dope the semiconductor layer 47. Also, in embodiments, the semiconductor layer 47 could be doped to provide control of the ballast resistance amount based on the doping amount.

[0043] With reference to Fig. 2D, the ESD device 40 also includes contacts 58a, 58b, and 58c formed respectively on the collector-side ballast resistor 47a, the emitter-side ballast resistor 47b, and the base region 50. These contacts 58a, 58b, and 58c are formed in a manner similar to that described above for Fig. 1E with respect to contacts 32a, 32b and 32c, so that no further explanation is required herein.

[0044] Due to the use of lateral ballast resistance arrangements, which are designed with respect to Fig. 1E and Fig. 2D, it is possible to increase the ballast resistance significantly compared to known ESD devices. For example, in a lateral NPN bipolar ESD device using FinFet technology, where the ballast resistance is only the vertical resistance in the fins themselves, under conditions of a threshold voltage of 8.75 volts and a holding voltage of 5.0 volts, a typical ballast resistance is 100 ohms. This is often insufficient to allow triggering of all devices in a multi-finger ESD device array, for example, using several hundred individual ESD devices. In comparison, in simulations using the Fig. 1E, with similar threshold and holding voltages, the ballast resistance for each ESD device was 350 ohms. Similarly, in the arrangement shown in Fig. 2D with a lateral collector-side ballast resistor 47a and a lateral emitter-side ballast resistor 47b, and with similar threshold and holding voltages, the ballast resistance for each ESD device is 300 ohms.

[0045] In any case, this increase in ballast resistance is achieved using the added lateral ballast resistance provided in the arrangements of Fig. 1E and Fig. 2D is sufficient to ensure that all ESD devices in a multi-finger ESD arrangement are triggered, as described below with respect to Fig. 3. It should be understood that these resistance values ​​are exemplary and that such resistance values ​​can be increased or decreased based on different variables, e.g., material types and doping profiles.

[0046] Fig. Figure 3 shows a graph comparing ESD devices of the present disclosure with an ESD FinFET device that does not have a lateral ballast resistor, as described with respect to Fig. 1E and Fig. 2D. In the graph of Fig. 3, the ESD devices described in the present disclosure are shown as line "B," and the ESD FinFET device, which does not have a lateral ballast resistor, is shown as line "A." The x-axis is representative of voltage, and the y-axis is representative of current. As shown in the comparison graph, line "A" and line "B" behave similarly in that line "A" has a similar trigger voltage to line "B" at point "1" before snapping back at point "2" and then failing at point "3." At point "3," the x-axis voltage for line "B" would be higher than the x-axis voltage for line "A." In other words, the voltage for line "B" rises above point "1" immediately after point "2," and then point "3 would be at a much higher voltage than is the case for line "A." This results in multi-finger triggering with a device that has multiple fingers in parallel to form a wide device (ie10 fingers, 20µm each finger, total width 200µm).

[0047] In particular, point 1 is representative of Vt1, at which the transistor turns ON, point 2 is representative of Vh, which is when the voltage of the transistor (NPN) snaps back to a lower voltage, and point 3 is representative of Vt2, which is a failure of the circuit. By increasing the resistance with the lateral ballast resistor using the Fig. Using the techniques discussed in Figures 1A-2D, it is possible to increase Vt2, which in turn allows subsequent fingers (e.g., ESD devices) in a multi-finger application to turn ON. This effectively allows all fingers (NPN) in the multi-finger device to turn ON, thus increasing ESD performance.

[0048] By way of another example, it will be clear that Vt may be slightly different for different devices due to process variations. Also, assume that an NPN triggers at 6 V to 7 V and the snapback is approximately 2 V. In this example, without the additional ballast resistor provided by the arrangements of the present disclosure, once the snapback occurs on the first transistor (NPN) and the voltage drops to approximately 5 V, subsequent transistors in a multi-finger device are prevented from triggering (e.g., turning ON). However, by adding the lateral ballast resistor using the methods described above for Fig. 1E and Fig. 2D, the trigger voltage for switching ON can be increased, allowing subsequent devices in the multi-finger device to switch ON even with the snap-back phenomenon. Thus, the lateral ballast resistance used in the fin-based bipolar structures of Fig. 1E and the FDSOI structure of Fig. 2D, the ESD performance in FinFET technologies. In summary, with respect to Fig. 3, Ron rises after an initial triggering of one or more transistors in a multi-finger device to enable multi-finger triggering of all transistors of the multi-finger device.

[0049] From TCAD simulations, it has been determined that the devices described above using FDSOI technology can increase Ron by up to approximately 3x. Similarly, in the fin-ballasted NPN device, Ron increased by up to approximately 3.5x. The net result is that both the FDSOI and fin-ballasted devices described above exhibit increased Ron in the 3-3.5x range, enabling these two devices to handle current finger-to-finger (good width scaling), whereas regular lateral NPN structures do not scale finger-to-finger. For example, in a device with 10 fingers, the ballasted devices using the devices described above can handle approximately 10x more current than regular lateral NPN devices, transforming from non-functional to functional for ESD protection.

[0050] The ESD devices can be used in system-on-chip (SoC) technology. It should be clear to those skilled in the art that an SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume much less power and occupy much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in the mobile computing (such as smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0051] The process(es) described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip assembly (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip assembly (such as a ceramic carrier containing one or both surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that include a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure comprising: a bipolar transistor comprising a collector region (24), an emitter region (28) and a base region (26); and a lateral ballast resistor comprising semiconductor material adjacent to the collector region (24), wherein the collector region (24) comprises a collector fin structure (25) of a first dopant type, the emitter region (28) comprises an emitter fin structure (29) of the first dopant type, the base region (26) comprises a base fin structure (27) of a second dopant type, and the lateral ballast resistor comprises lateral ballast fin structures (23) of the first dopant type adjacent to the collector fin structure (25). [2] The structure of claim 1, wherein the lateral ballast resistor comprises an epitaxial semiconductor material (30) connecting a surface of the collector fin structure (25) and surfaces of the ballast resistor fin structures (23). [3] The structure of claim 1 or 2, wherein the collector region (24), the emitter region (28) and the base region (26) are in a first well (14) of the second dopant type, the ballast resistor fin structures (23) are in a second well (16) of the first dopant type, and the second well (16) is adjacent to and contacts the first well (14) of the second dopant type in the collector region (24). [4] The structure of claim 3, wherein the second well (16) of the first dopant type comprises an N-well and the first well (14) of the second dopant type comprises a P-well. [5] The structure of any one of claims 1 to 4, further comprising shallow trench isolation regions (18a) separating the emitter region (28) from the collector region (24) and the emitter region (28) from the base region (26). [6] The structure of claim 5, wherein a width of one of the shallow trench isolation regions (18a) separating the emitter region (28) from the collector region (24) is greater than a distance between a collector fin structure (25) and an adjacent ballast resistor fin (23). [7] Structure comprising: a bipolar transistor comprising a collector region (46), an emitter region (48) and a base region (50); and a lateral ballast resistor (47a) comprising semiconductor material adjacent to the collector region (46), wherein the collector region (46), the emitter region (48) and the base region (50) comprise a bulk semiconductor substrate, and the semiconductor material of the lateral ballast resistor (47a) comprises a semiconductor-on-insulator, SOI, adjacent to the collector region (46). [8] The structure of claim 7, wherein the semiconductor material of the SOI comprises one of: a partially depleted SOI and a fully depleted SOI, and wherein the semiconductor material contacts a side surface of the collector region (46). [9] Structure comprising: a fin-based bipolar electrostatic discharge device, or ESD device for short, comprising: a collector fin structure (25) over a first well (14) of a first dopant type, and Ballast resistance fin structures (23) above a second well (16) of a second dopant type, which contact the collector fin structure (25), wherein the collector fin structure (25) and the ballast resistor fin structures (23) comprise the second dopant type. [10] The structure of claim 9, further comprising epitaxial semiconductor material (30) connecting the collector fin structure (25) to the ballast resistor fin structures (23). [11] The structure of claim 10, wherein the first well (14) and the second well (16) comprise an n-type dopant, and the epitaxial semiconductor material (30) comprises a lateral ballast resistor region. [12] The structure of claim 10 or 11, further comprising shallow trench isolation structures (18a) separating a base region (26) from an emitter region (28) of the fin-based bipolar ESD device and separating a collector region (24) from the emitter region (28) of the fin-based bipolar ESD device. [13] The structure of any one of claims 9 to 12, wherein the first dopant type comprises a P-type dopant type and the second dopant type comprises an N-type dopant type. [14] The structure of any one of claims 9 to 13, wherein the fin-based bipolar ESD device comprises a lateral bipolar device comprising the collector fin structure (24), a base fin structure (26) and an emitter fin structure (29). [15] Structure according to one of claims 9 to 14, wherein the ballast resistance fin structures (23) contact the second well (16) and are separated from each other by at least one shallow trench isolation (18b) in contact with the second well (16). [16] The structure of claim 15, further comprising an epitaxial semiconductor layer (30) extending over each of the ballast fin structures (23), the collector fin structure (24), the first shallow trench isolation region (18a), and a second shallow trench isolation region (18b), the collector fin structure (25) contacting the first well (14) and being separated from an adjacent one of the ballast fin structures (23) by the second shallow trench isolation region (16). [17] Procedure comprising: Forming a bipolar transistor comprising a collector region (24), an emitter region (28) and a base region (26); and Forming a lateral ballast resistor (23) comprising semiconductor material adjacent to the collector region (24), wherein the collector region (24) comprises a collector fin structure (25) of a first dopant type, the emitter region (28) comprises an emitter fin structure (29) of the first dopant type, the base region (26) comprises a base fin structure (27) of a second dopant type, and the lateral ballast resistor comprises lateral ballast fin structures (23) of the first dopant type adjacent to the collector fin structure (25). [18] The method of claim 17, wherein the lateral ballast resistor comprises semiconductor material (30) contacting the collector region (24). [19] The method of claim 17 or 18, wherein the collector region (24) comprises a collector fin (25) formed from a substrate material, and the lateral ballast resistor comprises dummy fins (23) joined to the collector fin (25) by an epitaxial semiconductor growth process.

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