Double-pulse and short-circuit testing device and testing equipment for NPC T-type three-level circuit

Abstract

The utility model belongs to the field of inverter circuits, and comprises a double-pulse and short-circuit test device of an NPC T type three-level circuit, which is used for carrying out half-bus voltage double-pulse and short-circuit test on a first IGBT tube Q1 or a second IGBT tube Q2 in a test circuit of the NPC T type three-level circuit. Comprising a third selection device S3 which is arranged in parallel between two ends of a third IGBT tube Q3 and a fourth IGBT tube Q4 which are connected in sequence in a test circuit of the NPC T type three-level circuit; and the half-bus voltage double-pulse test module is used for selectively performing half-bus voltage double-pulse test and short-circuit test on the first IGBT tube Q1 or the second IGBT tube Q2. The method is used for avoiding too long time consumption in the test process, so that the test process can be quickly switched.

Description

Technical Field

[0001] This application belongs to the field of inverter circuits, specifically relating to a dual-pulse and short-circuit test device for an NPC T-type three-level circuit. Background Technology

[0002] The NPC T-type three-level circuit is a multi-level inverter topology. For example... Figure 1 As shown, a T-type three-level circuit consists of two half-bridge inverter units and a neutral point (usually capacitively coupled), forming a "T"-shaped circuit topology. Each half-bridge contains two switching elements (such as IGBTs) and corresponding freewheeling diodes, while the neutral point capacitor is used for voltage support and level switching. The operating principle of the T-type three-level inverter circuit is based on the resonance principle and the capacitor charging and discharging principle. By controlling the switching states of the two half-bridges, the T-type three-level circuit can generate a five-level line voltage waveform at the load end. The coordination of the capacitor charging and discharging process and the switching states allows the output voltage to smoothly transition between three different levels, reducing the harmonic content caused by the stepped waveform in traditional two-level inverters. In existing technologies, double-pulse testing and short-circuit testing are performed on the IGBTs in the NPC T-type three-level circuit. These tests must be performed separately to obtain the required data, resulting in low testing efficiency. Furthermore, the inductor positions and short-circuit test locations need to be manually changed, making the testing process cumbersome, with low integration and low reliability. Utility Model Content

[0003] To address the technical problems of cumbersome testing procedures, low integration, and low reliability, this application proposes a double-pulse and short-circuit testing method and a double-pulse and short-circuit testing device for NPC T-type three-level circuits.

[0004] Firstly, a double-pulse and short-circuit test method is provided for an NPC T-type three-level circuit, used to perform a half-bus voltage double-pulse and short-circuit test on the first IGBT transistor Q1 in the test circuit of the NPC T-type three-level circuit, including the following steps:

[0005] In the test circuit of the NPC T-type three-level circuit, a third selection device S3 is set in parallel across the two ends of the third IGBT Q3 and the fourth IGBT Q4 connected in sequence. This device is used to select whether to perform a half-bus voltage double pulse test or a short-circuit test on the first IGBT Q1.

[0006] When the third selection device S3 is set to half bus voltage double pulse test, it simultaneously sends a double pulse signal to the gate of the first IGBT Q1, a low-level signal to the gate of the second IGBT Q2, a low-level signal to the gate of the third IGBT Q3, and a high-level signal to the gate of the fourth IGBT Q4.

[0007] When the third selection device S3 is set as the half bus voltage short circuit test, a low level signal is simultaneously sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

[0008] The second aspect further provides a double pulse and short circuit test method of an NPC T-type three-level circuit, which is used for performing a half bus voltage double pulse and short circuit test on a second IGBT tube Q2 in a test circuit of an NPC T-type three-level circuit, and includes the following steps:

[0009] A third selection device S3 is connected in parallel across the third IGBT tube Q3 and the fourth IGBT tube Q4 in the test circuit of the NPC T-type three-level circuit, and is used for selecting a half bus voltage double pulse test or a short circuit test on the second IGBT tube Q2.

[0010] When the third selection device S3 is set as the half bus voltage double pulse test, a low level signal is simultaneously sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0011] When the third selection device S3 is set as the half bus voltage short circuit test, a low level signal is simultaneously sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0012] The third aspect further provides a double pulse and short circuit test method of an NPC T-type three-level circuit, which is used for performing a half bus voltage double pulse and short circuit test on a third IGBT tube Q3 in a test circuit of an NPC T-type three-level circuit, and includes the following steps:

[0013] A first selection device S1 is connected in parallel across the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, and is used for selecting a half bus voltage double pulse test or a short circuit test on the third IGBT tube Q3.

[0014] When the first selection device S1 is set as the half bus voltage double pulse test, a low level signal is simultaneously sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a double pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

[0015] When the first selection device S1 is set as the half bus voltage short circuit test, low level signals are simultaneously sent to the gates of the first IGBT tube Q1 and the second IGBT tube Q2, a single pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4.

[0016] The fourth aspect further provides a double pulse and short circuit test method of the NPC T-type three-level circuit, which is used for performing the half bus voltage double pulse and short circuit test on the fourth IGBT tube Q4 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0017] The second selection device S2 is arranged in parallel across the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, and is used for selecting the half bus voltage double pulse test or the short circuit test on the second IGBT tube Q2.

[0018] When the second selection device S2 is set as the half bus voltage double pulse test, low level signals are simultaneously sent to the gates of the first IGBT tube Q1 and the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4.

[0019] When the second selection device S2 is set as the half bus voltage short circuit test, low level signals are simultaneously sent to the gates of the first IGBT tube Q1 and the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4.

[0020] The fifth aspect further provides a double pulse and short circuit test method of the NPC T-type three-level circuit, which is used for performing the full bus voltage double pulse and short circuit test on the first IGBT tube Q1 in the NPC T-type three-level circuit, and includes the following steps:

[0021] The second selection device S2 is arranged in parallel across the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, and is used for selecting the full bus voltage double pulse test or the short circuit test on the first IGBT tube Q1.

[0022] When the second selection device S2 is set as the full bus voltage double pulse test, a double pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0023] When the second selection device S2 is set to full bus voltage short circuit test, a single pulse signal is simultaneously sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0024] The sixth aspect also provides a double pulse and short circuit test method of the NPC T-type three-level circuit, which is used for full bus voltage double pulse and short circuit test of the second IGBT tube Q2 in the NPC T-type three-level circuit, and includes the following steps:

[0025] The first selection device S1 is arranged in parallel at the two ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, and is used for selecting full bus voltage double pulse test or short circuit test of the second IGBT tube Q2;

[0026] When the first selection device S1 is set to full bus voltage double pulse test, a low level signal is simultaneously sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4;

[0027] When the first selection device S1 is set to full bus voltage short circuit test, a low level signal is simultaneously sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4.

[0028] Preferably, the first selection device S1 includes a first switch SW1, a first inductor L1 and a first copper sheet U1; the first switch SW1 is used for connecting the first inductor L1 in parallel at the two ends of the first IGBT tube Q1 during full bus voltage or half bus voltage double pulse test, or is used for connecting the first copper sheet U1 in parallel at the two ends of the first IGBT tube Q1 during full bus voltage or half bus voltage short circuit test;

[0029] The second selection device S2 includes a second switch SW2, a second inductor L2 and a second copper sheet U2; the second switch SW2 is used for connecting the second inductor L2 in parallel at the two ends of the second IGBT tube Q2 during full bus voltage or half bus voltage double pulse test, or is used for connecting the second copper sheet U2 in parallel at the two ends of the second IGBT tube Q2 during full bus voltage or half bus voltage short circuit test;

[0030] The third selection device S3 includes a third converter SW3, a third inductor L3, and a third copper sheet U3; the third converter SW3 is used to connect the third inductor L3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence when performing the half bus voltage double pulse test; or used to connect the third copper sheet U3 in parallel to the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence when performing the half bus short circuit test.

[0031] The seventh aspect further provides a double pulse and short circuit test device of an NPC T-type three-level circuit, which is used for performing a half bus voltage double pulse and short circuit test on a first IGBT tube Q1 or a second IGBT tube Q2 in a test circuit of the NPC T-type three-level circuit, and includes:

[0032] The third selection device S3 is arranged in parallel between the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit; and is used for selecting to perform a half bus voltage double pulse test and a short circuit test on the first IGBT tube Q1 or the second IGBT tube Q2.

[0033] The eighth aspect further provides a double pulse and short circuit test device of an NPC T-type three-level circuit, which is used for performing a half bus voltage double pulse and short circuit test on a third IGBT tube Q3 in a test circuit of the NPC T-type three-level circuit, or used for performing a full bus voltage double pulse and short circuit test on a second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, and includes:

[0034] The first selection device S1 is arranged in parallel at the two ends of the first IGBT tube Q1; and is used for selecting to perform a half bus voltage double pulse test and a short circuit test on the third IGBT tube Q3, or used for performing a full bus voltage double pulse and a short circuit test on the second IGBT tube Q2.

[0035] The ninth aspect further provides a double pulse and short circuit test device of an NPC T-type three-level circuit, which is used for performing a half bus voltage double pulse and short circuit test on a fourth IGBT tube Q4 in a test circuit of the NPC T-type three-level circuit, or used for performing a full bus voltage double pulse and short circuit test on a first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, and includes:

[0036] The second selection device S2 is arranged in parallel at the two ends of the second IGBT tube Q2; and is used for selecting to perform a half bus voltage double pulse test and a short circuit test on the fourth IGBT tube Q4, or used for performing a full bus voltage double pulse and a short circuit test on the first IGBT tube Q1.

[0037] In summary, the present application includes at least one of the following beneficial technical effects:

[0038] 1. The first selection device S1, the second selection device S2 or the third selection device S3 are used to quickly switch between the half bus voltage double pulse test and the short circuit test of the IGBT tube, avoiding the technical problems of high test cost and low test efficiency;

[0039] 2. The first selection device S1 and the second selection device S2 are used to quickly switch between the full bus voltage double pulse test and the short circuit test of the IGBT tube, avoiding the technical problems of high test cost and low test efficiency;

[0040] 3. The scheme has high integration, improves the reliability of the test system, and has simple and clear test steps, improves the test efficiency, optimizes the test method of the NPC T-type module under full bus voltage, improves the data accuracy, and can perform more accurate comparison and analysis by obtaining the full bus voltage and half bus voltage data in the same test process, and find potential problems and improvement points. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a NPC T-type three-level circuit diagram;

[0042] Figure 2 is a diagram for half bus voltage double pulse and short circuit test of the first IGBT tube Q1 and the second IGBT tube Q2 respectively;

[0043] Figure 3 is a diagram for half bus voltage double pulse and short circuit test of the third IGBT tube Q3, or full bus voltage double pulse and short circuit test of the second IGBT tube Q2;

[0044] Figure 4 is a diagram for half bus voltage double pulse and short circuit test of the fourth IGBT tube Q4, or full bus voltage double pulse and short circuit test of the first IGBT tube Q1;

[0045] Figure 5 is a diagram of the first selection device S1, the second selection device S2 and the third selection device S3;

[0046] Figure 6 is a diagram of the third selection device S3 when the first IGBT tube Q1 and the second IGBT tube Q2 are tested by half bus voltage double pulse and short circuit test respectively;

[0047] Figure 7 is a diagram of the first selection device S1 when the third IGBT tube Q3 is tested by half bus voltage double pulse and short circuit test, or the second IGBT tube Q2 is tested by full bus voltage double pulse and short circuit test;

[0048] Figure 8 This is a diagram showing the configuration of the second selection device S2 when performing a half-bus voltage double-pulse and short-circuit test on the fourth IGBT Q4, or a full-bus voltage double-pulse and short-circuit test on the first IGBT Q1. Detailed Implementation

[0049] Terminology Explanation:

[0050] NPC T-type three-level circuit: NPC (Neutral Point Clamped) is a neutral point clamping circuit; that is, an NPC circuit arranged in a T-shape.

[0051] This application proposes a double-pulse and short-circuit test method and a double-pulse and short-circuit test device for an NPC T-type three-level circuit.

[0052] Firstly, such as Figure 2 As shown, a double-pulse and short-circuit test method for an NPC T-type three-level circuit is provided. This method is used to perform a half-bus voltage double-pulse and short-circuit test on the first IGBT Q1 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0053] In the test circuit of the NPC T-type three-level circuit, a third selection device S3 is connected in parallel across the two ends of the third IGBT Q3 and the fourth IGBT Q4, which are connected in sequence. This device is used to select whether to perform a half-bus voltage double-pulse test or a short-circuit test on the first IGBT Q1. The third selection device S3 can be implemented in various ways, such as by an active device or a switching circuit. Whether it is an active device or a switching circuit, it can be controlled by a control circuit to make the third selection device S3 be in a conducting, short-circuited, or open state, thereby achieving the state of performing a double-pulse test, a short-circuit test, or disconnection on the first IGBT Q1.

[0054] When the third selection device S3 is set to perform a half-bus voltage double-pulse test, it simultaneously sends a double-pulse signal to the gate of the first IGBT Q1, a low-level signal to the gate of the second IGBT Q2, a low-level signal to the gate of the third IGBT Q3, and a high-level signal to the gate of the fourth IGBT Q4. At this time, the voltage applied between the gate and source of the first IGBT Q1 is the half-bus voltage, i.e., as shown below. Figure 2The voltage between the DC+ and 0 in the middle. At this time, the current flows as follows: DC+ terminal - first IGBT tube Q1 - third selection device S3 - 0 terminal. Since, at this time, the gate of the fourth IGBT tube Q4 is high, it is always on, and the freewheeling circuit is completed by using the diode in parallel with the third IGBT tube Q3, therefore, at this time, the reverse recovery parameters of the diode FRD (Fast Recover Diode) in parallel with the third IGBT tube Q3 can also be tested.

[0055] When the third selection device S3 is set to the half bus voltage short circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection at the third selection device S3 should use a device with strong overcurrent capacity, and cannot use a wire type device with poor current carrying capacity. At this time, the voltage is added between the DC+ terminal and the 0 terminal.

[0056] In the second aspect, as Figure 2 shown, a double pulse and short circuit test method of the NPC T-type three-level circuit is also provided, which is used for half bus voltage double pulse and short circuit test of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0057] The third selection device S3 is arranged in parallel between the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, which is used for selecting half bus voltage double pulse test or short circuit test of the second IGBT tube Q2; the third selection device S3 can be realized in multiple ways, for example, composed of active devices, or composed of a switching circuit; whether it is an active device or a switching circuit, it can be controlled by a control circuit, so that the third selection device S3 is in a conducting, short circuit or open state, achieving the state of double pulse test, short circuit test or disconnection of the second IGBT tube Q2.

[0058] When the third selection device S3 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a double pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage between the gate and the source of the second IGBT tube Q2 is half bus voltage, that is, as Figure 2The voltage between the 0 terminal and DC- is described in the middle. At this time, the current flows as follows: 0 terminal--third selection terminal S3--second IGBT tube Q2--DC- terminal. Since the gate of the third IGBT tube Q3 is high at this time, it is always on, and the freewheeling circuit is completed by using the diode of the fourth IGBT tube Q4 in parallel, so at this time, the reverse recovery parameters of the diode FRD (Fast Recover Diode) in parallel in the fourth IGBT tube Q4 can also be tested.

[0059] When the third selection device S3 is set to the half bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a single pulse signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a low level signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection at the third selection device S3 should use a device with strong overcurrent capacity, and cannot use a wire with poor current carrying capacity. At this time, the voltage is added to: 0 terminal--DC- terminal.

[0060] In a third aspect, as Figure 3 shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used for half bus voltage double pulse and short circuit test of the third IGBT tube Q3 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0061] A first selection device S1 is arranged in parallel at the two ends of the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, which is used for selecting half bus voltage double pulse test or short circuit test of the third IGBT tube Q3; the first selection device S1 can be realized in multiple ways, for example, composed of active devices, or composed of switching circuits; whether it is an active device or a switching circuit, it can be controlled by a control circuit, so that the first selection device S1 is in the on, short circuit or off state, to achieve the state of double pulse test, short circuit test or disconnection of the third IGBT tube Q3.

[0062] When the first selection device S1 is set to the half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a double pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage between the gate and the source of the third IGBT tube Q3 is half bus voltage, that is, as Figure 3The voltage between DC+ and 0 in the middle. At this time, the current flows as follows: DC+ terminal - first selection device S1 - third IGBT tube Q3 - fourth IGBT tube Q4 - 0 terminal. At this time, the gate of the fourth IGBT tube Q4 is high, which is always on, and a pulse is applied to the third IGBT tube Q3, and the diode connected in parallel with the first IGBT tube Q1 completes the freewheeling circuit, so the reverse recovery parameters of the diode FRD (Fast Recover Diode) connected in parallel with the first IGBT tube Q1 can also be tested at this time.

[0063] When the first selection device S1 is set to half bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a single pulse signal is sent to the gate of the third IGBT tube Q3, and a high level signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection at the first selection device S1 should use a device with strong overcurrent capability, and cannot use a wire with poor current carrying capacity. At this time, the voltage is applied to: DC+ terminal - 0 terminal.

[0064] In a fourth aspect, as shown in Figure 4 A double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used for half bus voltage double pulse and short circuit test of the fourth IGBT tube Q4 in the test circuit of the NPC T-type three-level circuit, and includes the following steps:

[0065] A second selection device S2 is connected in parallel across the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, which is used for selecting half bus voltage double pulse test or short circuit test of the second IGBT tube Q2; the second selection device S2 can be realized in multiple ways, for example, by active devices or switch circuits; whether it is an active device or a switch circuit, it can be controlled by a control circuit to make the second selection device S2 in a conductive, short-circuit or open state, so as to achieve the state of double pulse test, short circuit test or disconnection of the fourth IGBT tube Q4.

[0066] When the second selection device S2 is set to half bus voltage double pulse test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a high level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4; at this time, the voltage between the gate and the source of the fourth IGBT tube Q4 is half bus voltage, i.e. Figure 4The voltage between the 0 terminal and the DC- terminal in the middle. At this time, the current flows as follows: 0 terminal ---- fourth IGBT tube Q4 ---- third IGBT tube Q3 ---- second selection device S2 ---- DC- terminal. Since the gate of the third IGBT tube Q3 is high at this time, it is always on, a pulse is applied to the fourth IGBT tube Q4, and the diode connected in parallel with the second IGBT tube Q2 completes the freewheeling circuit, so at this time the reverse recovery parameters of the diode FRD (Fast Recover Diode) connected in parallel with the second IGBT tube Q2 can also be tested.

[0067] When the second selection device S2 is set to half bus voltage short circuit test, a low level signal is sent to the gate of the first IGBT tube Q1, a low level signal is sent to the gate of the second IGBT tube Q2, a low level signal is sent to the gate of the third IGBT tube Q3, and a double pulse signal is sent to the gate of the fourth IGBT tube Q4. At this time, the connection at the second selection device S2 should use a device with strong overcurrent capacity, and cannot use a wire with poor current carrying capacity. At this time, the voltage is applied to: 0 terminal -- DC- terminal.

[0068] In a fifth aspect, as Figure 4 shown, a double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used for full bus voltage double pulse and short circuit test of the first IGBT tube Q1 in the NPC T-type three-level circuit, and includes the following steps:

[0069] A second selection device S2 is arranged in parallel at the two ends of the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, which is used for selecting full bus voltage double pulse test or short circuit test of the first IGBT tube Q1; the second selection device S2 can be realized in multiple ways, for example, composed of active devices, or composed of switching circuits; whether it is an active device or a switching circuit, it can be controlled by a control circuit to make the second selection device S2 be in a conduction or short circuit state, so as to achieve full bus voltage double pulse and short circuit test of the first IGBT tube Q1.

[0070] When the second selection device S2 is set to full bus voltage double pulse test, double pulse signals are simultaneously sent to the gate of the first IGBT tube Q1, low level signals are sent to the gate of the second IGBT tube Q2, low level signals are sent to the gate of the third IGBT tube Q3, and low level signals are sent to the gate of the fourth IGBT tube Q4; at this time, the current flows as follows: DC+ end--first IGBT tube Q1--second selection device S2--DC- end; obviously, the full bus voltage is applied between the gate and the source of the first IGBT tube Q1. In actual application, if "abnormal blocking" occurs, that is, the horizontal tube (the third IGBT tube Q3 and the fourth IGBT tube Q4) is turned off first, the vertical tube (here: the first IGBT tube Q1) will be directly commutated, and the voltage borne by the vertical tube (here: the first IGBT tube Q1) when it is turned off becomes the full bus voltage. It is also necessary to simulate this extreme working condition for double pulse test in the test.

[0071] When the second selection device S2 is set to full bus voltage short circuit test, a single pulse signal is sent to the gate of the first IGBT tube Q1, low level signals are sent to the gate of the second IGBT tube Q2, low level signals are sent to the gate of the third IGBT tube Q3, and low level signals are sent to the gate of the fourth IGBT tube Q4. Here, a conductor with strong overcurrent capacity should be used to connect the second selection device S2, and a wire with poor current-carrying capacity should not be used to connect the second selection device S2. At this time, the current flows as follows: DC+ end--first IGBT tube Q1--second selection device S2--DC- end; the test is to test the state of the first IGBT tube Q1 under full bus voltage short circuit.

[0072] In a sixth aspect, as shown in Figure 3 A double pulse and short circuit test method for an NPC T-type three-level circuit is also provided, which is used for full bus voltage double pulse and short circuit test of a second IGBT tube Q2 in the NPC T-type three-level circuit, and includes the following steps:

[0073] A first selection device S1 is arranged in parallel with the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, which is used for selecting full bus voltage double pulse test or short circuit test of the second IGBT tube Q2; the first selection device S1 can be realized in multiple ways, for example, by active devices or by switch circuits; whether it is an active device or a switch circuit, it can be controlled by a control circuit to make the first selection device S1 in a conduction or short circuit state, so as to achieve full bus voltage double pulse and short circuit test of the second IGBT tube Q2.

[0074] When the first selection device S1 is set to full bus voltage double pulse test, low level signals are simultaneously sent to the gates of the first IGBT tube Q1, double pulse signals are sent to the gates of the second IGBT tube Q2, low level signals are sent to the gates of the third IGBT tube Q3 and the fourth IGBT tube Q4; at this time, the current flows as follows: DC+ end--first selection device S1--second IGBT tube Q2--DC- end; obviously, the full bus voltage is applied between the gate and the source of the second IGBT tube Q2. In actual application, if "abnormal blocking" occurs, that is, the horizontal tube (the third IGBT tube Q3 and the fourth IGBT tube Q4) is turned off first, the vertical tube (here: the second IGBT tube Q2) will be directly commutated, and the voltage borne by the vertical tube (here: the second IGBT tube Q2) when it is turned off becomes the full bus voltage. It is also necessary to simulate this extreme working condition for double pulse test in the test.

[0075] When the first selection device S1 is set to full bus voltage short circuit test, low level signals are simultaneously sent to the gates of the first IGBT tube Q1, single pulse signals are sent to the gates of the second IGBT tube Q2, low level signals are sent to the gates of the third IGBT tube Q3 and the fourth IGBT tube Q4. Here, a conductor with strong overcurrent capacity should be used to connect the first selection device S1, and a wire with poor current-carrying capacity should not be used to connect it. At this time, the current flows as follows: DC+ end--first selection device S1--second IGBT tube Q2--DC- end; the test is to test the state of the second IGBT tube Q2 under full bus voltage short circuit.

[0076] Preferably, as shown in Figure 5 The first selection device S1 includes a first converter SW1, a first inductor L1 and a first copper sheet U1; the first converter SW1 is used to connect the first inductor L1 in parallel across the first IGBT tube Q1 when full bus voltage or half bus voltage double pulse test is performed; or used to connect the first copper sheet U1 in parallel across the first IGBT tube Q1 when full bus voltage or half bus voltage short circuit test is performed; the first selection device S1 includes the first inductor L1, the first copper sheet U1 and the first converter SW1; one end of each of the first inductor L1 and the first copper sheet U1 is connected with the emitter of the first IGBT tube Q1; the other end of each of the first inductor L1 and the first copper sheet U1 is connected with the two terminals of one end of the first converter SW1; the other end of the first converter SW1 is connected with the collector of the first IGBT tube Q1.

[0077] The second selection device S2 includes a second converter SW2, a second inductor L2 and a second copper sheet U2; the second converter SW2 is used to connect the second inductor L2 in parallel across the two ends of the second IGBT tube Q2 during full bus voltage or half bus voltage double pulse test; or used to connect the second copper sheet U2 in parallel across the two ends of the second IGBT tube Q2 during full bus voltage or half bus voltage short circuit test; the second selection device S2 includes the second inductor L2, the second copper sheet U2 and the second converter SW2; one end of each of the second inductor L2 and the second copper sheet U2 is connected with the emitter of the second IGBT tube Q2; the other end of each of the second inductor L2 and the second copper sheet U2 is connected with two terminals of one end of the second converter SW2; the other end of the second converter SW2 is connected with the collector of the second IGBT tube Q2.

[0078] The third selection device S3 includes a third converter SW3, a third inductor L3 and a third copper sheet U3; the third converter SW3 is used to connect the third inductor L3 in parallel across the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during half bus double pulse test; or used to connect the third copper sheet U3 in parallel across the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence during half bus short circuit test. The third selection device S3 includes the third inductor L3, the third copper sheet U3 and the third converter SW3; one end of each of the third inductor L3 and the third copper sheet U3 is connected with the collector of the third IGBT tube Q3; the other end of each of the third inductor L3 and the third copper sheet U3 is connected with two terminals of one end of the third converter SW3 respectively; the other end of the third converter SW3 is connected with the collector of the fourth IGBT tube Q4.

[0079] In a seventh aspect, as shown in Figure 2 、 Figure 6 Also provided is a double pulse and short circuit test device of an NPC T-type three-level circuit, used for half bus voltage double pulse and short circuit test on the first IGBT tube Q1 or the second IGBT tube Q2 in a test circuit of the NPC T-type three-level circuit, including:

[0080] The third selection device S3 is arranged in parallel between the two ends of the third IGBT tube Q3 and the fourth IGBT tube Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit; used for selecting half bus voltage double pulse test and short circuit test on the first IGBT tube Q1 or the second IGBT tube Q2.

[0081] In an eighth aspect, as shown in Figure 3 、 Figure 7The NPC T-type three-level circuit double-pulse and short-circuit test device is used for performing half bus voltage double-pulse and short-circuit test on the third IGBT tube Q3 in the test circuit of the NPC T-type three-level circuit, or is used for performing full bus voltage double-pulse and short-circuit test on the second IGBT tube Q2 in the test circuit of the NPC T-type three-level circuit, and comprises:

[0082] The first selection device S1 is arranged in parallel at two ends of the first IGBT tube Q1, and is used for selecting to perform half bus voltage double-pulse test and short-circuit test on the third IGBT tube Q3, or is used for selecting to perform full bus voltage double-pulse and short-circuit test on the second IGBT tube Q2.

[0083] In a ninth aspect, as Figure 4 、 Figure 8 The NPC T-type three-level circuit double-pulse and short-circuit test device is used for performing half bus voltage double-pulse and short-circuit test on the fourth IGBT tube Q4 in the test circuit of the NPC T-type three-level circuit, or is used for performing full bus voltage double-pulse and short-circuit test on the first IGBT tube Q1 in the test circuit of the NPC T-type three-level circuit, and comprises:

[0084] The second selection device S2 is arranged in parallel at two ends of the second IGBT tube Q2, and is used for selecting to perform half bus voltage double-pulse test and short-circuit test on the fourth IGBT tube Q4, or is used for selecting to perform full bus voltage double-pulse and short-circuit test on the first IGBT tube Q1.

[0085] The first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 or the fourth IGBT tube Q4 can be replaced by a MOSFET tube.

[0086] The MOSFET tube can be SiC or / and GaN.

[0087] The first IGBT tube Q1, the second IGBT tube Q2, the third IGBT tube Q3 or the fourth IGBT tube Q4 can be SiC or / and GaN.

[0088] A test device comprises the NPC T-type three-level circuit double-pulse and short-circuit test device in any one of the above technical solutions.

[0089] By obtaining full bus voltage and half bus voltage data in the same test process, more accurate comparison and analysis can be performed, and potential problems and improvement points can be found. The above process does not need to replace the device, saves time, and improves detection efficiency.

[0090] In summary, the present application has at least one of the following beneficial technical effects:

[0091] 1. The first selection device S1, the second selection device S2 or the third selection device S3 are used to quickly switch between the half bus voltage double pulse test and the short circuit test of the IGBT tube, avoiding the technical problems of high test cost and low test efficiency;

[0092] 2. The first selection device S1 and the second selection device S2 are used to quickly switch between the full bus voltage double pulse test and the short circuit test of the IGBT tube, avoiding the technical problems of high test cost and low test efficiency;

[0093] 3. The scheme has high integration, improves the reliability of the test system, and has simple and clear test steps, improves the test efficiency, optimizes the test method of the NPC T-type module under full bus voltage, improves the data accuracy, and can perform more accurate comparison and analysis by obtaining the full bus voltage and half bus voltage data in the same test process, and can find potential problems and improvement points.

[0094] The above are preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in the specification (including the abstract and drawings) can be replaced by other equivalent or similar features unless specifically described. That is, each feature is only an example of a series of equivalent or similar features unless specifically described.

Claims

1. A double pulse and short circuit testing device of NPC T-type three-level circuit, for conducting half bus voltage double pulse and short circuit testing on a first IGBT tube Q1 or a second IGBT tube Q2 in a testing circuit of NPC T-type three-level circuit, characterized in that, The third selection device S3 is arranged in parallel between the two ends of the third IGBT Q3 and the fourth IGBT Q4 connected in sequence in the test circuit of the NPC T-type three-level circuit, and is used for selecting to perform the half bus voltage double-pulse test and the short circuit test on the first IGBT Q1 or the second IGBT Q2. The third selection device S3 comprises a third inductor L3, a third copper sheet U3 and a third switch SW3. One end of each of the third inductor L3 and the third copper sheet U3 is connected to the collector of the third IGBT Q3. The other end of each of the third inductor L3 and the third copper sheet U3 is connected to two terminals of one end of the third switch SW3. The other end of the third switch SW3 is connected to the collector of the fourth IGBT Q4.

2. The double pulse and short circuit test device for NPC T-type three-level circuit according to claim 1, characterized in that, The first selection device S1 is arranged in parallel between the two ends of the first IGBT Q1, and is used for selecting to perform the half bus voltage double-pulse test and the short circuit test on the third IGBT Q3, or for performing the full bus voltage double-pulse test and the short circuit test on the second IGBT Q2.

3. A double pulse and short circuit testing device for NPC T-type three-level circuit, used for conducting half bus voltage double pulse and short circuit testing on the third IGBT tube Q3 in the testing circuit of the NPC T-type three-level circuit, or used for conducting full bus voltage double pulse and short circuit testing on the second IGBT tube Q2 in the testing circuit of the NPC T-type three-level circuit, characterized in that, The first selection device S1 comprises a first inductor L1, a first copper sheet U1 and a first switch SW1. One end of each of the first inductor L1 and the first copper sheet U1 is connected to the emitter of the first IGBT Q1. The other end of each of the first inductor L1 and the first copper sheet U1 is connected to two terminals of one end of the first switch SW1. The other end of the first switch SW1 is connected to the collector of the first IGBT Q1. The second selection device S2 is arranged in parallel between the two ends of the second IGBT Q2, and is used for selecting to perform the half bus voltage double-pulse test and the short circuit test on the fourth IGBT Q4, or for performing the full bus voltage double-pulse test and the short circuit test on the first IGBT Q1.

4. The double pulse and short circuit test device for NPC T-type three-level circuit according to claim 3, characterized in that, The second selection device S2 comprises a second inductor L2, a second copper sheet U2 and a second switch SW2. One end of each of the second inductor L2 and the second copper sheet U2 is connected to the emitter of the second IGBT Q2. The other end of each of the second inductor L2 and the second copper sheet U2 is connected to two terminals of one end of the second switch SW2. The other end of the second switch SW2 is connected to the collector of the second IGBT Q2.

5. A double pulse and short circuit test device for NPC T-type three-level circuit, used for half bus voltage double pulse and short circuit test of the fourth IGBT tube Q4 in the test circuit of NPC T-type three-level circuit, or used for full bus voltage double pulse and short circuit test of the first IGBT tube Q1 in the test circuit of NPC T-type three-level circuit, characterized in that, The first IGBT Q1, the second IGBT Q2, the third IGBT Q3 or the fourth IGBT Q4 can be replaced by a MOSFET tube. The MOSFET tube can be SiC or / and GaN.

6. The double pulse and short circuit test device for NPC T-type three-level circuit according to claim 5, characterized in that, The first IGBT Q1, the second IGBT Q2, the third IGBT Q3 or the fourth IGBT Q4 can each be SiC or / and GaN.

7. The double pulse and short circuit test device for NPC T-type three-level circuit according to any one of claims 1-6, characterized in that, The double-pulse and short circuit test device of the NPC T-type three-level circuit comprises the device according to any one of claims 1 to 6.

8. The double pulse and short circuit test device for NPC T-type three-level circuit according to claim 7, characterized in that, ​ 9. The double pulse and short circuit test device for NPC T-type three-level circuit according to any one of claims 1-6, characterized in that, ​ 10. A test apparatus, characterized by, ​

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