Integrator and chip
By introducing a third switching component and adjusting capacitor bank into the integrator, the loop bandwidth during the sampling stage is adjusted, thus solving the stability problem in high-speed and high-precision applications and achieving stable signal establishment.
Patent Information
- Application Number
- CN202520399824.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2035-03-07
AI Technical Summary
In high-speed, high-precision applications, excessively high loop bandwidth during the sampling phase of the integrator can affect stability and lead to unstable signal establishment.
A third switching component and a regulating capacitor bank are introduced into the integrator. The regulating capacitor bank works with the integrating capacitor bank to adjust the loop bandwidth during the sampling phase, thereby reducing the loop bandwidth during the sampling phase.
This improves the stability of the integrator in high-speed, high-precision applications and ensures effective signal establishment.
Smart Images
Figure CN223843771U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of integrated circuit technology, specifically relating to an integrator and chip. Background Technology
[0002] Switched capacitor amplifier circuits are widely used in integrator circuits, which are a crucial module in sigma-delta ADCs. Figure 1 This is a capacitor integrator built from a switched-capacitor amplifier structure. It mainly has two operating phases (states): a sampling (holding) phase and a conversion phase. The timing of each switch controlled by control signals S1 and S2 is as follows: Figure 2 As shown.
[0003] Sampling phase: When control signal S1 is high, the corresponding switch is closed; when control signal S2 is low, the corresponding switch is open; capacitor C1 samples the input voltage across its terminals; and simultaneously, operational amplifier OPA is in a unity-gain negative feedback state with a feedback coefficient of 1.
[0004] Conversion phase: When control signal S1 is low, the corresponding switch is open; when control signal S2 is high, the corresponding switch is closed. The charge corresponding to the voltage difference sampled across capacitor C1 during the sampling phase is transferred to capacitor C2 by operational amplifier OPA to achieve charge integration. At this time, operational amplifier OPA is in a negative feedback state with a feedback coefficient of C2 / (C1+C2).
[0005] From the above analysis, we know that the feedback in the sampling stage is a unity-gain negative feedback with a feedback coefficient of 1, and the feedback coefficient in the conversion stage is less than 1. Therefore, the loop bandwidth f1 in the sampling stage is higher than the loop bandwidth f2 in the conversion stage, and f1 / f2 = (C1+C2) / C2.
[0006] In capacitor-type integrator circuits that require high speed and high precision, the loop bandwidth f2 of the conversion stage needs to be very high (far higher than the sampling frequency) in order to accurately integrate the signal. Based on the above analysis, the loop bandwidth f1 of the sampling stage is even higher. However, since the output oscillation is small in the sampling stage, it does not need to be particularly high. Excessive loop bandwidth is actually detrimental to stability and may result in a low phase margin, which is not conducive to signal establishment.
[0007] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content
[0008] The purpose of this invention is to provide an integrator and chip that can avoid affecting stability in high-speed, high-precision applications due to excessive loop bandwidth during the sampling stage.
[0009] To achieve the above objectives, a specific embodiment of the present invention provides an integrator, comprising: an operational amplifier, a first switch group, a first sampling capacitor group, a second switch group, an integrating capacitor group, a third switch assembly, and an adjustment capacitor group;
[0010] The first switch group is connected to the first sampling capacitor group and the first input signal. The first switch group is used to control the first sampling capacitor group to collect charge from the first input signal during the sampling phase. The second switch group is connected to the first sampling capacitor group and the integrating capacitor group. The second switch group is used to control the integrating capacitor group to receive charge from the first sampling capacitor group during the conversion phase. The integrating capacitor group is simultaneously connected to the input and output terminals of the operational amplifier to cooperate with the operational amplifier in charge integration during the conversion phase. The adjusting capacitor group is connected to the input terminal of the operational amplifier through a third switch assembly to cooperate with the integrating capacitor group to adjust the loop bandwidth during the sampling phase.
[0011] In one or more embodiments of this utility model, the first switch group includes a first switch, a second switch, a third switch, and a fourth switch; the first sampling capacitor group includes a first sampling capacitor and a second sampling capacitor; the first terminal of the first switch and the first terminal of the second switch are used to receive a first input signal; the first terminal of the first sampling capacitor is connected to the second terminal of the first switch; the first terminal of the second sampling capacitor is connected to the second terminal of the second switch; the first terminal of the third switch is connected to the second terminal of the first sampling capacitor; the first terminal of the fourth switch is connected to the second terminal of the second sampling capacitor; and the second terminals of the third switch and the second terminals of the fourth switch are connected to a reference voltage.
[0012] In one or more embodiments of this utility model, the third switch group includes a fifth switch and a sixth switch, the regulating capacitor group includes a first regulating capacitor and a second regulating capacitor, the fifth switch and the first regulating capacitor are connected in series between the first input terminal of the operational amplifier and the reference voltage, and the sixth switch and the second regulating capacitor are connected in series between the second input terminal of the operational amplifier and the reference voltage.
[0013] In one or more embodiments of this utility model, the integrating capacitor group includes a first integrating capacitor and a second integrating capacitor. The first terminal of the first integrating capacitor is connected to the first input terminal of the operational amplifier and the second switch group. The second terminal of the first integrating capacitor is connected to the first output terminal of the operational amplifier. The first terminal of the second integrating capacitor is connected to the second input terminal of the operational amplifier and the second switch group. The second terminal of the second integrating capacitor is connected to the second output terminal of the operational amplifier.
[0014] In one or more embodiments of this utility model, the second switch group includes a seventh switch, an eighth switch, and a ninth switch, and the first sampling capacitor group includes a first sampling capacitor and a second sampling capacitor. The first terminal of the seventh switch is connected to the first terminal of the first sampling capacitor, and the second terminal of the seventh switch is connected to the first terminal of the second sampling capacitor. The first terminal of the eighth switch is connected to the second terminal of the first sampling capacitor, and the second terminal of the eighth switch is connected to the first input terminal of the operational amplifier. The first terminal of the ninth switch is connected to the second terminal of the second sampling capacitor, and the second terminal of the ninth switch is connected to the second input terminal of the operational amplifier.
[0015] In one or more embodiments of this utility model, the integrator further includes a second sampling capacitor group, a fourth switch group, and a fifth switch group. The fourth switch group is connected to the second sampling capacitor group and the second input signal. The fourth switch group is used to control the second sampling capacitor group to collect charge from the second input signal during the sampling phase. The fifth switch group is connected to the first sampling capacitor group, and the first sampling capacitor group is also connected to the second switch group. The fifth switch group is used to cooperate with the second switch group to control the integrator capacitor group to receive the charge on the first and second sampling capacitor groups during the conversion phase.
[0016] In one or more embodiments of this utility model, the second sampling capacitor group includes a third sampling capacitor and a fourth sampling capacitor, and the fourth switch group includes a tenth switch, an eleventh switch, a twelfth switch, and a thirteenth switch. The first terminals of the tenth switch and the eleventh switch are used to receive a second input signal. The second terminal of the tenth switch is connected to the first terminal of the third sampling capacitor. The second terminal of the eleventh switch is connected to the first terminal of the fourth sampling capacitor. The first terminal of the twelfth switch is connected to the second terminal of the third sampling capacitor. The first terminal of the thirteenth switch is connected to the second terminal of the fourth sampling capacitor. The second terminals of the twelfth switch and the thirteenth switch are connected to a reference voltage.
[0017] In one or more embodiments of this utility model, the second sampling capacitor group includes a third sampling capacitor and a fourth sampling capacitor, the fifth switch group includes a fourteenth switch, the first terminal of the fourteenth switch is connected to the first terminal of the third sampling capacitor, the second terminal of the fourteenth switch is connected to the first terminal of the fourth sampling capacitor, and the second terminals of the third sampling capacitor and the fourth sampling capacitor are connected to the second switch group.
[0018] In one or more embodiments of this utility model, each adjusting capacitor of the adjusting capacitor group has the same capacitance value as each sampling capacitor of the first sampling capacitor group.
[0019] This utility model also discloses a chip, including the integrator mentioned above.
[0020] Compared with the prior art, the integrator and chip of this utility model are provided with a third switching component and an adjustment capacitor group at the input of the operational amplifier. By adjusting the loop bandwidth in conjunction with the integration capacitor group during the sampling stage, the loop bandwidth of the integrator during the sampling stage is reduced in high-speed and high-precision applications, thereby improving the stability of the integrator in high-speed and high-precision applications and facilitating signal establishment. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 This is a circuit diagram of an integrator in the prior art.
[0023] Figure 2 This is a waveform diagram of the control signal for the integrator.
[0024] Figure 3 This is the circuit schematic of the integrator in Example 1.
[0025] Figure 4 This is the circuit diagram of the integrator in Example 2. Detailed Implementation
[0026] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.
[0027] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.
[0028] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.
[0029] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.
[0030] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0031] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.
[0032] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.
[0033] Example 1
[0034] like Figure 3As shown in the figure, an integrator in an embodiment of the present invention includes: an operational amplifier (OPA), a first switch group 10, a first sampling capacitor group 20, a second switch group 30, an integrating capacitor group 40, a third switch assembly 50, and an adjustment capacitor group 60.
[0035] The first switch group 10 is connected to the first sampling capacitor group 20 and the first input signals INP and INN. The first switch group 10 is used to control the first sampling capacitor group 20 to collect the charge of the first input signals INP and INN during the sampling phase.
[0036] The second switch group 30 is connected to the first sampling capacitor group 20 and the integrating capacitor group 40. The second switch group 30 is used to control the integrating capacitor group 40 to receive the charge on the first sampling capacitor group 20 during the conversion stage. The integrating capacitor group 40 is also connected to the input terminal and the output terminal of the operational amplifier OPA to cooperate with the operational amplifier OPA in charge integration during the conversion stage. The adjusting capacitor group 60 is connected to the input terminal of the operational amplifier OPA through the third switch assembly 50 to cooperate with the integrating capacitor group 40 to adjust the loop bandwidth during the sampling stage.
[0037] Specifically, such as Figure 3 As shown, the first switch group 10 includes a first switch K1, a second switch K2, a third switch K3 and a fourth switch K4, and the first sampling capacitor group 20 includes a first sampling capacitor C1 and a second sampling capacitor C2.
[0038] The first terminal of the first switch K1 and the first terminal of the second switch K2 are used to receive the first input signals INP and INN. The first terminal of the first sampling capacitor C1 is connected to the second terminal of the first switch K1. The first terminal of the second sampling capacitor C2 is connected to the second terminal of the second switch K2. The first terminal of the third switch K3 is connected to the second terminal of the first sampling capacitor C1. The first terminal of the fourth switch K4 is connected to the second terminal of the second sampling capacitor C2. The second terminals of the third switch K3 and the second terminals of the fourth switch K4 are connected to a reference voltage. In one embodiment, the reference voltage is a reference common-mode voltage.
[0039] The second switch group 30 includes a seventh switch K7, an eighth switch K8, and a ninth switch K9. The first terminal of the seventh switch K7 is connected to the first terminal of the first sampling capacitor C1, and the second terminal of the seventh switch K7 is connected to the first terminal of the second sampling capacitor C2. The first terminal of the eighth switch K8 is connected to the second terminal of the first sampling capacitor C1, and the second terminal of the eighth switch K8 is connected to the first input terminal of the operational amplifier OPA. The first terminal of the ninth switch K9 is connected to the second terminal of the second sampling capacitor C2, and the second terminal of the ninth switch K9 is connected to the second input terminal of the operational amplifier OPA. In one embodiment, the first input terminal of the operational amplifier OPA is a positive input terminal, and the second input terminal of the operational amplifier OPA is a negative input terminal. In other embodiments, the first input terminal of the operational amplifier OPA can be a negative input terminal, and the second input terminal of the operational amplifier OPA can be a positive input terminal.
[0040] The integrating capacitor group 40 includes a first integrating capacitor C3 and a second integrating capacitor C4. The first terminal of the first integrating capacitor C3 is connected to the first input terminal of the operational amplifier OPA and the second switch group K2 30. The second terminal of the first integrating capacitor C3 is connected to the first output terminal of the operational amplifier OPA. The first terminal of the second integrating capacitor C4 is connected to the second input terminal of the operational amplifier OPA and the second switch group K2 30. The second terminal of the second integrating capacitor C4 is connected to the second output terminal of the operational amplifier OPA.
[0041] The third switch group 50 includes a fifth switch K5 and a sixth switch K6, and the regulating capacitor group 60 includes a first regulating capacitor C5 and a second regulating capacitor C6.
[0042] The fifth switch K5 and the first regulating capacitor C5 are connected in series between the first input terminal of the operational amplifier OPA and the reference voltage. The sixth switch K6 and the second regulating capacitor C6 are connected in series between the second input terminal of the operational amplifier OPA and the reference voltage. In one embodiment, the reference voltage is a reference common-mode voltage.
[0043] The first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are all subject to the following: Figure 2 Controlled by the control signal S1 shown, the seventh switch K7, the eighth switch K8, and the ninth switch K9 are all affected by the signal. Figure 2 The control signal S2 shown is used for control.
[0044] Sampling Phase: Switches K1, K2, K3, K4, K5, and K6 are closed under the control of control signal S1, while switches K7, K8, and K9 are open. This allows the first sampling capacitor C1 and the second sampling capacitor C2 to sample the first input signals INP and INN. Simultaneously, the operational amplifier OPA is in a negative feedback state with a feedback coefficient of c3 / (c5+c3), where c3 is the capacitance of the first integrating capacitor C3, which is equal to the capacitance of the second integrating capacitor C4, and c5 is the capacitance of the first regulating capacitor C5, which is equal to the capacitance of the second regulating capacitor C6.
[0045] Conversion phase: Switches K1, K2, K3, K4, K5, and K6 are opened under the control of control signal S1, while switches K7, K8, and K9 are closed under the control of control signal S2. The charge corresponding to the voltage difference between the first sampling capacitor C1 and the second sampling capacitor C2 during the sampling phase is fed into the first integrating capacitor C3 and the second integrating capacitor C4 by the operational amplifier OPA to achieve charge integration. At this time, the operational amplifier OPA is in a negative feedback state with a feedback coefficient of c3 / (c1+c3), where c1 is the capacitance of the first sampling capacitor C1, and the capacitance of the first sampling capacitor C1 is equal to that of the second sampling capacitor C2.
[0046] As can be seen from the above, by adding the first regulating capacitor C5 and the second regulating capacitor C6, the loop bandwidth of the sampling stage can be adjusted, so as to avoid the integrator of the capacitor type from being affected by the excessively high loop bandwidth of the sampling stage in high-speed and high-precision applications, which would affect the stability and thus affect the establishment.
[0047] Furthermore, the capacitance value of each regulating capacitor in the regulating capacitor group 60 is equal to the capacitance value of each sampling capacitor in the first sampling capacitor group 20. That is, the capacitance values of the first regulating capacitor C5, the second regulating capacitor C6, the first sampling capacitor C1, and the second sampling capacitor C2 are all equal. At this time, the feedback coefficient of the operational amplifier OPA is equal during the sampling and conversion stages, which is more conducive to improving stability.
[0048] Example 2
[0049] like Figure 4As shown, based on Embodiment 1, the integrator further includes a second sampling capacitor group 70, a fourth switch group 80, and a fifth switch group 90. The fourth switch group 80 is connected to the second sampling capacitor group 70 and the second input signals VREFP and VREFN. The fourth switch group 80 is used to control the second sampling capacitor group 70 to collect charge from the second input signals during the sampling phase. The fifth switch group 90 is connected to the first sampling capacitor group 20, which is simultaneously connected to the second switch group 30. The fifth switch group 90 is used to cooperate with the second switch group 30 to control the integrating capacitor group 40 to receive the charge from the first sampling capacitor group 20 and the second sampling capacitor group 70 during the conversion phase. In other embodiments, multiple groups of the second sampling capacitor group 70, the fourth switch group 80, and the fifth switch group 90 can be set as needed.
[0050] The second sampling capacitor group 70 includes the third sampling capacitor C7 and the fourth sampling capacitor C8, and the fourth switch group 80 includes the tenth switch K10, the eleventh switch K11, the twelfth switch K12 and the thirteenth switch K13.
[0051] The first terminal of the tenth switch K10 and the first terminal of the eleventh switch K11 are used to receive the second input signal. The second terminal of the tenth switch K10 is connected to the first terminal of the third sampling capacitor C7. The second terminal of the eleventh switch K11 is connected to the first terminal of the fourth sampling capacitor C8. The first terminal of the twelfth switch K12 is connected to the second terminal of the third sampling capacitor C7. The first terminal of the thirteenth switch K13 is connected to the second terminal of the fourth sampling capacitor C8. The second terminals of the twelfth switch K12 and the thirteenth switch K13 are connected to the reference voltage.
[0052] The fifth switch group 90 includes a fourteenth switch K14. The first terminal of the fourteenth switch K14 is connected to the first terminal of the third sampling capacitor C7, and the second terminal of the fourteenth switch K14 is connected to the first terminal of the fourth sampling capacitor C8. The second terminals of the third sampling capacitor C7 and the second terminals of the fourth sampling capacitor C8 are connected to the second switch group 30.
[0053] The tenth switch K10, the eleventh switch K11, the twelfth switch K12 and the thirteenth switch K13 are all controlled by the control signal S1, and the fourteenth switch K14 is controlled by the control signal S2.
[0054] By setting a third sampling capacitor C7 and a fourth sampling capacitor C8, during the sampling phase: the first sampling capacitor C1 and the second sampling capacitor C2 sample the charge of the first input signals INP and INN, and the third sampling capacitor C7 and the fourth sampling capacitor C8 sample the charge of the second input signals VREFP and VREFN; during the conversion phase, the first sampling capacitor C1 and the second sampling capacitor C2, the third sampling capacitor C7 and the fourth sampling capacitor C8 simultaneously transfer and integrate the charge of the first integrating capacitor C3 and the second integrating capacitor C4, and the voltage on the first integrating capacitor C3 and the second integrating capacitor C4 is (INP-INN)+(VREFP-VREFN), thereby meeting the needs of different application scenarios such as sampling and conversion for different input voltages.
[0055] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0056] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. An integrator, characterized in that, include: Operational amplifier, first switch group, first sampling capacitor group, second switch group, integrating capacitor group, third switch assembly, and adjustment capacitor group; The first switch group is connected to the first sampling capacitor group and the first input signal. The first switch group is used to control the first sampling capacitor group to collect charge from the first input signal during the sampling phase. The second switch group is connected to the first sampling capacitor group and the integrating capacitor group. The second switch group is used to control the integrating capacitor group to receive charge from the first sampling capacitor group during the conversion phase. The integrating capacitor group is simultaneously connected to the input and output terminals of the operational amplifier to cooperate with the operational amplifier in charge integration during the conversion phase. The adjusting capacitor group is connected to the input terminal of the operational amplifier through a third switch assembly to cooperate with the integrating capacitor group to adjust the loop bandwidth during the sampling phase.
2. The integrator according to claim 1, characterized in that, The first switch group includes a first switch, a second switch, a third switch, and a fourth switch. The first sampling capacitor group includes a first sampling capacitor and a second sampling capacitor. The first terminal of the first switch and the first terminal of the second switch are used to receive a first input signal. The first terminal of the first sampling capacitor is connected to the second terminal of the first switch. The first terminal of the second sampling capacitor is connected to the second terminal of the second switch. The first terminal of the third switch is connected to the second terminal of the first sampling capacitor. The first terminal of the fourth switch is connected to the second terminal of the second sampling capacitor. The second terminals of the third switch and the second terminals of the fourth switch are connected to a reference voltage.
3. The integrator according to claim 1, characterized in that, The third switch group includes a fifth switch and a sixth switch, and the regulating capacitor group includes a first regulating capacitor and a second regulating capacitor. The fifth switch and the first regulating capacitor are connected in series between the first input terminal of the operational amplifier and the reference voltage, and the sixth switch and the second regulating capacitor are connected in series between the second input terminal of the operational amplifier and the reference voltage.
4. The integrator according to claim 1, characterized in that, The integrating capacitor bank includes a first integrating capacitor and a second integrating capacitor. The first terminal of the first integrating capacitor is connected to the first input terminal of the operational amplifier and the second switch group. The second terminal of the first integrating capacitor is connected to the first output terminal of the operational amplifier. The first terminal of the second integrating capacitor is connected to the second input terminal of the operational amplifier and the second switch group. The second terminal of the second integrating capacitor is connected to the second output terminal of the operational amplifier.
5. The integrator according to claim 1, characterized in that, The second switch group includes a seventh switch, an eighth switch, and a ninth switch. The first sampling capacitor group includes a first sampling capacitor and a second sampling capacitor. The first terminal of the seventh switch is connected to the first terminal of the first sampling capacitor, and the second terminal of the seventh switch is connected to the first terminal of the second sampling capacitor. The first terminal of the eighth switch is connected to the second terminal of the first sampling capacitor, and the second terminal of the eighth switch is connected to the first input terminal of the operational amplifier. The first terminal of the ninth switch is connected to the second terminal of the second sampling capacitor, and the second terminal of the ninth switch is connected to the second input terminal of the operational amplifier.
6. The integrator according to claim 1, characterized in that, The integrator further includes a second sampling capacitor bank, a fourth switch bank, and a fifth switch bank. The fourth switch bank is connected to the second sampling capacitor bank and the second input signal. The fourth switch bank is used to control the second sampling capacitor bank to collect charge from the second input signal during the sampling phase. The fifth switch bank is connected to the first sampling capacitor bank. The first sampling capacitor bank is also connected to the second switch bank. The fifth switch bank is used to cooperate with the second switch bank to control the integrator capacitor bank to receive charge from the first and second sampling capacitor banks during the conversion phase.
7. The integrator according to claim 6, characterized in that, The second sampling capacitor group includes a third sampling capacitor and a fourth sampling capacitor. The fourth switch group includes a tenth switch, an eleventh switch, a twelfth switch, and a thirteenth switch. The first terminals of the tenth switch and the eleventh switch are used to receive a second input signal. The second terminal of the tenth switch is connected to the first terminal of the third sampling capacitor. The second terminal of the eleventh switch is connected to the first terminal of the fourth sampling capacitor. The first terminal of the twelfth switch is connected to the second terminal of the third sampling capacitor. The first terminal of the thirteenth switch is connected to the second terminal of the fourth sampling capacitor. The second terminals of the twelfth switch and the thirteenth switch are connected to a reference voltage.
8. The integrator according to claim 6, characterized in that, The second sampling capacitor group includes a third sampling capacitor and a fourth sampling capacitor. The fifth switch group includes a fourteenth switch. The first terminal of the fourteenth switch is connected to the first terminal of the third sampling capacitor, and the second terminal of the fourteenth switch is connected to the first terminal of the fourth sampling capacitor. The second terminals of the third sampling capacitor and the second terminals of the fourth sampling capacitor are connected to the second switch group.
9. The integrator according to claim 1, characterized in that, Each adjusting capacitor in the adjusting capacitor group has the same capacitance value as each sampling capacitor in the first sampling capacitor group.
10. A chip, characterized in that, Including the integrator as described in any one of claims 1 to 9.