A mesa triac structure for improved igt consistency

Abstract

This invention belongs to, but is not limited to, the field of thyristor technology, and discloses a mesa thyristor structure for improving IGT consistency. It includes a glass tank terminal, a cathode, and a gate, with no adjacent gate region. The glass tank terminal ensures high voltage for the device. The cathode is the current outflow terminal. The gate receives a trigger current, which flows from the gate to the cathode region, controlling the thyristor's conduction. This invention reduces the distance between the cathode region and the glass tank to zero, eliminating the boron-expanded region, which no longer affects IGT parameters, resulting in minimal IGT differences between the wafer edge and central regions. During mesa etching, the width of the glass tank does not affect IGT parameters, making the requirements for mesa etching less stringent and suitable for mass production.

Description

Technical Field

[0001] This invention belongs to, but is not limited to, the field of thyristor technology, and particularly relates to a mesa thyristor structure for improving IGT consistency. Background Technology

[0002] In existing mesa-type unidirectional thyristor products, the distance between the cathode region (or MT1 region) and the glass bath is 10-100 micrometers. During mesa etching, inconsistent bath widths can easily occur. At the wafer edges, the mesa etching rate is faster, resulting in a wider glass bath, while at the wafer center, the etching rate is slower, resulting in a narrower glass bath. This ultimately leads to unequal distances between the cathode region and the glass bath, affecting the IGT (Integrated Ground Tariff) parameters. The greater the difference in distance between the cathode region and the glass bath, the greater the difference in IGT parameters. Existing mesa-type thyristor structures have a boron-expanding region between the cathode region and the glass bath. Current flows through this region when the thyristor is triggered, and the area of ​​this region affects the IGT parameters.

[0003] Therefore, a mesa thyristor structure is needed to improve IGT consistency. Utility Model Content

[0004] To address the problems existing in the prior art, this utility model provides a mesa thyristor structure that improves IGT consistency.

[0005] This invention is implemented as follows: a mesa thyristor structure for improving IGT consistency includes a glass trough terminal, a cathode region, and a gate region; the glass trough terminal ensures that the device achieves high voltage; the cathode is the current outflow terminal of the device; the gate receives a trigger current, which flows from the gate to the cathode region to control the thyristor to conduct.

[0006] Furthermore, the distance between the cathode region and the glass tank is zero.

[0007] Furthermore, the trigger current consists of a portion of the trigger current: the trigger current that flows directly from the gate to the cathode region.

[0008] Furthermore, the glass tank terminal and the cathode region are directly connected on the chip platform, without a gate adjacent diffusion region.

[0009] Furthermore, the cathode region is composed of multiple n⁺ injection islands, which are disposed on the surface of the p-type substrate and distributed in a ring around the gate region.

[0010] Furthermore, the glass trench terminal is located in the edge region of the chip and has a silicon oxide-glass stack structure continuously packaged along the chip edge.

[0011] Furthermore, the gate region has a stepped structure, consisting of a p⁺ doped region embedded in a p-type substrate and an n⁺ doped region disposed thereon.

[0012] Furthermore, a direct contact area without intermediate insulating medium is formed on the chip surface between the glass tank terminal and the cathode region.

[0013] Furthermore, an injection channel from the n⁺ region to the p⁻ region is formed between the gate region and the cathode region through a doping structure, and no transition buffer layer is provided on the chip mesa of the injection channel.

[0014] Based on the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solution to be protected by this utility model are as follows:

[0015] This invention reduces the distance between the cathode region and the glass bath to zero, eliminates the boron expansion region, and the boron expansion region no longer affects the IGT parameters, resulting in a small difference in IGT between the wafer edge and the central region.

[0016] The width of the glass groove does not affect the IGT parameters during the corrosion of the table surface, and the requirements for table surface corrosion are relatively relaxed, making it suitable for large-scale production.

[0017] During the etching of the glass bath, the entire wafer of a thyristor undergoes a rotating circular motion. With a conventional thyristor structure, the outermost ring of the wafer etches rapidly, resulting in a wide glass bath and a narrow gate adjacency region (GGT). The center of the wafer etches the slowest, with the widest GGT. This significant difference in GGT width between the center and outermost rings leads to a noticeable difference in IGT between the wafer edge and center. Using this patented structure, there is no gate adjacency region, significantly improving the consistency of IGT parameters for unidirectional thyristors, greatly reducing the IGT difference between the wafer edge and center, and significantly increasing yield. For example, one of our thyristor products requires an IGT parameter of 40-80µA. With a conventional thyristor structure, the IGT parameter distribution is 40-100µA, while the required IGT parameter is 40-80µA, resulting in an IGT pass rate of 83%. With the new structure, the IGT parameter distribution is 40-85uA, the IGT parameter requirement is 40-80uA, the IGT pass rate is 99%, and the product profit has increased by 15%. Overall, IGT consistency has been significantly improved, and the IGT pass rate has been significantly increased. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a mesa-type thyristor structure provided by existing technology;

[0019] Figure 2 This is a schematic diagram of a mesa thyristor structure for improving IGT consistency provided in an embodiment of this utility model;

[0020] Figure 3 This is an equivalent circuit diagram of a mesa-type silicon controlled rectifier chip structure for improving IGT consistency provided in this embodiment of the present invention;

[0021] Figure 4 This is an equivalent circuit diagram of a mesa thyristor for improving IGT consistency provided in this embodiment of the utility model;

[0022] In the diagram: 1. Cathode; 2. Glass tank terminal; 3. Gate electrode. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this utility model clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this utility model.

[0024] like Figure 2 As shown, this utility model embodiment provides a mesa thyristor structure for improving IGT consistency, including a glass slot terminal 2, a cathode 1, and a gate 3; the glass slot terminal 2 ensures that the device achieves high voltage; the cathode 1 is the current outflow terminal of the device; the gate 3 receives trigger current, and the trigger current flows from the gate 3 to the cathode 1 to control the thyristor to conduct.

[0025] The distance between the cathode 1 and the glass tank terminal 2 is zero.

[0026] The trigger current consists of a portion of the trigger current: the trigger current that flows directly from the gate 3 to the cathode 1.

[0027] Unidirectional thyristors, as a type of AC switch, are widely used in relays and motorcycles. Their chip structure is as follows: Figure 2 As shown, it includes regions n1, n2, P1, and P2, as well as electrodes K and G formed on the front side of the chip, and electrode A on the back side of the chip. Currently, all thyristor manufacturers are working hard to improve the consistency of IGTs to meet the requirements of end customers.

[0028] When a trigger current IG is applied to the gate, it is amplified into current IC2 by transistor V2. IC2 can also be considered as the base current of transistor V1, which is amplified into current IC1 by V1. If the current amplification factors of V1 and V2 are a1 and a2 respectively, then the following relationship holds:

[0029] IC1 = a1 * IA (1)

[0030] IC2=a2*Ik (2)

[0031] IK = IG + IA (3)

[0032] IA = IC1 + IC2 (4)

[0033] Substituting (1) and (3) into (4), we have IA = a1*IA + a2*IK (5)

[0034] Substituting (3) into (5) and rearranging, we get

[0035] IA = a2 * IG / (1 - (a1 + a2))

[0036] It is evident that when a1+a2=1, the anode current IA is infinite, and both transistors quickly enter the saturation conduction state. Therefore, the current amplification factor a1+a2=1 of the two transistors of the thyristor is the condition for the thyristor to switch from cutoff to conduction.

[0037] This invention is mainly applied to unidirectional thyristor products.

[0038] In the device structure, cathode 1 and glass tank terminal 2 are physically connected with zero gap on the mesa structure. This connection method plays a decisive role in the convergence characteristics of the terminal electric field. Since there is no redundant oxide buffer, 2 forms a continuous closed field distribution under static high voltage, allowing the terminal region to maintain a smooth electric field transition without relying on additional field plates or metal shielding. This near-field coupling mechanism fundamentally changes the dependence of traditional terminal designs on edge effects, enabling the device to extend its voltage withstand capability without increasing the additional silicon area.

[0039] During the triggering process, gate 3 serves as the minority carrier injection starting point, and its structural characteristics are particularly critical. Instead of a resistor or diffusion redundancy region between gate 3 and cathode 1, a collimated electron migration path is achieved using a doping gradient between a highly doped n⁺ region and a low-doped p region. Actual tests show that when gate 3 receives a microsecond-level current pulse, the main component of its trigger current directly crosses the extremely narrow p region and is injected into the outer ring n⁺ island of gate 1, avoiding the energy loss and response delay caused by the gate-cathode resistance in typical structures.

[0040] Further analysis of its conduction mechanism reveals that during the initial conduction phase, the injected electrons from gate 3 rapidly form an intrinsic inversion region in the n⁺ region where 1 is located, exciting the release of holes in the p region. Subsequently, a stable n⁺-pnp⁺ four-layer channel is formed in the vertical structure, where minority carriers accumulate at the interface and drift stably through the region near the glass trough terminal 2. The embedded oxide layer structure in 2 releases surface charge, suppressing lateral electric field drift and providing stable boundary conditions for the bipolar conduction process.

[0041] During the stable conduction phase, a typical bipolar diffusion injection mechanism is formed between cathode 1 and anode, with current primarily flowing along the longitudinal path. Since 1 and 2 are structurally continuous boundaries, no "tail current" caused by residual charge on the traditional silicon boundary wafer is observed during device conduction, nor is any localized breakdown luminescence observed. This implies that, at the design level, the device effectively shields against breakdown sources that might be induced by micron-level structural asymmetry.

[0042] When an external turn-off signal is applied, the device enters the turn-off transition state. At this point, the material properties of the glass trough terminal 2 become crucial: its deep-level trap adsorption capability, combined with the multilayer glass-silica composite structure, enables rapid recombination of residual minority carriers. The device exhibits extremely low turn-off overshoot and IGT drift rate between repeated turn-on cycles in experiments, demonstrating its ability to maintain stable gate control accuracy in industrial control scenarios with frequent turn-on and turn-off cycles.

[0043] The device structure is optimized by combining the trigger channel between gate 3 and cathode 1 with the terminal drift surface formed by glass tank terminal 2. This not only enhances trigger consistency under high temperature and high pressure conditions, but also effectively improves the overall switching reliability and batch uniformity of the device. Its physical essence lies in the coordinated matching of doping profile and structural layout, rather than simply relying on the adjustment of doping depth or area parameters, which has significant practical engineering value.

[0044] Figure 3 This is an equivalent circuit diagram of a mesa-type silicon controlled rectifier chip structure for improving IGT consistency provided in this embodiment of the present invention;

[0045] Figure 4 This is an equivalent circuit diagram of a mesa thyristor for improving IGT consistency provided in this embodiment of the utility model;

[0046] This invention adjusts the distance between the cathode region and the glass trough to zero, as in Example 1. Figure 2 Compared to the traditional structure, the distance between the cathode region and the glass bath is reduced to zero, and the boron expansion region is eliminated. This boron expansion region no longer affects the IGT parameters, and the IGT difference between the wafer edge and the central region is small.

[0047] The core of this structure lies in eliminating the boron-diffused P+ termination on the cathode region (corresponding to the P diffusion being far from the gate region in traditional designs), and by connecting the glass bath termination to the cathode region (n1 region) in... Figure 3 The planar structure shown is spliced ​​with zero spacing, resulting in no spikes in the overall mesa electric field at the edge region. Due to the high fixed charge density of the SiO2 / quartz composite interface embedded in the glass groove, the edge potential can be naturally leveled. The electric field lines converge inward from the terminal glass region rather than pointing to the p1-p2 interface, effectively suppressing hole back-injection disturbances at the mesa edge and achieving a highly consistent gate control boundary.

[0048] Before the triggering action occurs, the minority carrier injected at the gate G first generates an inversion channel in the p2-n2 adjacent region ( Figure 4The structure shown in the left figure corresponds to n2 as the gate injection region, while the PN junction between p2 and n1 becomes the initial carrier feedback channel. Because this structure places n1 close to the glass terminal, the boundary electric field is uniform and the well depth variation is small, resulting in minimal deviation of the trigger threshold (IGT) at different locations within the chip. This method of eliminating IGT drift sources at the structural physics level is far more reliable than relying on external damping or parasitic adjustments.

[0049] Figure 4 The equivalent circuit diagram on the right further reveals that the gate triggering path consists of a three-transistor equivalent loop, where the IG current generated by gate injection is directly coupled to the K-terminal (cathode). Its response time and threshold are highly dependent on the symmetry of the diffusion characteristics between regions n1 and n2. This structure avoids the risk of minority carrier recombination or uncontrolled drift in the boundary region during gate triggering by eliminating the boron-diffusing layer (p2) around the cathode. Especially in multi-chip array packaging, the maximum IGT difference between edge devices and center devices is reduced to less than 5 mA, significantly better than the traditional distributed drift of over 30 mA.

[0050] Furthermore, due to the absence of a remote anti-diffusion terminal in the device design, the path from n1 to the K electrode is short, and carrier accumulation is rapid. Combined with the surface electric field modulation capability provided by the glass bath, the mesa forms a locally controllable carrier injection platform. The dynamic response of the entire cathode region unfolds almost synchronously at the moment of triggering, avoiding the conduction delay or non-uniform IGT distribution problems caused by the boron diffusion barrier in conventional structures. This structure exhibits good temperature drift stability and process tolerance in high-frequency pulse rectification and medium-to-low voltage AC / DC triggering scenarios.

[0051] Example 1: 1. The silicon wafer selected is an N-type monocrystalline silicon wafer with a thickness of 200-250 μm and a resistivity of 30-40 ohm-cm;

[0052] 2. Place the silicon wafer into SC-1 for cleaning to remove surface impurities;

[0053] 3. Field oxidation;

[0054] 4. One-time double-sided through-path diffusion lithography and etching;

[0055] 5. Concentrated boron pre-diffusion;

[0056] 6. Main diffusion of concentrated boron;

[0057] 7. Rinse off the oxide layer;

[0058] 8. Pre-diffusion of dilute boron;

[0059] 9. Main diffusion of dilute boron;

[0060] 10. Secondary double-sided cathode photolithography and etching;

[0061] 11. Phosphorus pre-diffusion;

[0062] 12. Phosphorus main diffusion;

[0063] 13. The silicon wafer is subjected to front-side groove photolithography, the back side is coated with resist to protect the back side, and then the silicon dioxide in the front-side groove window is etched away;

[0064] 14. Silicon wafers undergo silicon etching to create groove-shaped structures;

[0065] 15. Clean the silicon wafer;

[0066] 16. Apply glass powder to the glass tank, dry the glass powder, and wipe off the surface glass powder, leaving only the glass powder in the tank;

[0067] 17. Low-temperature sintered glass;

[0068] 18. High-temperature sintered glass;

[0069] 19. Photolithography and etching of the front-side leadholes;

[0070] 20. Front-side aluminum deposition,

[0071] 21. Front-side metal photolithography and etching, etching away the isolation area and terminal metal;

[0072] 22. Titanium-nickel-silver deposited on the back;

[0073] 23. Vacuum alloy;

[0074] 24. Parameter testing; reject any defective products.

[0075] 25. School district.

[0076] In the description of this utility model, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," "front end," "rear end," "head," "tail," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. In addition, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0077] The above description is only a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any modifications, equivalent substitutions and improvements made by those skilled in the art within the technical scope disclosed in this utility model, and within the spirit and principles of this utility model, should be included within the protection scope of this utility model.

Claims

1. A mesa thyristor structure for improved IGT uniformity comprising a glass trench termination, a cathode region and a gate region, characterized by, The glass tank terminal and the cathode region are directly connected on the chip platform, without a gate adjacent to the diffusion region.

2. The table thyristor structure according to claim 1, wherein The cathode region consists of multiple n⁺ injection islands, which are disposed on the surface of the p-type substrate and distributed in a ring around the gate region.

3. The table thyristor structure of claim 1, wherein, The glass tank terminal is located in the edge region of the chip and has a silicon oxide-glass stack structure that is continuously packaged along the edge of the chip.

4. The table thyristor structure of claim 1, wherein, The gate region has a stepped structure, consisting of a p⁺ doped region embedded in a p-type substrate and an n⁺ doped region disposed thereon.

5. The table thyristor structure of claim 1, wherein, A direct contact area without intermediate insulating medium is formed between the glass tank terminal and the cathode region on the chip surface.

6. The table thyristor structure of claim 1, wherein, The gate region and the cathode region are connected by a doped structure to form an injection channel from the n⁺ region to the p⁻ region. The injection channel does not have a transition buffer layer on the chip mesa.

Images