A 50g error code instrument test board

Abstract

The utility model provides a 50G error code appearance test board of high speed circuit design and PCB engineering application technical field, include: one layer auxiliary signal layer, one layer auxiliary ground layer, be located in the top of auxiliary signal layer, one layer power supply layer, be located in the top of auxiliary ground layer, be connected with auxiliary ground layer through high frequency decoupling capacitor, one layer high speed signal inner layer, be located in the top of power supply layer, one layer complete ground layer, be located in the top of high speed signal inner layer with auxiliary ground layer is connected, one layer high speed signal surface layer, be located in the top of complete ground layer with one error code appearance test chip, a plurality of differential microstrip line, a plurality of differential line, a plurality of high speed connector, one decoupling capacitor array, one terminal capacitance resistance, one ground via array, one shield GND copper skin and one power module are equipped. The utility model has the advantages of: greatly promoted the signal integrity of error code appearance, test sensitivity and measurement accuracy.

Description

Technical Field

[0001] This utility model relates to the field of high-speed circuit design and PCB engineering application technology, and specifically to a 50G bit error rate test board. Background Technology

[0002] With the rapid development of emerging technologies such as 5G communication, data centers, and artificial intelligence (AI) computing, the demand for high-speed data transmission with rates of 50Gbps and above is becoming increasingly urgent. Bit error rate testers (BERTs) play an indispensable role in the critical process of evaluating the performance of such high-speed links. The quality of the BERT's core component—the test board (PCB)—directly affects the integrity of signal transmission and ultimately determines the accuracy and reliability of the bit error rate test.

[0003] However, in the traditional PCB stack-up structure used in high-speed bit error rate test boards, the following inherent defects generally exist when processing high-speed differential signals of 50Gbps and above:

[0004] 1. Insufficient differential impedance control accuracy: This leads to increased signal reflection and waveform distortion;

[0005] 2. Significantly high insertion loss: This weakens the test system's sensitivity to detecting weak bit errors;

[0006] 3. Excessive interlayer coupling interference: This can easily lead to severe signal crosstalk.

[0007] 4. Insufficient high-frequency noise suppression performance: significantly affects the accuracy of bit error rate (BER) measurement.

[0008] The root cause is that existing high-speed PCB stack-up structures rarely feature holistic optimization designs for bit error rate tester (BER) requirements of 50Gbps and above. Their inherent structural limitations make it difficult to adapt to the stringent requirements of current high-speed testing scenarios for high bandwidth, ultra-low insertion loss, and strong anti-crosstalk capabilities.

[0009] Therefore, how to provide a 50G bit error rate test board that can improve the signal integrity, test sensitivity and measurement accuracy of the bit error rate tester has become an urgent technical problem to be solved. Summary of the Invention

[0010] The technical problem to be solved by this utility model is to provide a 50G bit error rate test board, which improves the signal integrity, test sensitivity and measurement accuracy of the bit error rate tester.

[0011] This utility model is implemented as follows: a 50G bit error rate test board, comprising:

[0012] A single auxiliary signal layer;

[0013] An auxiliary ground layer is disposed at the top of the auxiliary signal layer;

[0014] A power layer is located on top of the auxiliary ground layer and is connected to the auxiliary ground layer through a high-frequency decoupling capacitor.

[0015] A high-speed signal inner layer is disposed on top of the power layer;

[0016] A complete ground layer is disposed at the top of the high-speed signal inner layer and connected to the auxiliary ground layer;

[0017] A high-speed signal surface layer is located at the top of the complete ground layer, and includes a bit error rate test chip, several differential microstrip lines, several differential lines, several high-speed connectors, a decoupling capacitor array, several terminating capacitors and resistors, a grounding via array, a shielded GND copper foil, and a power module.

[0018] The power layer, decoupling capacitor array, power module, bit error rate test chip, differential microstrip line, and high-speed connector are connected in sequence; the bit error rate test chip, differential line, terminating capacitor and resistor, complete ground layer, ground via array, and shielded GND copper foil are connected in sequence.

[0019] The bit error rate test chip is located in the middle of the high-speed signal surface layer; each of the high-speed connectors is symmetrically arranged around the bit error rate test chip; the decoupling capacitor array is located on the side of the power module; each of the terminating capacitors and resistors is located on the side of the high-speed connectors; the grounding via array is located on both sides of the differential line; the shielding GND copper foil covers the differential microstrip line and the differential line.

[0020] Furthermore, the auxiliary signal layer, auxiliary ground layer, power layer, high-speed signal inner layer, complete ground layer, and high-speed signal outer layer are all PCB boards, and the dielectric constant is ≤3.6.

[0021] Furthermore, the thickness range of the auxiliary signal layer, auxiliary ground layer, power layer, high-speed signal inner layer, complete ground layer, and high-speed signal surface layer is [100μm, 200μm].

[0022] Furthermore, the copper thickness of the auxiliary signal layer, auxiliary ground layer, power layer, high-speed signal inner layer, complete ground layer, and high-speed signal outer layer is 1 oz.

[0023] Furthermore, the high-speed connector is a SAM high-frequency connector.

[0024] Furthermore, the power module is either a DC-DC module or an LDO module.

[0025] The advantages of this utility model are:

[0026] 1. The system consists of an auxiliary signal layer, an auxiliary ground layer, a power layer, a high-speed signal inner layer, a complete ground layer, and a high-speed signal outer layer, arranged sequentially. The power layer is connected to the auxiliary ground layer via high-frequency decoupling capacitors. The complete ground layer is connected to the auxiliary ground layer. The high-speed signal outer layer contains a bit error rate test chip, differential microstrip lines, differential lines, high-speed connectors, a decoupling capacitor array, terminating resistors, a grounding via array, shielded GND copper foil, and a power module. The power layer, decoupling capacitor array, power module, bit error rate test chip, differential microstrip lines, and high-speed connectors are connected sequentially. The bit error rate test chip, differential lines, terminating resistors, complete ground layer, grounding via array, and shielded GND copper foil are connected sequentially. The bit error rate test chip is located in the center of the high-speed signal outer layer. Each high-speed connector is symmetrically arranged around the bit error rate test chip. The decoupling capacitor array is located next to the power module. Each terminating resistor is located next to the high-speed connector. The top layer features a grounding via array positioned on both sides of the differential line. A shielded GND copper layer covers both the differential microstrip line and the differential line. This "auxiliary ground layer-power layer-complete ground layer" stacked structure, combined with a fully covered shielded GND copper layer and grounding via array, constructs a continuous low-impedance reference plane to stabilize the differential impedance, effectively suppressing signal reflection and waveform distortion. The use of a ≤3.6 dielectric constant material and an ultra-thin 100-200μm layer thickness significantly reduces dielectric loss, effectively decreasing insertion loss and improving the sensitivity to weak bit error signals. Simultaneously, a high-frequency decoupling capacitor array and a configurable power supply module for DC-DC / LDO compress power supply noise, and a SAM high-frequency connector achieves end-to-end impedance matching. Ultimately, at a 50Gbps rate, this effectively improves the signal eye diagram opening and reduces the bit error detection threshold, significantly enhancing the signal integrity, test sensitivity, and measurement accuracy of the bit error rate analyzer.

[0027] 2. The structure is reasonable and supports high-speed signal transmission of 50Gbps and above; it effectively controls the differential line impedance to reduce signal reflection and distortion; it has low insertion loss and low crosstalk, which improves the accuracy of bit error rate testing; it supports high-frequency noise suppression and enhances the stability of the test platform; it is easy to mass-produce and is suitable for the development of various high-speed test boards.

[0028] 3. By using a symmetrical center layout, differential signals are ensured to be of equal length, reducing skew; by using decoupling capacitors close to the chip, power supply noise is effectively reduced, and PI is improved; by using a grounding via array, crosstalk is suppressed, and EMC is enhanced; by using shielded GND grounding, EMI radiation is effectively reduced, and SI is improved; by using terminating resistors for near-end matching, signal reflection is effectively reduced, and test accuracy is improved.

[0029] 4. A star connection is used, i.e., "chip → capacitor → power layer", through power pins → decoupling capacitors → power layer to avoid chain-like traces; AC coupling or DC termination is achieved by connecting the differential lines to terminating resistors → GND, with one end of the terminating resistor connected to the differential line and the other end connected to the GND layer via a via; multiple grounding points are achieved through shielded GND copper traces → grounding vias → GND to ensure a low-impedance return path; and multiple grounding vias are interconnected between all GND layers, with interlayer ground planes connected by ≥36 vias per inch to reduce ground bounce noise. Attached Figure Description

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a side view of a 50G bit error rate test board according to this utility model.

[0032] Figure 2 This is a top view of the high-speed signal surface of this utility model.

[0033] Figure 3 This is a circuit block diagram of a 50G bit error rate test board according to the present invention.

[0034] Marker explanation:

[0035] 100 - A 50G bit error rate tester test board, 1 - Auxiliary signal layer, 2 - Auxiliary ground layer, 3 - Power layer, 4 - High-speed signal inner layer, 5 - Complete ground layer, 6 - High-speed signal surface layer, 31 - High-frequency decoupling capacitor, 61 - Bit error rate tester chip, 62 - Differential microstrip line, 63 - Differential line, 64 - High-speed connector, 65 - Decoupling capacitor array, 66 - Termination capacitor and resistor, 67 - Grounding via array, 68 - Shielding GND copper foil, 69 - Power module. Detailed Implementation

[0036] This utility model embodiment provides a 50G bit error rate test board 100, which solves the technical problem that existing high-speed PCB stack-up structures rarely have an overall optimized design for bit error rate tester testing requirements of 50Gbps and above. Their inherent structural limitations make it difficult to adapt to the stringent requirements of current high-speed testing scenarios for high bandwidth, ultra-low insertion loss and strong anti-crosstalk capability. This invention achieves a significant improvement in the signal integrity, test sensitivity and measurement accuracy of the bit error rate tester.

[0037] The technical solution in this embodiment of the utility model is to solve the above problems. The overall idea is as follows: By combining the "auxiliary ground layer 2-power layer 3-complete ground layer 5" stacked structure with the fully covered shielded GND copper foil 68 and grounding via array 67, a continuous low impedance reference plane is constructed to stabilize the differential impedance and completely suppress signal reflection and waveform distortion. With the use of materials with a dielectric constant of ≤3.6 and an ultra-thin layer thickness of 100-200μm, the dielectric loss is significantly reduced, the insertion loss is effectively reduced, and the detection sensitivity of weak bit error signals is improved. At the same time, the decoupling capacitor array 65 and the configurable power supply module 69 of DCDC / LDO are used to compress power supply noise, and the high-speed connector 64 is used to achieve end-to-end impedance matching. Finally, at a rate of 50Gbps, the signal eye diagram opening is effectively improved and the bit error detection threshold is reduced, thereby improving the signal integrity, test sensitivity and measurement accuracy of the bit error rate meter.

[0038] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0039] Please refer to Figures 1 to 3 As shown, a preferred embodiment of the 50G bit error rate test board 100 of this utility model includes:

[0040] Bottom Layer 1 (auxiliary signal layer);

[0041] An auxiliary ground layer (GND2) 2 is disposed on top of the auxiliary signal layer 1 to enhance the shielding effect;

[0042] A power layer 3 is located on top of the auxiliary ground layer 2 and is connected to the auxiliary ground layer 2 through a high-frequency decoupling capacitor 31 to form a local low impedance network. The power layer 3 adopts a low noise design.

[0043] A high-speed signal inner layer (Internal Signal) 4 is located on top of the power layer 3 and is used for critical signal routing;

[0044] A complete ground plane (GND1) 5 is located at the top of the high-speed signal inner layer 4 and connected to the auxiliary ground plane 2, serving as a high-speed signal return path; the complete ground plane 5 and the auxiliary ground plane 2 are interconnected with low impedance through multiple ground vias (not shown);

[0045] A high-speed signal top layer 6 is located at the top of the complete ground layer 5, and includes a bit error rate test chip 61, several differential microstrip lines 62, several differential lines 63, several high-speed connectors 64, a decoupling capacitor array 65, several terminating resistors 66, a grounding via array 67, a shielded GND copper foil 68, and a power module 69.

[0046] The bit error rate test chip 61 is the core signal source, generating a 50Gbps high-speed differential signal; the high-speed connector 64 is used to connect to the device under test (DUT) and transmit the differential signal; the decoupling capacitor array 65 (0.1μF, 10nF high-frequency ceramic capacitors) is used to filter out power supply noise and stabilize power supply; the terminating resistor (93Ω differential matching resistor) 66 is used to achieve impedance matching and reduce reflection; the grounding via array 67 is used to form a shielding wall to suppress crosstalk; the shielding GND copper foil 68 is used to surround the high-speed signal line and reduce EMI radiation; the power module 69 is used to provide a stable voltage to the bit error rate test chip 61.

[0047] The line width and spacing of the differential line 63 must be precisely designed according to the target impedance of 93Ω±8%; the single-ended lines in the open copper area and at the high-speed connector 64 shall be precisely routed according to 50Ω±8%.

[0048] The differential microstrip lines 62 are coplanar and evenly distributed, with return ground vias evenly distributed along the lines to ensure signal integrity.

[0049] The power layer 3, decoupling capacitor array 65, power module 69, bit error rate test chip 61, differential microstrip line 62, and high-speed connector 64 are connected in sequence; the bit error rate test chip 61, differential line 63, terminating capacitor 66, complete ground layer 5, ground via array 67, and shielded GND copper foil 68 are connected in sequence.

[0050] The bit error rate test chip 61 is located in the middle of the high-speed signal surface layer 6 (to facilitate symmetrical wiring to the high-speed connectors 64 on both sides, ensuring equal length); each of the high-speed connectors 64 is symmetrically arranged around the bit error rate test chip 61 to ensure symmetrical signal paths and reduce skew; the decoupling capacitor array 65 is located on the side of the power module 69, with the traces as short and straight as possible, and preferentially uses inner layer blind vias (not shown) to connect to the power layer 3; each of the terminating capacitors 66 is located on the side of the high-speed connectors 64 to achieve the shortest distance matching and avoid signal reflection; the grounding via array 67 is located on both sides of the differential line 63 to form a "return ground wall" to enhance the shielding effect; the shielding GND copper foil 68 covers the differential microstrip line 62 and the differential line 63 to reduce external interference, and is grounded through multiple vias to form a coplanar waveguide structure.

[0051] The auxiliary signal layer 1, auxiliary ground layer 2, power layer 3, high-speed signal inner layer 4, complete ground layer 5, and high-speed signal surface layer 6 are all PCB boards with a dielectric constant ≤ 3.6.

[0052] The thickness range of the auxiliary signal layer 1, auxiliary ground layer 2, power layer 3, high-speed signal inner layer 4, complete ground layer 5, and high-speed signal surface layer 6 is [100μm, 200μm].

[0053] The copper thickness of the auxiliary signal layer 1, auxiliary ground layer 2, power layer 3, high-speed signal inner layer 4, complete ground layer 5, and high-speed signal surface layer 6 is 1 oz (approximately 35 μm) to balance the high-frequency skin effect and manufacturing cost.

[0054] The high-speed connector 64 is a SAM high-frequency connector.

[0055] The power module 69 is either a DC-DC module or an LDO module.

[0056] Working principle of this utility model:

[0057] The auxiliary signal layer 1, located at the bottom layer, is electromagnetically isolated by the auxiliary ground layer 2 and then powered by the power layer 3, which is anchored to the auxiliary ground layer 2 via the high-frequency decoupling capacitor 31. The high-speed signal inner layer 6 routes key signals under the clamping of the power layer 3 and the complete ground layer 5. The complete ground layer 5 is interconnected with the auxiliary ground layer 2 through the ground via array 67 to form a continuous low-impedance reference plane. The bit error rate test chip 61 is centrally connected to symmetrically distributed high-speed connectors 64. The differential microstrip line 62 and differential line 63 are fully covered by shielded GND copper foil 68 and form a coplanar waveguide structure with the dual-sided ground via array 67. The terminal capacitor 66 is matched near the end to suppress signal reflection. At the same time, the decoupling capacitor array 65 adopts a star topology and is directly connected to the power layer 3 to compress power supply noise.

[0058] In summary, the advantages of this utility model are as follows:

[0059] 1. The system consists of an auxiliary signal layer, an auxiliary ground layer, a power layer, a high-speed signal inner layer, a complete ground layer, and a high-speed signal outer layer, arranged sequentially. The power layer is connected to the auxiliary ground layer via high-frequency decoupling capacitors. The complete ground layer is connected to the auxiliary ground layer. The high-speed signal outer layer contains a bit error rate test chip, differential microstrip lines, differential lines, high-speed connectors, a decoupling capacitor array, terminating resistors, a grounding via array, shielded GND copper foil, and a power module. The power layer, decoupling capacitor array, power module, bit error rate test chip, differential microstrip lines, and high-speed connectors are connected sequentially. The bit error rate test chip, differential lines, terminating resistors, complete ground layer, grounding via array, and shielded GND copper foil are connected sequentially. The bit error rate test chip is located in the center of the high-speed signal outer layer. Each high-speed connector is symmetrically arranged around the bit error rate test chip. The decoupling capacitor array is located next to the power module. Each terminating resistor is located next to the high-speed connector. The top layer features a grounding via array positioned on both sides of the differential line. A shielded GND copper layer covers both the differential microstrip line and the differential line. This "auxiliary ground layer-power layer-complete ground layer" stacked structure, combined with a fully covered shielded GND copper layer and grounding via array, constructs a continuous low-impedance reference plane to stabilize the differential impedance, effectively suppressing signal reflection and waveform distortion. The use of a ≤3.6 dielectric constant material and an ultra-thin 100-200μm layer thickness significantly reduces dielectric loss, effectively decreasing insertion loss and improving the sensitivity to weak bit error signals. Simultaneously, a high-frequency decoupling capacitor array and a configurable power supply module for DC-DC / LDO compress power supply noise, and a SAM high-frequency connector achieves end-to-end impedance matching. Ultimately, at a 50Gbps rate, this effectively improves the signal eye diagram opening and reduces the bit error detection threshold, significantly enhancing the signal integrity, test sensitivity, and measurement accuracy of the bit error rate analyzer.

[0060] 2. The structure is reasonable and supports high-speed signal transmission of 50Gbps and above; it effectively controls the differential line impedance to reduce signal reflection and distortion; it has low insertion loss and low crosstalk, which improves the accuracy of bit error rate testing; it supports high-frequency noise suppression and enhances the stability of the test platform; it is easy to mass-produce and is suitable for the development of various high-speed test boards.

[0061] 3. By using a symmetrical center layout, differential signals are ensured to be of equal length, reducing skew; by using decoupling capacitors close to the chip, power supply noise is effectively reduced, and PI is improved; by using a grounding via array, crosstalk is suppressed, and EMC is enhanced; by using shielded GND grounding, EMI radiation is effectively reduced, and SI is improved; by using terminating resistors for near-end matching, signal reflection is effectively reduced, and test accuracy is improved.

[0062] 4. A star connection is used, i.e., "chip → capacitor → power layer", through power pins → decoupling capacitors → power layer to avoid chain-like traces; AC coupling or DC termination is achieved by connecting the differential lines to terminating resistors → GND, with one end of the terminating resistor connected to the differential line and the other end connected to the GND layer via a via; multiple grounding points are achieved through shielded GND copper traces → grounding vias → GND to ensure a low-impedance return path; and multiple grounding vias are interconnected between all GND layers, with interlayer ground planes connected by ≥36 vias per inch to reduce ground bounce noise.

[0063] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A 50G bit error rate test board, characterized in that: include: A single auxiliary signal layer; An auxiliary ground layer is disposed at the top of the auxiliary signal layer; A power layer is located on top of the auxiliary ground layer and is connected to the auxiliary ground layer through a high-frequency decoupling capacitor. A high-speed signal inner layer is disposed on top of the power layer; A complete ground layer is disposed at the top of the high-speed signal inner layer and connected to the auxiliary ground layer; A high-speed signal surface layer is located at the top of the complete ground layer, and includes a bit error rate test chip, several differential microstrip lines, several differential lines, several high-speed connectors, a decoupling capacitor array, several terminating capacitors and resistors, a grounding via array, a shielded GND copper foil, and a power module. The power layer, decoupling capacitor array, power module, bit error rate test chip, differential microstrip line, and high-speed connector are connected in sequence; the bit error rate test chip, differential line, terminating capacitor and resistor, complete ground layer, ground via array, and shielded GND copper foil are connected in sequence. The bit error rate test chip is located in the middle of the high-speed signal surface layer; each of the high-speed connectors is symmetrically arranged around the bit error rate test chip; the decoupling capacitor array is located on the side of the power module; each of the terminating capacitors and resistors is located on the side of the high-speed connectors; the grounding via array is located on both sides of the differential line; the shielding GND copper foil covers the differential microstrip line and the differential line.

2. The 50G bit error rate test board as described in claim 1, characterized in that: The auxiliary signal layer, auxiliary ground layer, power layer, high-speed signal inner layer, complete ground layer, and high-speed signal outer layer are all PCB boards with a dielectric constant ≤ 3.

6.

3. The 50G bit error rate test board as described in claim 1, characterized in that: The thickness range of the auxiliary signal layer, auxiliary ground layer, power layer, high-speed signal inner layer, complete ground layer and high-speed signal surface layer is [100μm, 200μm].

4. The 50G bit error rate test board as described in claim 1, characterized in that: The copper thickness of the auxiliary signal layer, auxiliary ground layer, power layer, high-speed signal inner layer, complete ground layer, and high-speed signal outer layer is 1 oz.

5. A 50G bit error rate test board as described in claim 1, characterized in that: The high-speed connector is a SAM high-frequency connector.

6. The 50G bit error rate test board as described in claim 1, characterized in that: The power module is either a DC-DC module or an LDO module.

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