A pulse timing output controller

Abstract

This application provides a pulse timing output controller, comprising: a microcontroller with network communication capabilities for system control, pulse detection, and network communication; the microcontroller having a built-in network controller, transceiver, and oscillator load capacitor; an input buffer for signal buffering, control, and driving output signals; and an output buffer for controlling and driving output signals. The microcontroller is connected to the input buffer for detecting second pulses. The microcontroller is also connected to the output buffer for controlling the output signal switching or output signal. The microcontroller includes three outputs: one output connected to the output buffer for outputting pulse signals, and the other two outputs connected to the enable terminals of the output buffer, respectively controlling the switching of the microcontroller's output signals and the switching of forwarding the input second pulse signals. This controller can convert the second pulse signal output by a high-precision time device into a synchronous trigger signal for other devices, achieving time synchronization between the two devices.

Description

Technical Field

[0001] This application belongs to the technical field of electronic circuits and relates to a pulse timing output controller. Background Technology

[0002] In some hardware-in-the-loop simulation systems, other devices within the system need to synchronize with high-precision time reference devices such as rubidium clocks and navigation discipline clocks. Synchronization methods include second pulses and the PTP network protocol.

[0003] Using the above synchronization methods in general-purpose devices presents certain difficulties. For example, when using second pulses for synchronization, the second pulse is merely a timing-generated logical signal, lacking second-level time information. General-purpose devices need to adapt to the host computer's control protocol or low-precision time synchronization protocols such as NTP, generally requiring software development for protocol conversion. Using sub-microsecond time synchronization methods such as PTP network time synchronization protocol or IRIG-B time code synchronization requires specialized hardware and software support. However, general-purpose devices typically do not include such hardware. Therefore, achieving high-precision time synchronization with general-purpose devices is difficult and usually quite costly. Utility Model Content

[0004] The purpose of this application is to provide a pulse timing output controller that can achieve high-precision time synchronization at low cost.

[0005] This application provides a pulse timing output controller, wherein the pulse timing output controller includes:

[0006] The microcontroller has network communication capabilities and is used for system control, pulse detection, and network communication. The microcontroller has a built-in network controller, transceiver, and oscillator load capacitor.

[0007] Input buffer, used for signal buffering, control and drive output signals;

[0008] Output buffer, used to control and drive output signals.

[0009] The microcontroller is connected to the input buffer and is used to detect the second pulse.

[0010] The microcontroller is connected to the output buffer and is used to control the switching of the output signal or the output signal. The microcontroller has three outputs, one of which is connected to the output buffer to output a pulse signal. The other two outputs are connected to the enable terminal of the output buffer to control the switching of the microcontroller's output signal and the switching of forwarding the input second pulse signal, respectively.

[0011] The input buffer's input terminal is connected to the signal input terminal, and its output terminal is divided into two paths: one path connects to the microcontroller for detecting the second pulse signal, and the other path connects to the output buffer for forwarding and outputting the second pulse signal.

[0012] The input terminal of the output buffer is connected to the output terminal of the input buffer, and the output of the output buffer is connected to the signal output terminal.

[0013] According to one embodiment of this application, a pulse timing output controller is provided, wherein the pulse timing output controller further includes a power supply regulator.

[0014] According to one embodiment of this application, a pulse timing output controller is provided, wherein only two triggers are used on the signal path of the pulse timing output controller for signal buffering and driving.

[0015] According to one embodiment of this application, a pulse timing output controller is provided, wherein the microcontroller is connected to a network port for network communication and is capable of receiving instructions, configuration parameters, and time information sent by a host computer.

[0016] According to one embodiment of this application, a pulse timing output controller is provided, wherein the input buffer is a Schmitt trigger.

[0017] According to one embodiment of this application, a pulse timing output controller is provided, wherein the Schmitt trigger has electrostatic protection capability and serves as a signal buffer, level conversion, and anti-static function.

[0018] According to one embodiment of this application, a pulse timing output controller is provided, wherein the input buffer employs a high-speed comparator.

[0019] According to an embodiment of this application, a pulse timing output controller is provided, wherein the output buffer uses two tri-state flip-flops to control and drive the output signal. The enable terminals of the two tri-state flip-flops are both connected to a microcontroller, and their output terminals are connected in parallel to control the switching of the output signal.

[0020] According to one embodiment of this application, a pulse timing output controller is provided, wherein one output of the output buffer directly forwards the second pulse signal, and the other output is connected to a microcontroller, which controls the output time to compensate for delay.

[0021] According to an embodiment of this application, a pulse timing output controller is provided, wherein the pulse timing output controller is used to convert the second pulse signal output by the time base device into a synchronization trigger signal of the synchronization device, and to replace the synchronization device in accepting control from the host computer.

[0022] This application has the following advantages compared with the prior art:

[0023] (1) The pulse timing output controller of this application has low usage cost. The related time synchronization scheme does not require modification of the existing equipment's hardware and software, and utilizes the interfaces commonly found in general-purpose equipment to achieve high-precision time synchronization.

[0024] (2) The pulse timing output controller of this application can meet the requirements of high-precision time synchronization. The synchronization delay is within hundreds of nanoseconds, which is low. Moreover, the delay is stable, and there is the possibility of subsequent error compensation. Attached Figure Description

[0025] The following description, in conjunction with the accompanying drawings, will further illustrate the above-mentioned features, technical characteristics, advantages, and implementation methods of this application in a clear and understandable manner. The accompanying drawings are for illustrative and explanatory purposes only and do not limit the scope of this application. Wherein:

[0026] Figure 1 This is a system architecture diagram of the pulse timing output controller of this application;

[0027] Figure 2 This is the software control flowchart of this application;

[0028] Figure 3 This is a schematic diagram of the main control process of the software in this application. Detailed Implementation

[0029] To provide a clearer understanding of the technical features, objectives, and effects of this application, specific embodiments of this application will now be described with reference to the accompanying drawings.

[0030] Considering that when using frequency reference signals from devices such as rubidium clocks and navigation discipline clocks as reference clock inputs, the clocks of other devices within the system (hereinafter collectively referred to as synchronization devices) are consistent with the time base device. The time deviation between devices can meet the requirements for a period of time after synchronization. Therefore, in simulation systems with short running times, the system's time synchronization requirement can be reduced to only one time synchronization using a second pulse signal at startup, but the system can only run synchronously for a few minutes to tens of minutes.

[0031] The synchronization trigger interface commonly found on the device can be used to trigger the device startup, which is equivalent to performing a time synchronization. The aforementioned second pulse interface and reference clock interface are also common in their respective types of devices. Therefore, this method is universal.

[0032] This method also requires the addition of a signal controller. The main function of the controller is to convert the second pulse signal output by the time base device into a synchronization trigger signal for the synchronization device, and to replace the synchronization device in accepting control from the host computer.

[0033] This application provides a pulse timing output controller that meets the above-mentioned functional requirements. The pulse timing output controller has a signal output switch, which allows the pulse signal to be output to the backend only during a set time period. The pulse timing output controller has a pulse detection function, which can use an external second pulse as a time reference. It also has network communication capabilities, allowing control parameters to be configured via a network and is compatible with the network control protocol of a host computer.

[0034] The pulse timing output controller provided in this application mainly includes a microcontroller, an input buffer, and an output buffer.

[0035] Microcontrollers are used for system control, pulse detection, and network communication.

[0036] The microcontroller's internal timer enables pulse detection, which is used for time synchronization with high-precision time reference devices. Considering that even high-precision frequency synthesizers or high-stability crystal oscillators cannot achieve the time and frequency accuracy of devices like rubidium clocks, the microcontroller can use a low-cost passive crystal oscillator. The crystal oscillator's performance only needs to meet the requirements of network communication clocks.

[0037] The microcontroller has network communication capabilities. Because the controller mainly relies on the second pulse for time synchronization within seconds, the requirements for network communication latency are not high. A microcontroller with an integrated network controller and transceiver can be used, or a low-cost network control chip can be used.

[0038] The input buffer is used for signal buffering.

[0039] Signal buffering can prevent increased input conversion delays caused by signal strength weakening after transmission. Additionally, the input buffer has a certain signal driving capability to prevent insufficient driving capability when the output signal flows to both the microcontroller and the output buffer simultaneously. For short-distance transmission only, the commonly used Schmitt trigger is sufficient.

[0040] The output buffer is used to control and drive the output signal. The output buffer needs to have a switching function to control the output of the second pulse signal. Considering only the controller being near the synchronization device, a three-state trigger has a certain signal driving capability, which can meet the requirements. Furthermore, the output can be in a high-impedance state by controlling the enable terminal.

[0041] The key performance indicator for a pulse timing output controller is the forwarding delay. Using only two flip-flops in the signal path of the pulse timing output controller for signal buffering and driving reduces input-output switching delay. The input-output switching delay of the flip-flops is typically below 10ns, and the rise time width of the input signal is typically 10–50ns. The overall switching delay of the pulse timing output controller provided in this application is estimated to be within the hundreds of nanoseconds, which can meet the requirements of high-precision time synchronization. Using a high-speed comparator, such as the TLV3501, as the input flip-flop can further reduce the input delay, but additional design is required for level conversion, electrostatic discharge protection, and interference immunity.

[0042] The following is in conjunction with the appendix Figure 1 The system architecture diagram in the document further illustrates the technical solution of this application.

[0043] like Figure 1 As shown, a pulse timing output controller according to an embodiment of this application includes four parts: a microcontroller, an input buffer, an output buffer, and a power supply regulator.

[0044] See Figure 1 The microcontroller used in this system is the CH32V208. One of its features is its built-in network controller and transceiver, enabling network communication functionality on a single chip without the need for additional network interface chips. Another feature is its built-in oscillator load capacitor, requiring only connection to a 32MHz crystal oscillator and eliminating the need for additional load capacitors.

[0045] The microcontroller connects to the network port (RJ45 female connector) for network communication. It can receive commands, configuration parameters, time information, etc., sent by the host computer. The RJ45 female connector used is HR911105A, which has a built-in network isolation transformer, eliminating the need for an additional isolation transformer.

[0046] The microcontroller is connected to the input buffer to detect the second pulse. It can achieve sub-microsecond time synchronization and second counting functions.

[0047] The microcontroller is connected to the output buffer to control the switching of the output signal or to output the signal. One output is connected to the output buffer to output a pulse signal. Two other outputs are connected to the enable pins of the output buffer to control the switching of the microcontroller's output signal and the switching of forwarding the input second pulse signal, respectively.

[0048] See Figure 1The input buffer uses a Schmitt trigger SN74LVC1G17. Its maximum normal input level is 5.5V and it has electrostatic discharge (ESD) protection, serving as a signal buffer, level converter, and ESD protection mechanism. The trigger's input is connected to an SMA connector, and its output is split into two paths: one connected to a microcontroller for second pulse detection, and the other connected to an output buffer for forwarding the second pulse signal.

[0049] See Figure 1 The output buffer uses two tri-state flip-flops, SN74LVC1G125. The enable pins of both flip-flops are connected to the microcontroller, and their outputs are connected in parallel. Controlling the enable pins can shut down the outputs to a high-impedance state. One output of the output buffer can directly relay the second pulse signal with minimal delay; the other output is connected to the microcontroller, allowing the microcontroller to control the output time and compensate for delays.

[0050] See Figure 1 The medium voltage regulator circuit uses a linear regulator to convert an external 5V voltage to a 3.3V voltage.

[0051] The above describes the specific technical solution for this example. The prototype made according to this example features high functional integration, low cost, small size, and low power consumption. It uses only low-cost components, has a size of only 4.5cm × 3.5cm, and an operating current of only 26mA. The measured forwarding output delay of the prototype is 59ns, and the delay is stable.

[0052] The following is in conjunction with the appendix Figure 2 Appendix Figure 3 The software functionality implementation process of this example will be further explained.

[0053] It should be noted that the software function implementation process and signal detection method involved in the signal example are general techniques and methods used by those skilled in the art, and are not within the scope of protection of this application.

[0054] Figure 2 This is the software control flow of this application.

[0055] First, the time reference device and synchronization device are already operational. The time reference device stably outputs a reference clock (frequency reference signal) and a second pulse signal. The synchronization device locks onto the reference clock. The device is configured to start upon receiving an external synchronization trigger.

[0056] After powering on, the controller establishes a network connection with the host computer and receives configuration parameters sent by the host computer. These configuration parameters include the controller's operating mode settings, the current system time, and the output signal time. Upon receiving the start command, the controller enables its internal timer and begins detecting external second pulses. After detecting a second pulse, it synchronizes its time to the arrival time of the second pulse and starts counting seconds.

[0057] Figure 3 The main control process of the controller is described, including pulse detection and timing signal output. The pulse detection incorporates leaky pulse processing and glitch filtering. The controller operates in two modes: forwarding mode and timing output mode. Forwarding mode directly forwards the second pulse signal, resulting in a fixed delay in the controller's latency; timing output mode compensates for this fixed delay.

[0058] When operating in forwarding mode, the controller enables the forwarding output switch after the set time is reached. One second later, the second pulse passes through the controller's input and output buffers and is output to the backend synchronization device, triggering the synchronization device to start and achieving time synchronization with the time reference device.

[0059] It should be understood that although this specification is described according to various embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0060] The above description is merely an illustrative embodiment of this application and is not intended to limit the scope of this application. Any equivalent changes, modifications, and combinations made by those skilled in the art without departing from the concept and principles of this application shall fall within the scope of protection of this application.

Claims

1. A pulse timing output controller, characterized in that, The pulse timing output controller includes: The microcontroller has network communication capabilities and is used for system control, pulse detection, and network communication. The microcontroller has a built-in network controller, transceiver, and oscillator load capacitor. Input buffer, used for signal buffering, control and drive output signals; Output buffer, used to control and drive output signals. The microcontroller is connected to the input buffer and is used to detect the second pulse. The microcontroller is connected to the output buffer and is used to control the switching of the output signal or the output signal. The microcontroller has three outputs, one of which is connected to the output buffer to output a pulse signal. The other two outputs are connected to the enable terminal of the output buffer to control the switching of the microcontroller's output signal and the switching of forwarding the input second pulse signal, respectively. The input buffer's input terminal is connected to the signal input terminal, and its output terminal is divided into two paths: one path connects to the microcontroller for detecting the second pulse signal, and the other path connects to the output buffer for forwarding and outputting the second pulse signal. The input terminal of the output buffer is connected to the output terminal of the input buffer, and the output of the output buffer is connected to the signal output terminal.

2. The pulse timing output controller according to claim 1, characterized in that, The pulse timing output controller also includes a power regulator.

3. The pulse timing output controller according to claim 1, characterized in that, The pulse timing output controller uses only two triggers on its signal path for signal buffering and driving.

4. The pulse timing output controller according to claim 1, characterized in that, The microcontroller is connected to the network port for network communication and can receive instructions, configuration parameters, and time information sent by the host computer.

5. The pulse timing output controller according to claim 1, characterized in that, The input buffer is a Schmitt trigger.

6. The pulse timing output controller according to claim 5, characterized in that, The Schmitt trigger has electrostatic protection capabilities, serving as a signal buffer, level conversion, and anti-static agent.

7. The pulse timing output controller according to claim 1, characterized in that, The input buffer uses a high-speed comparator.

8. The pulse timing output controller according to claim 1, characterized in that, The output buffer uses two tri-state flip-flops to control and drive the output signal. The enable terminals of the two tri-state flip-flops are connected to the microcontroller, and their output terminals are connected in parallel to control the switching of the output signal.

9. The pulse timing output controller according to claim 1, characterized in that, One output of the output buffer directly forwards the second pulse signal, while the other output is connected to a microcontroller, which controls the output time and compensates for the delay.

10. The pulse timing output controller according to claim 1, characterized in that, The pulse timing output controller is used to convert the second pulse signal output by the time base device into a synchronous trigger signal of the synchronization device, and to replace the synchronization device in accepting control from the host computer.

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