A solid state drive

Abstract

The utility model discloses an embodiment relates to data storage technical field, especially, relate to a solid state disk, the solid state disk provided in an embodiment of the utility model, through adopting the storage particle of appropriate capacity storage error correction code, like this, reduce the capacity waste of storage particle, and the storage particle in multiple different storage arrays is connected to different clock line respectively, like this, through multiple clock controls the storage particle in multiple different storage arrays respectively, as far as possible ensure clock signal integrity and the stability of clock swing, thereby reduce the distortion of clock signal, ensure the reliability of storage particle operation.

Description

Technical Field

[0001] This utility model relates to the field of data storage technology, and in particular to a solid-state drive. Background Technology

[0002] In related technologies, solid-state drives (SSDs) use a "64-bit Data + 8-bit ECC" scheme to implement a 4KB mapped address table. The larger the platter capacity, the greater the required storage chip capacity. Larger capacity storage chips are more difficult to procure and more expensive, leading to high procurement costs and pressure. In single-rank, single-clock designs, when a 16-bit data width storage chip is paired with an 8-bit ECC, the 16-bit data width storage chip used to store the 8-bit ECC suffers from significant capacity waste, reducing storage resource utilization. Furthermore, the high clock load may pose stability risks to clock signal integrity and clock swing, affecting the reliability of the storage chip's operation. Utility Model Content

[0003] In view of this, one of the objectives of this utility model is to provide a solid-state drive (SSD) that aims to improve the situation in related technologies where there is wasted storage chip capacity and risks to the stability of clock signals and clock swing.

[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solutions: In a first aspect, embodiments of the present invention provide a solid-state drive, comprising: The circuit board has data lines, control lines, multiple clock lines, and multiple memory arrays, with the number of memory arrays being the same as the number of clock lines; The memory array includes at least one memory chip. The data bit width of the reference memory chip is the same as the data bit width of the error correction code. The reference memory chip is configured to store the error correction code. The memory chips of each memory array are communicatively connected to the same clock line, and the clock lines to which the memory chips of any two memory arrays are communicatively connected are different. All memory chips are communicatively connected to data lines and control lines. The control chip is mounted on the circuit board, and the data lines, control lines, and clock lines are all connected to the control chip for communication.

[0005] In some embodiments, at least two memory arrays are respectively disposed on a first side and a second side of the circuit board, and the difference between the number of memory arrays disposed on the first side and the number of memory arrays disposed on the second side is less than or equal to a preset number threshold.

[0006] In some embodiments, the number of storage arrays is two, and the two storage arrays are respectively disposed on the first side and the second side of the circuit board.

[0007] In some embodiments, the connection traces between the memory chips and the clock lines of the memory array adopt a fly-by topology routing method.

[0008] In some embodiments, the connection between the storage chips and the control lines of the storage array adopts a T-shaped topology routing method.

[0009] In some embodiments, the solid-state drive further includes a termination power supply, the output of which is electrically connected to a first end of a control line, and the second end of the control line is electrically connected to a control chip.

[0010] In some embodiments, the solid-state drive further includes a power input circuit, a first voltage release circuit, and a second voltage release circuit. The power input circuit is electrically connected to the first voltage release circuit and the second voltage release circuit, respectively, and the power input circuit, the first voltage release circuit, and the second voltage release circuit are electrically connected to the storage particles. The power input circuit is configured to output voltage to the storage chip to provide the required operating voltage to the storage chip; The first voltage release circuit is configured to release the residual first voltage in the power input circuit after the power input circuit stops supplying power to the storage chip; The second voltage release circuit is configured to release the residual second voltage in the power input circuit after the power input circuit stops supplying power to the storage chip.

[0011] In some embodiments, the first voltage release circuit includes a first MOSFET and a first resistor. The gate of the first MOSFET is connected to the voltage drive terminal of the power input circuit, the drain of the first MOSFET is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first output terminal of the power input circuit, and the source of the first MOSFET is grounded.

[0012] In some embodiments, the second voltage release circuit includes a second MOSFET and a second resistor. The gate of the second MOSFET is connected to the voltage drive terminal of the power input circuit, the drain of the second MOSFET is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the second output terminal of the power input circuit, and the source of the second MOSFET is grounded.

[0013] In some embodiments, the solid-state drive further includes an enable signal circuit, and the power input circuit includes a first voltage conversion chip, a second voltage conversion chip, a third resistor, a fourth resistor, a fifth resistor, and a transistor. The input terminal of the first voltage conversion chip is connected to the power supply, and the output terminal of the first voltage conversion chip is electrically connected to the second terminal of the first resistor and the storage chip, respectively, as the first output terminal. The input terminal of the second voltage conversion chip is connected to the power supply, and the output terminal of the second voltage conversion chip is electrically connected to the second terminal of the second resistor and the storage chip, respectively. The first end of the third resistor is connected to the power supply. The second end of the third resistor is connected as a voltage driving end to the collector of the transistor, the gate of the first MOSFET, and the gate of the second MOSFET. The base of the transistor and the first end of the fifth resistor are both connected to the first end of the fourth resistor. The second end of the fourth resistor is connected to the enable signal circuit. The second end of the fifth resistor and the emitter of the transistor are both grounded. The enable signal circuit is also connected to the signal input terminals of the first voltage conversion chip and the second voltage conversion chip respectively. The enable signal circuit is configured to output an enable signal to control the first voltage conversion chip and the second voltage conversion chip. The first voltage conversion chip is configured to convert the voltage output by the power supply to the first voltage required by the storage chip, and output the first voltage to the storage chip; The second voltage conversion chip is configured to convert the voltage output by the power supply to the second voltage required by the memory chip, and output the second voltage to the memory chip.

[0014] The present invention provides the following beneficial effects: The solid-state drive provided in this invention includes a circuit board and a control chip. The circuit board is provided with data lines, control lines, multiple clock lines, and multiple storage arrays. The number of storage arrays is the same as the number of clock lines. Each storage array includes at least one storage chip. The data bit width of the reference storage chip is the same as the data bit width of the error correction code. The reference storage chip is configured to store the error correction code. The storage chips of each storage array are communicatively connected to the same clock line, and the clock lines communicatively connected to the storage chips of any two storage arrays are different. All storage chips are communicatively connected to the data lines and control lines. The control chip is disposed on the circuit board, and the data lines, control lines, and clock lines are all communicatively connected to the control chip.

[0015] In the solid-state drive provided by this utility model embodiment, error correction codes are stored using storage chips of appropriate capacity, thereby reducing the waste of storage chip capacity. Furthermore, storage chips in multiple different storage arrays are connected to different clock lines, so that storage chips in multiple different storage arrays can be controlled by multiple clocks, ensuring the integrity of clock signals and the stability of clock swing as much as possible, thereby reducing clock signal distortion and ensuring the reliability of storage chip operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below only show some embodiments of this utility model and should not be considered as limiting the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a solid-state drive provided in some embodiments of this utility model; Figure 2 This is a structural schematic diagram of a solid-state drive provided in some other embodiments of the present invention; Figure 3 This is a schematic diagram of the structure of a solid-state drive provided in some embodiments of the present invention; Figure 4 This is a structural schematic diagram of a solid-state drive provided in some embodiments of the present invention; Figure 5 This is a structural schematic diagram of a solid-state drive provided in some embodiments of the present invention; Figure 6 This is a schematic diagram of the structure of some circuit modules in a solid-state drive provided in some embodiments of this utility model.

[0018] Explanation of reference numerals in the attached figures: 100. Solid State Drive (SSD); 110. Circuit board; 111. Data line; 112. Control line; 113. Clock line; 114. Memory array; 1141. Memory chip; 120. Control chip; 130. Connect to power supply; 140. Power input circuit; U1, first voltage conversion chip; U2, second voltage conversion chip; R3, third resistor; R4, fourth resistor; R5, fifth resistor; Q3, transistor; 150. First voltage release circuit; Q1. First MOSFET; R1. First resistor; 160. Second voltage release circuit; Q2. Second MOSFET; R2. Second resistor; 170. Enable signal circuit. Detailed Implementation

[0019] To provide a clearer understanding of the technical features, objectives, and effects of this utility model, the technical solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, not all of them. The detailed description of the embodiments of this utility model in the accompanying drawings is not intended to limit the scope of protection claimed by this utility model, but only to represent selected embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0020] It should be noted that when an element is referred to as being "fixed to" another element, it means that it can be directly attached to the other element or that an intervening element may be present. When an element is considered to be "connected to" another element, it can be directly connected to the other element or that an intervening element may be present simultaneously. The terms "vertical," "horizontal," "left," "right," "up," and "down," etc., used in this specification indicate orientation or position based on the orientation or position shown in the accompanying drawings.

[0021] It should be noted that the terms "first," "second," and other similar expressions used in this specification are for illustrative purposes and to distinguish between identical or similar items with substantially the same function and effect, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. "A plurality of" means two or more items, unless otherwise explicitly defined. It is worth noting that although functional modules are divided in the device or structural diagram, in some cases, a different module division may be used than that shown in the device or structure.

[0022] Unless otherwise defined, the technical and scientific terms used in this specification have the same meanings as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. It should be understood that the technical features involved in the various embodiments of the invention described below can be combined with each other, provided that no conflict is established.

[0023] Please see Figure 1 , Figure 1 The schematic diagram illustrates the structure of a solid-state drive provided in some embodiments of the present invention.

[0024] like Figure 1As shown, the solid-state drive 100 includes a circuit board 110 and a control chip 120. The control chip 120 is disposed on the circuit board 110. It should be understood that the control chip 120 can be disposed at any suitable position on the circuit board 110.

[0025] The circuit board 110 includes a data line 111, a control line 112, multiple clock lines 113, and multiple memory arrays 114, with the number of memory arrays 114 being the same as the number of clock lines 113.

[0026] Storage array 114 includes at least one storage chip 1141, for example Figure 1 As shown, the two storage arrays 114 respectively include Individual and There are 1141 storage particles. The reference storage particle in the storage array 114, used for storing error correction codes, has the same data bit width as the error correction code; that is, the reference storage particle is configured to store error correction codes. The error correction code is a check code that detects and corrects errors in data transmission or storage, such as an ECC code. The data bit width of the storage particles in the storage array 114, excluding the reference storage particle, can be any suitable value, and this embodiment of the invention does not impose any limitations on this.

[0027] In this configuration, each memory chip 1141 of the memory array 114 is communicatively connected to the same clock line 113, and the clock lines 113 for communication between any two memory chips 1141 of the memory array 114 are different. For example, see [link to relevant documentation]. Figure 1 As shown, one of the two storage arrays 114 Each memory chip 1141 is communicatively connected to the red clock line 123, and the other memory array 114 of the two memory arrays 114... Each memory chip 1141 is communicatively connected to the green clock line 123.

[0028] For example, data line 111, control line 112, and clock line 113 are all communicatively connected to control chip 120. Data line 111 is connected to the data interface of control chip 120, for example... Figure 1 As shown, data line 111 is connected to the data interface DQ of control chip 120, thereby realizing the communication connection between data line 111 and control chip 120. Control line 112 is connected to the control interface of control chip 120, for example... Figure 1 As shown, control line 112 is connected to the control interface CA of control chip 120, thereby realizing the communication connection between control line 112 and control chip 120. Each clock line 113 is connected to a clock interface in control chip 120, for example, see [reference needed]. Figure 1As shown, the red clock line 113 is connected to the clock interface CLK1 in the control chip 120, and the green clock line 113 is connected to the clock interface CLK2 in the control chip 120, thereby realizing the communication connection between the clock line 113 and the control chip 120.

[0029] In this configuration, all memory chips 1141 are communicatively connected to data lines 111 and control lines 112, enabling the control chip 120 to perform data transmission and instruction interaction with all memory chips 1141 via data lines 111 and control lines 112. Specifically, the clock lines 113 connecting the memory chips 1141 of any two memory arrays 114 to communicate are different, meaning that the memory chips 1141 in any two memory arrays 114 are connected to the control chip 120 via different clock lines 113.

[0030] In the solid-state drive provided by this utility model embodiment, error correction codes are stored using storage chips of appropriate capacity, thereby reducing the waste of storage chip capacity. Furthermore, storage chips in multiple different storage arrays are connected to different clock lines, so that storage chips in multiple different storage arrays can be controlled by multiple clocks, ensuring the integrity of clock signals and the stability of clock swing as much as possible, thereby reducing clock signal distortion and ensuring the reliability of storage chip operation.

[0031] Please see Figure 2 In some embodiments, at least two memory arrays 114 are respectively disposed on a first side and a second side of the circuit board 110. The difference between the number of memory arrays 114 disposed on the first side and the number of memory arrays 114 disposed on the second side is less than or equal to a preset threshold value; that is, the difference between the number of memory arrays 114 on the first side and the number of memory arrays 114 on the second side of the circuit board 110 is within the preset threshold value range. Understandably, engineers can set the preset threshold value according to actual needs and equipment characteristics. For example, the preset threshold value can be set to 2, so that the difference between the number of memory arrays 114 disposed on the first side and the second side of the circuit board 110 does not exceed 2.

[0032] It is understood that in some embodiments, the first side of the circuit board 110 is the T-side, and the second side of the circuit board 110 is the B-side. In other embodiments, the first side of the circuit board 110 is the B-side, and the second side of the circuit board 110 is the T-side.

[0033] In this embodiment, when there are many storage arrays 114, the storage arrays 114 are evenly arranged on both sides of the circuit board 110 in the above manner to ensure that the usable area of ​​the circuit board 110 is maximized and the weight of the circuit board 110 is more balanced, thus avoiding the excessive concentration of storage arrays 114 and the resulting reduction in the performance of the solid-state drive 100.

[0034] Please refer to it again. Figure 2 In some embodiments, there are two storage arrays 114, which are respectively disposed on the first and second sides of the circuit board 110. When two storage arrays 114 are included, distributing them on the first and second sides of the circuit board 110 makes the weight of the circuit board 110 more balanced, maximizes the use of the area of ​​the circuit board 110, and improves the performance of the solid-state drive 100.

[0035] Understandably, Figure 2 In the solid-state drive 100 shown, one of the two storage arrays 114 (hereinafter referred to as the first storage array) includes five storage chips 1141. The first storage array is disposed on the first side of the circuit board 110 and is communicatively connected to the clock interface CLK1 of the control chip 120 via clock line 113. The other storage array 114 (hereinafter referred to as the second storage array) includes four storage chips 1141. The second storage array is disposed on the second side of the circuit board 110 and is communicatively connected to the clock interface CLK2 of the control chip 120 via clock line 113.

[0036] Please refer to it again. Figure 2 In some embodiments, the connection traces between the memory chips 1141 of each memory array 114 and the clock line 113 adopt a fly-by topology routing method.

[0037] Fly-by topology is a special daisy-chain structure. Its core characteristic is that the path length from the signal source to each receiver is unequal, and the signal is transmitted sequentially rather than branching out simultaneously. In solid-state drive systems, the fly-by topology is mainly used to transmit clock signals, while the data lines (DQ) and data strobe signals (DQS) use a point-to-point connection. The routing of the fly-by topology allows the control chip 120 to send the clock signal sequentially to each memory chip 1141, rather than sending the clock signal to all memory chips 1141 simultaneously.

[0038] The application of the Fly-by topology in solid-state drive (SSD) systems follows strict specifications. First, the trunk line must remain continuous, with the clock signal output by the control chip 120 passing sequentially through each memory chip 1141. Second, the stub length must be extremely short, ideally zero, to minimize signal reflection. Third, trace lengths must be strictly controlled; the difference in trace length between memory chips 1141 must be within ±20 mils to ensure signal quality. Finally, the stub length of vias must be less than 120 mils to reduce the impact of capacitive loads on the signal.

[0039] In this embodiment, the Fly-by topology, through its extremely short or zero-length branch point design, significantly reduces signal reflection issues and improves signal quality. The Fly-by topology ensures that the clock signal arrives sequentially at each memory chip 1141, dispersing the switching timing and reducing synchronous switching noise peaks. The Fly-by topology increases wiring flexibility and scalability, making it more suitable for high-density memory chip 1141 designs, saving wiring space, simplifying the design process, and reducing design complexity. The Fly-by topology facilitates the configuration of Direct Quad Write Leveling (DQS). The control chip 120 compensates for differences in signal arrival time by adjusting the delay of the DQS signal, ensuring that each memory chip 1141 can correctly sample data. Because the clock signal arrives at each memory chip 1141 at different times, the solid-state drive system can dynamically adjust the phase of the DQS signal through write leveling, aligning the DQS signal with the clock signal and ensuring reliable data transmission.

[0040] Please see Figure 3 In some embodiments, the connection between the storage chip 1141 in each storage array 114 and the control line 112 adopts a T-shaped topology routing method.

[0041] It is understandable that when the connection between the memory chip 1141 and the clock line 113 of the memory array 114 adopts the Fly-by topology routing method, since the clock line 113 and the control line 112 need to meet the constraint of equal length, the routing length of the corresponding control line 112 can also be shortened, so that the routing length meets the specification constraint of less than 4 inches, and finally meets the conditions of equal length and routing length limit.

[0042] Understandably, Figure 3In the solid-state drive 100 shown, the first storage array and the second storage array of the two storage arrays 114 are respectively disposed on the first side and the second side of the circuit board 110, and the first storage array and the second storage array are connected to the control interface CA of the control chip 120 through the control line 112.

[0043] Please see Figure 4 or Figure 5 In some embodiments, the solid-state drive 100 further includes a terminating power supply 130 and a terminating resistor Rt. The output terminal of the terminating power supply 130 is electrically connected to the first terminal of the control line 112, that is, the output terminal of the terminating power supply 130 is connected to the first terminal of the terminating resistor Rt, and the second terminal of the terminating resistor Rt is electrically connected to the first terminal of the control line 112. The second terminal of the control line 112 is electrically connected to the control chip 120, that is, the second terminal of the control line 112 is electrically connected to the control interface CA of the control chip 120.

[0044] In this embodiment, the terminating resistor Rt is placed at the farthest end of the signal link. The terminating resistor Rt is a resistor with a resistance of 40-60Ω and is pulled up to the terminating power supply 130 (i.e., electrically connected to power supply VTT). The voltage of the terminating power supply 130 (i.e., power supply VTT) is 0.6V.

[0045] Understandably, when the signal propagates through control line 112 and reaches the end of the link, a suitable terminating resistor Rt matches the characteristic impedance of control line 112, ensuring continuous signal impedance. This allows the signal to be completely absorbed upon reaching the end of the link, reducing or preventing signal reflection back to the source (i.e., control chip 120), minimizing signal distortion, and avoiding ringing, overshoot, or undershoot, thus ensuring signal integrity and normal system operation. Furthermore, the terminating resistor Rt, pulled up to the terminating power supply 130, provides a stable reference level for the signal. When the signal reaches the end of the link, the pull-up resistor Rt to the terminating power supply 130 (i.e., power supply VTT) ensures a clear high-level state at the receiving end, preventing signal attenuation and other factors from causing incorrect signal level identification. It also helps reduce or avoid the impact of noise on the signal level, improving the signal's anti-interference capability and maintaining high signal quality during transmission.

[0046] Please refer to the following: Figure 4 and Figure 6 In some embodiments, the solid-state drive 100 further includes a power input circuit 140, a first voltage release circuit 150, and a second voltage release circuit 160. The power input circuit 140 is electrically connected to the first voltage release circuit 150 and the second voltage release circuit 160, respectively. The power input circuit 140, the first voltage release circuit 150, and the second voltage release circuit 160 are electrically connected to the storage chip 1141.

[0047] Specifically, the power input circuit 140 is configured to output voltage to the storage chip 1141 to provide the storage chip 1141 with the required operating voltage, i.e. Figure 6 The power input circuit 140 outputs a first voltage (e.g., 2.5V) as a first power supply VPP or outputs a second voltage (e.g., 1.2V) as a second power supply VDD to power the memory chip 1141.

[0048] When the power input circuit 140 is enabled for normal power supply, the first voltage release circuit 150 and the second voltage release circuit 160 are disconnected from the power input circuit 140 and do not participate in normal power supply.

[0049] The first voltage release circuit 150 is configured to release the residual first voltage in the power input circuit 140 after the power input circuit 140 stops supplying power to the storage chip 1141. When the storage array 114 in the solid-state drive 100 loses power, that is, after the power input circuit 140 stops supplying the first voltage to the storage chip 1141, the power input circuit 140 still retains the first voltage, which is released by the first voltage release circuit 150.

[0050] The second voltage release circuit 160 is configured to release the residual second voltage in the power input circuit 140 after the power input circuit 140 stops supplying power to the storage chip 1141. When the storage array 114 in the solid-state drive 100 loses power, that is, after the power input circuit 140 stops supplying the second voltage to the storage chip 1141, the power input circuit 140 still retains the second voltage, which is released by the second voltage release circuit 160.

[0051] Please refer to it again. Figure 6 In some embodiments, the first voltage release circuit 150 includes a first MOSFET Q1 and a first resistor R1. The gate G1 of the first MOSFET Q1 is connected to the voltage drive terminal of the power input circuit 140, the drain D1 of the first MOSFET Q1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first output terminal of the power input circuit 140, and the source S1 of the first MOSFET Q1 is grounded.

[0052] The second voltage release circuit 160 includes a second MOSFET Q2 and a second resistor R2. The gate G2 of the second MOSFET Q2 is connected to the voltage drive terminal of the power input circuit 140. The drain D2 of the second MOSFET Q2 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the second output terminal of the power input circuit 140. The source S2 of the second MOSFET Q2 is grounded.

[0053] In some embodiments, the solid-state drive 100 further includes an enable signal circuit 170, and the power input circuit 140 includes a first voltage conversion chip U1, a second voltage conversion chip U2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a transistor Q3.

[0054] In this embodiment, the input terminal of the first voltage conversion chip U1 is connected to the power supply, and the output terminal of the first voltage conversion chip U1, as the first output terminal, is electrically connected to the second terminal of the first resistor R1 and the storage chip 1141. The input terminal of the second voltage conversion chip U2 is connected to the power supply, and the output terminal of the second voltage conversion chip U2, as the second output terminal, is electrically connected to the second terminal of the second resistor R2 and the storage chip 1141.

[0055] In this circuit, the first end of the third resistor R3 is connected to the power supply, and the second end of the third resistor R3 serves as the voltage driving end, which is connected to the collector C of transistor Q3, the gate G1 of the first MOSFET Q1, and the gate G2 of the second MOSFET Q2. The base B of transistor Q3 and the first end of the fifth resistor R5 are both connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the enable signal circuit 170. The second end of the fifth resistor R5 and the emitter E of transistor Q3 are both grounded.

[0056] Specifically, the enable signal circuit 170 is also connected to the signal input terminal of the first voltage conversion chip U1 and the signal input terminal of the second voltage conversion chip U2, respectively. The enable signal circuit 170 is configured to output an enable signal to control the first voltage conversion chip U1 and the second voltage conversion chip U2.

[0057] Specifically, the first voltage conversion chip U1 is configured to convert the voltage output by the power supply to the first voltage required by the storage chip 1141, and output the first voltage to the storage chip 1141. The second voltage conversion chip U2 is configured to convert the voltage output by the power supply to the second voltage required by the storage chip 1141, and output the second voltage to the storage chip 1141.

[0058] When the enable signal circuit 170 outputs the first enable signal (i.e., EN=1), the power input circuit 140 normally supplies power to the storage chip 1141 of the solid-state drive 100. That is, the first voltage conversion chip U1 or the second voltage conversion chip U2 is enabled, i.e., the pin of the first voltage conversion chip U1 or the second voltage conversion chip U2 is pulled high, thus supplying power to the storage chip 1141 of the solid-state drive 100. Figure 6 The voltage (e.g., 12V) output by the power supply VBUS shown is converted into a first voltage (e.g., 2.5V) or a second voltage (e.g., 1.2V) required by the storage chip 1141, and the first voltage or the second voltage is output to the storage chip 1141.

[0059] While the first voltage conversion chip U1 or the second voltage conversion chip U2 is enabled to supply power to the storage chip 1141, the two "residual voltage release" transistors, the first MOSFET Q1 and the second MOSFET Q2, are kept off and do not discharge. That is, the first enable signal drives the fourth resistor R4 to supply power to the base B of the NPN transistor Q3, turning on the NPN transistor Q3. The third resistor R3 clamps the gate node down to 0.1 to 0.2V (near ground). Since the gate G1 of the first MOSFET Q1 or the gate G2 of the second MOSFET is close to 0V, the gate-source voltage Vgs of the first MOSFET Q1 / second MOSFET Q2 is close to 0V. The first MOSFET Q1 / second MOSFET Q2 are turned off, the outputs of the first voltage conversion chip U1 / second voltage conversion chip U2 are not shorted to ground, and the power input circuit 140 is powered normally.

[0060] When the enable signal circuit 170 outputs the second enable signal (i.e., EN=0), the power input circuit 140 stops supplying power to the storage chip 1141 of the solid-state drive 100. That is, the first voltage conversion chip U1 or the second voltage conversion chip U2 is enabled and stops working, thus stopping the output. There is still residual voltage on the power supply VBUS, that is, the first voltage VPP or the second voltage VDD does not immediately drop to 0V. When the base B of NPN transistor Q3 is pulled low, NPN transistor Q3 enters the cutoff / turn-off state. The third resistor R3 pulls the gate node to the power supply VBUS. At this time, the gate G1 of the first MOSFET Q1 or the gate G2 of the second MOSFET Q2 is pulled up (relatively high to ground). The gate-source voltage Vgs of the first MOSFET Q1 or the gate-source voltage Vgs of the second MOSFET Q2 meets the turn-on voltage condition, so the first MOSFET Q1 or the second MOSFET Q2 is turned on. Thus, the first power supply VPP / first voltage VPP or the second power supply VDD / second voltage VDD is released to ground by the first MOSFET Q1 and the first resistor R1 or the second MOSFET Q2 and the second resistor R2, thereby releasing the residual charge on the output of the power supply VBUS. During the discharge process, when the capacitor of the first voltage VPP / second voltage VDD is discharged, or when the first voltage VPP / second voltage VDD approaches ground, the drain-source voltage Vds of the first MOSFET Q1 / second MOSFET Q2 decreases, resulting in insufficient gate-source Vgs and shutdown. The voltage of the power supply VBUS also decreases. Finally, the gate node and the source of the first MOSFET Q1 / second MOSFET Q2 return to low level, and the discharge ends.

[0061] The first end of the third resistor R3 is connected to the power supply VBUS, and the second end of the third resistor R3 is connected to the "gated node". The gated node serves as the voltage drive terminal (or common node) of the power input circuit 140 and is connected to the gate G1 of the first MOSFET Q1 and the gate G2 of the second MOSFET Q2. The third resistor R3 is configured to pull the gated node up to the power supply VBUS and limit the pull-up current.

[0062] In this configuration, the collector C of the NPN transistor Q3 is connected to the gate node. The base B of the NPN transistor Q3 is driven by the enable signal circuit 170 through the fourth resistor R4, and is pulled down to ground through the fifth resistor R5. The emitter E of the NPN transistor Q3 is grounded. Therefore, the function of the NPN transistor Q3 is to act as a low-impedance pull-down switch for the gates of the first MOSFET Q1 and the second MOSFET Q2. When the NPN transistor Q3 is turned on (power-on EN=1), it clamps the gate node down to near 0V, making the gate G1 of the first MOSFET Q1 or the gate G2 of the second MOSFET Q2 0V. When the NPN transistor Q3 is turned off (power-off EN=0), the third resistor R3 pulls up the gate G1 of the first MOSFET Q1 or the gate G2 of the second MOSFET Q2 to the level of the power supply VBUS.

[0063] When powered on normally (EN=1), the first voltage conversion chip U1 is enabled and outputs the first voltage VPP. The NPN transistor Q3 is turned on, pulling the gate node low. The gate G1 of the first MOSFET Q1 is close to 0V (low level). Therefore, the first MOSFET Q1 is turned off and will not directly short the first voltage VPP / first power supply VPP to ground. The first voltage conversion chip U1 normally outputs the first voltage VPP to power the memory chip 1141.

[0064] When power is lost (EN=0), the EN pin of the first voltage conversion chip U1 is disabled, the output of the first voltage conversion chip U1 is floating / has residual voltage, the NPN transistor Q3 is cut off / turned off, and the third resistor R3 pulls the gate G1 of the first MOSFET Q1 to the level of the power supply VBUS (high level). The gate-source voltage Vgs of the first MOSFET Q1 increases (positive relative to ground), the first MOSFET Q1 turns on, and the residual charge of the first voltage VPP / first power supply VPP is released to ground through the first MOSFET Q1. The first resistor R1 acts as a current limiter / damper, limiting the discharge current and reducing transient interference. That is, the first resistor R1 is used as a current limiter / voltage reducer to reduce the instantaneous current of the first MOSFET Q1 during conduction and suppress ringing, while ensuring that the maximum gate-source voltage Vgs_max and power consumption of the first MOSFET Q1 can withstand the discharge current allowed by the first resistor R1.

[0065] When powered on normally (EN=1), the second voltage conversion chip U2 is enabled to output the second voltage VDD. The NPN transistor Q3 is turned on, pulling the gate node low. The gate G2 of the second MOSFET Q2 is close to 0V (low level). Therefore, the second MOSFET Q2 is turned off, and the second voltage VDD / second power supply VDD will not be directly shorted to ground. The second voltage conversion chip U2 normally outputs the second voltage VDD to power the memory chip 1141.

[0066] When power is lost (EN=0), the EN pin of the second voltage conversion chip U2 is disabled, the output of the second voltage conversion chip U2 is floating / has residual voltage, the NPN transistor Q3 is cut off / turned off, and the third resistor R3 pulls the gate G2 of the second MOSFET Q2 to the level of the power supply VBUS (high level). The gate-source voltage Vgs of the second MOSFET Q2 increases (positive relative to ground), and the second MOSFET Q2 turns on. The residual charge of the second voltage VDD / second power supply VDD is released to ground through the second MOSFET Q2. The second resistor R2 acts as a current limiter / damper, limiting the discharge current and reducing transient interference. That is, the second resistor R2 is used as a current limiter / voltage reducer to reduce the instantaneous current of the second MOSFET Q2 during conduction and suppress ringing, while ensuring that the maximum gate-source voltage Vgs_max and power consumption of the second MOSFET Q2 can withstand the discharge current allowed by the second resistor R2.

[0067] The enable signal circuit 170 is used to generate and output an enable signal, which is transmitted to the signal pins of the first voltage conversion chip U1 and the second voltage conversion chip U2. At the same time, the base B of the NPN transistor Q3 is driven through the fourth resistor R4, and the base B is pulled down by the fifth resistor R5.

[0068] The enable signal circuit 170 outputs a first enable signal (EN=high, logic 1) to enable the first voltage conversion chip U1 or the second voltage conversion chip U2, and provides bias current to the base B of the NPN transistor Q3 through the fourth resistor R4, so that the NPN transistor Q3 is turned on, thereby pulling the gate node low and keeping the first MOSFET Q1 / second MOSFET Q2 off.

[0069] Specifically, the enable signal circuit 170 outputs a second enable signal (EN=low, logic 0), which disables the first voltage conversion chip U1 or the second voltage conversion chip U2. The fifth resistor R5 pulls the base B of the NPN transistor Q3 low, causing the NPN transistor Q3 to be cut off / turned off. The third resistor R3 pulls the gate G1 of the first MOSFET Q1 or the gate G2 of the second MOSFET Q2 up to the power supply VBUS, triggering the conduction of the first MOSFET Q1 or the second MOSFET Q2.

[0070] In summary, the solid-state drive provided by this utility model uses storage chips of appropriate capacity to store error correction codes, thereby reducing the waste of storage chip capacity. Furthermore, storage chips in multiple different storage arrays are connected to different clock lines, so that storage chips in multiple different storage arrays can be controlled by multiple clocks, ensuring the integrity of clock signals and the stability of clock swing as much as possible, thereby reducing clock signal distortion and ensuring the reliability of storage chip operation.

[0071] Those skilled in the art will understand that the above-mentioned technical features can be used in any combination without limitation. The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to more clearly understand the technical features, purpose and effects of this utility model and implement it accordingly. They should not be construed as limiting the scope of protection of this utility model. Any equivalent structural or procedural transformations made based on the content of this utility model specification and drawings, or direct or indirect applications in other related technical fields, should also be included within the scope of protection of the claims of this utility model.

Claims

1. A solid-state drive, characterized in that, include: The circuit board includes data lines, control lines, multiple clock lines, and multiple memory arrays, wherein the number of memory arrays is the same as the number of clock lines. The storage array includes at least one storage particle. The data bit width of the reference storage particle is the same as the data bit width of the error correction code. The reference storage particle is configured to store the error correction code. Each storage particle in the storage array is communicatively connected to the same clock line, and the clock lines communicatively connected to any two storage particles in the storage array are different. All storage particles are communicatively connected to the data line and the control line. A control chip is mounted on the circuit board, and the data line, the control line, and the clock line are all communicatively connected to the control chip.

2. The solid-state drive according to claim 1, characterized in that, At least two of the storage arrays are respectively disposed on the first side and the second side of the circuit board, and the difference between the number of storage arrays disposed on the first side and the number of storage arrays disposed on the second side is less than or equal to a preset number threshold.

3. The solid-state drive according to claim 2, characterized in that, The number of storage arrays is two, and the two storage arrays are respectively disposed on the first side and the second side of the circuit board.

4. The solid-state drive according to any one of claims 1-3, characterized in that, The connection between the memory chips in the memory array and the clock line adopts a fly-by topology routing method.

5. The solid-state drive according to any one of claims 1-3, characterized in that, The connection between the storage chips in the storage array and the control lines adopts a T-shaped topology routing method.

6. The solid-state drive according to any one of claims 1-3, characterized in that, The solid-state drive also includes a termination power supply, the output terminal of which is electrically connected to the first end of the control line, and the second end of the control line is electrically connected to the control chip.

7. The solid-state drive according to any one of claims 1-3, characterized in that, The solid-state drive further includes a power input circuit, a first voltage release circuit, and a second voltage release circuit. The power input circuit is electrically connected to the first voltage release circuit and the second voltage release circuit, respectively. The power input circuit, the first voltage release circuit, and the second voltage release circuit are electrically connected to the storage particles. The power input circuit is configured to output voltage to the storage chip to provide the storage chip with the required operating voltage. The first voltage release circuit is configured to release the residual first voltage in the power input circuit after the power input circuit stops supplying power to the storage chip; The second voltage release circuit is configured to release the residual second voltage in the power input circuit after the power input circuit stops supplying power to the storage chip.

8. The solid-state drive according to claim 7, characterized in that, The first voltage release circuit includes a first MOSFET and a first resistor. The gate of the first MOSFET is connected to the voltage drive terminal of the power input circuit, the drain of the first MOSFET is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the first output terminal of the power input circuit, and the source of the first MOSFET is grounded.

9. The solid-state drive according to claim 8, characterized in that, The second voltage release circuit includes a second MOSFET and a second resistor. The gate of the second MOSFET is connected to the voltage drive terminal of the power input circuit, the drain of the second MOSFET is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the second output terminal of the power input circuit, and the source of the second MOSFET is grounded.

10. The solid-state drive according to claim 9, characterized in that, The solid-state drive also includes an enable signal circuit, and the power input circuit includes a first voltage conversion chip, a second voltage conversion chip, a third resistor, a fourth resistor, a fifth resistor, and a transistor. The input terminal of the first voltage conversion chip is connected to the power supply, and the output terminal of the first voltage conversion chip is electrically connected to the second terminal of the first resistor and the storage chip, respectively, as the first output terminal. The input terminal of the second voltage conversion chip is connected to the power supply, and the output terminal of the second voltage conversion chip is electrically connected to the second terminal of the second resistor and the storage chip, respectively, as the second output terminal. The first end of the third resistor is connected to the power supply, and the second end of the third resistor serves as the voltage driving end, connected to the collector of the transistor, the gate of the first MOSFET, and the gate of the second MOSFET respectively. The base of the transistor and the first end of the fifth resistor are both connected to the first end of the fourth resistor. The second end of the fourth resistor is connected to the enable signal circuit. The second end of the fifth resistor and the emitter of the transistor are both grounded. The enable signal circuit is also connected to the signal input terminal of the first voltage conversion chip and the signal input terminal of the second voltage conversion chip respectively. The enable signal circuit is configured to output an enable signal to control the first voltage conversion chip and the second voltage conversion chip. The first voltage conversion chip is configured to convert the voltage output by the power supply to a first voltage required by the memory chip, and output the first voltage to the memory chip; The second voltage conversion chip is configured to convert the voltage output by the power supply to a second voltage required by the memory chip, and output the second voltage to the memory chip.

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