STRUCTURE AND FORMATION METHOD FOR FIN-TYPE FIELD EFFECT TRANSISTOR

Abstract

Semiconductor device structure, comprising: a semiconductor carrier layer (100); a fin structure (102N, 102P) over the semiconductor carrier layer (100); a gate stack (104N, 104P) covering a section of the fin structure (102N, 102P); an epitaxially grown source / drain structure (116N, 126P) above the fin structure (102N, 102P) and next to the gate stack (104N, 104P); and a semiconductor protective layer (118, 128) over the epitaxially grown source / drain structure (116N, 126P) to protect the epitaxially grown source / drain structure (116N, 126P) from damage by etching and / or cleaning processes, wherein the semiconductor protective layer (118, 128) has an atomic carbon concentration that is higher than that of the epitaxially grown source / drain structure (116N, 126P), wherein the atomic carbon concentration in the semiconductor protective layer (118, 128) gradually decreases along a direction from a surface of the semiconductor protective layer (118, 128) towards the epitaxially grown source / drain structure (116N, 126P).

Description

BACKGROUND

[0001] The integrated semiconductor (IC) industry is experiencing rapid growth. Ongoing advances in semiconductor manufacturing processes have led to semiconductor devices with finer elements and / or higher levels of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased, while element size (i.e., the smallest component that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs.

[0002] Despite groundbreaking advances in materials and manufacturing, scaling up planar devices, such as the metal-oxide-semiconductor field-effect transistor (MOSFET), has proven challenging. To overcome these challenges, circuit designers are seeking novel structures to achieve improved performance, leading to the development of three-dimensional designs, such as fin-like field-effect transistors (FinFETs). The FinFET is fabricated with a thin vertical "ridge" (or fin structure) extending upward from a substrate layer. The FinFET's channel is formed within this vertical ridge. A gate is positioned above the ridge, allowing the gate to control the channel from multiple sides. Advantages of the FinFET include reduced short-channel effect, decreased leakage, and higher current flow.

[0003] However, as element sizes constantly decrease, manufacturing processes become increasingly difficult to execute. Therefore, creating a reliable semiconductor device containing the FinFET is a challenge.

[0004] The prior art relevant to the present invention is given by DE 11 2005 000 704 B4 and US 2006 / 0 065 927 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood from the following detailed description in conjunction with the accompanying figures. It should be noted that, according to standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be enlarged or reduced arbitrarily for the sake of clarity. Fig. Figures 1A-1F are perspective views of different stages of a process for forming a semiconductor device according to some embodiments. Fig. Figures 2A-9A are cross-sectional views of various stages of a process for forming a semiconductor device according to some embodiments. Fig. Figures 2B-9B are cross-sectional views of various stages of a process for forming a semiconductor device according to some embodiments. Fig. Figure 10 is a cross-sectional view of a process chamber according to some embodiments. Fig. Figure 11 is a cross-sectional view of a stage of a process for forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are subsequently described to simplify the present disclosure. These are, of course, only examples and are not intended as limitations. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features cannot be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself establish a relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatial terms such as "below," "under," "lower," "above," and "upper," and the like, can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatial terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptions used here can be interpreted accordingly.

[0008] Several embodiments of the revelation are described. Fig. Figures 1A-1F are perspective views of various stages of a process for forming a semiconductor device according to some embodiments. Additional processes may be shown before, during, and / or after the stages shown. Fig. Stages 1A-1F described should be provided. Fig. Figures 2A-9A are cross-sectional views of various stages of a process for forming a semiconductor device according to some embodiments. For example, Fig. 2A-9A Cross-sectional views along line AA in Fig. 1A-1F. Fig. Figures 2B-9B are cross-sectional views of various stages of a process for forming a semiconductor device according to some embodiments. For example, Fig. 2B-9B Cross-sectional views along line BB in Fig. 1A-1F. Some of the described stages may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor device. Some of the features described below may be replaced or eliminated for different embodiments.

[0009] As in Fig. 1A, Fig. 2A and Fig. As shown in Figure 2B, a semiconductor support layer 100 is provided. In some embodiments, the semiconductor support layer 100 is a bulk semiconductor support layer. The bulk semiconductor support layer can be a semiconductor wafer such as a silicon wafer. In some embodiments, the semiconductor support layer 100 contains an elemental semiconductor material such as silicon or other elemental semiconductor materials such as germanium. In some other embodiments, the semiconductor support layer 100 contains a compound semiconductor. The compound semiconductor can be silicon carbide, gallium arsenide, indium arsenide, indium phosphide, another suitable compound semiconductor, or a combination thereof.

[0010] In some embodiments, the semiconductor support layer 100 is a semiconductor-on-insulator (SOI) support layer. The SOI support layer can be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof.

[0011] In some embodiments, the semiconductor substrate layer contains 100 different doped regions (not shown), depending on the design requirements of the semiconductor device. The doped regions include, for example, p-type and / or n-type wells. In some embodiments, the doped regions are doped with p-type dopants. For example, the doped regions are doped with boron or BF₂. In some embodiments, the doped regions are doped with n-type dopants. For example, the doped regions are doped with phosphorus or arsenic. In some embodiments, some of the doped regions are p-type and the other doped regions are n-type.

[0012] Subsequently, one or more fin structures are formed above the semiconductor carrier layer 100. As in Fig. 1A, Fig. 2A and Fig. As shown in Figure 2B, fin structures 102N1, 102N2, 102P1, and 102P2 are formed according to some embodiments. In some embodiments, the fin structures 102N1, 102N2, 102P1, and 102P2 are formed by etching into the semiconductor substrate layer 100. The semiconductor substrate layer 100 is partially removed to form depressions (or grooves). A photolithography process and an etching process can be used to form the depressions. This results in the fin structures 102N1, 102N2, 102P1, and 102P2 being formed between the depressions.

[0013] As in Fig. 1A, Fig. 2A and Fig. As shown in Figure 2B, according to some embodiments, one or more insulating features are formed above the semiconductor substrate layer 100. The insulating features 103 are used to define or electrically insulate various device elements formed in and / or above the semiconductor substrate layer 100. In some embodiments, the insulating features 103 surround lower sections of the fin structures 102N1, 102N2, 102P1, and 102P2. Upper sections of the fin structures 102N1, 102N2, 102P1, and 102P2 project from the upper surfaces of the insulating features 103.

[0014] In some embodiments, the insulating features 103 include shallow trench insulation (STI) features, local oxidation of silicon (LOCOS) features, other suitable insulating features, or a combination thereof. In some embodiments, each of the insulating features 103 has a multilayer structure. In some embodiments, the insulating features 103 consist of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (PDG), a low-dielectric material, other suitable materials, or a combination thereof. In some embodiments, an STI lining (not shown) is formed to reduce crystalline defects at the interface between the semiconductor substrate layer 100 and the insulating features 103.

[0015] In some embodiments, a dielectric material layer is deposited over the semiconductor support layer 100. The dielectric material layer covers the fin structures 102N1, 102N2, 102P1, and 102P2. In some embodiments, the dielectric material layer is formed using a chemical vapor deposition (CVD) process, a spin deposition process, another applicable process, or a combination thereof. In some embodiments, a planarization process, such as a chemical-mechanical polishing (CMP) process, is performed to thin the dielectric material layer until the fin structures 102N1, 102N2, 102P1, and 102P2 are exposed. An etching process is then carried out to remove an upper part of the dielectric material layer, so that the fin structures 102N1, 102N2, 102P1 and 102P2 protrude from the remaining dielectric material layer.As a result, the isolation features 103 are formed. This also allows the fin structures 102N1, 102N2, 102P1 and 102P2 to be selectively processed in subsequent operations.

[0016] As in Fig. 1A, Fig. 2A and Fig. As shown in Figure 2B, according to some embodiments, one or more gate stacks are formed above the semiconductor support layer 100 and the fin structures. For example, gate stacks 104N and 104P are formed. Each of the gate stacks 104N and 104P contains, according to some embodiments, a gate dielectric layer 106 and a gate electrode 108. In some embodiments, each of the gate stacks 104N and 104P contains a hard mask 110. The hard mask 110 is used to support the formation of the gate stacks 104N and 104P. In some embodiments, the hard mask 110 consists of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. In some embodiments, the hard mask 110 has a multilayer structure.

[0017] In some embodiments, the gate dielectric layer 106 consists of silicon oxide, silicon nitride, silicon oxynitride, a high dielectric material (high K-number), another suitable dielectric material, or a combination thereof. Examples of high dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer 106 is a dummy gate dielectric layer that is removed in a subsequent process. The dummy gate dielectric layer is, for example, a silicon oxide layer.

[0018] In some embodiments, the gate electrode 108 contains polysilicon, a metallic material, another suitable conductive material, or a combination thereof. In some embodiments, the gate electrode is a dummy gate electrode layer and is replaced by another conductive material, such as a metallic material. The dummy gate electrode layer consists, for example, of polysilicon.

[0019] In some embodiments, a gate dielectric material and a gate electrode layer are deposited over the semiconductor support layer 100 and the fin structures 102N1, 102N2, 102P1, and 102P2. In some embodiments, the gate dielectric material and the gate electrode layer are deposited sequentially using suitable deposition methods. The suitable deposition methods include a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof. Subsequently, the gate dielectric material and the gate electrode layer are structured using the hard mask 110 to form the gate stacks, which contain the gate dielectric layer 106 and the gate electrode 108.

[0020] As in Fig. 1B, Fig. 3a and Fig. As shown in Figure 3B, according to some embodiments, a mask layer 113 is formed over the gate stack 104B and the fin structures 102P1 and 102P2. Therefore, the gate stack 104B and the fin structures 102P1 and 102P2 are blocked and protected from adverse effects during subsequent processes performed on the fin structures 102N1 and 102N2. In some embodiments, the mask layer 113 consists of a dielectric material. The dielectric material can be silicon nitride, silicon oxynitride, silicon carbide, another suitable dielectric material, or a combination thereof.

[0021] In some embodiments, a mask material layer is deposited over the semiconductor support layer 100, the fin structures 102N1, 102N2, 102P1, and 102P2, and the gate stacks 104N and 104P. The mask material layer can be deposited using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a spin deposition process, another applicable process, or a combination thereof. Subsequently, the mask material layer is partially removed using a photolithography and an etching process. For example, a structured photoresist layer (not shown) is formed on the mask material layer. The portion of the mask material layer not covered by the photoresist layer is etched, thereby forming the mask layer 113.

[0022] As in Fig. 1B and Fig. As shown in Figure 3A, spacer elements 112A are formed across the side walls of the gate stack 104N according to some embodiments. The spacer elements 112A can be used in subsequent processes to assist in the formation of source and drain structures (or regions). In some embodiments, the spacer elements consist of silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

[0023] In some embodiments, a spacer layer is deposited over the semiconductor substrate layer 100, the fin structures 102N1, 102N2, 102P1, and 102P2, and the gate stacks 104N and 104P. The spacer layer can be deposited using a CVD process, a PVD process, a spin deposition process, another applicable process, or a combination thereof. Subsequently, an etching process, such as an anisotropic etching process, is performed to partially remove the spacer layer. As a result, the remaining portions of the spacer layer over the sidewalls of the gate stack 104N form the spacer elements 112A.

[0024] As in Fig. 3A and Fig. As shown in Figure 3B, support elements 112B are formed over the side walls of the fin structures 102N1 and 102N2 according to some embodiments. The support elements 112B can be used to support the growth of source and drain structures (or regions). In some embodiments, the support elements consist of silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof.

[0025] In some embodiments, a material layer is deposited over the semiconductor substrate layer 100, the fin structures 102N1, 102N2, 102P1 and 102P2, and the gate stacks 104N and 104P. The material layer can be deposited using a CVD process, a PVD process, a spin deposition process, another applicable process, or a combination thereof. Subsequently, an etching process, such as an anisotropic etching process, is performed to partially remove the material layer. As a result, the remaining portions of the material layer over the sidewalls of the fin structures 102N1 and 102N2 form the support elements 112B.

[0026] In some embodiments, the mask layer 113, the spacer elements 112A, and the support elements 112B are sections of the same dielectric layer. In some embodiments, a dielectric layer is deposited over the semiconductor substrate layer 100, the fin structures 102N1, 102N2, 102P1, and 102P2, and the gate stacks 104N and 104P. In some embodiments, the dielectric layer is deposited by a CVD process, a PVD process, a spin-deposition process, another applicable process, or a combination thereof. In some embodiments, the dielectric layer comprises several sublayers.

[0027] A structured photoresist layer (not shown) is then formed over the portion of the dielectric layer on the gate stack 104P and the fin structures 102P1 and 102P2. An anisotropic etching process is then performed to back-etch the portion of the dielectric layer not covered by the photoresist. As a result, the remaining portions of the dielectric layer over the side walls of the gate stack 104N form the spacer elements 112A. The remaining portions of the dielectric layer over the side walls of the fin structures 102N1 and 102N2 form the support elements 112B. The remaining portion of the dielectric layer under the photoresist layer forms the mask layer 113. In these cases, the spacer elements 112A, the support elements 112B, and the mask layer 113 are made of the same material.In some embodiments, the photoresist layer is removed after the formation of the spacer elements 112A and the support elements 112B.

[0028] The embodiments of the disclosure have many variations and are not limited to the embodiments listed above. In some embodiments, the spacer elements 112A are not formed. In some other embodiments, the support elements 112B are not formed. In some other embodiments, neither spacer elements 112A nor support elements 112B are formed.

[0029] As in Fig. 1B, Fig. 4A and Fig. As shown in Figure 4B, according to some embodiments, a section of the fin structures 102N1 and 102N2 is removed to reduce the height of the fin structures 102N1 and 102N2 and to form depressions 114. During the formation of depressions in the fin structures 102N1 and 102N2, the fin structures 102P1 and 102P2 are blocked or protected by the mask layer 113. Therefore, damage to the fin structures 102P1 and 102P2 is prevented.

[0030] In some embodiments, recesses are formed in the fin structures 102N1 and 102N2 down to a level below the top surfaces of the support elements 112B. In some embodiments, recesses are formed in the fin structures 102N1 and 102N2 down to a level below the upper surfaces of the insulating features 103. In some embodiments, an etching process is used to form the recesses 114. However, it should be clear that embodiments of the disclosure have many variations. In some other embodiments, the fin structures 102N1 and 102N2 are not partially removed to form the recesses 114.

[0031] As in Fig. 1C, Fig. 5A and Fig. As shown in Figure 5B, source / drain structures 116N1 and 116N2 are formed over the fin structures 102N1 and 102N2, respectively, according to some embodiments. In some embodiments, a semiconductor material is grown epitaxially in the wells 114 and continues to grow beyond the wells 114 to form the source / drain structures 116N1 and 116N2. The support elements 112B can serve as a template to control the growth of the source / drain structures 116N1 and 116N2. As shown in Fig. 1C, Fig. 5A and Fig. As shown in Figure 5B, the support elements 112B cover lower sections of the source / drain structures 116N1 and 116N2. In some embodiments, the support elements 112B are in direct contact with the source / drain structures 116N1 and 116N2.

[0032] During the growth of the source / drain structures 116N1 and 116N2, the fin structures 102P1 and 102P2 are blocked or protected by the mask layer 113. Therefore, the growth of the semiconductor material on the fin structures 102P1 and 102P2 is prevented.

[0033] In some embodiments, the source / drain structures 116N1 and 116N2 project beyond the support elements 112B. The source / drain structures 116N1 and 116N2 can also be referred to as raised source and drain features. In some embodiments, the source / drain structures 116N1 and 116N2 are stressed structures. The source / drain structures 116N1 and 116N2 impart stress or load to the channel region below the gate stack 104N to enhance the support mobility of the device and improve its performance.

[0034] In some embodiments, the source / drain structures 116N1 and 116N2 are an n-type semiconductor material. The source / drain structures 116N1 and 116N2 can contain expitaxially grown silicon, expitaxially grown silicon phosphide (SIP), or another suitable expitaxially grown semiconductor material. The source / drain structures 116N1 and 116N2 are not limited to an n-type semiconductor material. In some other embodiments, the source / drain structures 116N1 and 116N2 are a p-type semiconductor material. For example, the structures 116N1 and 116N2 can contain expitaxially grown silicon germanium.

[0035] In some embodiments, the source / drain structures 116N1 and 116N2 are formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum (UHV) CVD process), a molecular beam epitaxy process, another applicable process, or a combination thereof. The formation process of the source / drain structures 116N1 and 116N2 can utilize gaseous and / or liquid precursors that can interact with the composition of the underlying fin structures 102N2 and 102N1.

[0036] In some embodiments, the source / drain structures 116N1 and 116N2 are doped with one or more suitable dopants. For example, the source / drain structures 116N1 and 116N2 are Si source / drain features doped with phosphorus (P), antimony (Sb), or another suitable dopant. Alternatively, the source / drain structures 116N1 and 116N2 are SiGe source / drain features doped with boron (B) or another suitable dopant.

[0037] In some embodiments, the source / drain structures 116N1 and 116N2 are doped in situ during their growth. In other embodiments, they are not doped during this process. After the formation of the source / drain structures 116N1 and 116N2, they are doped in a subsequent process. In some embodiments, the doping is achieved by an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, another applicable process, or a combination thereof. In some embodiments, the source / drain structures 116N1 and 116N2 are further subjected to annealing steps to activate the dopants. For example, a rapid thermal annealing process is performed.

[0038] As in Fig. 1C, Fig. 6A and Fig. As shown in Figure 6B, according to some embodiments, a semiconductor protective layer 118 is formed over the source / drain structures 116N1 and 116N2. The semiconductor protective layer 118 is used to protect the source / drain structures 116N1 and 116N2 from damage during subsequent processes, such as cleaning and / or etching. Therefore, the size or morphology of the source / drain structures 116N1 and 116N2 can be maintained after the subsequent cleaning and / or etching processes. The performance and reliability of the semiconductor device are improved.

[0039] In some embodiments, the semiconductor protective layer 118 contains carbon. In some embodiments, the semiconductor protective layer 118 has an atomic carbon concentration that is higher than that of the source / drain structures 116N1 and 116N2. In some other embodiments, the atomic carbon concentration is in the range of about 1% to about 10%. In some other embodiments, the atomic carbon concentration is in the range of about 1.5% to about 4%. In some cases, if the atomic carbon concentration is less than about 1%, the semiconductor protective layer 118 might not be able to withstand the subsequent cleaning and / or etching processes. Therefore, the underlying source / drain structures 116N1 and 116N2 could be damaged.

[0040] In some embodiments, the semiconductor protective layer 118 has a varying or gradient concentration profile. The atomic carbon concentration in the semiconductor protective layer 118 gradually decreases along a direction from a surface 119 of the semiconductor protective layer 118 towards the source / drain structures 116N1 and 116N2.

[0041] In some embodiments, the source / drain structures 116N1 and 116N2 are an n-type semiconductor material. In these cases, the semiconductor protection layer 118 can contain a silicon layer doped with carbon or a germanium layer doped with carbon. In some embodiments, the source / drain structures 116N1 and 116N2 are a p-type semiconductor material. In these cases, the semiconductor protection layer 118 can contain a silicon-germanium layer doped with carbon.

[0042] The thickness of the semiconductor protection layer 118 should be finely adjustable. In some embodiments, the semiconductor protection layer 118 has a thickness in the range of approximately 2 nm to approximately 10 nm. In some cases, if the thickness of the semiconductor protection layer 118 is less than approximately 2 nm, the semiconductor protection layer 118 might not be able to prevent damage to the source / drain structures 116N1 and 116N2 by the subsequent cleaning and / or etching processes. In some other cases, if the thickness of the semiconductor protection layer 118 is greater than approximately 10 nm, the electrical quality of the semiconductor device might be adversely affected.

[0043] However, it should be clear that the embodiments of the disclosure are not limited to those mentioned above. In some other embodiments, the semiconductor protective layer 118 has a thickness in the range of about 0.5 nm to about 15 nm.

[0044] In some embodiments, the semiconductor protection layer 118 is grown epitaxially on the source / drain structures 116N1 and 116N2. Therefore, the semiconductor protection layer 118 is in direct contact with the source / drain structures 116N1 and 116N2. In some embodiments, the semiconductor protection layer 118 covers the exposed surfaces of the source / drain structures 116N1 and 116N2. In some embodiments, the semiconductor protection layer 118 does not cover the lower sections of the source / drain structures 116N1 and 116N2, which are covered by the support elements 112B.

[0045] In some embodiments, the semiconductor protective layer 118 is formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof. The formation process of the semiconductor protective layer 118 can utilize gaseous and / or liquid precursors that can interact with the composition of the underlying source / drain structures 116N1 and 116N2. The precursor used to form the semiconductor protective layer 118 can include SiH₂Cl₂, SiH₄, Si₂H₆, Si₃H₈, GeH₄, SiH₂CH₃, another suitable precursor, or a combination thereof.By fine-tuning the process parameters, the composition of the semiconductor protective layer 118 can be varied to meet requirements.

[0046] In some embodiments, the source / drain structures 116N1 and 116N2 and the semiconductor protection layer 118 are formed in situ in the same process chamber. Fig. Figure 10 is a cross-sectional view of a process chamber 302 according to some embodiments. In some embodiments, both the source / drain structures 116N1 and 116N2 and the semiconductor protection layer 118 are formed in the process chamber 302. In some embodiments, the Fig. The structure shown in Figure 1B is transferred to process chamber 302 to form the source / drain structures 116N1 and 116N2. After the formation of the source / drain structures 116N1 and 116N2, the semiconductor support layer 100 is not removed from process chamber 302. One or more parameters (such as the precursor gas) of the process are then varied to grow the semiconductor protective layer 118 directly onto the exposed surfaces of the source / drain structures 116N1 and 116N2.

[0047] As in Fig. 1D, Fig. 7A and Fig. As shown in Figure 7B, in some embodiments a mask layer 120 is formed over the gate stack 104N, the semiconductor protection layer 118, and the support elements 112B. The mask layer 120 has an opening that exposes the mask layer 113 over the gate stack 104P and the fin structures 102P1 and 102P2. Therefore, the gate stack 104N and the semiconductor protection layer 118 are blocked and protected from adverse influences while subsequent processes are carried out on the fin structures 102P1 and 102P2. In some embodiments, the mask layer 120 consists of a dielectric material. The dielectric material can be silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. The mask layer 120 can be formed using a method similar to that used to form the mask layer 113.

[0048] Then, as in Fig. 1D and Fig. As shown in Figure 7A, according to some embodiments, spacer elements 122 are formed over the side walls of the gate stack 104P. The material and formation method of the spacer elements 122 can be similar to those of the spacer elements 112A. For example, a photoresist layer (not shown) is used to structure the mask layer 120. The structured mask layer 120 has an opening that exposes the mask layer 113 (see Figure 7A). Fig. 1C or Fig. 6A). In some embodiments, the anisotropic etching process is carried out to partially remove the exposed mask layer 113. This forms the spacer elements 122. In some embodiments, the mask layer 120 is not etched during the formation of the spacer elements 122 due to the photoresist layer, as shown in Fig. Figure 7B is shown. In some embodiments, the photoresist layer is then removed.

[0049] In some embodiments, the section of the mask layer 113, which was originally positioned over the side walls of the fin structures 102P1 and 102P2, is removed after the formation of the spacer elements 122. No support element is formed over the side walls of the fin structures 102P1 and 102P2. However, it should be clear that embodiments of the disclosure are not limited to this. In some other embodiments, support elements similar to the support elements 118 are formed over the side walls of the fin structures 102P1 and 102P2.

[0050] As in Fig. 1D and Fig. As shown in Figure 7A, according to some embodiments, sections of the fin structures 102P1 and 102P2 are removed to reduce the thickness of the fin structures 102P1 and 102P2 and to form depressions 124. During the depression of the fin structures 102P1 and 102P2, the semiconductor protection layer 118 over the source / drain structures 116N1 and 116N2 is blocked or protected by the mask layer 120, as shown in Figure 7A. Fig. 1D, Fig. 7A and Fig. 7B is shown. Therefore, damage to the semiconductor protective layer 118 is prevented.

[0051] In some embodiments, the fin structures 102P1 and 102P2 are recessed into a plane below the top surfaces of the insulating features 103. In some embodiments, an etching process is used to form the recesses 124. Embodiments of the disclosure have many variations. In some other embodiments, the fin structures 102P1 and 102P2 are not partially removed to form the recesses 124.

[0052] As in Fig. 1E and Fig. As shown in Figure 8A, according to some embodiments, the source / drain structures 126P1 and 126P2 are formed over the fin structures 102P1 and 102P2, respectively. In some embodiments, a semiconductor material is formed epitaxially in and over the recesses 124 to form the source / drain structures 126P1 and 126P2. In some embodiments, no support element is used to assist in the growth of the source / drain structures 126P1 and 126P2. In some other embodiments, support elements are used.

[0053] During the growth of the source / drain structures 126P1 and 126P2, the semiconductor protection layer 118 is blocked or protected by the mask layer 120 in some embodiments. This prevents the semiconductor material from being grown on the semiconductor protection layer 118.

[0054] In some embodiments, the source / drain structures 126P1 and 126P2 project from the insulation features 103. The source / drain structures 126P1 and 126P2 can also be referred to as raised source and drain features. In some embodiments, the source / drain structures 126P1 and 126P2 are stressed structures. The source / drain structures 126P1 and 126P2 impart stress or load to the channel region under the gate stack 104N to enhance the carrier mobility of the device and improve its performance.

[0055] In some embodiments, the source / drain structures 126P1 and 126P2 are a p-type semiconductor material. The source / drain structures 126P1 and 126P2 may contain expitaxially grown silicon germanium. The source / drain structures 126P1 and 126P2 are not limited to a p-type semiconductor material. In some other embodiments, the source / drain structures 126P1 and 126P2 are an n-type semiconductor material. For example, the structures 126P1 and 126P2 may contain expitaxially grown silicon, expitaxially grown silicon phosphide (SIP), or another suitable expitaxially grown semiconductor material.

[0056] In some embodiments, the source / drain structures 126P1 and 126P2 are formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof. The formation process of the source / drain structures 126P1 and 126P2 can utilize gaseous and / or liquid precursors that can interact with the composition of the underlying fin structures 102P2 and 102P1.

[0057] In some embodiments, the source / drain structures 126P1 and 126P2 are doped with one or more suitable dopants. For example, the source / drain structures 126P1 and 126P2 are SiGe source / drain features doped with boron (B) or another suitable dopant. Alternatively, the source / drain structures 126P1 and 126P2 are SiGe source / drain features doped with phosphorus (P), antimony (Sb), or another suitable dopant.

[0058] In some embodiments, the source / drain structures 126P1 and 126P2 are doped in situ during their growth. In other embodiments, they are not doped during this process. After the formation of the source / drain structures 126P1 and 126P2, they are doped in a subsequent process. In some embodiments, the doping is achieved by an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, another applicable process, or a combination thereof. In some embodiments, the source / drain structures 126P1 and 126P2 are further subjected to annealing steps to activate the dopants. For example, a rapid thermal annealing process is performed.

[0059] As in Fig. 1E, Fig. 8A and Fig. As shown in Figure 8B, according to some embodiments, a semiconductor protection layer 128 is formed over the source / drain structures 126P1 and 126P2. The semiconductor protection layer 128 is used to protect the source / drain structures 126P1 and 126P2 from damage during subsequent processes, such as cleaning and / or etching. Therefore, the size or morphology of the source / drain structures 126P1 and 126P2 can be maintained after the subsequent cleaning and / or etching processes. The performance and reliability of the semiconductor device are improved.

[0060] In some embodiments, the semiconductor protection layer 128 covers a larger surface area of ​​the source / drain structures 126P1 and 126P2 compared to the semiconductor protection layer 118. In some other embodiments, support elements (not shown) are formed to aid the formation of the source / drain structures 126P1 and 126P2. In these cases, both semiconductor protection layers 118 and 128 can cover similar surface areas of the corresponding source / drain structures.

[0061] In some embodiments, the semiconductor protective layer 128 contains carbon. In some embodiments, the semiconductor protective layer 128 consists of a similar material to the semiconductor protective layer 118. In some embodiments, the materials of the semiconductor protective layers 118 and 128 are the same. In some other embodiments, the materials of the semiconductor protective layers 118 and 128 are different. In some embodiments, the semiconductor protective layer 118 contains silicon and carbon. In some embodiments, the semiconductor protective layer 129 contains silicon, carbon, and germanium.

[0062] In some embodiments, the semiconductor protective layer 128 has a varying or gradient concentration profile. The atomic carbon concentration in the semiconductor protective layer 128 gradually decreases along a direction from a surface of the semiconductor protective layer 128 towards the source / drain structures 126P1 and 126P2.

[0063] The thickness of the semiconductor protection layer 128 should be finely adjustable. In some embodiments, the semiconductor protection layer 128 has a thickness in the range of approximately 2 nm to approximately 10 nm. In some cases, if the thickness of the semiconductor protection layer 128 is less than approximately 2 nm, the semiconductor protection layer 128 might not be able to prevent damage to the source / drain structures 126P1 and 126P2 by the subsequent cleaning and / or etching processes. In some other cases, if the thickness of the semiconductor protection layer 128 is greater than approximately 10 nm, the electrical quality of the semiconductor device might be negatively affected.

[0064] However, it should be clear that the embodiments of the disclosure are not limited to those mentioned above. In some other embodiments, the semiconductor protective layer 128 has a thickness in the range of about 0.5 nm to about 15 nm.

[0065] In some embodiments, the semiconductor protection layer 128 is grown epitaxially on the source / drain structures 126P1 and 126P2. Therefore, the semiconductor protection layer 128 is in direct contact with the source / drain structures 126P1 and 126P2. In some embodiments, the semiconductor protection layer 128 covers the exposed surfaces of the source / drain structures 126P1 and 126P2. In some embodiments, the semiconductor protection layer 128 covers the lower sections of the source / drain structures 126P1 and 126P2 above the insulating features 103.

[0066] In some embodiments, the semiconductor protective layer 128 is formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof. The formation process of the semiconductor protective layer 128 can utilize gaseous and / or liquid precursors that can interact with the composition of the underlying source / drain structures 126P1 and 126P2. The precursor used to form the semiconductor protective layer 128 can include SiH₂Cl₂, SiH₄, Si₂H₆, Si₃H₈, GeH₄, SiH₃CH₃, another suitable precursor, or a combination thereof.By fine-tuning the process parameters, the composition of the semiconductor protective layer 128 can be varied to meet requirements. In some embodiments, the source / drain structures 126P1 and 126P2 and the semiconductor protective layer 128 are formed in situ in the same process chamber.

[0067] Then, as in Fig. 1F, Fig. 9A and Fig. As shown in Figure 9B, in some embodiments the mask layer 120 is removed to expose the gate stack 104N and the semiconductor protection layer 118. In some embodiments, an etching process is used to remove the mask layer 120. The etching process can be a wet etching process, a dry etching process, or a combination thereof. Due to the semiconductor protection layers 118 and 128, the source / drain structures 116N1, 116N2, 126P1, and 126P2 are protected without being damaged or seriously damaged during the etching process and / or other associated cleaning processes. The performance and reliability of the semiconductor device are improved.

[0068] Subsequently, various processes can be performed to complete the formation of the semiconductor device. These processes include, for example, a contact hole formation process, a metal silicide application process, a gate exchange process, another suitable process, or a combination thereof. These processes may involve the application of etching agents and / or cleaning chemicals over the source / drain structures 116N1, 116N2, 126P1, and 126P2. In these cases, the semiconductor protection layers 118 and / or 128 are able to protect the underlying structures from damage. The performance and reliability of the semiconductor device are improved.

[0069] In some embodiments, a section of the semiconductor protective layers 118 or 128 is thinner than the other sections. For example, the section of the semiconductor protective layers 118 or 128 exposed by contact holes may be thinner. The exposed section of the semiconductor protective layers 118 or 128 may be damaged or consumed after etching and / or cleaning processes. Therefore, some sections of the semiconductor protective layer 118 or 128 may be thinner.

[0070] Fig. Figure 11 is a cross-sectional view of a stage of a process for forming a semiconductor device according to some embodiments. The in Fig. The structure shown in 11 can be found using the information in Fig. The methods described in 1A-1F, 2A-9A and 2B-9B are formed. In some embodiments, a dielectric layer 402 is deposited and structured to form a contact hole 404. The right side of Fig. Figure 11 shows the section of the semiconductor protection layer 118 that is covered by the dielectric layer 402. The left side of Fig. Figure 11 shows the section of the semiconductor protective layer (designated by reference numeral 118') exposed through the contact hole 404. In some embodiments, the section of the semiconductor protective layer 118' is thinner than the section of the semiconductor protective layer 118 that is covered by the dielectric layer 402. In these cases, a first section of the semiconductor protective layer 118 or 128 is thinner than a second section of the semiconductor protective layer 118 or 128. In some embodiments, the first section is located beneath a contact hole.

[0071] However, it should be clear that embodiments of the disclosure are not limited to those mentioned above. In some embodiments, the portion of the semiconductor protective layer 118' exposed by the contact hole 404 has a thickness that is substantially equal to that of the semiconductor protective layer 118 that is not exposed by the contact hole 404. In these cases, the etching and / or cleaning processes for forming the contact hole 404 do not substantially damage or consume the exposed semiconductor protective layer 118.

[0072] An embodiment of the disclosure provides a structure and a method for forming a semiconductor device with a fin structure (or a raised source / drain structure). A semiconductor protective layer is formed over the fin structure. The semiconductor protective layer could be grown in situ on the fin structure. The semiconductor protective layer contains carbon and has an atomic carbon concentration that is higher than that of the underlying fin structure. The semiconductor protective layer can protect the fin structure from damage or serious deterioration during subsequent processes such as etching and / or cleaning processes. Therefore, the performance and reliability of the semiconductor device are improved.

[0073] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate layer and a fin structure above the semiconductor substrate layer. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source / drain structure above the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer above the epitaxially grown source / drain structure. The semiconductor protection layer has a carbon atom concentration higher than that of the epitaxially grown source / drain structure.

[0074] According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate layer and a first fin structure above the semiconductor substrate layer. The semiconductor device also includes a first epitaxially grown source / drain structure above the first fin structure. The semiconductor substrate layer further includes a second fin structure above the semiconductor substrate layer and a second epitaxially grown source / drain structure above the second fin structure. Additionally, the semiconductor device includes a first semiconductor protection layer above the first epitaxially grown source / drain structure, and the first semiconductor protection layer has an atomic carbon concentration that is higher than that of the first epitaxially grown source / drain structure.The semiconductor device further includes a second semiconductor protective layer over the second epitaxially grown source / drain structure, and the second semiconductor protective layer has an atomic carbon concentration that is higher than that of the second epitaxially grown source / drain structure.

[0075] According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a fin structure over a semiconductor support layer, forming a gate stack over the semiconductor support layer, and covering a portion of the fin structure. The method also includes epitaxially growing source / drain structures over the fin structure and adjacent to the gate stack. The method further includes forming a semiconductor protective layer over the source / drain structures. The semiconductor protective layer contains carbon.

Claims

[1] A semiconductor device structure comprising: a semiconductor carrier layer (100); a fin structure (102N, 102P) over the semiconductor carrier layer (100); a gate stack (104N, 104P) covering a portion of the fin structure (102N, 102P); an epitaxially grown source / drain structure (116N, 126P) above the fin structure (102N, 102P) and adjacent to the gate stack (104N, 104P); and a semiconductor protection layer (118, 128) over the epitaxially grown source / drain structure (116N, 126P) for protecting the epitaxially grown source / drain structure (116N, 126P) from damage by the etching process and / or cleaning process, wherein the semiconductor protection layer (118, 128) has an atomic carbon concentration higher than that of the epitaxially grown source / drain structure (116N, 126P), wherein the atomic carbon concentration in the semiconductor protective layer (118, 128) gradually decreases along a direction from a surface of the semiconductor protective layer (118, 128) toward the epitaxially grown source / drain structure (116N, 126P). [2] A semiconductor device according to claim 1, wherein the semiconductor protection layer (118, 128) is in direct contact with the epitaxially grown source / drain structure (116N, 126P). [3] A semiconductor device according to claim 1, wherein the semiconductor protective layer (118, 128) contains silicon and carbon. [4] A semiconductor device according to claim 1, wherein the semiconductor protective layer (118, 128) contains silicon, carbon and germanium. [5] The semiconductor device of claim 1, wherein the atomic carbon concentration in the semiconductor protective layer (118, 128) is in the range of about 1% to about 10%. [6] A semiconductor device according to claim 1, wherein the epitaxially grown source / drain structure (116N, 126P) is an n-type semiconductor material. [7] A semiconductor device according to claim 1, wherein the epitaxially grown source / drain structure (116N, 126P) is a p-type semiconductor material. [8] The semiconductor device according to claim 1, further comprising support members (112B) covering a lower portion of the epitaxially grown source / drain structure (116N, 126P), the support members (112B) being in direct contact with the epitaxially grown source / drain structure (116N, 126P), and the support members (112B) being located between the semiconductor protection layer (118, 128) and the semiconductor support layer (100). [9] The semiconductor device according to claim 1, wherein the semiconductor protective layer (118, 128) has a first portion and a second portion, and the first portion is thinner than the second portion. [10] A semiconductor device comprising: a semiconductor carrier layer; a first fin structure (102N, 102P) over the semiconductor carrier layer (100); a first epitaxially grown source / drain structure (116N, 126P) over the first fin structure (102N, 102P; a second fin structure (102N, 102P) over the semiconductor carrier layer (100); a second epitaxially grown source / drain structure (116N, 126P) over the second fin structure (102N, 102P; a first semiconductor protection layer (118, 128) over the first epitaxially grown source / drain structure (116N, 126P) for protecting the first epitaxially grown source / drain structure (116N, 126P) from damage by etching processes and / or cleaning processes, wherein the first semiconductor protection layer (118, 128) has an atomic carbon concentration higher than that of the first epitaxially grown source / drain structure (116N, 126P); and a second semiconductor protection layer (118, 128) over the second epitaxially grown source / drain structure (116N, 126P) for protecting the second epitaxially grown source / drain structure (116N, 126P) from damage by the etching process and / or cleaning process, wherein the second semiconductor protection layer (118, 128) has an atomic carbon concentration higher than that of the second epitaxially grown source / drain structure (116N, 126P), wherein the atomic carbon concentration in the first semiconductor protective layer (118, 128) gradually decreases along a direction from a surface of the first semiconductor protective layer (118, 128) toward the epitaxially grown source / drain structure (116N, 126P). [11] A semiconductor device according to claim 10, wherein the first semiconductor protective layer (118, 128) and the second semiconductor protective layer (118, 128) are made of different materials. [12] The semiconductor device according to claim 10, wherein the atomic carbon concentration in the first semiconductor protective layer (118, 128) or the second semiconductor protective layer (118, 128) is in the range of about 1% to about 10%. [13] The semiconductor device of claim 10, wherein the first epitaxially grown source / drain structure (116N, 126P) is an n-type semiconductor material and the second epitaxially grown source / drain structure (116N, 126P) is a p-type semiconductor material. [14] A method of forming a semiconductor device, comprising: Forming a fin structure (102N, 102P) over a semiconductor carrier layer (100); Forming a gate stack (104N, 104P) over the semiconductor substrate (100) covering a portion of the fin structure (102N, 102P); epitaxial growth of source / drain structures (116N, 126P) over the fin structure (102N, 102P) and next to the gate stack (104N, 104P); and Forming a semiconductor protection layer (118, 128) over the source / drain structures (116N, 126P) to protect the epitaxially grown source / drain structures (116N, 126P) from damage by an etching process and / or cleaning process, wherein the semiconductor protective layer (118, 128) has an atomic carbon concentration, which is higher than that of the epitaxially grown source / drain structures (116N, 126P), wherein the atomic carbon concentration in the first semiconductor protective layer (118, 128) gradually decreases along a direction from a surface of the first semiconductor protective layer (118, 128) toward the epitaxially grown source / drain structure (116N, 126P). [15] A method of forming a semiconductor device according to claim 14, wherein the semiconductor protection layer (118, 128) is grown expitaxially on the source / drain structures (116N, 126P). [16] A method of forming a semiconductor device according to claim 14, wherein the source / drain structures (116N, 126P) and the semiconductor protection layer (118, 128) are formed in situ in the same process chamber. [17] A method of forming a semiconductor device according to claim 14, further comprising: Forming a second fin structure (102N, 102P) over the semiconductor carrier layer (100); Forming a second gate stack (104N, 104P) over the semiconductor support layer (100) covering a portion of the second fin structure (102N, 102P); Blocking the second fin structure (102N, 102P) before the epitaxially grown source / drain structures (116N, 126P) and the semiconductor protection layer (118, 128) are formed; epitaxially growing second source / drain structures (116N, 126P) over the second fin structure (102N, 102P) and adjacent to the second gate stack (104N, 104P); and Blocking the semiconductor protection layer (118, 128) before the second source / drain structures (116N, 126P) are formed. [18] A method of forming a semiconductor device according to claim 17, further comprising forming a second semiconductor protection layer (118, 128) over the second source / drain structures (116N, 126P) after blocking the semiconductor protection layer (118, 128).

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