Electronic component and method for dissipating heat from a semiconductor chip

Abstract

Electronic component (10), comprising: a dielectric core layer (11) with a thickness; at least one semiconductor chip (12) embedded in the dielectric core layer (11) and electrically coupled to at least one contact pad (13) arranged on a first side (14) of the dielectric core layer (11), wherein the semiconductor chip (12) has a thickness greater than or equal to the thickness of the dielectric core layer (11), and a heat dissipation layer (15) arranged on a second side (16) of the dielectric core layer (11) and thermally coupled to the semiconductor chip (12), wherein the heat dissipation layer (15) comprises a material with an isotropic thermal conductivity, where the semiconductor chip (12) is attached by an adhesive layer (20) in an opening (19) of the dielectric core layer (11); the adhesive layer (20) is positioned between the side surfaces (21) of the semiconductor chip (12) and side surfaces (22) that define the opening (19); the semiconductor chip (12) is further secured in the opening (19) by the use of reinforcing layers (23, 24) made of dielectric material; the reinforcing layers (23, 24) are positioned at the periphery of the semiconductor chip (12) and extend across the adhesive layer (20) to the second side (16) and the first side (14) of the dielectric core layer (11) and to peripheral regions of a second surface (26) and a first surface (27) of the semiconductor chip (12); and the reinforcing layers (23, 24) and the adhesive layer (20) together form an I-shaped fastening element (36).

Description

[0001] Semiconductor devices can generate heat during operation. Excessive heat can reduce the performance of these devices. One approach to mitigating the effects of excessive heat on device performance is to provide an additional heat dissipation component that is thermally coupled to the heat-generating semiconductor device and configured to remove heat from it.

[0002] From DE 10 2012 104 067 A1, an integrated circuit is known in which a chip is arranged in a layer of a package module that has approximately the same thickness as the chip. A filler material is located between this layer and the chip. The chip has forward contacts on one side, which are coupled to circuit connections located below the chip. On the side of the chip facing away from the forward contacts, there is a top layer, e.g., made of copper, which also extends over the layer of the package module. Publications US 2010 / 0 300 737 A1 and US 2009 / 0 250 257 A1 each disclose an arrangement with a substrate and a semiconductor chip embedded in the substrate. SUMMARY

[0003] In one embodiment, an electronic component comprises a dielectric core layer of a certain thickness, at least one semiconductor chip embedded in the dielectric core layer and electrically coupled to at least one contact pad located on a first side of the dielectric core layer, and a heat dissipation layer located on a second side of the dielectric core layer and thermally coupled to the semiconductor chip. The semiconductor chip has a thickness that is substantially greater than or equal to the thickness of the dielectric core layer. The heat dissipation layer comprises a material with isotropic thermal conductivity. The semiconductor chip is secured in an opening in the dielectric core layer by an adhesive layer. The adhesive layer is positioned between the side faces of the semiconductor chip and side faces that define the opening.The semiconductor chip is further secured in the opening by the use of reinforcing layers made of dielectric material. These reinforcing layers are positioned at the periphery of the semiconductor chip and extend across the adhesive layer to the second and first sides of the dielectric core layer, as well as to peripheral regions of a second and first surface of the semiconductor chip. Together, the reinforcing layers and the adhesive layer form an I-shaped mounting element.

[0004] In one embodiment, a method includes embedding at least one semiconductor chip in a dielectric core layer, wherein the semiconductor chip has a thickness substantially greater than or equal to the thickness of the dielectric core layer, electrically coupling the at least one semiconductor chip to at least one contact pad arranged on a first side of the dielectric core layer, and arranging a heat dissipation layer on a second side of the dielectric core layer and thermally coupling the heat dissipation layer to the semiconductor chip. The heat dissipation layer comprises a material with isotropic thermal conductivity. The semiconductor chip is secured in an opening of the dielectric core layer by an adhesive layer. The adhesive layer is positioned between the side faces of the semiconductor chip and side faces that define the opening.The semiconductor chip is further secured in the opening by the use of reinforcing layers of dielectric material. These reinforcing layers are positioned at the periphery of the semiconductor chip, extending across the adhesive layer to the second and first sides of the dielectric core layer and to peripheral regions of a second and first surface of the semiconductor chip, forming a substantially I-shaped mounting element. BRIEF DESCRIPTION OF THE IMAGES

[0005] The elements in the drawings are not necessarily to scale with each other. Identical reference numerals denote corresponding identical parts. The features of the various illustrated embodiments can be combined, provided they are not mutually exclusive. Embodiments are shown in the drawings and are explained in detail in the following description. Fig. Figure 1a illustrates a cross-sectional view of an electronic component according to a first embodiment. Fig. Figure 1b illustrates an enlarged view of a section of the in Fig. 1a illustrated electronic component. Fig. Figure 2a illustrates a perspective top view and a perspective bottom view of the electronic component according to the first embodiment. Fig. Figure 2b illustrates an enlarged section of a contact pad from a perspective bottom view. Fig. 2a. Fig. Figure 3 illustrates a perspective top view and a perspective bottom view of an electronic component according to a second embodiment. Fig. Figure 4 illustrates a perspective top view and a perspective bottom view of an electronic component according to a third embodiment. Fig. Figure 5 illustrates a cross-sectional view of an electronic component according to a fourth embodiment. Fig. Figure 6 illustrates a perspective top view and a perspective bottom view of the electronic component according to the fourth embodiment. DETAILED DESCRIPTION

[0006] The following detailed description refers to the accompanying drawings, which form part thereof and illustrate specific embodiments in which the invention can be implemented. In this respect, directional terminology such as "above," "below," "front," "back," "leading," "following," etc., is used with reference to the orientation of one or more of the described figures. Since components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes. It is understood that other embodiments may be used and that structural or logical modifications may be made. The scope of the present invention is defined by the attached claims.

[0007] A number of embodiments are described below. In this case, identical structural features in the figures are identified by identical or similar reference symbols. In the context of this description, "lateral" or "lateral direction" is to be understood as a direction or extension that generally runs parallel to the lateral extent of a semiconductor material or semiconductor substrate. The lateral direction thus generally extends parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is to be understood as a direction that generally runs perpendicular to these surfaces or sides and thus perpendicular to the lateral direction. The vertical direction therefore runs in the direction of the thickness of the semiconductor material or semiconductor substrate.

[0008] When, according to the usage herein, an element is described as being "connected" or "electrically connected" or "coupled" or "electrically coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0009] When, according to the usage herein, an element such as a layer, region, or substrate is described as being "on" another element or extending "over" another element, it may be located directly on or extending directly over the other element, or there may be intermediate elements. Conversely, when an element is described as being "directly on" another element or extending "directly over" another element, there are no intermediate elements.

[0010] A "high-voltage component," as used herein, for example, a depletion-type high-voltage transistor, is an electronic component optimized for high-voltage switching applications. This means that when the transistor is off, it is capable of blocking high voltages such as approximately 300 V or more, approximately 600 V or more, or approximately 1200 V or more, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used; that is, it experiences sufficiently low conduction losses when a substantial current flows through the component. A high-voltage component may be capable of blocking at least a voltage equal to the high-voltage supply or the maximum voltage in the circuit in which it is used.A high-voltage component may be able to block 300 V, 600 V, 1200 V or any other suitable blocking voltage required by the application.

[0011] A “low-voltage component”, such as a low-voltage enhancement transistor used herein, is an electronic component capable of handling low voltages such as between 0 V and V niedrig to lock, however voltages of more than V niedrig cannot lock. V niedrig It can be approximately 10 V, approximately 20 V, approximately 30 V, approximately 40 V or between approximately 5 V and 50 V, such as between approximately 10 V and 30 V.

[0012] Fig. Figure 1a illustrates a cross-sectional view of an electronic component 10. Fig. Figure 1b illustrates an enlarged view of a section of the in Fig. 1a illustrated electronic component 10. Fig. Figure 2 illustrates a perspective top view (top left) and a perspective bottom view (bottom right) of the electronic component 10 according to the first embodiment.

[0013] The electronic component 10 comprises at least one semiconductor chip 12 and a dielectric core layer 11. The semiconductor chip 12 is embedded in the dielectric core layer 11 and electrically connected to at least one contact pad 13, which is arranged on a first side 14 of the dielectric core layer 11. The semiconductor chip 12 has a thickness t s on, which are essentially equal to or greater than or equal to a thickness t d of the dielectric core layer 11. The electronic component 10 further includes a heat dissipation layer 15, which is arranged on a second side 16 of the dielectric core layer 11. The second side 16 of the dielectric core layer is opposite the first side 14.

[0014] The heat dissipation layer 15 is thermally coupled to the semiconductor chip 12 and contains a material with a substantially isotropic thermal conductivity. The heat dissipation layer 15 can, for example, contain a metal such as copper or aluminum, or an alloy such as a copper alloy or an aluminum alloy.

[0015] The electronic component 10 can be considered as an active component section 17, which is essentially planar and has a laminated structure, and comprising a heat dissipation section 18, which contains the heat dissipation layer 15. In this embodiment, the heat dissipation section 18 is essentially planar.

[0016] The active component section 17 contains the at least one semiconductor chip 12 which is / are embedded in the dielectric layer 11 and an electrically conductive redistribution structure which contains the at least one contact pad 13.

[0017] The heat dissipation section 18 can have a thickness t h exhibiting thicknesses between 3 and 10 times the thickness t a of the active component section 17, i.e. 3t a ≤ t h ≤ 10t a The dielectric core layer 11 can have a thickness between 25 µm and 500 µm. The semiconductor chip 12 can have a thickness between 25 µm and 550 µm. The active section 17 can have a thickness t a between 45 µm and 1000 µm. The heat dissipation section 62 can have a thickness t h between 100 µm and 1000 µm.

[0018] The dielectric core layer 11 can contain a prefabricated plate, which may contain a fiber-reinforced matrix. For example, the dielectric core layer can contain a glass fiber-reinforced epoxy resin, such as FR4. The dielectric core layer can contain, for example, PTFE (polytetrafluoroethylene), PEN (polyethylene naphthalate), PET (polyethylene terephthalate), BT laminate (bismaleimide triazine), or polyimide.

[0019] The dielectric core layer 11 can include an opening 19 with a surface configured to receive the surface of the semiconductor chip 12. The semiconductor chip 12 can be fixed in the opening 19 by an adhesive layer 20 positioned between the side surfaces 21 of the semiconductor chip 12 and side surfaces 22 defining the opening 19. The semiconductor chip 12 is further fixed in the opening 19 by the use of reinforcing layers 23, 24 made of dielectric material, which are positioned at the periphery of the semiconductor chip 12 and extend across the adhesive layer 20 to the second side 16 and the first side 14 of the dielectric core layer 11 and to peripheral regions of the second surface 26 and the first surface 27 of the semiconductor chip 12. The reinforcing layers 23, 24 and the adhesive layer 20 together form an essentially I-shaped fixing element 36.

[0020] The fastening element 36 has an I-shape according to the claim. In some embodiments, the first surface 27 of the semiconductor chip 12 can be covered by a dielectric layer, for example, an adhesive layer. This arrangement can be used for a semiconductor chip for which no electrical connections with the first surface 27 are required, for example, a semiconductor chip containing a logic component, a gate driver circuit, etc.

[0021] The semiconductor chip 12 can contain a vertical component, such as a vertical transistor component or a vertical diode, which has at least one electrode on the first surface 27 and on the second surface 26.

[0022] The active component section 17 can further comprise a first metallic layer 25 positioned on a second surface 26 of the semiconductor chip and on the second surface 16 of the dielectric core layer 11. In this embodiment, the contact pad 13 arranged on the first side 14 of the dielectric layer 11 is also positioned on the first surface 27 of the semiconductor chip 12. The contact pad 13 and the first metallic layer 25 are surrounded by respective dielectric layers 28, 29. The dielectric layers 28, 29 can, for example, contain PEN or polyimide. One or more of the contact pad 13 and the metallic layers 25 can comprise two or more sections that are electrically isolated from each other by sections of the corresponding dielectric layer 28, 29.

[0023] The active component section 17 can further include at least one electrically conductive via located in the dielectric core layer 11, which couples a section of the metallic layer 25 to another contact pad positioned on the first side 14 of the dielectric core layer 11. The lower surface 30 of the active component section 17 contains the outer contact pads for the active component section 17. The metallic layer 25 and the electrically conductive via can be used to provide a redistribution structure from the second surface 26 of the semiconductor chip 11 to the lower surface 30 of the active component section 17.This arrangement can be used for embodiments in which the semiconductor chip 12 includes a vertical component, such as a power transistor with a vertical drift path or a diode with a vertical drift path, which includes at least one electrode arranged on two opposing main surfaces.

[0024] The dielectric core layer 11 can further comprise a metallic foil bonded to at least one section of two opposing main surfaces 14, 16 of the dielectric core layer 11. In these embodiments, the metallic foil and the dielectric core layer 11 can be provided in the form of a printed circuit board in which the metallic foil is bonded to the dielectric core layer 11. The metallic foil can be structured to provide an arrangement suitable for providing at least one section of the first metallic layer 25 and / or at least one section of an outer contact pad.

[0025] Another metallic layer can be applied to the metallic foil, for example by electroplating, to electrically couple the semiconductor chip 12 with a section of the metallic foil and / or to increase the thickness of the regions of the metallic foil that are adjacent to the side surfaces of the semiconductor chip 12 on the dielectric core layer 11.

[0026] The heat dissipation section 18 of the electronic component 10, including the heat dissipation layer 15, can be mounted on the active component section 17 by means of an adhesive layer 31. The adhesive layer 31 can be electrically insulating or electrically conductive.

[0027] In embodiments where one or more of the regions of the metallic layer 25, which are arranged on the second surface 16 of the dielectric core layer 11, are used to transmit signals or a voltage, an electrically insulating adhesive 31 can be used to electrically isolate the heat dissipation layer 15 from the metallic layer 25. In embodiments where the metallic layer 25 is at ground potential, an electrically conductive adhesive can be used to attach the heat dissipation layer 15 to the metallic layer 25 in order to couple the heat dissipation layer 15 to ground potential.

[0028] The heat dissipation layer 15 has a top and a bottom surface, wherein at least one of the top and bottom surfaces is substantially planar. In some embodiments, both the top and bottom surfaces of the heat dissipation layer 15 are substantially planar. The heat dissipation layer 15 may include a further insulating layer on at least two opposing surfaces, for example, on the top and bottom surfaces.

[0029] In embodiments where the heat dissipation layer 15 contains aluminum, the insulating layer can be provided by anodized aluminum. A freestanding aluminum plate can be anodized and then singulated to provide a plurality of heat dissipation layers 15 with the desired lateral dimensions. In these embodiments, the side faces of the heat dissipation layer 15 can contain aluminum with a native aluminum oxide layer, and the top and bottom faces can contain a thicker anodized aluminum oxide layer. The anodized aluminum oxide layer can be used to further electrically insulate the heat dissipation layer 15 from the semiconductor chip 12.

[0030] In some embodiments, at least the lower surface of the heat dissipation layer has an area substantially equal to the area of ​​the dielectric core layer. The heat dissipation section 18 and the active component section 17 can be configured such that the electronic component 10 conforms to a JEDEC (Joint Electron Device Engineering Council) package footprint or JEDEC package outline. For example, the electronic component 10 can conform to a "Super SO8" or a "TO268" package outline.

[0031] The lateral dimensions of the active component section 17 and the heat dissipation section 18 can be selected to conform to the JEDEC package outline. The electronic component 10 differs from a cast package with a resin housing in that it lacks a leadframe and a casting compound to provide the housing. The material providing the JEDEC package outline is largely supplied by the heat dissipation layer 15. The lower surface 30 of the active component section 17 provides the JEDEC footprint.

[0032] In the case of a semiconductor chip 12 containing a transistor component such as a MOSFET, the contact pad 13 can be electrically coupled to a drain electrode positioned on the second side 27 of the semiconductor chip 12, and a source electrode and a gate electrode can be arranged on the first side 26 of the semiconductor chip 12.

[0033] In some embodiments, at least the upper edge regions of the heat dissipation layer 15 are embedded in a further insulating material. This further insulating material can be a dielectric material, such as that applied to the upper edge region of the heat dissipation layer 15. For example, an additional dielectric material can be applied to a peripheral recess provided in the upper edge region of the heat dissipation layer 15. In some embodiments, the heat dissipation layer 15 can be embedded in a second core layer containing a fiber-reinforced matrix, such as a glass fiber-reinforced epoxy resin.

[0034] Fig. Figure 2a illustrates (bottom right) that the lower surface 30 of the electronic component 10 contains eight contact pads arranged in the boundary region of two opposite edges of the lower surface 30. The contact pad 13, which extends over the drain electrode on the lower surface 27 of the semiconductor chip 12, contains four contact pads extending over a first boundary region 37 of the lower surface 30. The four contact pads 13 are defined by three rectangular dielectric regions 32. On the opposite boundary region 33 of the lower surface 30, three contact pads 34 are coupled to the source electrode, and the fourth contact pad 35 is coupled to the gate electrode of the semiconductor chip 12. The outer dimensions and arrangement of the contact pads 13, 34, 35 correspond to a "Super SO8" JEDEC packing outline.

[0035] The contact pads 13, 34, 35 can contain a thicker layer of metal than the rest of the contact pad positioned on the semiconductor chip 12. This is shown in the detailed view of Fig. 2b illustrated.

[0036] Fig. Figure 3 illustrates a perspective top view (top left) and a perspective bottom view (bottom right) of an electronic component 40 according to a second embodiment. The electronic component 40 comprises an active component section 17 and a heat dissipation section 41, which is mounted on an upper surface 38 of the active component section 17. The active component section 17 has the Fig. 1 and Fig. 2 illustrated arrangements.

[0037] The heat dissipation section 41 contains a heat dissipation layer 42 embedded in a frame 43 provided by a second dielectric core layer 44. The heat dissipation layer 42 can contain a metal, for example, aluminum, which may be secured within the opening 45 of the frame 43 by an adhesive layer 46 extending between the side walls defining the frame 43 and the side faces of the heat dissipation layer 42. The frame 43 provides electrical insulation for the metallic heat dissipation layer 45 and can be useful for higher-voltage applications or for applications where conductive side faces and conductive top edges of the electronic component 40 are undesirable.

[0038] Fig. Figure 4 illustrates a perspective top view (top left) and a perspective bottom view (bottom right) of an electronic component 50 according to a third embodiment. The electronic component 50 includes an active component section 51 with a [missing information] in the view of Fig. 4. A semiconductor chip not visible, embedded in a first dielectric core layer. The lower surface 58 of the electronic component 50, formed by the lower surface of the active component section 51, contains three contact pads 52, 53 and 54 with a size and arrangement corresponding to a “TO268” package outline.

[0039] The contact pad 52 has a larger area and is located in a first boundary region of the underside of the electronic component 50. The contact pads 53 and 54 each have a smaller area and are located in a second boundary region of the underside of the electronic component, opposite the first boundary region. In embodiments in which the semiconductor chip contains a transistor component such as a MOSFET, the contact pad 52 can be coupled to the drain electrode, the contact pad 53 to a gate electrode, and the contact pad 54 to a source electrode.

[0040] The electronic component 50 includes a heat dissipation section 55 mounted on the upper surface of the component section 51. The heat dissipation section 55 contains a second dielectric core layer 56, which includes an opening in which a heat dissipation layer 57 is embedded. The heat dissipation layer 57 is positioned above the semiconductor chip towards a peripheral region 58 of the electronic component 50 and is located in adjacent regions of the active component section 51 where the contact pads 53 and 54 are arranged. The heat dissipation layer 57 is therefore positioned asymmetrically within the lateral region of the top surface 59 of the electronic component 50. The heat dissipation layer 57 may contain a metal or alloy and has a substantially isotropic thermal conductivity.

[0041] Electronic components 10, 40, and 50 each contain an outer contact pad that covers and is coupled to the semiconductor chip. This arrangement facilitates heat dissipation from the semiconductor chip via this outer contact pad, in addition to the heat dissipation section. This arrangement can be used to provide an electronic component that incorporates heat dissipation paths from two opposing main surfaces, i.e., an upper and a lower main surface of the electronic component.

[0042] Fig. Figure 5 illustrates a cross-sectional view and Fig. Figure 6 illustrates a perspective top view (top left) and a perspective bottom view (bottom right) of an electronic component 60 according to a fourth embodiment.

[0043] The electronic component 60 includes an active component section 61 and a heat dissipation section 62, which is arranged on a first main surface 63 of the active component section 61.

[0044] The active component section 61 has a multi-layer laminate structure and is essentially planar with a width and depth that is much greater than its height.

[0045] The active component section 61 comprises a dielectric core layer 64 and a semiconductor chip 65, which contains a vertical power transistor embedded in the dielectric core layer 64. In this embodiment, the semiconductor chip 65 has a thickness that is essentially equal to the thickness of the dielectric core layer 64. However, the semiconductor chip 65 can also have a thickness that is greater than or equal to the thickness of the dielectric core layer 64.

[0046] The dielectric core layer 64 can contain a prefabricated plate, for example, a fiber-reinforced epoxy resin plate such as FR4. The semiconductor chip 65 can be embedded in the dielectric core layer 64 by forming an opening in the dielectric core layer 64, inserting the semiconductor chip 65 into the opening, and securing the semiconductor chip 65 in the opening by means of an adhesive applied to the peripheral regions of the opening between the semiconductor chip 65 and the dielectric core layer 64.

[0047] The semiconductor chip 65 can contain a vertical power transistor component, such as a power MOSFET. The semiconductor chip 65 includes a first main surface 66, which contains a first current electrode 67, for example a source electrode, and a control electrode, for example a gate electrode, which are shown in the cross-sectional view of Fig. 5 is not visible. The semiconductor chip 65 further contains a second main surface 68, which contains a second current electrode 69, for example a drain electrode.

[0048] The active component section 61 includes a first conductive layer 70 arranged on the second current electrode 69, which extends over the second main surface 68 of the semiconductor chip 65 and a second main surface 71 of the dielectric core layer 64. The first conductive layer 70 can extend over a region of the second main surface 71 that is adjacent to a side surface 72 of the semiconductor chip 65. The remaining regions of the second main surface 71 of the dielectric core layer 64 are covered by a first dielectric layer 73.

[0049] A second conductive layer 74 is positioned on a peripheral region of the conductive layer 70, such that it is adjacent to and peripherally positioned with respect to the semiconductor chip 65. The second conductive layer 74 provides an external contact for the electronic component 60 and, in particular, an external contact that is electrically coupled to the second current electrode 69.

[0050] The active component section 61 includes a third conductive layer 75, which is arranged on the first main surface 66 of the semiconductor chip 65 and extends to regions of the second main surface 76 of the dielectric core layer 64 that are located peripherally to at least one side face of the semiconductor chip 65. In this embodiment, the third conductive layer 75 extends over a peripheral region opposite the peripheral region on which the first conductive layer 70 is arranged.

[0051] The active component section 61 further includes a second dielectric layer 77, which is arranged on the remaining sections of the second main surface 76 of the dielectric core layer 64 to provide a substantially planar first main surface 63 for the active component section 61.

[0052] The active component section 61 further comprises one or more conductive vias 78, which extend from the third conductive layer 75 through the dielectric core layer 64 to the second main surface 79, which provides the lower surface of the active component section 61. The conductive vias 78 are electrically coupled to a fourth conductive layer 80, which provides an outer contact pad for the first current electrode and the control electrode. The outer contact pad for the control electrode is shown in the cross-sectional view of Fig. 5 not visible. The fourth conductive layer 80 is adjacent to and peripherally located on the semiconductor chip 65. The regions between the outer contact 74 and the outer contact 80 are filled with a third dielectric layer 81. The outer contacts 74 and 80 may protrude from the dielectric layer 81.

[0053] The heat dissipation section 62 of the electronic component 60 contains a second dielectric core layer 82, which may contain a prefabricated plate, for example, a glass fiber reinforced epoxy resin plate such as FR4. The second dielectric core layer 82 contains an opening 83 in which a heat dissipation layer 84 is arranged. The heat dissipation layer 84 contains a material with a substantially isotropic thermal conductivity, such as a metal foil or plate, for example, aluminum. The heat dissipation layer 84 may be attached in the opening 83 of the second dielectric core layer 82 by an adhesive layer positioned at the periphery of the opening 83 between the side faces of the heat dissipation layer 84 and the wall defining the opening 83 in the second dielectric core layer 82.

[0054] The heat dissipation section 62 can be mounted on the active component section 61 by means of an adhesive layer 86. The adhesive 86 can be electrically insulating to isolate the metallic heat dissipation layer 84 from the underlying first current electrode.

[0055] In other embodiments, the adhesive layer 86 can be conductive to electrically couple the heat dissipation layer 84 to the first current electrode 67. If the first current electrode 67 is a source electrode, the electrically conductive layer can be used to couple the heat dissipation layer 84 to ground potential.

[0056] The heat dissipation layer 84 is thermally coupled to the semiconductor chip 65, as it is located on the semiconductor chip 65 and separated from it only by a thin adhesive layer 86 and the third conductive layer 75. The arrangement of the outer contacts 74, 80 peripherally to the side faces of the semiconductor chip 65 and the provision of a thin first metal layer 70 on the second current electrode 69 promotes heat dissipation through the heat dissipation layer 84 and inhibits heat dissipation in the opposite direction, for example, through the outer contacts 74, 80.

[0057] Therefore, the arrangement of the outer contacts 74, 80 peripherally to the side faces of the semiconductor chip 65 can be used to provide an electronic component 60 with improved top-side cooling and reduced heat dissipation into the printed circuit board on which the outer contacts 74, 80 are mounted. The outer contacts 74, 80 can be arranged to adjust the proportion of heat dissipated from the top side relative to the proportion of heat dissipated from the top side into the printed circuit board. In some embodiments, the proportion of heat dissipated from the top side can be at least twice the proportion dissipated into the printed circuit board.

[0058] As in the Fig. As can be seen in the illustrated perspective top view of Figure 6, the second dielectric core layer 82 provides a closed peripheral frame around a central heat dissipation layer 84. The upper surface of the heat dissipation layer 84 is exposed in the upper surface 90 of the electronic component 60. The area of ​​the heat dissipation section 62 corresponds to the area of ​​the active component section 61. The active component section 61 and the heat dissipation section 62 each have a substantially planar shape.

[0059] As in the Fig.As can be seen in the perspective under-view of the electronic component 60 illustrated in Figure 6, the outer contact 80 electrically coupled to the first current electrode 67, the outer contact 74 electrically coupled to the second current electrode 69 and the outer contact 87 electrically coupled to the control electrode are positioned adjacent to the semiconductor chip 65, so that they do not cover the semiconductor chip 65.

[0060] In this particular embodiment, a single contact pad 74 is provided for the second current electrode, which extends substantially over the entire boundary region 88 of the second main surface 79 of the active component section 61. However, other arrangements of the outer contact 74 can also be used; for example, two or more outer contacts can be provided, which are electrically coupled by another conductive layer positioned within the electronic component 61, for example, by the first conductive layer 70.

[0061] The outer contact 80 coupled to the source electrode has a larger lateral area than the outer contact 86 coupled to the control electrode. In this particular embodiment, the outer contact 84 coupled to the first current electrode and the outer contact 86 coupled to the control electrode are positioned in the peripheral edge region 89 of the active component section 61 opposite the outer contact 74. However, other arrangements can be used in which the outer contacts are arranged in one, three, or four regions peripheral to the semiconductor chip 65.

[0062] The semiconductor chip can contain a transistor component, such as a vertical drift power transistor. The power transistor component can be a MOSFET, an insulated gate bipolar transistor (IGBT), or a bipolar junction transistor (BJT). For MOSFETs, the first current electrode can be the source electrode, the control electrode the gate electrode, and the second current electrode the drain electrode. For IGBTs, the first current electrode can be the emitter electrode, the control electrode the gate electrode, and the second current electrode the collector electrode. For BJTs, the first current electrode can be the emitter electrode, the control electrode the base electrode, and the second current electrode the collector electrode.

[0063] In some embodiments, the electronic component includes at least one semiconductor chip containing a switching element that includes a vertical drift path. The switching element may be a transistor or a diode. The electronic component is not limited to containing a single semiconductor chip and may also contain two or more semiconductor chips, for example, a transistor such as an IGBT and a diode, or two transistors.

[0064] The electronic component according to each of the embodiments described herein may contain two or more semiconductor chips, which may be electrically coupled to provide a desired circuit. For example, the electronic component may contain two transistor components configured to provide a half-bridge circuit, two transistor components configured as a half-bridge circuit and another logic component such as a gate driver circuit, a transistor component and a freewheeling diode, four transistors configured to provide a full-bridge circuit, etc.

[0065] Spatially related terms such as "below," "under," "lower," "above," "upper," and the like are used to simplify the description and describe the positioning of one element relative to another. These terms are intended to encompass various orientations of the component, in addition to the different orientations shown in the figures.

[0066] Furthermore, terms like "first," "second," and the like are also used to describe different elements, regions, sections, etc. Throughout the description, identical elements are referred to by the same terms.

[0067] The expressions "to exhibit," "to contain," "to include," "to encompass," and the like are open terms that indicate the presence of the mentioned elements or features but do not exclude any additional elements or features. The articles "ein," "eine," and "der," "die," "das," as well as their declensions, are intended to include both the plural and the singular unless the context clearly indicates otherwise.

[0068] It is understood that the features of the various embodiments described herein may be combined with one another, unless expressly stated otherwise.

Claims

[1] Electronic component (10), comprising: a dielectric core layer (11) with a thickness; at least one semiconductor chip (12) embedded in the dielectric core layer (11) and electrically coupled to at least one contact pad (13) arranged on a first side (14) of the dielectric core layer (11), wherein the semiconductor chip (12) has a thickness greater than or equal to the thickness of the dielectric core layer (11), and a heat dissipation layer (15) arranged on a second side (16) of the dielectric core layer (11) and thermally coupled to the semiconductor chip (12), wherein the heat dissipation layer (15) comprises a material with an isotropic thermal conductivity, where the semiconductor chip (12) is attached by an adhesive layer (20) in an opening (19) of the dielectric core layer (11); the adhesive layer (20) is positioned between the side surfaces (21) of the semiconductor chip (12) and side surfaces (22) that define the opening (19); the semiconductor chip (12) is further secured in the opening (19) by the use of reinforcing layers (23, 24) made of dielectric material; the reinforcing layers (23, 24) are positioned at the periphery of the semiconductor chip (12) and extend across the adhesive layer (20) to the second side (16) and the first side (14) of the dielectric core layer (11) and to peripheral regions of a second surface (26) and a first surface (27) of the semiconductor chip (12); and the reinforcing layers (23, 24) and the adhesive layer (20) together form an I-shaped fastening element (36). [2] Electronic component according to claim 1, further comprising metallic foil bonded to at least one section of two opposing main surfaces (14, 16) of the dielectric core layer (11). [3] Electronic component according to claim 1 or claim 2, further comprising an electrically conductive redistribution structure arranged on at least one side of the dielectric core layer (11). [4] Electronic component according to one of claims 1 to 3, further comprising at least one electrically conductive via (78) arranged in the dielectric core layer (11). [5] Electronic component according to any one of claims 1 to 4, wherein the dielectric core layer (11) has a thickness between 25 µm and 500 µm. [6] Electronic component according to any one of claims 1 to 5, wherein the base area of ​​the electronic component (10) corresponds to a JEDEC package base area. [7] Electronic component according to any one of claims 1 to 6, wherein the package outline of the electronic component (10) corresponds to a JEDEC package outline. [8] Electronic component according to any one of claims 1 to 7, further comprising a heat sink arranged on the heat dissipation layer (15). [9] Electronic component according to any one of claims 1 to 8, wherein the heat dissipation layer (15) has a top and a bottom, wherein at least one of the top and the bottom is planar. [10] Electronic component according to any one of claims 1 to 9, wherein the heat dissipation layer (15) comprises an insulating layer on at least two opposing surfaces. [11] Electronic component according to claim 10, wherein the insulating layer comprises anodized aluminium oxide. [12] Electronic component according to any one of claims 1 to 11, wherein at least the lower surface of the heat dissipation layer (15) has a surface similar to the surface of the dielectric core layer (11). [13] Electronic component according to one of claims 1 to 12, wherein at least upper edge regions of the heat dissipation layer (15) are embedded in a further insulating material. [14] Electronic component according to one of claims 1 to 13, wherein at least one of the contact pads on the first side (14) of the dielectric core layer (11) is arranged peripherally to the at least one semiconductor chip (12). [15] Electronic component according to any one of claims 1 to 14, wherein at least one of the contact pads covering the semiconductor chip (12) is arranged on the first side (14) of the dielectric core layer (11). [16] Procedure, comprehensive: Embedding at least one semiconductor chip (12) in a dielectric core layer (11), wherein the semiconductor chip (12) has a thickness that is greater than or equal to the thickness of the dielectric core layer (11); electrical coupling of the at least one semiconductor chip (11) with at least one contact pad (13) arranged on a first side (14) of the dielectric core layer (11); and Arranging a heat dissipation layer (15) on a second side of the dielectric core layer (11) and thermally coupling the heat dissipation layer (15) to the semiconductor chip (12), wherein the heat dissipation layer (15) comprises a material with an isotropic thermal conductivity. the semiconductor chip (12) is fixed by an adhesive layer (20) in an opening (19) of the dielectric core layer (11); the adhesive layer (20) is positioned between the side surfaces (21) of the semiconductor chip (12) and side surfaces (22) that define the opening (19); the semiconductor chip (12) is further secured in the opening (19) by the use of reinforcing layers (23, 24) made of dielectric material; the reinforcing layers (23, 24) are positioned at the periphery of the semiconductor chip (12) such that they extend across the adhesive layer (20) to the second side (16) and the first side (14) of the dielectric core layer (11) and to peripheral regions of a second surface (26) and a first surface (27) of the semiconductor chip (12), and that the reinforcing layers (23, 24) and the adhesive layer (20) together form an essentially I-shaped fastening element (36). [17] Method according to claim 16, further comprising arranging a heat sink on the heat dissipation layer (15). [18] Method according to claim 17, wherein the heat dissipation layer (15) comprises an insulating layer and the insulating layer is arranged on the heat dissipation layer. [19] Method according to any one of claims 16 to 18, wherein the at least one contact pad (13) is arranged on the first side (14) of the dielectric core layer (11) by applying a metallic layer to the first side (14) of the dielectric core layer (11).

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