Semiconductor component, assembly with a multitude of semiconductor components and process by which an assembly is manufactured

Abstract

Semiconductor component (300) with: a case (308); a substrate inside the housing (308); a first and a second semiconductor circuit on the substrate; and a first planar connection (302A) and a second planar connection (302B), wherein the second planar connection (302B) has a contact section, a main section and an offset section with an offset, wherein the contact section is offset relative to the main section by the offset of the offset section, the first planar terminal (302A) is electrically connected to the first semiconductor circuit, the contact section of the second planar terminal (302B) is electrically connected to the second semiconductor circuit, the first planar connection (302A) and the main section of the second planar connection (302B) are stacked on top of each other in the opposite direction to the direction of the offset of the offset section of the second planar connection (302B) such that the main section of the second planar connection (302B) lies on the first planar connection (302A), the first planar connection (302A) and the main section of the second planar connection (302B) each extend from the housing (308); the first and second semiconductor circuits are arranged in a common plane on the substrate, and the semiconductor device (300) further exhibits the following: a first busbar (304A) adjacent to the first semiconductor circuit, wherein the first planar terminal (302A) is adjacent to the first busbar (304A); and a second busbar (304B) adjacent to the second semiconductor circuit, wherein the second planar terminal (302B) is adjacent to the second busbar (304B).

Description

background

[0001] Many conventional semiconductor devices have essentially similar forms: a package with thin leads extending from it. The package can be cuboid in shape, serving to enclose and protect the circuitry inside. The leads protrude from the package and are used to electrically connect the device to other components or circuits. This form factor is used, for example, for some types of insulated-gate bipolar transistors (IGBTs).

[0002] Since semiconductor devices are used to control electrical current, the efficiency with which they control that current plays a crucial role in the efficiency of the entire device in which they are used. For example, the performance and efficiency of an inverter—a converter that transforms direct current (DC) into alternating current (AC)—depend on the performance of the semiconductor devices in its circuitry. The performance of the device, in turn, can affect the performance of a larger system. For instance, in an electric vehicle (such as a EV or a hybrid), the range of electric current before the battery needs recharging is a critical characteristic. Therefore, improved semiconductor devices can enhance the performance and efficiency of electric vehicles and other systems.

[0003] DE 10 2012 212 119 A1 describes a power semiconductor device comprising: a first chip mounting substrate on which a switching device and a freewheeling diode are mounted; a second chip mounting substrate on which a switching device and a freewheeling diode are mounted; a pair of a collector electrode and an emitter electrode to electrically connect collector and emitter conductors on the two chip mounting substrates in parallel; and a filled insulating material, wherein the collector electrode and the emitter electrode face each other.

[0004] DE 10 2009 046 914 A1 describes a busbar arrangement for the electrical coupling of the first and second busbars with first and second contacts, respectively, on a power module. The arrangement comprises a first connection, which is integrally formed with the first busbar, and a second connection, which is integrally formed with the second busbar and overlaps the first connection. Furthermore, the arrangement comprises a first bridge electrode, which is electrically coupled to the first connection on one side and to the first contact on the other, and a second bridge electrode, which is electrically coupled to the second connection on one side and to the second contact on the other. The terms "connection" and "busbar" are to be understood as defined in DE 10 2009 046 914 A1.

[0005] DE 696 35 440 T2 describes a semiconductor device comprising: a circuit substrate provided with wiring patterns along its main surface and loaded with a switching element having a pair of main electrodes, a housing that accommodates the circuit substrate, a pair of electrically conductive main current terminals connected to the wiring patterns such that the first and second end sections of each pair of first end sections are electrically coupled to the first and second main electrodes of the pair of main electrodes, and an electrical insulating element for firmly coupling the pair of main current terminals to each other while maintaining electrical insulation between them.

[0006] US Patent 6,255,672 B1 describes a semiconductor device comprising a pair of semiconductor switching elements and a circuit board. Each semiconductor switching element has positive and control electrodes formed on one surface and a negative electrode formed on the other surface. The positive and control electrodes of one of the semiconductor switching elements are connected to the circuit board, and the negative electrode of the other semiconductor switching element, oriented in the opposite direction to that of one of the semiconductor switching elements, is also connected to the circuit board. Brief description

[0007] The object of the present invention is to provide an improved arrangement of planar terminals for a semiconductor device, an assembly comprising a plurality of semiconductor devices, and a method for manufacturing such an assembly. These terminals contact busbars that are electrically connected to semiconductor circuits of the semiconductor device or the plurality of semiconductor devices. This object is achieved by the subject matter of the dependent claims. Advantageous embodiments are specified in the dependent claims. Brief description of the drawings Fig. Figure 1 shows a sectional view of an example of a semiconductor device that is not in accordance with the invention as a whole and has stacked planar terminals. Fig. Figure 2 shows a top view of the semiconductor device. Fig. 1. Fig. Figure 3 shows a sectional view of an example of a semiconductor device according to the invention, which has stacked planar terminals. Fig. Figure 4 shows a perspective view of an assembly according to the invention consisting of semiconductor components and capacitors. Fig. 5 shows a sectional view of the assembly of Fig. 4. Detailed description

[0008] The invention is explained in more detail below with reference to the figures. This document describes examples of systems and methods relating to improved semiconductor devices. In some embodiments, a semiconductor device has relatively large, planar, or flat, high-voltage terminals that are stacked on top of each other. These planar terminals and their arrangement relative to the device as a whole can enable more efficient operation of the semiconductor devices and an advantageous manufacturing process. For example, some parts of the system that are conventionally arranged around the device can instead be integrated into the same package as the device. This can improve the electrical and thermal performance of the device, reduce its inductance, and lower manufacturing and assembly costs.

[0009] Some examples mention IGBTs or inverters. However, this is only for illustrative purposes, and other configurations include transistors other than IGBTs and / or a device other than an inverter.

[0010] In a conventional IGBT, the module essentially consists of a substrate with four semiconductor circuits (also known as silicon dies or silicon chips) arranged in a generally rectangular pattern on its top surface. The module also has two busbars soldered to the silicon dies, extending away from the module. That is, each busbar is positioned on two of the silicon dies, with one end of the busbar on the substrate and the other extending beyond its edge. These busbars are typically parallel to each other and spaced approximately the same distance apart as the arrangement of the silicon dies on the substrate. During operation, current flows into the semiconductor device via one busbar, through the silicon dies, and then out of the device via the other busbar.

[0011] One of the electrical properties that negatively affects the performance of a semiconductor device is its inductance. It is therefore desirable to reduce the inductance of a device without diminishing its ability to conduct and convert current. In the IGBT described above, the inductance is proportional to the area between the busbars. Viewing the IGBT at a higher level, the individual silicon dies are connected to each other by bond wires, which also connect them to one or more of the three terminals extending from the package. The bond wires often form loops between two silicon dies or between a chip and the terminal. Here, the inductance is proportional to the area under the bond wire loop. Therefore, the performance of the semiconductor device can be improved by reducing the area between the busbars or the area under the bond wire loops.

[0012] Fig. Figure 1 shows a sectional view of an example of a semiconductor device 100 that, in its entirety, does not conform to the invention and has stacked planar terminals 102A and 102B. The device is implemented using a substrate 104. The substrate can serve to dissipate heat from the device and simultaneously provide electrical insulation for high-voltage components. In some embodiments, the substrate comprises a DBC structure (DBC: direct bonded copper). The DBC structure can, for example, comprise a ceramic layer sandwiched between copper layers, as shown.

[0013] Semiconductor circuits are implemented on the substrate. Silicon dies 106A and 106B are shown here. These silicon dies contain the circuitry that defines the individual operating modes of the entire semiconductor assembly. In some embodiments, the silicon dies define an IGBT device. The silicon dies can, for example, be fabricated as chips (occasionally referred to as silicon chips) that are then mounted onto the top of the substrate.

[0014] In this example, the semiconductor device has stacked planar terminals 102A and 102B, each adjacent to silicon dies 106A and 106B, respectively. The stacked planar terminals have an arbitrary length, extending to the left in the figure. Each terminal forms a complete plane, can be made of a conductive material, and can be soldered to its respective silicon die(s). Planar terminal 102A is adjacent to silicon die 106A and is designated positive (+) for reference. Planar terminal 102B is adjacent to silicon die 106B and is designated negative (-) for reference. That is, the terminals are stacked on top of each other, and in this example, the negative terminal overlaps the positive one. A gap 108 is formed between the planar terminals.

[0015] In particular, since the silicon dies 106A and 106B are located in a common plane (on the substrate), the planar terminal 102B has an offset section 110 along the entire width of the plane to provide a contact section 112 adjacent to the silicon die 106B. In some embodiments, the contact section forms a plane that is parallel to and offset from the plane of the main section of the planar terminal 102B. The offset section can be produced by a suitable method, such as stamping or bending.

[0016] A package 114 encloses at least part of the semiconductor device. The package may have one or more openings. In some embodiments, the package has a common opening 116 through which the planar leads 102A and 102B pass. For example, after mounting the substrate, the silicon dies, and the planar leads, the package can be formed, cast, or injection molded over this assembly so that the leads protrude from the enclosed structure.

[0017] An electrical insulator 118 can be provided in the space between the planar terminals. The insulator enables electrical insulation across the entire width of the conductive layers that form the respective planar terminals. In some embodiments, insulating paper is used.

[0018] Thus, an example of a semiconductor device 100 has been described above, comprising a package 114, a substrate 104 inside the package, semiconductor circuits 106A and 106B on the substrate, and planar terminals 102A and 102B extending from the package and electrically connected to the first and second semiconductor circuits, respectively. In particular, the planar terminals are stacked on top of each other.

[0019] This makes the inductance proportional to the area between the planar terminals 102A and 102B plus the area between terminal 102B and the substrate 104, with the negative terminal overlapping the positive terminal. This allows the inductance to be significantly reduced compared to conventional device configurations. Since, for example, the planar terminals are adjacent to the silicon dies and also extend outside the package, the busbar structure can be considered (at least partially) integrated into the package. In some of the present embodiments, connecting IGBT terminals to an external busbar layer can be avoided, thus eliminating the need to create holes in this busbar layer, which could otherwise increase the inductance.

[0020] Fig. Figure 2 shows a top view of the semiconductor device 100 of Fig. 1. Fig. Figure 2 shows how the planar connection 102A is adjacent to the silicon die 106A and the planar connection 102B is adjacent to the silicon die 106B. Because the planar connections are stacked on top of each other and one of them partially overlaps the other, connection 102A and the silicon dies 106A and 106B are shown with dashed lines. For illustrative purposes only, connection 102A is shown here as narrower than connection 102B. This arrangement allows for a greater busbar width per chip area, which improves performance. In some embodiments, the respective surfaces of the planar connections largely overlap each other. Additional semiconductor circuits are also shown. In some embodiments, these semiconductor circuits include further silicon dies 200A and 200B, which are also part of the semiconductor device.The planar connections are attached to the respective silicon dies 106A and 106B as well as 200A and 200B using a suitable method, including soldering.

[0021] Fig. Figure 3 shows a sectional view of an example of a semiconductor device 300 according to the invention, which has stacked planar terminals 302A and 302B. The silicon dies and the substrate can be essentially the same as described above. However, here, busbars 304A and 304B run in a common plane and are not stacked on top of each other. The busbars 304A and 304B can be essentially planar conductors that establish a high-voltage connection to the silicon dies. The entire busbar 304A, or a part thereof, is exposed to the outside through an opening 306 in a housing 308, which encloses at least a part of the semiconductor device. Furthermore, the entire busbar 304B, or a part thereof, is exposed to the outside through an opening 310 in the housing 308. The openings can be produced, for example, as part of an overmolding process by which the device is encapsulated in an enclosed structure.

[0022] Here, the planar terminal 302A abuts the busbar 304A outside the housing. Furthermore, the planar terminal 302B abuts the busbar 304B, at least the portion thereof exposed through the opening 310. The planar terminal and the busbar can, for example, be welded together. In some embodiments, this method can lead to a simplified manufacturing process in which the planar terminals—which may be layers wide enough to span multiple IGBTs—can be easily aligned with and connected to the component busbars. In some embodiments, both busbars can be exposed through openings in a similar manner to that shown for busbar 304B.

[0023] Similar to the previous example, the planar terminal 302B has an offset section which provides a contact section - parallel to and offset from the main section of the planar terminal - to reach at least part of its busbar.

[0024] Electrical insulation 312 can be provided in the space between the planar terminals 302A and 302B. In some embodiments, the stacked structure of these planar terminals (with the insulation) can be pre-assembled, and this assembly can then be installed into the rest of the semiconductor device to establish the electrical connections. The present example can be considered as an example where the stacking takes place outside the semiconductor package rather than inside it, which can simplify the fabrication.

[0025] Fig. Figure 4 shows a perspective view of an assembly 400 according to the invention consisting of semiconductor components 402 and capacitors 404. Fig. 5 shows a sectional view of the assembly of Fig. 4. In some configurations, capacitors are coupled to the semiconductor components to protect them from crossover voltages and to help maintain a voltage on a DC busbar. The capacitors can, for example, serve as DC coupling capacitors. Any type of capacitor conductor can be used, including layers or films (which may be folded or rolled into a compact structure).

[0026] Here, a group of six semiconductor devices 402 is shown, but more or fewer can be used in other configurations. The semiconductor packages are omitted here for clarity. The semiconductor devices are arranged side by side in a row. Each device has a substrate 406 and busbars 408A and 408B. The busbars are connected to respective semiconductor circuits on the substrates (e.g., silicon dies), which are not shown in this illustration. In particular, the silicon dies would be arranged between the respective busbars 408A and 408B and the substrate 406.

[0027] Planar terminals 410A and 410B consist of conductive layers that connect capacitors 404 to individual semiconductor devices via the busbars. The planar terminals are stacked on top of each other, so that planar terminal 410A is adjacent to busbar 408A and planar terminal 410B is adjacent to busbar 408B. At the other end of the planar terminals, they are connected to the respective conductors of the capacitors. This means that each planar terminal connects multiple semiconductor devices to each of the multiple capacitors. Fig. Figure 4 also shows that the busbars can have a significant width relative to the semiconductor device as a whole (essentially the substrate width). For example, each busbar can have a width of at least 70% of the width of the semiconductor device.

[0028] One or more of the planar terminals 410A and 410B may have a stepped shape when viewed in profile. Here, the planar terminals are essentially flat planes in the area near the semiconductor devices. To adjust the relative position of the capacitors and the semiconductor devices, planar terminal 410B (the "lower" of the terminals in this example) makes curves 412A and 412B to provide a contact plane 414B for (in this example) the lower conductor of the capacitor. Planar terminal 410A may make corresponding curves to create a contact plane 414A for the opposite capacitor conductor.

[0029] The planar connections provide a continuous conductive plane for the current flowing to and from the capacitors. This means that since there are no holes in these layers or pins at their edges where they electrically connect to the semiconductor components, there are fewer or no constrictions or "necks" to impede the current flow.

[0030] The 400 module can be part of an inverter. In some configurations, the inverter can have two (or more) 400 modules, with the semiconductor devices (e.g., IGBTs) being controlled together to perform DC-AC conversion. For example, two of these modules can be aligned so that their respective semiconductor devices are close to each other, which can simplify the placement and operation of cooling systems (e.g., liquid-based heat sinks).

[0031] An example of how to assemble a device will now be described. This description refers to some examples of components mentioned above for illustrative purposes. However, other components can also be used instead of or in addition to these.

[0032] Semiconductor devices (e.g., 402) are positioned in a row. Each semiconductor device has a substrate (e.g., 406), a first and a second semiconductor circuit (e.g., 106A and 106B) on the substrate, and a first and a second busbar (e.g., 408B and 408A) adjacent to the first and second semiconductor circuits, respectively.

[0033] An assembly is produced by bringing a first planar terminal (e.g., 410B) into contact with the first busbar (e.g., 408B) of each of the multiple semiconductor devices, and a second planar terminal (e.g., 410A) into contact with the second busbar (e.g., 408A) of each of the multiple semiconductor devices. The first and second planar terminals are stacked on top of each other. For example, the terminals can first be stacked and then (as an assembled stack) brought into contact with the respective busbars.

[0034] The first planar connection is welded to the first busbar of each of the multiple semiconductor devices. This welding can be performed from one side of the assembly. Here, a 416B weld from below the assembly is shown schematically. Similarly, the second planar connection is welded to the second busbar of each of the multiple semiconductor devices. This welding can be performed from the opposite side of the assembly. Here, a 416A weld from above the assembly is shown schematically. Laser welding, for example, can be used.

[0035] An electrical insulating layer (e.g., 118) can be inserted between the first and second planar terminals. For example, insulating paper can be inserted before the terminals are stacked on top of each other.

[0036] The first and second planar terminals can each be electrically connected to a variety of capacitors (e.g., 404). For example, individual contact planes of the terminals can be connected (e.g., welded) to the respective capacitor terminals.

[0037] Some assembly processes can involve more or fewer steps. Furthermore, two or more steps can be performed in a different order.

Claims

[1] Semiconductor device (300) with: a case (308); a substrate inside the housing (308); a first and a second semiconductor circuit on the substrate; and a first planar connection (302A) and a second planar connection (302B), wherein the second planar connection (302B) has a contact section, a main section and an offset section with an offset, wherein the contact section is offset relative to the main section by the offset of the offset section, the first planar terminal (302A) is electrically connected to the first semiconductor circuit, the contact section of the second planar terminal (302B) is electrically connected to the second semiconductor circuit, the first planar connection (302A) and the main section of the second planar connection (302B) are stacked on top of each other in the opposite direction to the direction of the offset of the offset section of the second planar connection (302B) such that the main section of the second planar connection (302B) lies on the first planar connection (302A), the first planar connection (302A) and the main section of the second planar connection (302B) each extend from the housing (308); the first and second semiconductor circuits are arranged in a common plane on the substrate, and the semiconductor device (300) further exhibits the following: a first busbar (304A) adjacent to the first semiconductor circuit, wherein the first planar terminal (302A) is adjacent to the first busbar (304A); and a second busbar (304B) adjacent to the second semiconductor circuit, wherein the second planar terminal (302B) is adjacent to the second busbar (304B). [2] Semiconductor device (300) according to claim 1, wherein the first busbar (304A) is planar and extends outwards through the housing (308) and the first planar terminal (302A) is adjacent to the first busbar (304A) outside the housing. [3] Semiconductor device (300) according to claim 1, wherein the second busbar (304B) is planar and has a section exposed through an opening (310) in the housing (308). [4] Semiconductor device (300) according to claim 3, wherein the second planar terminal (302B) is arranged on a side of the first planar terminal (302A) that is facing away from the first and second busbars (304A, 304B), and the contact section of the second planar terminal (302B) is adjacent to the section of the second busbar (304B). [5] Semiconductor device (300) according to claim 1, wherein the surface of the first planar terminal (302A) and the surface of the second planar terminal (302B) overlap each other to a large extent. [6] Assembly (400) with: a plurality of semiconductor devices (402) each comprising a substrate (406), a first and a second semiconductor circuit arranged in a common plane on the substrate (406), a first busbar (408B) adjacent to the first semiconductor circuit, and a second busbar (408A) adjacent to the second semiconductor circuit; a capacitor (404) and a first planar terminal (410B) adjacent to the first busbar (408B) of each of the plurality of semiconductor devices (402) and electrically connected to the capacitor (404), and comprising a second planar connection (410A): a contact section of the second planar terminal (410A) adjacent to the second busbar (408A) of each of the plurality of semiconductor devices (402), a main section of the second planar terminal (410A) electrically connected to the capacitor (404), and an offset section of the second planar terminal (410A) with an offset, wherein the contact section of the second planar terminal (410A) is offset relative to the main section of the second planar terminal (410A) by the offset of the offset section of the second planar terminal (410A); wherein the first planar connection (410B) and the main section of the second planar connection (410A) are stacked on top of each other in the opposite direction to the direction of the offset of the offset section of the second planar connection (410A) such that the main section of the second planar connection (410A) lies on the first planar connection (410B). [7] Device (400) according to claim 6, further comprising a plurality of capacitors (404), wherein the first planar terminal (410B) and the second planar terminal (410A) are electrically connected to each of the plurality of capacitors (404). [8] Device (400) according to claim 6, wherein the first planar terminal (410B) and the second planar terminal (410A) each have a layer extending between the capacitor (404) and the plurality of semiconductor devices (402). [9] Device (400) according to claim 8, wherein at least one of the layers has a step shape to provide a first contact plane (414B) on a remote side of the capacitor (404). [10] Device (400) according to claim 9, wherein the other of the layers also has a step shape to provide a second contact level (414A) on a near side of the capacitor (404). [11] Procedure with the following steps: Positioning semiconductor devices (402) in a row, wherein the semiconductor devices each comprise a substrate (406), a first and a second semiconductor circuit arranged in a common plane on the substrate (406), a first busbar (408B) adjacent to the first semiconductor circuit, and a second busbar (408A) adjacent to the second semiconductor circuit; Manufacturing an assembly (400) by bringing a first planar terminal (410B) into contact with the first busbar (408B) of each of the plurality of semiconductor devices (402) and by bringing a contact section of a second planar terminal (410A) into contact with the second busbar (408A) of each of the plurality of semiconductor devices, wherein the second planar terminal (410A) further comprises a main section and an offset section with an offset, wherein the contact section is offset relative to the main section by the offset of the offset section, wherein the first planar terminal (410B) and the main section of the second planar terminal (410A) are stacked on top of each other in the opposite direction to the direction of the offset of the offset section of the second planar terminal (410A) such that the main section of the second planar terminal (410A) lies on the first planar terminal (410B); Welding (416B) the first planar terminal (410B) to the first busbar (408B) of each of the plurality of semiconductor devices (402), wherein the welding is carried out from one side of the assembly (400); and Welding (416A) the contact section of the second planar terminal (410A) to the second busbar (408A) of each of the plurality of semiconductor devices (402), wherein the welding is carried out from the opposite side of the assembly (400). [12] Method according to claim 11, further comprising the introduction of an electrical insulating layer between the first planar terminal (410B) and the second planar terminal (410A). [13] Method according to claim 11, further comprising electrically connecting the first planar terminal (410B) and the second planar terminal (410A) each to a plurality of capacitors (404). [14] Method according to claim 11, wherein the welding comprises laser welding.

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