Atomic layer deposition processes and processing systems for this purpose

Abstract

Methods for the fabrication of semiconductor devices, comprising the following: Forming (204) a gate dielectric layer (106) over a substrate (102); Deposition (206) of an exit work metal layer over the gate dielectric layer (106); Performing (208) a first in-situ process (410) comprising a pretreatment process of the exit work metal layer, wherein the pretreatment process includes a precursor selected from the following group: TiCl x , TaCl x , TiF x , HfCl x WF x and WCl x , where x is between approximately 1 and approximately 6, and where the pretreatment process removes an oxidized layer of the exit work metal layer to form a treated exit work metal layer; and after carrying out (208) the first in-situ process (410), carrying out (210) a second in-situ process which includes a deposition process of another metal layer over the treated exit work metal layer, wherein the deposition (206) of the exit work metal layer over the gate dielectric layer (106) is carried out in a first chamber (3) of a processing system (500), wherein the first in-situ process is carried out in a second chamber (4) of the processing system (500) and wherein the second in-situ process is carried out in a third chamber (5) of the processing system (500), wherein the first chamber (3), the second chamber (4) and the third chamber (5) are each different chambers of the processing system (500).

Description

BACKGROUND

[0001] The electronics industry faces a steadily growing demand for smaller and faster electronic components capable of supporting a greater number of increasingly complex and sophisticated functions. Accordingly, the semiconductor industry is experiencing a continued trend toward manufacturing cost-effective and energy-efficient high-performance integrated circuits (ICs). To date, these objectives have been largely achieved by scaling down the dimensions of semiconductor ICs (for example, the minimum size of structural elements), thereby increasing production efficiency and reducing manufacturing costs. However, this scaling has also increased the complexity of the semiconductor manufacturing process. Therefore, realizing further advances in semiconductor ICs and components requires similar advances in semiconductor manufacturing processes and technology.

[0002] For example, metallic gate electrodes and gate dielectrics with high k-values ​​have replaced conventional polysilicon gate electrodes and silicon dioxide dielectrics, so that one of the major challenges now is to find metallic electrode layers with usable work functions. To this end, a wide variety of metallic electrode layers and combinations thereof with a wide variety of work functions (e.g., near a conduction band edge, near a valence band edge, or near the band gap midpoint) have been investigated for their applicability in a wide variety of device types (e.g., 2D and / or 3D N-type or P-type FETs). In general, considerable attention has been paid to various work function tuning techniques.However, in at least some current processes, the effective work function of a given metallic layer is limited by the lack of a suitable tuning mechanism. Some conventional work function tuning approaches simply adjust the thickness of the metallic layer. For example, a thicker metallic layer may occasionally be used in an attempt to overcome work function-metal stress effects. Furthermore, in some current processes, poor metal layer deposition can introduce gaps or voids in the metal layer, thereby impairing the device's performance.

[0003] Thus, current techniques have not proven satisfactory in every respect. For the state of the art, reference is made to publications US 2015 / 0061027A1, KR 1020080002602A, US 2004 / 0222474A1, US 2009 / 0053893A1, and US 2015 / 0243507A1.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood by reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. The dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1A is a cross-sectional view of a MOS transistor according to some embodiments; Fig. Figure 1B is a perspective view of an embodiment of a FinFET device according to one or more aspects of the present disclosure; Fig. 2 is a flowchart of a method for performing a pre-deposition treatment of an exit working layer according to some embodiments; Fig. Figure 3A illustrates cross-sectional diagrams of a first component processed according to an exemplary, non-standard metal gate deposition process; Fig. Figure 3B illustrates cross-sectional diagrams of a second component processed according to an exemplary, non-compliance metal gate deposition process; Fig. Figure 4A illustrates cross-sectional diagrams of a first component processed according to an exemplary metal-gate deposition process and including an in-situ pre-deposition treatment, according to some embodiments; Fig. Figure 4B illustrates cross-sectional diagrams of a second component processed according to an exemplary metal-gate deposition process and incorporating an in-situ pre-deposition treatment, according to some embodiments; Fig. 5A is a top-view diagram of an exemplary multi-chamber processing system according to some embodiments; Fig. Figure 5B shows an exemplary list of possible configurations for each of the processing chambers of the processing system of Fig. 5A as well as exemplary process flows that can be carried out in-situ, according to some embodiments; and Fig. Figure 6 illustrates a curve diagram showing a flat band tension (Vfb) as a function of various processing conditions, according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0008] It should also be noted that the present disclosure presents embodiments in the form of gate-stacking methods and related gate-stacking structures that can be used in any of a variety of different device types. For example, embodiments of the present disclosure can be used to form gate stacks suitable for use in planar bulk metal-oxide-semiconductor field-effect transistors (MOSFETs), multi-gate transistors (planar or vertical), such as FinFET devices, gate-all-around (GAA) devices, omega-gate (Ω-gate) devices or pi-gate (Π-gate) devices, as well as strain semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, or other devices known to those skilled in the art.Furthermore, the embodiments disclosed in this text can be used to form P-type and / or N-type devices. The person skilled in the art will recognize other embodiments of semiconductor devices that can benefit from aspects of this disclosure. For example, some of the embodiments described in this text can also be used in the formation of contacts, vias, or interconnect connections.

[0009] We will go to the example of Fig. Figure 1A illustrates a MOS transistor 100, which represents an example of only a single type of device that may include embodiments of the present disclosure. It is understood that the exemplary transistor 100 is in no way intended to be limiting, and the person skilled in the art recognizes that embodiments of the present disclosure may be equally applicable to any of a multitude of different types of devices, such as those described above. The transistor 100 is fabricated on a substrate 102 and includes a gate stack 104. The substrate 102 may be a semiconductor substrate, such as a silicon substrate. The substrate 102 may contain various layers, including conductive or insulating layers, formed on the substrate 102. Depending on the design requirements, the substrate 102 may contain various doping configurations, as is known to the person skilled in the art.The substrate 102 can also contain other semiconductors, such as germanium, silicon carbide (SiC), silicon-germanium (SiGe), or diamond. Alternatively, the substrate 102 can contain a composite semiconductor and / or an alloy semiconductor. Furthermore, in some embodiments, the substrate 102 can contain an epitaxial layer (epi-layer); the substrate 102 can be stretched to increase performance; the substrate 102 can contain a silicon-on-insulator (SOI) structure; and / or the substrate 102 can have other suitable optimization features.

[0010] The gate stack 104 comprises a gate dielectric 106 and a gate electrode 108 arranged on the gate dielectric 130. In some embodiments, the gate dielectric 106 may contain an interface layer, such as a silicon oxide layer (SiO2) or silicon oxynitride (SiON), wherein such an interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some examples, the gate dielectric 106 comprises a dielectric layer with a high k-value, such as hafnium oxide (HfO2).Alternatively, the high k-value dielectric layer can also contain other high k-value dielectrics, such as TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, LaO, AlO, ZrO, TiO, Ta₂O₅, Y₂O₃, SrTiO₃ (STO), BaTiO₃ (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃ (BST), Al₂O₃, Si₃N₄, oxynitrides (SiON), combinations thereof, or other suitable materials. For the purposes of this text, high k-value gate dielectrics include dielectric materials with a high dielectric constant, for example, greater than that of thermal silicon dioxide (approximately 3.9). In further embodiments, the gate dielectric 106 can contain silicon dioxide or other suitable dielectrics. The gate dielectric 106 can be formed by ALD, physical vapor deposition (PVD), oxidation, and / or other suitable methods.In some embodiments, the gate electrode 108 can be deposited as part of a gate-first or gate-last (e.g., replacement-gate) process. In various embodiments, the gate electrode 108 contains a conductive layer, such as tungsten, TiN, TaN, WN, Re, Ir, Ru, Mo, Al, Cu, Co, Ni, combinations thereof, and / or other suitable compositions. In some examples, the gate electrode 108 can contain a first metallic material for an N-type transistor and a second metallic material for a P-type transistor. Thus, the transistor 100 can incorporate a dual work-function metal-gate configuration.For example, the first metallic material (for example, for N-type devices) can contain metals with a work function that is substantially aligned with the work function of the substrate conduction band or at least substantially aligned with the work function of the conduction band of a channel region 114 of the transistor 100. Likewise, the second metallic material (for example, for P-type devices) can contain metals with a work function that is substantially aligned with the work function of the substrate valence band or at least substantially aligned with the work function of the valence band of channel region 114 of the transistor 100. Thus, the gate electrode 104 can provide a gate electrode for the transistor 100, including both N-type and P-type devices. In some embodiments, the gate electrode 108 can alternatively or additionally contain a polysilicon layer.In various examples, the gate electrode 108 can be formed by PVD, CVD, electron beam (e-beam) deposition, and / or other suitable processes. In some embodiments, sidewall spacers are formed on the sidewalls of the gate stack 104. Such a sidewall spacer can contain a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.

[0011] The transistor 100 further comprises a source region 110 and a drain region 112, each formed within the semiconductor substrate 102 adjacent to and on each side of the gate stack 104. In some embodiments, the source and drain regions 110, 112 comprise diffused source / drain regions, ion-implanted source / drain regions, epitaxially grown regions, or a combination thereof. The channel region 114 of the transistor 100 is defined as the region between the source and drain regions 110, 112 beneath the gate dielectric 106 and within the semiconductor substrate 102. The channel region 114 has an associated channel length “L” and an associated channel width “W”. When a bias voltage greater than a threshold voltage (Vt) (i.e.,When a turn-off voltage (for example, a transistor drive current) is applied to the gate electrode 108 of transistor 100, together with a simultaneously applied bias voltage between the source and drain regions 110, 112, an electric current (for example, a transistor drive current) flows between the source and drain regions 110, 112 through the channel region 114. The magnitude of the drive current that arises for a given bias voltage (which is applied, for example, to the gate electrode 108 or between the source and drain regions 110, 112) depends, among other things, on the mobility of the material used to form the channel region 114. In some examples, the channel region 114 contains silicon (Si) and / or a material with high mobility, such as germanium, as well as one of the several compound semiconductors or alloy semiconductors known to those skilled in the art.Materials with high mobility include those materials with an electron and / or hole mobility greater than silicon (Si), which has an intrinsic electron mobility at room temperature (300 K) of about 1350 cm. 2 / Vs and a hole mobility of approximately 480 cm 2 / Vs has.

[0012] We turn to Fig. Reference 1B to Figure 150 illustrates a FinFET device 150, which represents an example of an alternative device type that may include embodiments of the present disclosure. For example, the FinFET device 100 includes one or more fin-based multi-gate field-effect transistors (FETs). The FinFET device 100 includes a substrate 152, at least one fin element 154 extending from the substrate 152, insulating regions 156, and a gate structure 158 arranged on and around the fin element 154. The substrate 152 may be a semiconductor substrate, such as a silicon substrate. In various embodiments, the substrate 152 may be substantially the same as the substrate 102, as described above.

[0013] The rib element 154, like the substrate 152, can comprise silicon or another elemental semiconductor, such as germanium; a composite semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor containing SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. The ribs 154 can be fabricated using suitable processes, including photolithography and etching. The photolithography process can include: forming a photoresist layer (resist) over the substrate (for example, on a silicon layer), contacting the resist with a structure, performing firing processes after contacting, and developing the resist to form a masking element containing the resist.In some embodiments, the resist can be structured to form the masking element using an electron beam (e-beam) lithography process. The masking element can then be used to protect regions of the substrate while an etching process forms recesses in the silicon layer, leaving a long rib 154. The recesses can be etched by dry etching (for example, chemical oxide removal), wet etching, and / or other suitable processes. Numerous other embodiments of methods for forming the ribs 154 on the substrate 102 are also possible.

[0014] Each of the multiple ribs 154 also contains a source region 155 and a drain region 157, the source / drain regions 155, 157 being formed in, on, and / or around the ribs 154. The source / drain regions 155, 157 can be grown epitaxially over the ribs 154. Furthermore, a channel region of a transistor within the rib 154, located beneath the gate structure 158, is arranged along a plane that is substantially parallel to a plane defined by section AA' of Fig. 1B is defined. In some examples, the channel region of the rib contains a material with high mobility, as described above.

[0015] The insulating regions 156 can be shallow trench insulation (STI) features. Alternatively, a field oxide, a LOCOS structural element, and / or other suitable insulating structural elements can be implemented on and / or in the substrate 152. The insulating regions 156 can be formed from silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a dielectric with a low k-value, combinations thereof, and / or other suitable materials known to those skilled in the art. In one embodiment, the insulating structures are STI structural elements and are formed by etching trenches in the substrate 152. The trenches can then be filled with insulating material, followed by a chemical-mechanical polishing (CMP) process. However, other embodiments are also possible.In some embodiments, the insulating regions 156 may, for example, contain a multilayer structure having one or more lining layers.

[0016] The gate structure 158 comprises a gate stack with an interface layer 160 formed over the channel region of the rib 154, a gate dielectric layer 162 formed over the interface layer 160, and a metal layer 164 formed over the gate dielectric layer 162. In various embodiments, the interface layer 160 is essentially the same as the interface layer described as part of the gate dielectric 106. In some embodiments, the gate dielectric layer 162 is essentially the same as the gate dielectric 106 and may contain high k-value dielectrics similar to those used for the gate dielectric 106. Likewise, in various embodiments, the metal layer 164 is essentially the same as the gate electrode 108 described above.In some embodiments, sidewall spacers are formed on the sidewalls of the gate structure 158. The sidewall spacers can contain a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof.

[0017] Embodiments of the present disclosure offer advantages over the prior art, although it is understood that other embodiments may offer other advantages, that not all advantages are necessarily discussed in this text, and that no single advantage need be apparent for all embodiments. For example, embodiments discussed in this text include methods and structures relating to a pre-deposition treatment (for example, of an exit work layer) and a subsequent atomic layer deposition (ALD) process (for example, subsequent ALD metal layer deposition), as well as the structures formed thereby. In some embodiments, the pre-deposition treatment and the subsequent ALD process are carried out in situ, as described below.For the purposes of this text, the term "in-situ" is used to describe processes that are carried out while a component or substrate remains within a processing system (for example, a load-lock chamber, a transfer chamber, a processing chamber, or any other flow-coupled chamber), and the processing system allows, for example, the substrate to continue to be kept under vacuum conditions. In this sense, the term "in-situ" can also be used more generally to refer to processes in which the processed component or substrate has no contact with an external environment (for example, outside the processing system).Furthermore, although embodiments of the present disclosure are predominantly discussed with reference to N-type transistors, it is understood that the embodiments disclosed in the present text can be applied equally to P-type transistors, and the person skilled in the art can readily derive such implementations, for example, by symmetry to the implementations for N-type devices discussed below.

[0018] At least some embodiments of the present disclosure relate to the work function tuning of devices fabricated using a 10-nanometer or 7-nanometer process technology, although it is understood that the embodiments disclosed herein can be applied equally to other process technologies without departing from the scope of protection of the present disclosure. Furthermore, embodiments of the present disclosure can simultaneously be used to mitigate gap-filling effects (for example, by means of ALD processing). For the purposes of this text, the term "gap-filling effects" can be used to describe the challenge of gate metal filling (for example, in a replacement metal gate process).In some current processes, poor metal gate deposition can introduce gaps or voids in the metal gate, thereby impairing device performance. Embodiments of the present disclosure, which advantageously employ ALD processing for metal gate layer deposition, provide high-quality, conformal metal gate layers that can be substantially free of voids, thus effectively mitigating potential problems related to the effects of gap filling. Furthermore, in at least some current processes (for example, some 10- or 7-nanometer processes), the effective work function is limited by the lack of suitable tuning mechanisms. Therefore, there is a need for an effective work function tuning mechanism, for example, to further enhance device performance, that goes beyond the conventional work function tuning approach of layer thickness adjustment.For example, in at least some current processes (which use ALD for gate stack deposition, for example), work function tuning can be achieved by deposition more ALD cycles to reduce metal surface loading effects.

[0019] As described above, embodiments of the present disclosure relate to a treatment prior to deposition (for example, of an exit work layer) and a subsequent ALD process, as well as the structures formed thereby. For the purposes of this text, the term "treatment prior to deposition" may be used interchangeably with the terms "pretreatment," "pre-deposition heating," or "pre-heating." Thus, several embodiments disclosed in this text are based on the cleaning of an oxidized surface (for example, an exit work layer on which an ALD metal film is subsequently deposited) using a pre-heating or pretreatment process with a chlorine [Cl] and / or fluorine [F]-based metal precursor.When using this pre-heating or pretreatment process, the work function of the subsequently deposited ALD metal film is not dependent on a varying substrate surface or the quality of an underlying substrate (such as an underlying work function layer with an oxidized layer), which can reduce the growth rate (and thus the thickness) of the ALD metal film, resulting in an improved device threshold voltage (Vt).Thus, at least some of the advantages of the present disclosure include improving the device vt by using a preheating process with a [Cl]- and / or [F]-based metal precursor to treat an exit work setting layer (for example, an N-type exit work layer) prior to the deposition of a suitable next metal layer (for example, another exit work layer, barrier layer, capping layer, or any other suitable next metal layer), which is carried out together or sequentially (for example, in-situ) in a processing system such as a cluster tool (for example, an ALD cluster tool where chambers are grouped into a cluster).Certainly, in some embodiments, a separate ex-situ pretreatment (for example, of the exit working layer), followed by deposition of the next metal layer, can realize some advantages (for example, an improvement in the threshold voltage).

[0020] Or, put another way: Based on a free oxide, using preheating with a [Cl] / [F]-based metal precursor to clean the oxidation surface of an ALD metal film, the next work function of the ALD metal film is not dependent on various substrates to reduce its thickness growth rate and also improve the Vt. The Vt is improved using a preheating process with a [Cl] / [F]-based metal precursor and an N-metal work function chamber connected to form a cluster.

[0021] We now turn Fig. 2, where a method 200 for performing a treatment prior to deposition (for example, of the exit working layer) and a subsequent ALD process according to some embodiments is illustrated. The method 200 can be applied to a planar single-gate device, such as the exemplary transistor 100 described above with reference to Fig. 1A, as well as on a multi-gate device, such as the FinFET device 150, which was described above with reference to Fig. The method described in Section 1B can be implemented. Thus, one or more aspects discussed above with reference to transistor 100 and / or FinFET 150 can also be applied to method 200. Certainly, method 200 can be implemented in various embodiments on other devices, such as gate-all-around (GAA) devices, omega-gate (Ω-gate) devices, or pi-gate (Π-gate) devices, as well as strain semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, or other devices known to those skilled in the art.

[0022] It is understood that parts of Method 200 and / or any of the exemplary transistor devices discussed with reference to Method 200 can be fabricated by a generally known complementary metal-oxide-semiconductor (CMOS) technology process flow, which is why some processes are only briefly described in this text. Furthermore, it is understood that any exemplary transistor devices discussed in this text may include various other components and structural elements, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., but these are simplified for a better understanding of the concept of the invention in this disclosure.Furthermore, in some embodiments, the exemplary transistor device(s) disclosed in this text may contain several semiconductor devices (for example, transistors) that may be interconnected. In addition, in some embodiments, various aspects of this disclosure may apply to a gate-last process or a gate-first process.

[0023] Furthermore, in some embodiments, the exemplary transistor devices illustrated in this text may include a representation of a device at an intermediate processing stage, such as is found during the processing of an integrated circuit or a section thereof, which may include Static Random Access Memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors and inductors, and active components such as P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells and / or combinations thereof.

[0024] Let us first turn to process 200. Process 200 provides a general process flow for performing a pre-deposition treatment (for example, of the exit working layer) and a subsequent ALD process according to some embodiments. Further details of the processes and exemplary associated structures according to embodiments of the present disclosure are given below in more detail with reference to the examples of Fig. 3A / 3B and 4A / 4B are discussed. Method 200 begins at block 202, where an interface layer is formed over the substrate 102, the interface layer being substantially similar to the interface layer described above as part of the gate dielectric 106. Method 200 proceeds to block 204, where a high k-value dielectric layer is formed on the interface layer, the high k-value dielectric layer being substantially similar to the high k-value dielectric layer described above as part of the gate dielectric 106. In some cases, a high k-value capping layer may be formed over the high k-value dielectric layer.

[0025] After the formation of the high k-value dielectric layer, the process 200 then proceeds to block 206, where a work-off metal is deposited over the high k-value dielectric layer. In some embodiments, the work-off metal is part of the gate electrode 108, which is described above with reference to Fig. 1A was described. Alternatively, in some embodiments, the exit work metal is part of the metal layer 164, which is described above with reference to Fig. 1B was described. For the purposes of this text, the term “work function metal” is used to describe a layer used to set a work function value of the gate electrode 108. In various embodiments, the work function metal may comprise TiN, TaN, TiAlC, TiAl, TiSiN, TaSi, TiAlN, a combination thereof, or other suitable metals. Thus, in some embodiments, the work function metal layer deposited over the high k-value dielectric layer may comprise multiple layers configured to set the work function value of the gate electrode 108. In various examples, the work function metal may be formed using ALD. For instance, the work function metal may be deposited by ALD at a temperature of approximately 200–600°C.In some cases, the exit work metal can alternatively be formed using PVD, CVD, electron beam (e-beam) evaporation, and / or other suitable processes. In some embodiments, a surface of the deposited exit work metal (for example, deposited by ALD) can oxidize (for example, due to contact with an external environment after deposition of the exit work metal), thereby creating an ALD metal oxidation surface on the exit work metal layer.

[0026] In at least some current processes, the oxidation of the exit work metal (formation of the ALD metal oxidation surface) can lead to a stress effect on a metal layer subsequently deposited on the oxidized exit work metal. For the purposes of this text, the term "stress effect" is used to describe an undesirable change in the characteristics or properties of the metal layer deposited on the oxidized exit work metal as a result of the oxidized exit work metal. Embodiments of this disclosure allow the removal (or substantial removal) of the oxidized layer of the exit work metal prior to the deposition of a subsequent metal layer, thereby preserving the desired characteristics or properties of the subsequently deposited metal layer.

[0027] Method 200 then proceeds to Block 208, where a pretreatment process of the exit work metal is performed. In one embodiment of Block 208, the ALD metal oxidation surface (for example, the oxidized layer of the exit work metal) can be removed by a pretreatment process containing a Cl-based or F-based metal precursor to treat the ALD metal oxidation surface prior to the deposition of a subsequent metal film over the exit work metal. In some embodiments, the Cl-based or F-based metal precursor contains TiClx, TaClx, TiFx, HfClx, WFx, or WClx, where “x” is approximately equal to 1–6. In various embodiments, the pretreatment process and the subsequent metal film deposition are, for example, an in-situ process performed within a processing system, such as an ALD cluster tool.For example, the Cl-based or F-based metal precursor can be introduced into a processing chamber of the processing system (where, for example, the processing chamber contains the substrate with the ALD metal oxidation surface) during the pretreatment process, for example at a pretreatment processing temperature of about 300-1000°C and with a flow rate of about 100-8000 standard cubic centimeters per minute (sccm).In various examples, the pretreatment processing conditions (for example, including the selection of the Cl-based or F-based metal precursor, the pretreatment temperature, and the flow rate of the Cl-based or F-based metal precursor) are selected to induce a thermal chemical reaction between the Cl-based or F-based metal precursor and the ALD metal oxidation surface. This reaction results in the oxidized layer of the exit work metal being removed or purified, leaving behind a non-oxidized, clean exit work metal surface. Certainly, in some embodiments, a separate ex-situ pretreatment (for example, of the exit work layer), followed by deposition of the next metal layer, can also offer certain advantages (for example, an improvement in the threshold stress).

[0028] Following the pretreatment process, the process 200 then proceeds to block 210, where a subsequent metal layer is deposited over the pretreated exit work metal. In some embodiments, the subsequent metal layer comprises an N-metal layer (such as TiAlC) and a TiN layer over the N-metal layer, and in some examples, the subsequent metal layer can be deposited by ALD. For example, in some embodiments, the subsequent metal layer can also be part of the gate electrode 108, which is described above with reference to Fig. 1A was described. Alternatively, in some embodiments, the next metal layer can also be part of metal layer 164, which was described above with reference to Fig. as described in Section 1B. Furthermore, in some embodiments, the next metal layer or layers deposited over the pretreated exit work layer may contain one or more other layers (for example, in addition to those described above). In some cases, the next one or more metal layers and any other layers deposited over the pretreated exit work layer may also be used to adjust the value of the exit work of the gate electrode 108. Since the oxidized layer of the exit work metal has been cleaned or removed during the pretreatment process, as described above, the next metal layer may, in particular, be deposited on the non-oxidized, clean exit work metal surface.This ensures that the desired characteristics or properties of the deposited next metal layer are retained, as the next metal layer is not subject to any stress effects (for example, due to an oxidized layer) from the underlying exit metal. As a further result, embodiments of the present disclosure lead to devices (for example, transistor 100) with an improved threshold voltage and improved device reliability.

[0029] The component manufactured according to method 200 (for example, transistor 100) can be further processed to form various structural elements and regions known to those skilled in the art. For example, subsequent processing can form various contacts, vias, and conductors, as well as multilayer interconnect structural elements (for example, metal layers and interlayer dielectrics) on the substrate containing the component. These interconnects are configured to connect the various structural elements to form a functional circuit that can contain one or more components (for example, one or more transistors 100). Continuing with this example, a multilayer interconnect can include vertical interconnect connections, such as vias or contacts, and horizontal interconnect connections, such as metallic conductors.The various interconnect structure elements can utilize different conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual-damascene process is used to form a copper-based multilayer interconnect structure. Furthermore, additional process steps can be implemented before, during, and after Method 200, and some of the process steps described above can be substituted or omitted according to different embodiments of Method 200.

[0030] We now turn to the Fig. 3A / 3B and 4A / 4B, which illustrate process flows for exemplary metal gate deposition processes. In particular, the Fig. 3A and Fig. 3B illustrates a process flow for a metal-gate deposition process, where the pretreatment process of the exit work metal and the deposition of the next metal layer (for example, TiAlC) on the pretreated exit work metal are not performed in situ. Alternatively, the Fig. 4A and Fig. 4B a process flow for a metal-gate deposition process according to various embodiments, in which the pretreatment process of the exit work metal and the deposition of the next metal layer on the pretreated exit work metal are carried out in situ. It should be noted that the Fig. Figures 3A / 3B and 4A / 4B illustrate exemplary compositions for stacking layers (for example, for a metal gate stack). These exemplary compositions serve only for better understanding and are not intended to represent a limitation to what is expressly claimed here.Various compositions within the scope of protection of this disclosure may (for example, within a single gate stack) include one or more exit-work layers, one or more barrier layers, one or more capping layers, one or more metal-filling layers, one or more polysilicon layers, one or more silicide layers, one or more doped layers, or other suitable layers, including—and / or beyond—those layers expressly mentioned herein and which may be configured as required or desired for a given technology or application. Furthermore, in some embodiments, the pretreatment process and subsequent metal layer deposition may be repeated multiple times for a given gate stack.In some examples, the pretreatment process can be repeated multiple times to treat a specific metal layer (for example, a specific exit work metal layer) before the deposition of a subsequent metal layer.

[0031] Starting with the exemplary processes of the Fig. 3A / 3B, illustrated Fig. 3A a method 302 for forming an illustrative gate stack that can be used for a first type of device (for example, for an N-type ultra-low threshold voltage (N-uLVT) device), and Fig. Figure 3B illustrates a procedure 304 for forming an illustrative gate stack that can be used for a second type of device (for example, for an N-type standard threshold voltage (N-SVT) device). It should be noted that the illustrative gate stacks and exemplary processes referred to in the Fig. The methods shown and described in 3A / 3B can be applied to any type of component, which may, for example, have a variety of different types of exit metal layers and / or combinations of layers, as described above.

[0032] We turn first to step 306. Each of the processes 302 (for example, for the N-uLVT device) and 304 (for example, for the N-SVT device) can begin with the formation of a high k-value cap layer (HK CAP), which can be formed over a high k-value gate dielectric layer, as described above, for example. In some embodiments, the HK CAP layer can be a lanthanum-based oxide layer (for example, LaO₂). x). In some examples, the HK CAP layer may contain other layers, such as an Al₂O₃ layer, a SiO₂ layer, a Y₂O₃ layer, a TiN layer, a TiSiN layer, a combination thereof, or another suitable capping layer. We remain at step 306, in which a TaN layer may be formed over the HK CAP layer for each of methods 302 (for example, for the N-uLVT device) and 304 (for example, for the N-SVT device). In various embodiments, the TaN layer may be the exit work metal, as described above. In various examples, the TaN layer may be part of the gate electrode 108 or the metal layer 164, which is described above with reference to Fig. 1A or Fig. 1B were described.

[0033] We turn next to step 308, where a TiN layer can be formed over the TaN layer for procedure 304 (for example, for the N-SVT device). In various examples, the TiN layer can also be part of the gate electrode 108 or the metal layer 164, which were mentioned above with reference to Fig. 1A or Fig. 1B. In some embodiments, the formation of the TiN layer (for example, over the TaN layer) can be carried out to adjust the threshold voltage of the N-SVT device and / or to serve as an additional exit work metal. In some embodiments, a surface of the TaN layer (for example, for the N-uLVT device) and / or a surface of the TiN layer (for example, for the N-SVT device) can oxidize (for example, due to contact with an external environment after deposition of the exit work metal), thereby creating an ALD metal oxidation surface.

[0034] We next turn to step 310, where each of processes 302 (for example, for the N-uLVT device) and 304 (for example, for the N-SVT device) can proceed to perform a pretreatment process. As described above, the pretreatment process can involve a Cl-based or F-based metal precursor, such as TiClx, TaClx, TiFx, HfClx, WFx, or WClx, where "x" is approximately equal to 1–6. For example, during the pretreatment process, the Cl-based or F-based metal precursor can be introduced into a processing chamber of the processing system (where, for example, the processing chamber contains the substrate with the ALD metal oxidation surface) at a pretreatment processing temperature of approximately 300–1000°C and a flow rate of approximately 100–8000 standard cubic centimeters per minute (sccm).In various examples, the pretreatment processing conditions (for example, including the selection of the Cl-based or F-based metal precursor, the pretreatment temperature, and the flow rate of the Cl-based or F-based metal precursor) can be selected to induce a thermal chemical reaction between the Cl-based or F-based metal precursor and a surface of the TiN layer (for example, for the N-SVT device). As a result of the pretreatment process of step 310, an oxidized layer of the TaN layer (for example, for the N-uLVT device) and / or an oxidized layer of the TiN layer (for example, for the N-SVT device) is removed or purified. In some examples, the TaN layer (for example, for the N-uLVT device) can be substantially completely oxidized.In some embodiments, the pretreatment process of step 310 can, in some cases, completely remove such a fully oxidized TaN layer (for example, for the N-uLVT device), thereby exposing the underlying HK CAP layer (for example, for the N-uLVT device).

[0035] We now turn to step 312. After performing the pretreatment process of step 310, each of the devices (for example, the N-uLVT device and the N-SVT device) can be removed from the processing system in which the pretreatment process was performed. For example, the N-uLVT device and the N-SVT device can be transferred ex-situ to another processing system and / or another processing chamber of the processing system for subsequent processing. As a result of this ex-situ transfer, the previously cleaned TaN layer (for example, for the N-uLVT device) and / or the previously cleaned TiN layer (for example, for the N-SVT device) can partially re-oxidize.In some examples, if the TaN layer (for example, for the N-uLVT device) is essentially completely oxidized and the pretreatment process completely removes such an oxidized TaN layer, the exposed and underlying HK CAP layer (for example, for the N-uLVT device) may be partially oxidized. In some embodiments, and despite the possibility of re-oxidation due to the ex-situ process, the pretreatment process can still achieve an improvement in device performance (for example, due to an improved Vt), as shown below with reference to [reference to figure]. Fig. 6 will be discussed in more detail. Then (where we remain at step 312, and as in the Fig. (as shown in 3A / 3B) a TiN layer / N-metal layer stack (in some examples a TiN / TiAlC stack, where, for example, the N-metal contains TiAlC) is deposited (for example, by ALD) over each of the devices (for example, the N-uLVT device and the N-SVT device). In various examples, the TiN layer / N-metal layer stack can be part of the gate electrode 108 or the metal layer 164, which are described above with reference to Fig. 1A or Fig. 1B. In some embodiments, due to the partial re-oxidation of underlying layers, the TiN layer / N-metal layer stack can be deposited onto a partially oxidized underlying surface. This can result in the desired characteristics or properties of the deposited TiN layer / N-metal layer stack being subject to some stress effects. However, it should be noted that the pretreatment process can still improve device performance, particularly compared to a device that does not undergo such a pretreatment process. Thus, in some embodiments, devices (for example, transistor 100) manufactured according to the embodiments of methods 302 / 304 can exhibit, for example, improved threshold voltage and improved device reliability compared to a device that does not undergo such a pretreatment process.

[0036] We now turn to step 314, where an adhesive layer can be deposited over the TiN layer / N-metal layer stack (for example, in some examples by ALD) for each of the devices (for example, the N-uLVT and N-SVT devices). In some examples, the adhesive layer contains a TiN-BLK layer; however, other adhesive layers known to those skilled in the art can likewise be used without departing from the scope of this disclosure. In some embodiments, a nucleating layer 309 (such as a tungsten (W) nucleating layer deposited by ALD) can be deposited over the adhesive layer, and a tungsten (W) filler layer can then be deposited (for example, by ALD) over the nucleating layer 309. In various examples, the adhesive layer, the nucleating layer 309, and the W filler layer can be part of the gate electrode 108 or the metal layer 164 described above with reference to Fig. 1A or Fig. 1B. Furthermore, embodiments of the present disclosure, which advantageously employ ALD processing for the deposition of the metal gate layers, provide high-quality, conformal metal gate layers that can be substantially free of vacancies and thereby effectively mitigate potential problems associated with the effects of vacancy filling. Thus, for example, in some embodiments the W-filler layer can be deposited as a substantially vacancy-free layer.

[0037] The illustrative components (for example, the N-uLVT and N-SVT components) of methods 302 / 304 can be further processed to form various structural elements and regions known to those skilled in the art. For example, subsequent processing can form various contacts, vias, and conductors, as well as multilayer interconnect structural elements (for example, metal layers and interlayer dielectrics) on the substrate containing the N-uLVT and N-SVT components, configured to connect the various structural elements to form a functional circuit that may contain one or more N-uLVT and N-SVT components. Continuing with the example, a multilayer interconnect can include vertical interconnect connections, such as vias or contacts, and horizontal interconnect connections, such as metallic conductors.The various interconnect structure elements can utilize different conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual-damascene process is used to form a copper-based multilayer interconnect structure. Furthermore, additional process steps can be implemented before, during, and after methods 302 / 304, and some of the process steps described above can be substituted or omitted according to various embodiments of methods 302 / 304.

[0038] We now turn to the Fig. 4A and Fig. 4B, in which a process flow for a metal-gate deposition process according to embodiments of the present disclosure is illustrated, wherein the pretreatment process of the exit work metal and the deposition of the next metal layer (such as TiAlC) on the pretreated exit work metal are carried out in situ. Starting with the Fig. 4A / 4B, and according to various embodiments, illustrated Fig. 4A a method 402 for forming an illustrative gate stack that can be used for a first type of device (for example, for an N-type ultra-low threshold voltage (N-uLVT) device), and Fig. Figure 4B illustrates a Method 404 for forming an illustrative gate stack that can be used for a second type of device (for example, for an N-type standard threshold voltage (N-SVT) device). It should be noted that the illustrative gate stacks and exemplary processes referenced in the Fig. The processes shown and described in 4A / 4B can be applied to any type of device that, for example, has a variety of different types of exit metal layers and / or combinations of layers, as described above. It should also be noted that various aspects of processes 402 and 404 are essentially similar to processes 302 and 304, respectively, which are described above with reference to the Fig. 3A and Fig. 3B were discussed. Therefore, in the interest of better understanding, some aspects of procedures 402 and 404 may only be discussed briefly.

[0039] We turn first to step 406. Similar to step 306 of processes 302 / 304, each of processes 402 (for example, for the N-uLVT device) and 404 (for example, for the N-SVT device) can begin with the formation of a high k-value capping layer (HK CAP) that is a lanthanum-based oxide layer (for example, LaO₂). x ), may contain an Al2O3 layer, a SiO2 layer, a Y2O3 layer, a TiN layer, a TiSiN layer, a combination thereof, or another suitable capping layer. We remain at step 406, in which a TaN layer can be formed over the HK CAP layer for each of methods 402 (for example, for the N-uLVT device) and 404 (for example, for the N-SVT device). In various embodiments, the TaN layer can be the exit work metal, as described above. In various examples, the TaN layer can be part of the gate electrode 108 or the metal layer 164, which is described above with reference to Fig. 1A or Fig. 1B were described.

[0040] We now turn to step 408. Similar to step 308 of procedures 302 / 304, a TiN layer can be formed over the TaN layer for procedure 404 (for example, for the N-SVT device). In various examples, the TiN layer can also be part of the gate electrode 108 or the metal layer 164, which were mentioned above with reference to Fig. 1A or Fig. 1B described. In some embodiments, a surface of the TaN layer (for example, for the N-uLVT device) and / or a surface of the TiN layer (for example, for the N-SVT device) can oxidize (for example, due to contact with an external environment after deposition of the exit work metal), resulting in an ALD metal oxidation surface.

[0041] We now turn to step 410, where procedures 402 and 404 differ from the procedures 302 / 304 discussed above. For example, procedures 302 / 304 provided an ex-situ process for the pretreatment process and subsequent TiN / N-metal layer stacking (shown, for example, as separate steps 310 and 312), whereas procedures 402 / 404 provide an in-situ process for the pretreatment process and subsequent TiN / N-metal layer stacking. For example, the two separate steps 310 and 312 of procedures 302 / 304 are combined into a single in-situ step 410 of procedures 402 / 404. It should be noted that element 409 is used to indicate processes that are performed in-situ for each of the procedures 402 / 404, as described in this text.

[0042] Thus, continuing with step 410, each of processes 402 (for example, for the N-uLVT device) and 404 (for example, for the N-SVT device) can proceed to perform a pretreatment process. As described above, the pretreatment process can involve a Cl-based or F-based metal precursor, such as TiClx, TaClx, TiFx, HfClx, WFx, or WClx, where "x" is approximately equal to 1-6. For example, during the pretreatment process, the Cl-based or F-based metal precursor can be introduced into a processing chamber of the processing system (where, for example, the processing chamber contains the substrate with the ALD metal oxidation surface) at a pretreatment processing temperature of approximately 300-1000°C and a flow rate of approximately 100-8000 standard cubic centimeters per minute (sccm).In various examples, the pretreatment processing conditions (for example, including the selection of the Cl-based or F-based metal precursor, the pretreatment temperature, and the flow rate of the Cl-based or F-based metal precursor) can be selected to induce a thermal chemical reaction between the Cl-based or F-based metal precursor and a surface of the TiN layer (for example, for the N-uLVT device) or between the Cl-based or F-based metal precursor and a surface of the TiN layer (for example, for the N-SVT device). As a result of the pretreatment process, an oxidized layer of the TaN layer (for example, for the N-uLVT device) and / or an oxidized layer of the TiN layer (for example, for the N-SVT device) is removed or purified.In some examples, the TaN layer (for example, for the N-uLVT device) can be essentially completely oxidized, as discussed above. As a result, in some embodiments, the pretreatment process can, in some cases, completely remove such a fully oxidized TaN layer (for example, for the N-uLVT device), thereby exposing the underlying HK CAP layer (for example, for the N-uLVT device).

[0043] For the in-situ process of Fig. 4A / 4B – after the pretreatment process has been carried out – the processed substrate can remain within the processing system or chamber used to perform the pretreatment process in order to prevent the substrate from coming into contact with an external environment (for example, outside the processing system) and to avoid possible re-oxidation of exposed layers. Thus, then – staying with step 410 – after the pretreatment process has been carried out, and as described in the Fig. As shown in Figures 4A / 4B, a TiN layer / N metal layer stack (in some examples a TiN / TiAlC stack) is formed over each of the devices (for example, the N-uLVT device and the N-SVT device). In various examples, the TiN layer / N metal layer stack can be part of the gate electrode 108 or the metal layer 164, which are described above with reference to Fig. 1A or Fig. 1B were described. Due to the in-situ form of the methods of Fig. In embodiments 4A / 4B, where all underlying layers remain non-oxidized and clean, the TiN layer / N-metal layer stack can be deposited onto a non-oxidized, clean underlying surface. This preserves the desired characteristics or properties of the deposited TiN layer / N-metal layer stack, as the stack is not subjected to any stress effects (e.g., due to an oxidized layer) from the underlying layer(s). As a further result, devices produced according to embodiments of methods 402 / 404 (e.g., transistor 100) exhibit improved threshold voltage and improved device reliability.In some embodiments, components manufactured according to the embodiments of methods 402 / 404 may additionally exhibit, for example, improved threshold voltage and improved component reliability compared to a component manufactured according to methods 302 / 304 described above.

[0044] We now turn to step 412. Similar to step 314 of methods 302 / 304, the adhesive layer can then be deposited over each TiN layer / N-metal layer stack (for example, in some examples by ALD) for each of the devices (for example, the N-uLVT and N-SVT devices). As discussed above, and in some examples, the adhesive layer can contain a TiN-BLK layer; however, other adhesive layers known to those skilled in the art can likewise be used without departing from the scope of this disclosure. In some embodiments, the nucleation layer 309 (such as a tungsten (W) nucleation layer deposited by ALD) can then be deposited over the adhesive layer, and a tungsten (W) filler layer can be deposited (for example, by ALD) over the nucleation layer 309.In various examples, the glue layer, the nucleation layer 309 and the W-filler layer can be part of the gate electrode 108 or the metal layer 164, which are referred to above. Fig. 1A or Fig. 1B. Furthermore, embodiments of the present disclosure, which advantageously employ ALD processing for the deposition of the metal gate layers, provide high-quality, conformal metal gate layers that can be substantially free of vacancies and thereby effectively mitigate potential problems associated with the effects of vacancy filling. Thus, for example, in some embodiments the W-filler layer can be deposited as a substantially vacancy-free layer.

[0045] The illustrative components (for example, the N-uLVT and N-SVT components) of methods 402 / 404 can be further processed to form various structural elements and regions known to those skilled in the art. For example, subsequent processing can form various contacts, vias, and conductors, as well as multilayer interconnect structural elements (for example, metal layers and interlayer dielectrics) on the substrate containing the N-uLVT and N-SVT components, configured to connect the various structural elements to form a functional circuit that may contain one or more N-uLVT and N-SVT components. Continuing with the example, a multilayer interconnect can include vertical interconnect connections, such as vias or contacts, and horizontal interconnect connections, such as metallic conductors.The various interconnect structure elements can utilize different conductive materials, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual-damascene process is used to form a copper-based multilayer interconnect structure. Furthermore, additional process steps can be implemented before, during, and after methods 402 / 404, and some of the process steps described above can be substituted or omitted according to various embodiments of methods 402 / 404.

[0046] We now turn Fig. Figure 5A illustrates a top-down diagram of an exemplary multi-chamber processing system 500. In some embodiments, the system 500 can also be referred to as a "cluster tool". The system 500 can generally include load-lock chambers 502, 504, a wafer handling chamber 506, and several processing chambers 1-6. In various embodiments, the load-lock chambers 502, 504 allow the transfer of substrates into and out of the system 500. In various embodiments, the system 500 is under vacuum (generated, for example, by a vacuum system that may include a mechanical pump, a turbomolecular pump, a cryopump, or another suitable vacuum pump), and the load-lock chambers 502, 504 can "pump down" the substrates that have been introduced into the system 500 (for example, by means of the vacuum system).In some embodiments, the load-lock chambers 502, 504 can be configured to receive a single wafer or multiple wafers (for example, loaded into a cassette). For example, the load-lock chambers 502, 504 can be separated from the wafer handling chamber 506 by a slide valve, so that the wafer handling chamber 506 can remain under vacuum when one or both of the load-lock chambers 502, 504 are vented.

[0047] In various embodiments, the wafer handling chamber 506 is equipped with an automated transfer arm 507 (for example, a robotic transfer arm) that can move uniformly along a horizontal, vertical, and / or rotational axis to transfer substrates between the load-lock chambers 502, 504, and the substrate processing chambers 1-6. Each processing chamber 1-6 can be configured to perform a range of substrate processing operations, such as atomic layer deposition (ALD), CVD, PVD, etching, pretreatment / preheating, degassing, or annealing, as well as a range of metrology operations, such as XPS analysis, AFM analysis, and / or other suitable processing or metrology operations.In various embodiments, the System 500 can have more or fewer processing chambers, as is necessary, for example, for a specific process that is to be carried out by the System 500.

[0048] We turn to the example of Fig. 5B to, where an exemplary list of possible configurations for each of the processing chambers 1-6 for the System 500 of Fig. 5A is illustrated according to some embodiments. For example, in some embodiments, processing chamber 1 can be configured for the deposition of the high k-value dielectric layer (for example, as part of the gate dielectric 106); processing chamber 2 can be configured for the deposition of TiN, TiSiN, and the HK CAP layer (or for the deposition of an HK CAP layer containing a TiN / TiSiN stack); processing chamber 3 can be configured for the deposition of TaN; processing chamber 4 can be configured to perform the preheating or pretreatment process with a [Cl]- and / or fluorine [F]-based metal precursor; processing chamber 5 can be configured for the deposition of the N-metal layer (such as TiAlC); and processing chamber 6 can be configured for the deposition of TiN or TiN / Co.It is understood that these processing chamber configurations are merely exemplary and are in no way intended to be restrictive. For illustrative purposes, the in-situ processes described above may include processes that are executed within a given processing chamber (for example, processing chamber 1-6), or they may include processes where a first process is executed in a first processing chamber and the substrate is transferred to a second processing chamber (for example, via wafer handling chamber 506), with a second process being executed in the second processing chamber.Notwithstanding the implementation of the in-situ process, the in-situ processes described in this text may include processes that are executed while a component or substrate remains within the system 500 (for example, including the load-lock chambers 502, 504, the wafer handling chamber 506 and / or one of the processing chambers 1-6) and where, for example, the system 500 remains under vacuum.

[0049] Fig. Figure 5B further illustrates, with reference to arrows 510, 512, 514, 516, and 518, some exemplary process flows that can be performed in situ. For example, with reference to arrow 510 and in some illustrative examples, the pretreatment process (chamber 4) using a [Cl]- and / or fluorine [F]-based metal precursor and the N-metal layer deposition (chamber 5) can both be performed in situ (and in some cases sequentially). As another example, with reference to arrow 512 and in some illustrative examples, the pretreatment process (chamber 4) using a [Cl]- and / or fluorine [F]-based metal precursor, the N-metal layer deposition (chamber 5), and the TiN or TiN / Co deposition (chamber 6) can all be performed in situ (and in some cases sequentially).Referring to the example of arrow 514, and in some illustrative embodiments, the TaN layer deposition (chamber 3), the pretreatment process (chamber 4) using a [Cl] and / or fluorine [F]-based metal precursor, the N metal layer deposition (chamber 5) and the TiN or TiN / Co deposition (chamber 6) can all be carried out in situ (and in some cases sequentially). Referring to the example of arrow 516, and in some illustrative embodiments, the HK CAP layer deposition (chamber 2), the TaN layer deposition (chamber 3), the pretreatment process using a [Cl] and / or fluorine [F]-based metal precursor (chamber 4), the N metal layer deposition (chamber 5) and the TiN or TiN / Co deposition (chamber 6) can all be carried out in situ (and in some cases sequentially).Referring to the example of arrow 518, and in some illustrative embodiments, the deposition of the high k-value dielectric layer (chamber 1), the HK CAP layer deposition (chamber 2), the TaN layer deposition (chamber 3), the pretreatment process operating with a [Cl] and / or fluorine [F]-based metal precursor (chamber 4), the N metal layer deposition (chamber 5) and the TiN or TiN / Co deposition (chamber 6) can all be carried out in situ (and in some cases sequentially).

[0050] We now turn Fig. Figure 6 illustrates a curve diagram 600 showing a flat-band voltage (Vfb) as a function of various processing conditions and further illustrates the usefulness for the device threshold voltage (Vt) for devices processed according to embodiments of the present disclosure. For better understanding of the discussion, it should be noted that the transistor threshold voltage (Vt) and the flat-band voltage (Vfb) can be generally expressed as: Vt=Vfb+2qεNA2φBCox Vfb=φms+2φB−QfCox

[0051] From these two expressions for Vt and Vfb, it is clear that Vt is influenced by changes in the flat-band voltage. As a reference point, we consider devices 602, 604, and 606, which contain a TiAlC layer over a TaN layer and a TiN layer over the TiAlC layer. In some cases, the TaN layer may be the exit-work layer described above, the TiAlC layer may be the N-metal layer described above, and the TiN layer may be part of the next metal layer described above (which may contain the stack of TiAlC and TiN). For example, and in some embodiments, the TaN layer may have a thickness of about 15 angstroms, and the TiN layer may have a thickness of about 10 angstroms. Furthermore, it should be noted that elements 608, 610 and 612 are used to indicate processes that can be executed in-situ for each of the components 602, 604 and 606 respectively, as described above.In addition, flashing light symbols (which are also in the . Fig. 3A / 3B and 4A / 4B were used) to indicate that the pretreatment process is being carried out for the given components (604 and 606).

[0052] Therefore, starting with component 602, it should be noted that the pretreatment process described in this text is not performed. After deposition of the TaN layer, the TiAlC and TiN layers can be deposited sequentially in-situ over the TaN layer. According to measurements, the resulting manufactured component with component 602 has a flat-band voltage (Vfb) of approximately -380 mV.

[0053] We will next turn to component 604. After deposition of the TaN layer, an ex-situ pretreatment process can be carried out, for example, as described above with reference to procedures 302 / 304. In the example of Fig. 6. The pretreatment process applied to the TaN layer of device 604 can include WCl5 gas treatment. However, as described above, other [Cl]- and / or fluorine [F]-based metal precursors can also be used to perform the pretreatment process described in this text. Subsequently, the TiAlC and TiN layers can be deposited sequentially in situ over the pretreated TaN layer. The resulting fabricated device, which contains device 604, has a flat band voltage (Vfb) of approximately -560 mV according to measurements. Thus, the WCl5 gas treatment for device 604 results in a Vfb shift of approximately -180 mV compared to device 602, which did not undergo a pretreatment process. In other words, the WCl5 gas treatment for device 604 leads to a band edge shift of approximately -180 mV for the TaN layer.In some embodiments, “band edge shift” can be used to describe the conduction band edge shift (for example, for NMOS transistors) or the valence band edge shift (for example, for PMOS transistors), so that one can say that the pretreatment process has tuned the work function of the work function layer (for example, the TaN layer).

[0054] With reference to component 606, for example, an in-situ pretreatment process can be carried out after the deposition of the TaN layer, as described above with reference to processes 402 / 404. In the example of Fig.6. The pretreatment process applied to the TaN layer of device 604 can include WCl5 gas treatment. However, as described above, other [Cl]- and / or fluorine [F]-based metal precursors can also be used to perform the pretreatment process described in this document. After performing the pretreatment process (for example, of the TaN layer for device 606), the processed substrate can remain within the processing system or chamber used to perform the pretreatment process. This prevents the substrate from coming into contact with an external environment (for example, outside the processing system) and avoids possible re-oxidation of exposed layers (for example, the TaN layer). Thus, after performing the pretreatment process, the TiAlC and TiN layers can be sequentially deposited in situ over the pretreated TaN layer.The resulting manufactured device, which contains component 606, has a measured flat band voltage (Vfb) of approximately -587 mV. Thus, the combined in-situ WCl5 gas treatment and subsequent deposition of the TiAlC and TiN layers for component 606 leads to a Vfb shift of approximately -27 mV compared to component 604, where the ex-situ pretreatment process is performed. In other words, the combined in-situ WCl5 gas treatment and subsequent deposition of the TiAlC and TiN layers for component 606 results in an additional band edge shift of approximately -27 mV for the TiN layer compared to component 604.

[0055] The various embodiments described in this text offer several advantages over the prior art. It is understood that not all advantages have necessarily been discussed in this text, that no single advantage need be apparent for all embodiments, and that other embodiments may offer different advantages. For example, embodiments discussed in this text include methods and structures relating to a pretreatment (for example, of an exit work layer) and a subsequent atomic layer deposition (ALD) process (for example, subsequent ALD metal layer deposition) over the pretreated layer. Furthermore, embodiments of this disclosure can be effectively used to achieve exit work tuning, as described above.In various embodiments, the pretreatment process preceding deposition involves cleaning an oxidized surface (for example, an exit working layer) using a preheating or pretreatment process with a chlorine [Cl] and / or fluorine [F]-based metal precursor. The pretreatment process described in this text can effectively reduce metal surface stress effects (for example, of the exit working layer), leading to an improved device threshold voltage (Vt).Thus, at least some of the advantages of the present disclosure include improving the device performance by using a preheating process with a [Cl]- and / or [F]-based metal precursor to treat an exit work setting layer (for example, an N-type exit work layer) prior to the deposition of a suitable next metal layer (for example, another exit work layer, barrier layer, capping layer, or any other suitable next metal layer), which is carried out together or sequentially (for example, in situ) in a processing system, such as a cluster tool (for example, an ALD cluster tool where chambers are grouped into a cluster). Embodiments of the present disclosure can also be used simultaneously to mitigate gap-filling effects (for example, by means of ALD processing), as described above.Certainly, in some embodiments, a separate ex-situ pretreatment (for example, of the exit working layer), followed by deposition of the next metal layer, can realize some advantages (for example, an improvement in the threshold voltage).

[0056] Thus, one embodiment of the present disclosure describes a method for fabricating a semiconductor device, wherein the method includes forming a gate dielectric layer over a substrate and depositing a work-source metal layer over the gate dielectric layer. In some embodiments, a first in-situ process is performed, which includes a pretreatment process of the work-source metal layer. For example, the pretreatment process removes an oxidized layer of the work-source metal layer to form a treated work-source metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process is performed, which includes a deposition process of another metal layer over the treated work-source metal layer.

[0057] In another embodiment, a method is discussed in which a gate dielectric layer is formed over a substrate in a first chamber of an evacuated processing system. Subsequently, while maintaining a vacuum in the processing system, an exit work metal layer is deposited over the gate dielectric layer in a second chamber of the evacuated processing system. In some embodiments, the substrate is transferred to a third chamber of the evacuated processing system while maintaining the vacuum, and a pretreatment process of the exit work metal layer is performed in the third chamber, resulting in a treated exit work metal layer.For example, the substrate can then be transferred to a fourth chamber of the evacuated processing system while maintaining the vacuum state of the evacuated processing system, and a subsequent metal layer can be deposited over the treated exit work metal layer in the fourth chamber.

[0058] In another embodiment, a device is discussed that includes a substrate with a gate stack formed thereon. For example, the device further includes a gate dielectric layer arranged over the substrate, a pretreated exit-work metal layer with a non-oxidized surface arranged over the gate dielectric layer, and a subsequent metal layer arranged over the non-oxidized surface of the pretreated exit-work metal layer. In various embodiments, the pretreated exit-work metal layer and the subsequent metal layer comprise layers deposited by atomic layer deposition (ALD) that are formed sequentially within a multi-chamber processing system while maintaining a vacuum condition of the multi-chamber processing system.

Claims

[1] Method for the manufacture of semiconductor devices comprising: Forming (204) a gate dielectric layer (106) over a substrate (102); Deposition (206) of an exit work metal layer over the gate dielectric layer (106); Performing (208) a first in-situ process (410) comprising a pretreatment process of the exit work metal layer, wherein the pretreatment process includes a precursor selected from the following group: TiCl x , TaCl x , TiF x , HfCl x WF x and WCl x , where x is between approximately 1 and approximately 6, and where the pretreatment process removes an oxidized layer of the exit work metal layer to form a treated exit work metal layer; and after carrying out (208) the first in-situ process (410), carrying out (210) a second in-situ process which includes a deposition process of another metal layer over the treated exit work metal layer, wherein the deposition (206) of the exit work metal layer over the gate dielectric layer (106) is carried out in a first chamber (3) of a processing system (500), wherein the first in-situ process is carried out in a second chamber (4) of the processing system (500) and wherein the second in-situ process is carried out in a third chamber (5) of the processing system (500), wherein the first chamber (3), the second chamber (4) and the third chamber (5) are each different chambers of the processing system (500). [2] Method according to claim 1, wherein the first and the second in-situ process are carried out while maintaining a vacuum state of the processing system (500). [3] The method of claim 1 or 2, comprising: prior to the deposition (206) of the exit work metal layer over the gate dielectric layer (106), forming a capping layer with a high k-value over the gate dielectric layer (106). [4] Method according to any of the preceding claims, wherein the exit work metal layer contains at least one of TiN, TaN, TiAlC, TiAl, TiSiN, TaSi and TiAlN. [5] Method according to any of the preceding claims, wherein the exit work metal is deposited at a temperature of approximately 200°C to approximately 600°C. [6] Method according to any of the preceding claims, wherein the pretreatment process is carried out at a temperature of approximately 300°C to approximately 1000°C. [7] Method according to any one of the preceding claims 3 to 6, wherein the flow rate of the precursor is between approximately 100 sccm and approximately 8000 sccm. [8] Method according to any of the preceding claims, wherein the exit work metal layer and the other metal layer are deposited by atomic layer deposition. [9] Method according to any of the preceding claims, wherein the other metal layer contains a TiAlC layer. [10] The method of claim 9, further comprising carrying out a third in-situ process comprising the deposition of a TiN layer over the TiAlC layer. [11] Method according to any of the preceding claims, wherein the pretreatment process displaces a strip edge of the exit working metal layer. [12] Method for manufacturing semiconductor devices comprising: in a first chamber (1) of an evacuated processing system (500), forming (204) a gate dielectric layer (106) over a substrate (102); while maintaining a vacuum condition of the processing system, deposition (206) of an exit work metal layer over the gate dielectric layer (106) in a second chamber (3) of the evacuated processing system (500); Transferring the substrate (102) to a third chamber (4) of the evacuated processing system (500) while maintaining the vacuum state of the evacuated processing system (500), and performing (208) a pretreatment process of the exit work metal layer in the third chamber (4) and thereby forming a treated exit work metal layer, wherein the pretreatment process includes a precursor selected from the following group: TiCl x , TaCl x , TiF x , HfCl x WF x and WCl x , where x is between approximately 1 and approximately 6; and Transferring the substrate (102) to a fourth chamber (5) of the evacuated processing system (500) while maintaining the vacuum condition of the evacuated processing system (500), and depositing (210) a subsequent metal layer over the treated exit working metal layer in the fourth chamber (5), wherein the first chamber (1), the second chamber (3), the third chamber (4) and the fourth chamber (5) are each different chambers of the evacuated processing system (500). [13] Method according to claim 12, wherein the pretreatment process removes an oxidized layer from a top surface of the exit working metal layer. [14] Method according to claim 12 or 13, wherein the exit work metal layer comprises an N-type exit work metal layer. [15] Method according to any one of claims 12 to 14, wherein the subsequent metal layer contains a TiAlC layer. [16] The method of claim 15, further comprising the deposition of a TiN layer over the TiAlC layer. [17] Processing system (500) comprising the following: several processing chambers (1, 2, 3, 4, 5, 6), each adjacent to a wafer handling chamber (506) containing a transfer arm (507) that transfers a substrate (102) from one to another of the several processing chambers (1, 2, 3, 4, 5, 6); a vacuum system coupled to the multiple processing chambers (1, 2, 3, 4, 5, 6) and the wafer handling chamber (506), wherein the vacuum system maintains a vacuum state of each of the multiple processing chambers (1, 2, 3, 4, 5, 6) and the wafer handling chamber (506); wherein a first chamber (1) of the several processing chambers (1, 2, 3, 4, 5, 6) is configured to deposit a gate dielectric layer (106) over the substrate (102); wherein a second chamber (3) of the multiple processing chambers (1, 2, 3, 4, 5, 6) is configured to deposit an exit work metal layer over the gate dielectric layer (106); wherein a third chamber (4) of the several processing chambers (1, 2, 3, 4, 5, 6) is configured to perform a pretreatment process of the exit work metal layer and thereby form a pretreated exit work metal layer, wherein the pretreatment process comprises introducing a precursor into the third chamber (4) which is selected from the following group: TiCl x , TaCl x , TiF x , HfCl x WF x and WCl x , where x is between approximately 1 and approximately 6; and wherein a fourth chamber (5) of the several processing chambers (1, 2, 3, 4, 5, 6) is configured to deposit a subsequent metal layer over the treated exit working metal layer. [18] Processing system (500) according to claim 17, wherein the precursor is introduced into the third chamber (4) at a pretreatment temperature and flow rate, wherein the pretreatment temperature is in the range of about 300-1000°C, and wherein the flow rate is in the range of about 100-8000 sccm. [19] Processing system (500) according to claim 17 or 18, wherein the subsequent metal layer contains a TiAlC layer.

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