METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Abstract

Method comprising: forming a dummy gate structure (75) over a semiconductor fin (64); forming a dielectric layer (90) on opposite sides of the dummy gate structure (75); removing the dummy gate structure (75) to form a recess (92) in the dielectric layer (90); successively forming a gate dielectric layer (94) and at least one conductive layer (96, 98) over side walls and a bottom surface of the recess (92);and treating the gate dielectric layer (94) and the at least one conductive layer (96, 98) with a fluoride-containing chemical, wherein the treatment comprises forming a film over the at least one conductive layer (96, 98) using a fluoride-containing precursor, wherein the fluoride-containing precursor is molybdenum hexafluoride, MoF6, iron(II) fluoride, FeF2, iron(III) fluoride, FeF3, nickel(II) fluoride, NiF2, cobalt(II) fluoride, CoF2, chromium(II) fluoride, CrF2, chromium(III) fluoride, CrF3, copper(I) fluoride, CuF, molybdenum(III) fluoride, MoF3, titanium(III) fluoride, TiF3, titanium(IV) fluoride, TiF4, aluminum fluoride, AlF3, tetrafluorosilane, SiF4, manganese(II) fluoride, MnF2, zirconium(IV) fluoride, ZrF4, niobium(V) fluoride, NbF5, hafnium(IV) fluoride, HfF4, tantalum(V) fluoride, TaF5, sodium fluoride, NaF, potassium fluoride, KF, lithium fluoride, LiF, magnesium fluoride, MgF2, calcium fluoride, CaF2, barium fluoride, BaF2, zinc fluoride, ZnF2 or lead(II) fluoride, PbF2.;

Description

Semiconductor Device and Procedure Priority Claim and Cross-Reference

[0001] This patent application claims priority over U.S. preliminary patent application No. 62 / 539,214, filed on July 31, 2017, entitled “Semiconductor Device and Method”, which is incorporated herein by reference as if it were reproduced in its entirety. STATE OF THE ART

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density stems from repeated reductions in the minimum feature size, allowing more components to be integrated into a given area.

[0003] Fin field-effect transistor devices (FinFETs) are commonly used in integrated circuits. FinFETs have a three-dimensional structure comprising a semiconductor fin projecting from a substrate. A gate structure, designed to control the flow of charge carriers within a conductive channel of the FinFET, surrounds the semiconductor fin. For example, in a tri-gate FinFET, the gate structure surrounds three sides of the semiconductor fin, thus forming conductive channels on three sides of the semiconductor fin. List of characters

[0004] For a more complete understanding of the present revelation and its advantages, reference is now made to the following descriptions in conjunction with the accompanying drawings. These show: Fig. 1 a perspective view of a Fin field-effect transistor (FinFET); Fig. 2 to Fig. 20 cross-sectional views of a FinFET device at various manufacturing stages in several embodiments; and Fig. 21 a flowchart of a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.

[0007] Embodiments of the present disclosure are discussed in the context of designing a semiconductor device and, in particular, in the context of improving the reliability of the gate oxide of FinFET devices. However, a person skilled in the art will readily recognize that the methods disclosed in the present disclosure can be used in other devices or applications, e.g., planar devices.

[0008] Fig. Figure 1 shows an example of a FinFET 30 in a perspective view. The FinFET 30 includes a substrate 32 , that one Finn 36 exhibits. The substrate 32 points to established isolation areas 34 and the Finn 36 It stands above this and out of the space between neighboring isolation areas. 34 A gate dielectric 38 It is located along the side walls and above an upper surface of the fin. 36 , and a gate electrode4o is located above the gate dielectric 38 Source / drainage areas 42 and 44 are located in the fin on opposite sides of the gate dielectric. 38 and the gate electrode 40 . Fig. Figure 1 further shows reference cross-sections that are used in later figures. The cross-section BB extends along a longitudinal axis of the gate electrode. 40 of FinFET 30 Cross-section CC is parallel to cross-section BB and runs transversely through a source / drain area. 42 The cross-section AA is perpendicular to the cross-section BB and runs along a longitudinal axis of the fin. 36 and, for example, in one direction of current flow between the source / drain areas 42 and 44 For clarity, the following figures refer to these reference cross-sections.

[0009] Fig. 2 to Fig. Figure 20 shows cross-sectional views of a FinFET device 100 at various manufacturing stages according to several embodiments. The FinFET device 100 is related to the FinFET 30 in Fig. 1, with the exception of several Finns, similar. Fig. 2 to Fig. Figure 5 shows cross-sectional views of the FinFET device 100 along cross-section BB, and Fig. 6 to Fig. Figure 20 shows cross-sectional views along cross-section AA.

[0010] Fig. Figure 2 shows a cross-sectional view of a substrate. 50 The substrate 50 The substrate can be a semiconductor substrate, such as a bulk semiconductor, an SOI substrate (semiconductor on an insulator), or the like, which can be doped (e.g., with a p-type or n-type dopant) or undoped. 50The substrate can be a wafer, such as a silicon wafer. Generally, a SOI substrate comprises a layer of semiconductor material deposited on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is deposited on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of the substrate can be... 50 silicon, germanium, a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GalnAsP, or combinations thereof.

[0011] The substrate 50may include integrated circuit devices (not shown). As a person skilled in the art will recognize, a wide variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, the like, or combinations thereof, may be integrated into and / or onto the substrate. 50 They will be trained to generate the structural and functional design requirements for the FinFET. The integrated circuit devices can be designed using any suitable methods.

[0012] With reference to Fig. 3 will be in Fig. 2 substrates shown 50 For example, it can be structured using photolithographic and etching techniques. For example, a mask layer, such as a pad oxide layer, can be created. 52 and an overlying pad nitride layer 56 , above the substrate 50 formed. The pad oxide layer 52It can be a thin film comprising silicon oxide, which is formed, for example, using a thermal oxidation process. The pad oxide layer 52 can act as an adhesive layer between the substrate 50 and the overlying pad nitride layer 56 It acts as an etch stop layer for etching the pad nitride layer. 56 act. In some embodiments, the pad nitride layer 56 formed from silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and can be formed, for example, using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0013] The mask layer can be textured using photolithographic techniques. Generally, photolithographic techniques use a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. In this example, the photoresist material is used to create the pad oxide layer. 52 and the pad nitride layer 56 to structure in order to create a structured mask 58 to train, as in Fig. 3 shown.

[0014] The structured mask 58 is then used to treat exposed sections of the substrate 50 to structure in order to fill trenches 61 to form semiconductor bridges 60 between adjacent ditches61 defined as in Fig. 3 shown. In some embodiments, the semiconductor bridges 60 by etching trenches in the substrate 50 For example, using reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. In some embodiments, the trenches can be 61 The strips (when viewed from above) are parallel to each other and closely spaced. In some embodiments, the trenches can be 61 be continuous and the semiconductor bridges 60 surrounded. After the semiconductor bridges 60 have been trained, the structured mask layer 58 removed by etching or any suitable method.

[0015] Fig. Figure 4 shows the formation of an insulating material between adjacent semiconductor bridges. 60, to create isolation areas 62The insulating material can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by chemical vapor deposition using high-density plasma (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by curing to convert it into another material, such as an oxide), the like, or a combination thereof. Other insulating materials and / or other formation processes can be used. In the embodiment shown, the insulating material is silicon dioxide formed by an FCVD process. A curing process can be performed after the insulating material has been formed. A planarization process, such as chemical-mechanical polishing (CMP), can remove any excess insulating material (and, if present, the structured mask layer).58 ) remove and top surfaces of the isolation areas 62 and upper surfaces of the semiconductor bridges 60 , which lie on the same level (not shown).

[0016] In some embodiments, the isolation areas include 62 a liner, e.g. a liner oxide (not shown), at the interface between the insulation area 62 and the substrate 50 / the semiconductor bridge 60 In some embodiments, the liner oxide is formed to fill the crystal defects at the interface between the substrate and the substrate. 50 and the isolation area 62 to reduce. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor bridge. 60 and the isolation area 62 to reduce. The liner oxide (e.g., silicon dioxide) can be a thermal oxide, which is formed by thermal oxidation of a surface layer of the substrate.50 is formed, although another suitable method for forming the liner oxide can also be used.

[0017] Next, the isolation zones will be identified. 62 excluded to form STI (Shallow Trench Isolation) areas 62. The isolation areas 62 are left out so that the upper sections of the semiconductor bridges 60 from the space between adjacent isolation areas 62 protrude and semiconductor fins 64 (who are also known as Finns) 64 (are designated) form. The upper surfaces of the isolation areas 62 They can have a flat surface (as shown), a convex surface, a concave surface (such as a curve), or a combination thereof. The upper surfaces of the isolation areas 62 They can be formed flat, convex and / or concave using a suitable etching process. The isolation areas 62can be achieved using a suitable etching process, such as one that is resistant to the material of the isolation areas. 62 Selective removal can be achieved by sparing certain areas. For example, chemical oxide removal can be performed using a CERTAS® etching tool, an Applied Materials SICONI tool, or dilute hydrofluoric acid (dHF).

[0018] Fig. 2 to Fig. Figure 4 shows an embodiment for forming fins. 64However, fins can be formed in many different processes. In one example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; homoepitaxic structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxic structures protrude from the dielectric layer to form fins. In another example, heteroepitaxic structures can be used for the fins. For instance, the semiconductor bridges can be recessed, and a material different from the semiconductor bridges can be epitaxially grown instead.

[0019] In yet another example, a dielectric layer can be formed over a top surface of a substrate; trenches can be etched through the dielectric layer; heteroepitaxic structures can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed such that the heteroepitaxic structures protrude from the dielectric layer to form fins.

[0020] In some embodiments where homoepitaxy or heteroepitaxy structures are grown epitaxially, the grown materials can be doped in situ during growth, thus avoiding prior and subsequent implantations, although in situ and implantation doping can be used together. Furthermore, it can be advantageous to grow a material in an NMOS region that is different from the material in a PMOS region. In various embodiments, the fins can be silicon germanium (Si₂O₆). x Ge 1-x, where x can be between approximately 0 and 1), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0021] Fig. Figure 5 shows the formation of a dummy gate structure. 75 above the semiconductor fins 64 The dummy gate structure 75 In some embodiments, it includes a gate dielectric. 66 and a gate 68 The dummy gate structure 75 can also be a mask 70 include. To include the dummy gate structure 75 To form a dielectric layer 66 on the semiconductor fins 64 and the isolation areas 62formed. The dielectric layer 66 This can be, for example, silicon oxide, silicon nitride, multiple layers thereof, or the like, and can be deposited or thermally grown using suitable techniques. In some embodiments, the dielectric layer can be 66 be a high-k dielectric material, and in these embodiments the dielectric layer can be 66 exhibiting a k-value greater than approximately 7.0, and can comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, multiple layers thereof, and combinations thereof. The methods for forming a dielectric layer 66 These may include molecular beam deposition (MBD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), and the like.

[0022] A gate layer 68 is above the dielectric layer 66 trained and a mask layer 70is above the gate layer 68 trained. The gate shift 68 can be above the dielectric layer 66 The mask layer is separated and then planarized, for example, using a CMP. 70 can be above the gate layer 68 be separated. The gate layer 68 It can be made of polysilicon, for example, although other materials can also be used. In some embodiments, the gate layer can be 68 The mask layer comprises a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiple layers thereof. 70 It can be formed, for example, from silicon nitride or the like.

[0023] After the layers (e.g. 66 , 68 and 70 ) have been trained, the mask layer 70 using suitable photolithographic and etching techniques to create a mask70 to train. The structure of the mask 70 can then access the gate layer 68 and the dielectric layer 66 transferred using a suitable etching technique to create a gate each 68 or a gate dielectric 66 to train. The Gate 68 and the gate dielectric 66 cover the respective channel areas of the semiconductor fins 64 off. The gate 68 may also have a longitudinal direction that corresponds to the longitudinal direction of the respective semiconductor fins 64 is essentially perpendicular.

[0024] Fig. 6 to Fig. Figure 20 shows the cross-sectional views of a further processing of the FinFET device. 100 along cross-section AA (along a longitudinal axis of the fin). As in Fig. Figure 6 shows weakly doped drainage areas (LDDs) 65 in the Finns 64 trained. The LDD areas 65They can be formed using a plasma doping process. The plasma doping process can introduce N-type or P-type impurities into the fins. 64 implant to treat the LDD areas 65 to develop. In some embodiments, the LDD areas are located 65 at the canal area of ​​the FinFET device 100 on. Sections of the LDD areas 65 can go under the gate 68 and extend into the channel area of ​​the FinFET device 100. Fig. Figure 6 shows a non-restrictive example of LDD areas. 65 Other designs, forms and methods for developing LDD areas 65 are also possible and should be fully included within the scope of this disclosure. For example, the LDD areas can 65 be trained after the first Gatespacers 72 were trained.

[0025] With further reference to Fig. 6 will be after the LDD areas 65 were trained, a gatespacer 87 The gate structure is designed for this purpose. 87 can provide an initial gatespacer 72 and a second gatespacer 86 include. In the example of Fig. 6 will be the first Gatespacer 72 on opposite side walls of the gate 68 and opposite side walls of the gate dielectric 66 trained. The first Gatespacer 72 can also be located above the upper surface of the semiconductor fin 64 and the upper surface of the isolation area 62 (see Fig. 5) extend. The second gatespacer 86 will be on the first gatespacer 72 trained, as in Fig. 6 shown. The first gatespacer 72can be formed from a nitride, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof, and can be formed, for example, using thermal oxidation, CVD, or another suitable deposition process. The second gate spacer 86 can be formed from silicon nitride, SiCN, a combination thereof or the like using a suitable deposition process.

[0026] In one embodiment, the gatespacer 87 formed by first creating an initial gate spacer layer 72 Above the FinFET device, 100 is deposited in a conformal manner, and then a second gate spacer layer is applied. 86 above the isolated first gatespacer layer 72conformally deposited. In the present disclosure, conformally (or in a conformal manner) means conformally (or in a conformal manner) within a process variation, as a person skilled in the art understands. For example, horizontal and vertical sections of the conformal first gate spacer layer can be 72 They essentially have the same thickness, with the difference between the vertical thickness of the vertical sections and the horizontal thickness of the horizontal sections being less than, for example, 20 percent of the horizontal thickness. Next, an anisotropic etching process, such as a dry etching process, is performed to create a first section of the second gatespacer layer. 86 , which is located on the upper surfaces of the FinFET device 100 (e.g., the upper surface of the semiconductor fins) 64 ) is arranged to remove, while a second section of the second gate spacer layer 86, which is arranged along the side walls of the gate structure, is maintained. The second section of the second gate spacer layer 86 , which remains after the anisotropic etching process, forms the second gatespacer 86 The anisotropic etching process also removes a section of the first gate spacer layer. 72 , which is outside the side walls of the second gatespacer 86 is arranged, and the remaining section of the first gatespacer layer 72 forms the first gatespacer 72 .

[0027] The forms and procedures for training the first gatespacer 72 and the second gatespacer 86 , as in Fig. Figure 6 shows only non-limiting examples, and other forms and methods of training are possible. For example, the second gatespacers 86 are formed after the epitaxial source / drain areas 80 (see Fig. 7) were formed. In some embodiments, dummy gate spacers are placed on the first gate spacer. 72 before the epitaxial process of the in Fig. 7 depicted epitaxial source / drain areas 80 trained and the dummy gatespacers are removed and replaced by the second gatespacers. 86 replaced after the epitaxial source / drain areas 80 were trained.

[0028] Next, as in Fig. 7 shown, source / drainage areas 80 trained. The source / drainage areas 80 are trained by the Finns 64Etched to create recesses, material is epitaxially grown within the recess using suitable techniques such as metal-organic etching (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), gas-phase epitaxy (VPE), selective epitaxial growth, the like, or a combination thereof. Following epitaxial growth of the source / drain regions... 80 , can a mask 70 They can be removed using a suitable method, such as etching.

[0029] As in Fig. Figure 7 shows the epitaxial source / drain areas 80 exhibit areas that are separated by the respective areas of the fins. 64 are increased (e.g., over the uncut sections of the fins) 64 increased), and they can exhibit facets. The source / drainage areas 80 the neighboring Finns 64can connect to form a continuous epitaxial source / drain area 80 to form. In some embodiments, the source / drain regions connect. 80 for neighboring Finns 64 They do not interact and separate source / drainage areas remain. 80 In some embodiments where the resulting FinFET is an n-channel FinFET, the source / drain regions comprise 80 Silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), or the like. In alternative embodiments where the resulting FinFET is a p-channel FinFET, the source / drain regions comprise 80 SiGe and a p-type impurity, such as boron or indium.

[0030] Into the epitaxial source / drain areas 80 Can dopants be implanted to optimize source / drain areas? 80to form, followed by healing. The implantation process may involve forming and structuring masks, such as a photoresist, to cover the FinFET regions that need protection before implantation. The source / drain regions 80 They can have an impurity concentration (e.g., of a dopant) in the range of approximately 1 x 19 cm⁻³ to approximately 1 x 21 cm⁻³. In some embodiments, the epitaxial source / drain regions can be doped in situ during growth.

[0031] Next, as in Fig. 8 shows a first dielectric intermediate layer (ILD) 90 above the in Fig. The structure shown in Figure 7 is formed, and a gate-last process (sometimes called an exchange gate process) is carried out. In a gate-last process, the gate 68 and the gate dielectric 66 (see Fig. 7) are considered as dummy structures and are removed and replaced by an active gate and an active gate dielectric, which together can be referred to as a replacement gate.

[0032] In some embodiments, the first ILD 90 The ILD is formed from a dielectric material, such as phosphorosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphorosilicate glass (BPSG), undoped silicate glass (USG), or the like, and can be deposited using any suitable process, such as CVD, PECVD, or FCVD. A planarization process, such as a CMP process, can be performed to flatten the top surface of the first ILD. 90 to planarize, so that the upper surface of the first ILD 90 at the same level as the upper surface of the gate 68 is located (see Fig. 7) Therefore, in some embodiments, after the CMP process, the upper surface of the gate is 68exposed.

[0033] According to some embodiments, the gate 68 and the gate dielectric 66 directly below the gate 68 removed in one etching step(s), so that recesses 92 in each of the Finns 64 They are trained. Each recess defines a channel area for a respective fin. 64 free. Each channel area is located between adjacent pairs of epitaxial source / drain areas. 80 arranged. During the removal of the dummy gate, the dummy gate dielectric layer can be 66 can be used as an etch stop layer when the dummy gate 68 is etched. The dummy gated dielectric layer 66 After removing the dummy gate 68 be removed.

[0034] Next, in Fig. 9 a gate dielectric layer 94 , a covering layer 96 and a barrier layer 98one after the other above the semiconductor device 100 trained. As in Fig. As shown in 9, the gate dielectric layer is 94 in the recess 92 and above an upper surface of the first ILD 90 Conformally separated. The cover layer 96 and the barrier layer 98 become conformal across the gate dielectric layer 94 formed, whereby the covering layer 96 between the gate dielectric layer 94 and the barrier layer 98 is arranged. The cover layer 96 can function as an exit working layer of the FinFET device 100, and the barrier layer 98 can function as an etch stop layer of the FinFET device 100. The gate dielectric layer 94 , the covering layer 96 and the barrier layer 98 can below be combined as a layer stack 121 be designated.

[0035] According to some embodiments, the gate dielectric layer comprises 94 Silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the gate dielectric layer comprises 94 a high-k dielectric material and in these embodiments the gate dielectric layers 94 They must have a k-value greater than approximately 7.0 and can comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The methods for forming the gate dielectric layer 94 These can include MBD, ALD, PECVD, and the like. In one embodiment, the gate dielectric layer is... 94 a high-k dielectric material comprising HfO2, and is formed using a suitable method, such as an ALD. In some embodiments, the gate dielectric layer 94a high-k dielectric material, and a layer of silicon oxide (SiO2) is placed between the gate dielectric layer 94 and the Finn 64 The silicon oxide layer can be formed by oxidation of the fin material. 64 or be formed using any suitable deposition method, such as CVD, PVD or ALD.

[0036] Next, the top layer will be applied. 96 above the gate dielectric layer 94 Conformally designed. The cover layer comprises any suitable material for an exit working layer. Examples of p-type exit working metals used in the gate structure. 97 (see Fig. 13) may be included, comprising TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type exit work materials, or combinations thereof. Examples of n-type exit work metals that may be included in the gate structure 97Suitable materials include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type exit work materials, or combinations thereof. An exit work value is associated with the material composition of the exit work layer, and therefore the material of the first exit work layer is selected to match its exit work value, such that a target threshold voltage V is achieved. t in the device to be installed in the respective area. The exit working layer(s) can be deposited using CVD, PVD, ALD and / or another suitable process.

[0037] Next, the barrier layer will be installed. 98 above the cover layer 96 Trained in accordance with regulations. The barrier layer 98It can comprise an electrically conductive material, such as titanium nitride, although other materials, such as tantalum nitride, titanium, tantalum, or the like, can be used alternatively. The barrier layer 98 It can be formed using a CVD process, such as PECDV. However, other alternative processes, such as sputtering, MOCVD, or ALD, can be used. The barrier layer 98 and the cover layer 96 In some embodiments, they include different materials to achieve etch selectivity between the barrier layer. 98 and the cover layer 96 to provide. In one embodiment, the cover layer comprises 96 TiN and the barrier layer comprises TaN, and suitable deposition methods, such as ALD, can be used to create the cover layer. 96 and the barrier layer 98 to train.

[0038] Next, as in Fig. 10 to Fig. 11 shown, the layer stack 121 treated using a surface treatment process employing a fluoride-containing chemical (which can also be referred to as a fluoride-containing precursor) to coat the gate dielectric layer 94 to dope with fluoride, and a thermal curing process is subsequently carried out to increase the dopant concentration (e.g. fluoride concentration) of the gate dielectric layer 94 to increase further. In particular, it shows Fig. 10 embodiments in which the surface treatment process includes a soak process, wherein the layer stack 121 in a preliminary stage 84 is soaked, which may be a fluoride-containing gas or a fluoride-containing plasma, and Fig. Figure 11 shows the thermal healing process that is carried out after the soak process. Fig. 12 and Fig. Figure 13 shows an embodiment in which the surface treatment process removes the gate dielectric layer 94 doped by a thin film 88 (see Fig. 12) above the layer stack 121 deposited using a fluoride-containing precursor, and a thermal curing process (see Fig. 13) further into the gate dielectric layer the dopant (e.g. fluoride) 94 inwards. Details of the surface treatment process and the thermal curing process are discussed below.

[0039] According to some embodiments, the surface treatment process drives fluoride (e.g., fluoride radicals) from an upper surface of the layer stack. 121 (e.g., an upper surface of the barrier layer) 98 ) into the gate dielectric layer 94 , thereby the gate dielectric layer 94is effectively doped with fluoride and has a concentration of fluoride in the gate dielectric layer 94 is increased. Doping of the gate dielectric layer 94 In some embodiments, the addition of fluoride improves the TDDB (Time-Dependent Dielectric Breakdown) performance of the FinFET device 100.

[0040] Time-dependent dielectric breakdown (TDDB) is a failure mechanism in metal-oxide-semiconductor field-effect transistors (MOSFETs) in which the gate oxide breaks down as a result of long-term exposure to a relatively low electric field (as opposed to instantaneous breakdown, which is caused by a strong electric field). The breakdown is caused by the formation of a conductive path through the substrate's gate oxide due to electron tunneling current when MOSFETs are operated near or beyond their specified operating voltages.

[0041] According to some embodiments, the surface treatment process includes exposing the layer stack. 121 a fluoride-containing chemical (e.g. chemical) 84 ). A molecular composition of the chemical (e.g., the chemical) 84 ) can be used as MF xare represented by F, where F stands for fluoride, M for another suitable element, and x represents the molecular ratio of F to M. In some embodiments, element M is a metal, such as tungsten (W), molybdenum (Mo), titanium (Ti), iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr), copper (Cu), aluminum (Al), manganese (Mn), silicon (Si), calcium (Ca), zirconium (Zr), niobium (Nb), hafnium (Hf), tantalum (Ta), lead (Pb), or the like. In other embodiments, element M is a non-metal, such as NC, S, Cl, or the like. Examples of the chemical 84 may include tungsten hexafluoride (WF6), nitrogen trifluoride (NF3), molybdenum hexafluoride (MoF6), FeF2, FeF3, NiF2, CoF2, CrF2, CrF3, CuF, MoF3, TiF3, TiF4, AlF3, SiF4, MnF2, ZrF4, NbF5, HfF4, TaF5, NaF, KF, LiF, MgF2, CaF2, BaF2, ZnF2, PbF2, CF4, C2F6, SF6, C3F8, CHF3.

[0042] With reference to Fig. 10 In some embodiments, the surface treatment process is a thermal process that uses a fluoride-containing gas as the chemical. 84 used. For example, a WF6-GAs can be used as the chemical 84 The following are used: FeF2, FeF3, NiF2, CoF2, CrF2, CrF3, CuF, MoF3, TiF3, TiF4, AlF3, SiF4, MnF2, ZrF4, NbF5, HfF4, TaF5, NaF, KF, LiF, MgF2, CaF2, BaF2, ZnF2, PbF2, CF4, C2F6, SF6, C3F8, CHF3. The fluoride-containing gas 84 is delivered in such a way that it is flush with the surface of the barrier layer 98 is in contact, as in Fig. 10. The fluoride-containing gas 84 It can be carried by a carrier gas, which can be an inert gas such as N2, Ar, He, the like, or combinations thereof. In some embodiments, the energy (e.g., thermal energy) of the thermal process breaks the bond between F and element M (e.g., the bond between F and W, if WF6 is the chemical). 84(is used) and generates fluoride radicals. As an example, the decomposition of WF6 can be described by the following chemical equation (1). W F 6 → W + 6 F

[0043] A layer (not shown) comprising the element M (e.g. W) can form above the barrier layer after the thermal process. 98 are formed. The thermal process drives the fluoride radicals into the layer stack. 121 to the gate dielectric layer 94 In some embodiments, the radicals of fluoride are introduced into the gate dielectric layer. 94 driven by the thermal process. The fluoride radicals can enter the trapping state at the interface between the gate dielectric layer. 94 and an adjacent dielectric layer (e.g., the first ILD) 90 and / or the first gatespacer 72 ) compensate, thereby increasing the trapping density (D it) is reduced at the interface.

[0044] Parameters of the surface treatment process, such as the temperature and / or duration of the surface treatment process, the flow rate of the chemical 84 , can be adjusted to achieve a target concentration of fluoride in the gate dielectric layer 94 to achieve this. For example, a low temperature (e.g., lower than 200°C) and / or a short duration (e.g., less than 30 seconds) may not allow enough fluoride to be deposited into the gate dielectric layer. 94 to drive in fluoride to achieve the target fluoride concentration. On the other hand, a high temperature (e.g., higher than 650 °C) and / or a long duration (e.g., longer than 30 seconds) can drive fluoride across the gate dielectric layer. 94 out and into the adjacent dielectric layer (e.g. the first ILD) 90 or the first gatespacer 72 ) drive in.

[0045] In one embodiment, the thermal process is carried out using a WF6 gas at a temperature between approximately 200 °C and approximately 650 °C. A low flow rate of WF6 can range from 5 standard cubic centimeters per minute (sccm) to approximately 10,000 sccm, such as 1000 sccm. A flow rate of the carrier gas can range from approximately 5 sccm to approximately 10,000 sccm, such as 6000 sccm. A pressure of the thermal process can range from approximately 0.5 Torr to approximately 300 Torr, such as 20 Torr, and a duration of the thermal process can range from approximately 0.1 seconds to approximately 300 seconds, such as 100 seconds.

[0046] With further reference to Fig. 10 In some embodiments, the surface treatment process is a plasma process that uses a fluoride-containing plasma as the chemical. 84used. For example, an NF3 gas can be activated to plasma and used as the chemical 84 can be used. The fluoride-containing plasma 84 can be carried by a carrier gas, which can be an inert gas such as N2, Ar, He, the like, or combinations thereof. The fluoride-containing plasma 84 is delivered in such a way that it is flush with the surface of the barrier layer 98 is in contact, as in Fig. Figure 10 illustrates this. The energy of the plasma process (e.g., the discharge energy) breaks the bond between F and the element M (e.g., F and N) and generates fluoride radicals. For example, the NF3 plasma bombards the surface of the barrier layer. 98 This breaks the bond between F and N, initiating several chemical reactions. The decomposition of the NF3 plasma can be represented by the following chemical equations (2) and (3). NF 3 → NF + + 2 F NF 3 → NF 2 + + F

[0047] The element M (e.g. N) from the decomposition of the chemical 84 can form a byproduct(s) that is / are evacuated (e.g. pumped out) from the deposition chamber (not shown) in which the FinFET device 100 is located, or it can form a layer (not shown) comprising the element M above the support layer 98 The energy of the plasma process drives the fluoride radicals into the layer stack. 121 to the gate dielectric layer 94 In some embodiments, the radicals of fluoride are introduced into the gate dielectric layer. 94 driven by the plasma process.

[0048] In one embodiment, the plasma process is carried out using NF3 gas plasma at a temperature between approximately 20 °C and approximately 400 °C. The plasma process energy ranges from approximately 5 volts to approximately 10,000 volts, for example, 500 volts. The NF3 flow rate can range from approximately 10 sccm to approximately 5,000 sccm, for example, 200 sccm. The carrier gas flow rate can range from approximately 5 sccm to approximately 10,000 sccm, for example, 3,000 sccm. The plasma process pressure can range from approximately 0.5 Torr to approximately 300 Torr, for example, 15 Torr, and the plasma process duration can range from approximately 0.1 seconds to approximately 300 seconds, for example, 100 seconds.

[0049] Next, as in Fig. Figure 11 shows an optional thermal curing process after the surface treatment process (e.g. a thermal process or a plasma process). 510This is carried out to remove fluoride (e.g., fluoride radicals in the cover layer). 96 and in the barrier layer 98 ), which is in the layer stack 121 contained, further into the gate dielectric layer 94 to drive in. In one embodiment, the thermal healing process 510 The test was performed at a temperature between approximately 400 °C and approximately 700 °C, e.g., 550 °C, for a duration of between approximately 0.1 seconds and approximately 300 seconds, e.g., 30 seconds. A fluoride concentration in the range of 1 x 15 / cm³ was used. 2 and 1E17 / cm 2 is achieved after the thermal healing process.

[0050] Now, reference is made to Fig. 12 and Fig. 13 taken. Fig. 12 and Fig. Figures 13 illustrate different embodiments of the surface treatment process and a subsequent thermal curing process, respectively. As in Fig. As shown in 12, the surface treatment process includes the formation of a film. 88 above the barrier layer 98 using a fluoride-containing precursor (not shown). For example, tungsten hexafluoride (WF6) or molybdenum hexafluoride (MoF6) can be used as the fluoride-containing precursor to produce the film. 88 to form. Other fluoride-containing precursors that contribute to the formation of the film. 88 Suitable precursor materials include FeF2, FeF3, NiF2, CoF2, CrF2, CrF3, CuF, MoF3, TiF3, TiF4, AlF3, SiF4, MnF2, ZrF4, NbF5, HfF4, TaF5, NaF, KF, LiF, MgF2, CaF2, BaF2, ZnF2, and PbF2. The precursor can be carried by a carrier gas, which may be an inert gas such as N2, Ar, He, or a combination thereof. A suitable deposition method, such as ALD, PVD, CVD, or a combination thereof, can be used to form the film. 88 be used.

[0051] In some embodiments, the fluoride-containing precursor (e.g., WF6 or MoF6) decomposes during the deposition process, thereby breaking the bond between F and the element M (e.g., W or Mo) of the precursor. After decomposition, the element M of the precursor forms the film. 88 and the fluoride is deposited into the layer stack after decomposition by the energy (e.g. thermal energy) of the deposition process 121 to the gate dielectric layer 94 driven there. For example, the film 88 The film includes a layer of W or a layer of Mo if WF6 or MoF6 is used as the precursor in the deposition process. 88 It may also contain fluoride and a small amount of undecomposed precursor. In some embodiments, fluoride is incorporated into the gate dielectric layer. 94 driven during the deposition process.

[0052] In one embodiment, the surface treatment process includes forming the film. 88 Using a fluoride-containing precursor at a temperature between approximately 200 °C and approximately 500 °C, such as 350 °C. The precursor flow rate can be between approximately 10 sccm and approximately 5,000 sccm, such as 500 sccm. The carrier gas flow rate can be between approximately 5 sccm and approximately 10,000 sccm, such as 3,000 sccm. A pressure of the deposition process for film formation. 88 The thickness of the film can range from approximately 0.5 Torr to approximately 300 Torr, such as 20 Torr. 88 It can range from approximately 3Å to approximately 200Å, such as 100Å, although other dimensions are also possible.

[0053] Next, as in Fig. 13 shown, after the surface treatment process of Fig. 12 an optional thermal healing process 610This is carried out to remove fluoride (e.g., fluoride radicals in the cover layer). 96 and in the barrier layer 98 ), which is in the layer stack 121 contained, further into the gate dielectric layer 94 to drive in. In one embodiment, the thermal healing process 610 The test was performed at a temperature between approximately 400 °C and approximately 700 °C, e.g., 550 °C, for a duration of between approximately 0.1 seconds and approximately 300 seconds, e.g., 30 seconds. A fluoride concentration in the range of 1 x 15 / cm³ was used. 2 and 1E17 / cm 2 is achieved after the thermal healing process.

[0054] As discussed above, the surface treatment process (e.g., the thermal process, the plasma process, or the film deposition process) can deposit a layer (not shown) containing the element M (e.g., W, Mo) over the area of ​​the barrier layer. 98form. This layer of element M is removed in some embodiments using a suitable process, such as etching, before the recess is formed. 92 is filled. In other embodiments, the layer containing element M is not removed. Instead, it remains above the support layer. 98 and is used as part of the exit working layer to control the threshold voltage V t to adjust the FinFET device 100. For the sake of simplicity, the layer encompassing element M (if not removed) is not shown in subsequent figures.

[0055] Embodiments of the surface treatment process offer many advantages. As the size of semiconductor devices in an advanced processing node becomes increasingly smaller, the implantation angle available for the ion implantation process used to dope the dielectric layer of FinFET devices is limited, for example, due to the close proximity of fins and / or gate structures. Therefore, an ion implantation process may not be able to dope certain areas of the gate dielectric layer to achieve the target dopant concentration. The present disclosure provides various non-destructive and effective methods for doping the gate dielectric layer. Consequently, the time-dependent dielectric breakdown (TDDB) performance of the FinFET device 100 is improved. Processing steps used in the disclosed surface treatment process, such as...The soak process, film deposition, and etching are well-established and widely available processing steps in semiconductor manufacturing. Furthermore, the starting materials used in the surface treatment process are inexpensive, enabling a cost-effective surface treatment process. Additionally, the disclosed surface treatment process can be easily integrated with existing exchange gate processes. For example, the surface treatment process disclosed here does not alter the formed metal gate stack, ensuring good compatibility with existing process flows.

[0056] Next, as in Fig. 14 to Fig. 20 shown, the processing according to the in Fig. 10 to Fig. The surface treatment process shown in section 13 continues. With reference to Fig. 14 will be the gate electrode 99 above the barrier layer98 isolated and fills the remaining sections of the recess 92 The gate electrode 99 can be manufactured from a metal-containing material, such as Cu, Al, W, the like, combinations thereof or multiple layers thereof, and can be formed, for example, by electroplating, electroless plating, PVD, CVD or another suitable process.

[0057] Next, as in Fig. Figure 15 shows that a planarization process, such as a CMP, is performed to remove the excess sections of the gate dielectric layer. 94 , the cover layer 96 , the barrier layer 98 and the material of the gate electrode 99 to remove the excess sections above the upper surface of the first ILD 90 The resulting remaining sections of the gate electrode material are located there. 99 , the barrier layer 98, the cover layer 96 and the gate dielectric layer 94 Therefore, they form a replacement gate 97 the resulting FinFET device 100.

[0058] Next, in Fig. 16 a second ILD 95 above the first ILD 90 isolated. In one embodiment, the second ILD is 95 a flowable film formed using a flowable CVD process. In some embodiments, the second ILD 95 Formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be deposited using any suitable method, such as CVD and PECVD. Contact openings 91 and 93 for contacts 102 (see Fig. 20) are through the first ILD 90 and / or the second ILD 95 trained. For example, the opening of contacts 91 through the second ILD 95trained and lays the replacement gate 97 free, while the contact openings 93 through the first ILD 90 and the second ILD 95 be trained and source / drainage areas 80 Expose the contact openings. 91 / 93 are shown in a single cross-section as an example, where the contact openings 91 / 93 could be found in different cross-sections.

[0059] Next, in Fig. 17 a barrier layer 104 above the second ILD 95 formed. In some embodiments, the barrier layer 104 conforming over the second ILD 95 trained, and coats side walls and undersides of the contact openings 91 / 93 out. The barrier layer 104It can comprise an electrically conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like, and can be formed using a CVD process, such as PECVD. However, other alternative processes, such as sputtering or MOCVD, PVD, or ALD, can also be used.

[0060] In some versions, silicide areas are designated. 82 over the epitaxial source / drain areas 80 , e.g. between the epitaxial source / drain areas 80 and the barrier layer 104 trained. The silicide areas 82 can be trained before the lockdown shift 104 is trained, although the silicide areas 82 also during the process of forming the barrier layer 104 can be trained. The silicide areas 82can be formed by first depositing a metal capable of reacting with semiconductor materials (e.g., silicon, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys, over the epitaxial source-drain regions. 80 is deposited, and subsequently a thermal curing process is carried out to eliminate the silicide areas. 82 to form. The unreacted parts of the deposited metal are then removed, for example, using an etching process. Although the areas 82 These areas can be designated as silicide-infected areas. 82 These could also be germanide areas, or silicon germanide areas (e.g. areas that include silicide and germanide).

[0061] Next, as in Fig. 18 shown, a germ layer 108 above the barrier layer 104separated. The germinal layer 108 can be deposited using PVD, ALD or CVD and can be formed from tungsten, copper or copper alloys, although other suitable methods and materials may be used alternatively.

[0062] After the germ layer 108 Once trained, the conductive material 110 on the germinal layer 108 be trained so that the contact openings 91 / 93 filled and overfilled, as in Fig. 19 shown. The conductive material 110The conductive material may include tungsten, although other suitable materials, such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys of these, combinations thereof, and the like, may be used alternatively. Any suitable deposition process, such as PVD, CVD, ALD, plating (e.g., electroplating), and remelting, may be used to form the conductive material. 110 be used.

[0063] With reference to Fig. 20 can, after the contact openings 91 / 93 were filled, an excess barrier layer 104 , germinal layer 108 and the conductive material 110 outside the contact openings 91 / 93 They can be removed using a planarization process, such as CMP, although any suitable removal process can be used. Contact plugs 102In this way, the contact openings are 91 / 93 trained.

[0064] Variations and modifications of the embodiments disclosed herein are possible. For example, different embodiments of the surface treatment process discussed above can be combined to adjust the fluoride concentration in the gate dielectric layer. 94 to improve further. As an example, the above with reference to Fig. The soak process discussed in point 10, which uses a fluoride-containing gas (e.g., WF6), is carried out, whereupon the above with reference to Fig. Following the film deposition process discussed in section 12, a thermal curing process, as described in [reference], can then take place. Fig. 13 discussed, to be carried out in order to further introduce the fluoride into the gate dielectric layer 94 to drive in. Other variations are possible. For example, the in Fig. 10 to Fig. The processing described in section 11 can be carried out, followed by the process described in Fig. 12 to Fig. The processing described in section 13 can be carried out. Therefore, Fig. 10 to Fig. Figure 14 shows another embodiment of the surface treatment process. Embodiments of the present disclosure are described using fluoride as the dopant for the gate dielectric layer. 94 discussed. In embodiments where elements other than fluoride are used as dopants to improve the TDDB performance of the gate dielectric layer. 94 To improve the surface treatment process, it can be modified to use chemicals or precursors containing a dopant other than fluoride. These and other modifications to the present disclosure are possible and are intended to be fully included within the scope of this disclosure.

[0065] Fig. Figure 21 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments. It is understood that the Fig. The embodiment shown in Figure 21 is merely one example of many possible embodiments. A person skilled in the art would recognize many variations, alternatives, and modifications. For example, various steps, as shown in Figure 21, can be used. Fig. 21 can be shown, added, omitted, replaced, rearranged and repeated.

[0066] With reference to Fig. 21 will be at step 1010 A dummy gate structure is formed over a semiconductor fin. At step 1020 A dielectric layer is formed on opposite sides of the dummy gate structure. In step 1030 The dummy gate structure is removed to create a recess in a dielectric layer. In step 1040A gate dielectric layer and at least one conductive layer are formed successively over the side walls and a bottom surface of the recess. In step 1050 The gate dielectric layer and the at least one conductive layer are treated with a chemical containing fluoride (F).

[0067] Embodiments can offer advantages. The surface treatment process disclosed herein provides various non-destructive and effective methods for doping the gate dielectric layer. Consequently, the TDDB performance of the semiconductor device is improved. Processing steps used in the disclosed surface treatment process, such as the soak process, film deposition, and etching, are mature and widely available. The starting materials used in the surface treatment process are cost-effective. Furthermore, the disclosed surface treatment process can be easily integrated with existing gate replacement processes. For example, there is no change to the metal gate stack formed using the methods disclosed herein, thus ensuring good compatibility with existing process flows.

[0068] In some embodiments, a method comprises: forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposite sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further comprises: successively forming a gate dielectric layer and at least one conductive layer over side walls and a bottom surface of the recess, and treating the gate dielectric layer and the at least one conductive layer with a fluoride-containing (F) chemical.

[0069] In some embodiments, a method for forming a fin field-effect transistor (FinFET) comprises: providing a substrate with a fin projecting above top surfaces of insulating structures arranged on opposite sides of the fin; forming a first gate structure over the fin; forming an intermediate dielectric layer (ILD) around the first gate structure, wherein the ILD layer exposes a top surface of the first gate structure; and removing the first gate structure to form a recess in the ILD layer. The method further comprises: forming a stack of layers in the recess, wherein the formation of the stack of layers comprises: conformally forming a high-k dielectric layer in the recess; conformally forming a conductive cover layer over the high-k dielectric layer; and conformally forming a conductive barrier layer over the conductive cover layer.The process further comprises: performing a surface treatment process for the layer stack using a fluoride-containing chemical, wherein the surface treatment process drives fluoride into the high-k dielectric layer, and performing a thermal curing process after the surface treatment process.

[0070] In some embodiments, a method comprises: forming a dielectric layer, covering the dielectric layer with at least one conductive layer, introducing a fluoride-containing precursor over the at least one conductive layer, and driving the fluoride-containing precursor into the dielectric layer.

[0071] The foregoing outlines features of several embodiments so that a person skilled in the art may better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. Although this disclosure has been described with reference to exemplary embodiments, this description should not be interpreted in a limiting sense.Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the disclosure, will be obvious to a person skilled in the art with reference to the description. It is therefore intended that the appended claims include any such modifications or embodiments. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 62539214

[0001]

Claims

[1] Procedure, encompassing: Forming a dummy gate structure over a semiconductor fin; Forming a dielectric layer on opposite sides of the dummy gate structure; Removing the dummy gate structure to create a recess in the dielectric layer; successive formation of a gate dielectric layer and at least one conductive layer over side walls and a bottom surface of the recess; and Treating the gate dielectric layer and the at least one conductive layer with a fluoride-containing (F) chemical. [2] Method according to claim 1, wherein forming the gate dielectric layer and the at least one conductive layer comprises: Formation of a gate dielectric layer over the side walls and the underside of the recess; Forming a cover layer over the gate dielectric layer, wherein the cover layer comprises a first conductive material; and Forming a barrier layer over the cover layer, wherein the barrier layer comprises a second conductive material different from the first conductive material. [3] Method according to claim 2, wherein the gate dielectric layer comprises a high-k dielectric material. [4] Method according to claim 3, wherein the cover layer comprises titanium nitride (TiN) and the barrier layer comprises tantalum nitride (TaN). [5] Method according to any of the preceding claims, wherein the treatment drives fluoride into the gate dielectric layer. [6] Method according to any of the preceding claims, wherein the treatment comprises carrying out a thermal process using tungsten hexafluoride (WF6). [7] Method according to any of the preceding claims, wherein the treatment comprises carrying out a plasma process using nitrogen trifluoride (NF3). [8] Method according to any of the preceding claims, wherein the treatment comprises forming a film over the at least one conductive layer using a fluoride-containing precursor. [9] The method of claim 8, wherein the fluoride-containing precursor comprises tungsten hexafluoride (WF6) or molybdenum hexafluoride (MoF6). [10] Method according to any of the preceding claims, further comprising a thermal healing process after treatment. [11] Method according to any of the preceding claims, wherein the treatment comprises: Exposure of the gate dielectric layer and the at least one conductive layer to a gas comprising fluoride or to a plasma comprising fluoride; Deposition of a film over the at least one conductive layer using a precursor comprising fluoride; and Performing a thermal curing process after film deposition. [12] Method according to any of the preceding claims, further comprising filling the recess using a conductive material after treatment. [13] Method for forming a Fin field-effect transistor (FinFET), comprising: Providing a substrate with a fin that protrudes above the upper surfaces of insulation structures located on opposite sides of the fin; Forming an initial gate structure above the fin; Forming a dielectric intermediate layer (ILD) around the first gate structure, wherein the ILD layer exposes an upper surface of the first gate structure; Removing the first gate structure to create a recess in the ILD layer; Forming a layer stack in the recess, wherein the formation of the layer stack comprises: conformal formation of a high-k dielectric layer in the recess; conformal formation of a conductive cover layer over the high-k dielectric layer; and conformal formation of a conductive barrier layer over the conductive cover layer; Performing a surface treatment process for the layer stack using a fluoride-containing chemical, wherein the surface treatment process drives fluoride into the high-k dielectric layer; and Performing a thermal curing process after the surface treatment process. [14] Method according to claim 13, wherein carrying out the surface treatment process comprises: impregnating the layer stack in a fluoride-containing gas, impregnating the layer stack in a fluoride-containing plasma or depositing a film over the conductive barrier layer using a fluoride-containing precursor. [15] Method according to claim 13 or 14, wherein carrying out the surface treatment process comprises: Soaking the stack of layers in a fluoride-containing gas or plasma; and Deposition of a film over the conductive barrier layer after impregnation using a fluoride-containing precursor. [16] The method of claim 15, further comprising: Removal of the film after the thermal curing process; and Filling the recess with a conductive material. [17] Procedures, including: Formation of a dielectric layer; Covering the dielectric layer with at least one conductive layer; Adding a fluoride-containing precursor above the at least one conductive layer; and Driving the fluoride-containing precursor into the dielectric layer. [18] Method according to claim 17, wherein the fluoride-containing precursor is a fluoride-containing gas or a fluoride-containing plasma. [19] Method according to claim 17 or 18, wherein the feeding process deposits a film over the at least one conductive layer. [20] Method according to any one of the preceding claims 17 to 19, wherein the dielectric layer comprises a high-k dielectric material, and wherein the drive-in process comprises at least one thermal drive-in process.

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