FIN-BASED BAND CELL STRUCTURE TO IMPROVE STORAGE PERFORMANCE

Abstract

Integrated circuit which features the following: a storage cell (20A) with a first well doping configuration comprising a first well region (114A-1), a second well region (112A), and a third well region (114A-2) arranged in a substrate (110), wherein the second well region (112A) is located between the first well region (114A-1) and the third well region (114A-2), and wherein the first well region (114A-1) and the third well region (114A-2) are further doped with a dopant of a first type, and the second well region (112A) is doped with a dopant of a second type; and a trough belt cell (50) which is arranged adjacent to the storage cell (20A), wherein: - the trough belt cell (50) has a first trough belt area (50B), a second trough belt area (50A) and a third trough belt area (50C), wherein the second trough belt area (50A) is arranged between the first trough belt area (50B) and the third trough belt area (50C), - the first trough belt area (50B) and the third trough belt area (50C) have the first trough doping configuration, - the second trough band area (50A) has a second trough doping configuration which includes a fourth trough region (114C) doped with the dopant of the first type, and - the tub band cell (50) contains first tub pickup regions (160B) which are arranged on the fourth tub region (114C) and second tub pickup regions (160A) which are arranged on a fifth tub region (112C) which extends without interruption into the second tub region (112A).

Description

GENERAL STATE OF THE ART

[0001] Static random access memory (SRAM) generally refers to any working memory or fixed storage that can retain stored data only while power is applied. As integrated circuit (IC) technologies evolve toward ever smaller technology nodes, SRAMs often incorporate fin-based structures, such as fin-like field-effect transistors (FinFETs), within SRAM cells to improve performance, with each SRAM cell capable of storing a small amount of data.Since SRAM cell performance is largely dependent on the layout (for example, it has been observed that an inner SRAM cell in an SRAM array performs differently than an edge SRAM cell in the same array), fin-based trough-band cells have been implemented to stabilize the trough potential, thereby enabling a uniform charge distribution throughout an entire SRAM array and thus uniform performance between SRAM cells within the array. However, as fin dimensions also decrease, it has been observed that fin-based trough-band cells increase the pickup resistance of SRAM arrays and / or decrease their latch-up performance. Therefore, existing trough-band cells are not entirely satisfactory in every respect, although they generally fulfill their respective uses in SRAM arrays.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 10 157 987 B1.

[0003] The invention provides for an integrated circuit according to claim 1, a memory according to claim 9, and a memory arrangement according to claim 18. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various features are not shown to scale and are for illustrative purposes only. In reality, the dimensions of various features may have been arbitrarily enlarged or reduced for the sake of clarity of discussion. Fig. Figure 1 is a fragmentary schematic top view of a storage facility according to various aspects of the present revelation. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F and Fig. 2G are fragmentary schematic views of a trough ribbon cell, section by section or in its entirety, stored in the memory of Fig. 1 may be implemented, according to various aspects of the present revelation. Fig. 3 is a simplified schematic top view of another embodiment of a trough belt cell, sectionally or completely, which is located in the storage of Fig. 1 may be implemented, according to various aspects of the present revelation. Fig. 4 is a fragmentary top view of a section of a bathtub band column, which is stored in the memory of Fig. 1 may be implemented, according to various aspects of the present revelation. Fig. Figure 5 is a circuit diagram of a single-terminal SRAM cell located in the memory of Fig. 1 may be implemented, according to various aspects of the present revelation. Fig. 6 is a fragmentary top view of an SRAM array, section by section or completely, located in the memory of Fig. 1 may be implemented, according to various aspects of the present revelation. DETAILED DESCRIPTION

[0005] The present disclosure relates generally to IC devices and in particular to fin-based ribbon cell structures for improving storage performance.

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact.

[0007] Furthermore, the present disclosure may repeat reference numbers and / or reference letters in various examples. This repetition serves the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed. Moreover, the formation of a feature on, connected with, and / or coupled to another feature in the present disclosure below may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be inserted between the features, so that the features may not be in direct contact. In addition, spatially relating terms, for example, "below," "above," "horizontal," "vertical," "above," "over," "below," "below," "top," "bottom," "uppermost," "lowest," etc., are used.and derivatives thereof (for example, "in a horizontal direction," "downward," "upward," etc.) are used for the simplicity of this disclosure to describe the relationship between one feature and another. These spatially related terms are intended to cover different orientations of the device containing the features.

[0008] For advanced IC technology nodes, fin-like field-effect transistors (FinFETs) (also known as non-planar transistors) have become a popular and promising candidate for low-loss, high-performance applications. Memory arrays, such as static random-access memory (SRAM) arrays, often incorporate FinFETs in memory cells to improve performance, with each cell capable of storing a small amount of data. Memory cell performance is largely dependent on the layout. For example, it has been observed that an inner memory cell in a memory array exhibits different performance than an edge memory cell. In some implementations, inner and edge memory cells have different threshold voltages (Vth). t ), different inflows (I on ) and / or different output currents (I off). Fin-based well-tie cells were thus implemented to stabilize the well potential, enabling a uniform charge distribution across an entire memory array and therefore uniform power across the memory cells. A fin-based well tie (also known as an "electrical tie") electrically connects a well region corresponding to a FinFET of a memory cell to a voltage node (or voltage line). For example, a fin-based n-well tie electrically connects an n-well region corresponding to a p-FinFET to a voltage node, such as a voltage node associated with the p-transistor, and a fin-based p-well tie electrically connects a p-well region corresponding to an n-FinFET to a voltage node, such as a voltage node associated with the n-transistor.

[0009] As FinFET technologies evolve toward increasingly smaller technology nodes (e.g., 20 nm, 16 nm, 10 nm, 7 nm and below), it has been observed that reducing fin spacing and fin width diminishes the benefits provided by fin-based trough bands. For example, reducing fin width has been observed to increase trough pickup resistance, such that the trough pickup resistance of fin-based (non-planar) trough bands is much higher than that of planar trough bands. Such increases in trough pickup resistance have been observed to degrade the latch-up performance of memory arrays using fin-based trough bands. The present disclosure therefore proposes modifications to fin-based trough band cells that can achieve performance improvements.For example, it has been observed that modifying the well doping configuration of fin-based well-band cells, such that the well doping configuration differs from that of fin-based memory cells, significantly improves memory performance. In some embodiments, the n-wells are removed from the p-well bands of the fin-based well-band cells to reduce the well pickup resistance associated with the p-well bands without affecting desired characteristics of the corresponding FinFETs (e.g., the voltage threshold) and / or requiring significant modifications to existing fabrication techniques. In such embodiments, the p-well bands contain only one p-well, while the n-well bands have an n-well positioned between p-wells.In some embodiments, such trough doping configurations of the n-trough bands are the same as the trough doping configurations in the fin-based memory cells. In some embodiments, a fin-based trough band cell contains a p-trough band arranged between n-trough bands, wherein the p-trough of the p-trough band and the p-troughs of the n-trough bands are combined to form an I-shaped p-trough in the fin-based trough band cell. In such embodiments, the n-trough band is a boundary section of the fin-based trough band cell, and the p-trough band is a central section of the fin-based trough band cell. In some embodiments, the disclosed fin-based trough band cells are arranged between memory cells. Details of the proposed fin-based trough band cell structures for improving memory performance are described below.Different embodiments may have different advantages, and no particular advantage requires any particular embodiment.

[0010] Fig. Figure 1 is a schematic top view of a memory 10, which can implement trough-configured tapes as described herein, according to various aspects of the present disclosure. The memory 10 is configured as a static random access memory (SRAM). However, the present disclosure also considers embodiments in which the memory 10 is configured as another type of memory, such as a dynamic random access memory (DRAM), a non-volatile random access memory (NVRAM), flash memory, or another suitable memory. The memory 10 can be contained in a microprocessor, main memory, and / or other IC device.In some implementations, Memory 10 can be a section of an integrated circuit (IC), a system-on-a-chip (SoC), or a section thereof, containing various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), LDMOS (laterally diffused MOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The various transistors can be planar transistors or multi-gate transistors, such as FinFETs, depending on the design requirements of Memory 10. Fig. For clarity, Figure 1 has been simplified to facilitate a better understanding of the concepts of the invention as presented in this disclosure. Additional features may be added to the memory 10, and some of the features described below may be replaced, modified, or omitted in other embodiments of the memory 10.

[0011] Memory 10 contains a memory array 12A and a memory array 12B, each containing memory cells 20, such as SRAM cells (also called bit cells), for storing data. The memory cells 20 contain various transistors, such as p-FinFETs and / or n-FinFETs, configured to enable reading and writing data to / from the memory cells 20. The memory cells 20 are arranged in column 1 (C1) to column N (CN), extending along a first direction (here in a y-direction), and row 1 (R1) to row M (RM), extending along a second direction (here in an x-direction), where N and M are positive integers.Columns 1 to N each contain a bit line pair extending along the first direction, such as a bit line (BL) and a bit line bar (BLB) (also referred to as a complementary bit line), which enables reading data from and / or writing data to corresponding memory cells 20 in true and complementary form, column by column. R1 to RM each contain a word line (WL), which enables access to corresponding memory cells 20 row by row. Each memory cell 20 is electrically connected to a corresponding BL, a corresponding BLB, and a corresponding WL, which are electrically connected to a control unit 20.The control unit 20 is configured to generate one or more signals for selecting at least one WL and at least one bit pair (here BL and BLB) for accessing at least one memory cell for read and / or write operations. The control unit 20 contains any circuitry suitable for enabling read / write operations to / from the memory cells, including, but not limited to, a column decoder circuit, a row decoder circuit, a column selector circuit, a row selector circuit, a read / write circuit (for example, configured to read data from and / or write data to the memory cells according to a selected bit pair (in other words, a selected column)), any other suitable circuitry, or combinations thereof.In some implementations, the control unit 20 includes at least one read amplifier configured to detect and / or amplify a voltage difference across a selected bit line pair. In some implementations, the read amplifier is configured to save or otherwise store data values ​​of the voltage difference.

[0012] A portion of the memory 10 is configured with dummy cells, such as edge dummy cells and trough-band cells, to ensure uniformity in the performance of the memory cells 20. Dummy cells are physically and / or structurally similar to the memory cells 20, but do not store any data. For example, dummy cells may include p-troughs, n-troughs, fin structures (containing one or more fins), gate structures, source / drain features, and / or contact features. Trough-band cells generally refer to dummy cells configured to electrically connect a voltage to an n-trough of the memory cells 20, a p-trough of the memory cells 20, or both.In the illustrated embodiment, the memory 10 contains the edge dummy cells 30 arranged along the first direction (here the y-direction) in an edge dummy cell column 35A and an edge dummy cell column 35B, wherein each R1 to RM of the memory cells 20 is arranged between an edge dummy cell 30 of edge dummy cell column 35A and an edge dummy cell 30 of edge dummy cell column 35B. Further referring to the illustrated embodiment, each C1 to CM of the memory cells 20 is arranged between the edge dummy cells 30. In some implementations, the edge dummy cell column 35A and / or the edge dummy cell column 35B extend essentially parallel to at least one bit line pair (here BL and BLB) of memory 10. In some implementations, the edge dummy cells 30 are configured to connect corresponding memory cells 20 with corresponding WLs.In some implementations, the edge dummy cells 30 contain circuitry for driving the WLs. In some implementations, the edge dummy cells 30 are electrically supplied with a voltage V. DD (for example, a positive supply voltage) and / or a supply voltage V SS (for example, an electrical ground) connected.

[0013] Referring further to the illustrated embodiment, a trough-band column 40 contains the trough-band cells 50 arranged along the first direction (here the y-direction). The trough-band column 40 is arranged between the memory arrangement 12A and the memory arrangement 12B, such that each row of memory cells 20 in the memory arrangement 12A is arranged between a corresponding edge dummy cell 30 and a corresponding trough-band cell 50, and each row of memory cells 20 in the memory arrangement 12B is arranged between a corresponding trough-band cell 50 and a corresponding edge dummy cell 30. In some implementations, the trough-band column 40 extends substantially parallel to at least one bit line pair (here BL and BLB) of the memory 10. In the illustrated embodiment, the trough-band cells 50 contain an n-trough-band, a p-trough-band, or combinations thereof.In some implementations, the tray-band cells 50 contain a p-tray arranged between n-tray-bands. The n-tray-band is configured to electrically couple an n-tray, corresponding to at least one p-FinFET of the memory cells 20, to a voltage source. As described herein, tray-band cells are configured to significantly reduce the tray pickup resistance, thereby improving the latch-up performance of the memory 10.

[0014] Fig. Figures 2A-2G are fragmentary schematic views of a trough belt cell, either sectionally or completely, such as trough belt cell 50, which is located in memory 10 of Fig. 1. is implemented, according to various aspects of the present revelation. Fig. 2A is a simplified schematic top view of the bathtub belt cell 50 (for example in an xy-plane); Fig. 2B is a schematic cross-sectional view of the bathtub belt cell 50 along line BB of Fig. 2A (for example, in a yz plane); Fig. 2C is a schematic cross-sectional view of the bathtub belt cell 50 along line CC of Fig. 2A (for example, in a yz plane); Fig. 2D is a schematic cross-sectional view of the bathtub belt cell 50 along line DD of Fig. 2A (for example, in an xz-plane); Fig. 2E is a schematic cross-sectional view of the bathtub belt cell 50 along line EE of Fig. 2A (for example, in an xz-plane); Fig. 2F is a schematic cross-sectional view of the bathtub belt cell 50 along line FF of Fig. 2A (for example, in an xz-plane); and Fig. 2G is a schematic cross-sectional view of the bathtub belt cell 50 along line GG of Fig. 2A (for example, in an xz plane). The trough-band cell 50 is located between an SRAM cell 20A of memory cells 20 and an SRAM cell 20B of memory cells 20. In some implementations, the width of the trough-band cell 50 (here along a y-direction) is essentially equal to the width of the memory cells 20 (here the SRAM cells 20A, 20B). The trough-band cell 50 contains a p-trough-band 50A located between an n-trough-band 50B and an n-trough-band 50C along a length of the trough-band cell 50 (here along an x-direction). In such a configuration, the n-tub tape 50B is arranged adjacent to a corresponding memory cell 20, such as the SRAM cell 20A, and the n-tub tape 50C is arranged adjacent to a corresponding memory cell 20, such as the SRAM cell 20B.In some implementations, the p-well strip 50A is arranged between the n-well strips 50B and n-well strips 50C along a fin longitudinal direction. The p-well strip 50A is used to electrically connect the p-wells of the memory cells 20 to a first supply voltage, such as a supply voltage V. SS , configured. The n-tubular strip 50B and the n-tubular strip 50C are each for electrically connecting n-tubular memory cells 20 to a second supply voltage, such as a supply voltage V. DD , configured. In some implementations, the supply voltage V DD a positive supply voltage and the supply voltage V SS is an electrical mass. Fig. For clarity, figures 2A-2G have been simplified to facilitate a better understanding of the concepts of the invention as presented in this disclosure. Additional features may be added in the trough belt cell 50, and some of the features described below may be replaced, modified, or omitted in other embodiments of the trough belt cell 50.

[0015] The tray-loading cell 50 is physically and / or structurally configured similarly to the memory cells 20. For example, the tray-loading cell 50 contains a substrate (a wafer) 110. In the illustrated embodiment, the substrate 110 is a bulk substrate containing silicon. Alternatively or additionally, the bulk substrate contains another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and / or cadmium telluride; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; other materials of Group III-V; other materials of Group II-IV; or combinations thereof.Alternatively, substrate 110 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated by separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Substrate 110 contains doped regions, such as an n-doped region 112A, an n-doped region 112B, an n-doped region 112C, an n-doped region 112D, a p-doped region 114A, a p-doped region 114B and a p-doped region 114C (hereinafter referred to as the n-wells 112A-112D and the p-wells 114A-114C).n-doped regions, such as n-wells 112A-112D, are doped with n-dopants, such as phosphorus, arsenic, another n-dopant, or combinations thereof. p-doped regions, such as p-wells 114A-114C, are doped with p-dopants, such as boron, indium, another p-dopant, or combinations thereof. In some implementations, substrate 110 contains doped regions formed with a combination of p- and n-dopants. The various doped regions can be formed directly on and / or within substrate 110, providing, for example, a p-well structure, an n-well structure, a double-well structure, an elevated structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process can be used to form the various doped regions.

[0016] The various doped regions are configured according to the design requirements of memory 10. SRAM cells 20A and 20B each contain an n-well region sandwiched between p-well regions. For example, SRAM cell 20A contains n-well 112A and p-well 114A, and SRAM cell 20B contains n-well 112B and p-well 114B. N-wells 112A and 112B are configured for PMOS FinFETs, such as pull-up (PU) FinFETs, and p-wells 114A and 114B are configured for NMOS FinFETs, such as pull-down (PD) FinFETs. The p-tub 114A contains a p-tub subregion 114A-1 and a p-tub subregion 114A-2, and the p-tub 114B contains a p-tub subregion 114B-1 and a p-tub subregion 114B-2.The n-tub 112A is located between the p-tub subregion 114A-1 and the p-tub subregion 114A-2 along the y-direction (here along a gate longitudinal direction), and the n-tub 112B is located between the p-tub subregion 114B-1 and the p-tub subregion 114B-2 along the y-direction. The n-tub 112A, the p-tub subregion 114A-1, and the p-tub subregion 114A-2 extend along the entire length of the SRAM cell 20A, such that the lengths of the n-tub 112A, the p-tub subregion 114A-1, and the p-tub subregion 114A-2 are essentially equal to one length of the SRAM cell 20A (here along the x-direction). The n-tub 112B, the p-tub subregion 114B-1 and the p-tub subregion 114B-2 extend along the entire length of the SRAM cell 20B, so that the lengths of the n-tub 112B, the p-tub subregion 114B-1 and the p-tub subregion 114B-2 are essentially equal to the length of the SRAM cell 20B (here along the x-direction).The n-wells 112A, 112B have a width W1, the p-well subregions 114A-1, 114B-1 have a width W2, and the p-well subregions 114A-2, 114B-2 have a width W3. The widths W1, W2, and W3 are narrower than the widths of the SRAM cells 20A, 20B. In the illustrated embodiment, the sum of the widths W1, W2, and W3 is essentially equal to the widths of the SRAM cells 20A, 20B (in other words, W1 + W2 + W3 = width of the SRAM cells 20A, 20B). In some implementations, the widths W1, W2, and W3 are the same. In other implementations, the widths W1, W2, and W3 are different. In some implementations, widths W2 and W3 are the same but differ from width W1. This disclosure considers any configuration of widths W1, W2, and W3.

[0017] The present disclosure proposes a trough doping configuration in the trough band cell 50 which significantly reduces the trough pickup resistance, in particular the trough pickup resistance associated with the p-trough band 50A. Fig. 2A-2G contains the trough-band cell 50, the n-trough 112C, the n-trough 112D, and the p-trough 114C. The p-trough 114C is I-shaped in a top view along one width of the trough-band cell 50 (here along the y-direction) and H-shaped in a top view along one length of the trough-band cell 50 (here along the x-direction). For example, the p-trough 114C contains a p-trough subregion 114C-1, a p-trough subregion 114C-2, and a p-trough subregion 114C-3. The n-tub 112C is located between the p-tub sub-region 114C-1 and the p-tub sub-region 114C-2 in the n-tub band 50B, and the n-tub 112D is located between the p-tub sub-region 114C-1 and the p-tub sub-region 114C-2 in the n-tub band 50C. The n-tub 112C extends uninterrupted into the n-tub 112A, and the n-tub 112D extends uninterrupted into the n-tub 112B.In some implementations, no actual interface may be observed between n-tub 112C and n-tub 112A, and no actual interface may be observed between n-tub 112D and n-tub 112B. n-tub 112C has a length L1 and a width W4. n-tub 112D has a length L2 and a width W5. The length L1 is shorter than the length of tub ribbon cell 50 and essentially equal to the length of n-tub ribbon 50B. The length L2 is shorter than the length of tub ribbon cell 50 and essentially equal to the length of n-tub ribbon 50C. The widths W4 and W5 are essentially equal to the width W1 of n-tubs 112A and 112B of SRAM cells 20A and 20B. In the embodiment shown, the width W4 is essentially equal to the width W5, although the present disclosure also considers embodiments in which the width W4 is wider or narrower than the width W5.

[0018] The p-trough subregions 114C-1 and 114C-2 extend along the entire length of trough band cell 50. Thus, p-trough subregions 114C-1 and 114C-2 span p-trough band 50A, n-trough band 50B, and n-trough band 50C. P-trough subregion 114C-1 extends uninterrupted into p-trough subregions 114A-1 and 114B-1 of p-troughs 114A and 114B. In some implementations, no actual interface may be observed between p-trough subregion 114C-1 and p-trough subregions 114A-1 and 114B-1. The p-tub subregion 114C-2 extends without interruption into the p-tub subregions 114A-2 and 114B-2 of the p-tubs 114A and 114B. In some implementations, no actual interface may be observed between the p-tub subregion 114C-2 and the p-tub subregions 114A-2 and 114B-2. The p-tub subregion 114C-1 has a length of L3 and a width of W6.The p-tub section 114C-2 has a length L4 and a width W7. The lengths L3 and L4 are essentially equal to the length of the tub belt cell 50. The widths W6 and W7 are narrower than the width of the tub belt cell 50. In the illustrated embodiment, the width W6 is essentially equal to the width W2 of the corresponding p-tub sections 114A-1 and 114B-1 of the p-tubs 114A and 114B, and the width W7 is essentially equal to the width W3 of the corresponding p-tub sections 114A-2 and 114B-2 of the p-tubs 114A and 114B. Referring further to the illustrated embodiment, the width W6 is essentially equal to the width W7, although the present disclosure also considers embodiments in which the width W6 is wider or narrower than the width W7.

[0019] The p-trough subregion 114C-3 is arranged between the p-trough subregions 114C-1 and 114C-2 along the width of the trough belt cell 50 in the p-trough belt 50A, such that the p-trough subregions 114C-3, 114C-2, and 114C-1 combined span the entire p-trough belt 50A. The p-trough subregion 114C-3 is further arranged between the n-trough 112C and the n-trough 112D along the length of the trough belt cell 50. The p-trough subregion 114C-3 thus forms a central (or middle) section of the trough belt cell 50 and the p-trough belt 50A. In some implementations, a symmetry axis of the p-tub subregion 114C-3 along the latitude direction (here y) is essentially aligned with a symmetry axis of the p-tub subregion 114C-1 along the latitude direction and a symmetry axis of the p-tub subregion 114C-2 along the latitude direction.In such implementations, the symmetry axes of the p-tub subregions 114C-1, 114C-2, and 114C-3 are aligned along a common axis of symmetry. The p-tub subregion 114C-3 has a length L5 and a width W8. The length L5 is shorter than the length of the tub belt cell 50 and essentially equal to the length of the p-tub belt 50A. The width W8 is narrower than the width of the tub belt cell 50. In the illustrated embodiment, the width W8 is essentially equal to the width W4 of the n-tub 112C and / or the width W5 of the n-tub 112D (and is thus essentially equal to the width W1 of the n-tubs 112A, 112B in the SRAM cells 20A, 20B). Further referring to the embodiment shown, the sum of the widths W6, W7 and W8 is essentially equal to the width of the tub band cell 50 (in other words, W6 + W7 + W8 = width of tub band cell 50 and W8 = width of tub band cell 50 - (W6 + W7)).

[0020] By implementing an I-shaped p-well 114C in the well-band cell 50, the well-doping configuration of the p-well band 50A differs from the well-doping configuration of the memory cells 20 (here, the SRAM cells 20A, 20B), while the well-doping configurations of the n-well bands 50B, 50C are the same as the well-doping configuration of the memory cells 20. For example, the p-well band 50A contains only one p-well and is free of an n-well, the n-well bands 50B, 50C contain an n-well arranged between the p-wells, and the SRAM cells 20A, 20B contain an n-well arranged between the p-wells.In such a configuration, the tubing pickup resistance associated with the p-tub band 50A is not limited because the p-tub of the p-tub band 50A is not divided into individual sections as in conventional tubing bands, but instead extends continuously without interruption within the p-tub band 50. This allows the p-tub band 50A to achieve the entire tubing pickup resistance and block noise from the n-tubs, such as those of the n-tub bands 50B and 50C. For example, it was observed that eliminating pn junctions from the p-well band 50A (and thus pn depletion regions that can increase resistance when the p-well band 50A is connected to a voltage) significantly reduces the well pickup resistance of the p-well band 50A, resulting in improved performance of the memory 10.

[0021] The trough-band cell 50 further comprises the fins 120 (also referred to as fin structures or active fin regions) arranged over the substrate 110, wherein the fins 120 are configured identically or similarly to the fins of the n-FinFETs and / or p-FinFETs of the SRAM cells 20A, 20B. The fins 120 are substantially parallel to one another and each has a length defined in the x-direction, a width defined in the y-direction, and a height defined in a z-direction. The fins 120 each have at least one channel region, at least one source region, and at least one drain region defined along their length in the x-direction, with a channel region being arranged between a source region and a drain region (generally referred to as source / drain regions).The channel regions contain a top section defined between sidewall sections, where the top section and the sidewall sections engage with a gate structure (as described below) so that current can flow between the source / drain regions during operation. The source / drain regions also contain top sections defined between sidewall sections. In some implementations, the fins 120 are a section of the substrate 110 (such as a section of a material layer of the substrate 110). For example, if the substrate 110 contains silicon, the fins 120 contain silicon. Alternatively, in some implementations, the fins 120 are defined in a material layer, such as one or more semiconductor material layers superimposed on the substrate 110.For example, the fins 120 can contain a semiconductor layer stack having various semiconductor layers (such as a heterostructure) arranged over the substrate 110. The semiconductor layers can contain any suitable semiconductor materials, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers can contain the same or different materials, etch rates, atomic fractions of the constituents, weight fractions of the constituents, thicknesses, and / or configurations. In some implementations, the semiconductor layer stack contains alternating semiconductor layers, such as semiconductor layers composed of a first material and semiconductor layers composed of a second material. For example, silicon layers and silicon germanium layers alternate in the semiconductor layer stack (e.g., SiGe / Si / ...).In some implementations, the semiconductor layer stack contains semiconductor layers of the same material, but with alternating atomic proportions of the constituents, such as semiconductor layers containing one constituent with a first atomic proportion and semiconductor layers containing the constituent with a second atomic proportion. For example, the silicon-germanium semiconductor layer stack contains silicon-germanium layers with alternating silicon and / or germanium atomic proportions (e.g., Si). a Ge b / Si c Ge d / . . ., where a, c are different atomic fractions of silicon and b, d are different atomic fractions of germanium).

[0022] The fins 120 are formed over the substrate 110 by any suitable process. In some implementations, a combination of deposition, lithography, and / or etching processes is performed to define the fins 120 extending from the substrate 110. For example, forming the fins 120 involves performing a lithography process to form a structured mask layer over the substrate 110 (or a material layer, such as a heterostructure, arranged over the substrate 110) and performing an etching process to transfer a structure defined in the structured mask layer onto the substrate 110 (or the material layer, such as the heterostructure, arranged over the substrate 110). The lithography process may involve forming a resist layer on a mask layer arranged over the substrate 110 (for example, by rotoplating).The process includes performing a pre-exposure baking process, an exposure process using a mask, a post-exposure baking process, and a development process. During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light). The mask blocks, transmits, and / or reflects the radiation onto the resist layer depending on the mask structure and / or type (e.g., a binary mask, a phase-shift mask, or an EUV mask), projecting an image onto the resist layer that corresponds to the mask structure. Because the resist layer is sensitive to radiant energy, exposed portions of the resist layer undergo chemical changes.Exposed (or non-exposed) sections of the resist layer are dissolved during the development process, depending on the properties of the resist layer and the properties of the developing solution used. After development, the structured resist layer contains a resist structure corresponding to the mask. The etching process uses the structured resist layer as an etching mask to remove sections of the mask layer and then uses the structured mask layer to remove sections of substrate 110 (or a layer of material placed over substrate 110). The etching process can be a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process,include another suitable etching process or combinations thereof. The structured resist layer is removed during or after the etching process, for example, by a resist peeling process. Alternatively or additionally, the fins 120 are patterned by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric patterning (SIDP) process, another double patterning process, or combinations thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELE) process),a self-aligned triple patterning (SATP) process, another triple patterning process, or combinations thereof, another multiple patterning process (for example, a self-aligned quadruple patterning (SAQP) process), or combinations thereof. In general, double patterning and / or multiple patterning processes combine lithography processes and self-aligned processes, enabling the creation of structures with, for example, smaller spacing dimensions than can otherwise be obtained using a single direct lithography process. For example, in some implementations, a mandrel layer is used as an etching mask to remove portions of the mask layer.wherein the spine layer is formed using a spacer structuring technique. For example, forming the spine layer involves forming a structured sacrificial layer (containing sacrificial features exhibiting a first spacing) over the mask layer using a lithographic process (for example, using the structured resist layer), forming a spacer layer over the structured sacrificial layer, etching the spacer layer to form spacers along sidewalls of each sacrificial feature (for example, the spacer layer is removed from a top surface of the sacrificial features and a section of a top surface of the mask layer), and removing the structured sacrificial layer, leaving spacers exhibiting a second spacing (which may be described as a structured spacer layer containing openings,(which release a section of the mask layer). The spike layer and its spikes can thus be referred to as a spacer layer and spacers, respectively. In some implementations, the spacer layer is conformally formed over the structured sacrificial layer, so that the spacer layer has a substantially uniform thickness. In some implementations, the spacers are trimmed before or after the removal of the structured sacrificial layer. In some implementations, directed self-assembly (DSA) techniques are implemented during fin formation.

[0023] An insulating feature 122 is / are formed above and / or within the substrate 110 to isolate different regions, such as different device regions, of the IC device 100. For example, the insulating feature 122 separates and isolates active device regions and / or passive device regions from one another, such as the different FinFETs of the memory 10. The insulating feature 122 also separates and isolates the fins 120 from one another. In the illustrated embodiment, the insulating feature 122 surrounds a lower portion of the fins 120. The insulating feature 122 contains silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (containing, for example, silicon, oxygen, nitrogen, carbon, and / or another suitable insulating component), or combinations thereof.The insulation feature 122 can contain various structures, such as shallow trench isolation (STI), deep trench isolation (DTI), and / or local oxidation of silicon (LOCOS) structures. In some implementations, STI features can be formed by etching a trench in the substrate 110 (for example, using a dry etching process and / or a wet etching process) and filling the trench with insulator material (for example, using a chemical vapor deposition process or a spin-on-glass process). A chemical mechanical polishing (CMP) process can be performed to remove excess insulator material and / or to planarize the top surface of the insulation feature 122.In some implementations, STI features can be formed by depositing an insulator material over the substrate 110 after the fins 120 have formed (in some implementations such that the insulator material layer fills gaps (trenches) between the fins 120) and etching back the insulator material layer to form the insulation feature 122. In some implementations, the insulation feature 122 contains a multilayer structure that fills the trenches, such as a dielectric mass layer arranged over a dielectric lining layer, wherein the dielectric mass layer and the dielectric lining layer contain materials depending on the design requirements (for example, a dielectric mass layer containing silicon nitride arranged over a dielectric lining layer containing a thermal oxide).In some implementations, the insulation feature 122 includes a dielectric layer arranged over a doped lining layer (which may contain, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG)).

[0024] The trough-band cell 50 further contains the gate structures 130 arranged over the fins 120 and the insulating feature 122, wherein the gate structures 130 are configured identically or similarly to the gate structures of the n-FinFETs and / or p-FinFETs of the SRAM cells 20A, 20B. The gate structures 130 extend along the y-direction (for example, substantially perpendicular to the fins 120) and intersect corresponding fin structures 120, such that the gate structures 130 enclose upper sections of the corresponding fins 120. The gate structures 130 are arranged over and enclose channel regions of the fins 120, thereby interposing corresponding source / drain regions of the fins 120. The gate structures 130 are in interaction with the corresponding channel regions of the fins 120, so that during operation current can flow between the corresponding source / drain regions of the fins 120.The gate structures 130 in the trough-band cell 50 are dummy gate structures, whereas the gate structures in the memory cells 20 are active gate structures (the gate structures 130 are configured identically to the gate structures of the FinFETs in the memory cells 20). An "active gate structure" generally refers to an electrically functional gate structure, whereas a "dummy gate structure" generally refers to an electrically non-functional gate structure. For example, the gate structures 130 mimic physical properties of the active gate structures of the FinFETs in the memory cells 20, such as the physical dimensions of the active gate structures, but are electrically non-functional (in other words, they do not allow current flow between source / drain regions).In some implementations, the gate structures 130 enable a substantially uniform processing environment, for example, by allowing uniform epitaxial material growth in source / drain regions of the fins 120 (e.g., during the formation of epitaxial source / drain features), uniform etch rates in source / drain regions of the fins 120 (e.g., during the formation of source / drain recesses), and / or uniform, substantially planar surfaces (e.g., by reducing (or preventing) CMP-induced warping effects). In the illustrated embodiment, the gate structures 130 contain gate stacks configured identically to the gate stacks of the FinFET gate structures in the memory cells 20.For example, a gate stack of each gate structure 130 contains a gate dielectric 132, a gate electrode 134, and a hard mask layer 136, together with gate spacers 138 arranged adjacent to the gate stack (for example, along its sidewalls). The gate dielectric 132, the gate electrode 134, and / or the hard mask layer 136 may contain the same or different layers and / or materials in the gate structures 130. Since the gate structures 130 span the p-tub band 50A, the n-tub band 50B, and the n-tub band 50C, the gate structures 130 may have different layers in regions corresponding to the p-tub band 50A, the n-tub band 50B, and the n-tub band 50C.For example, the number, configuration and / or materials of layers of the gate dielectric 132 and / or the gate electrode 134 corresponding to the p-tub band 50A may differ from the number, configuration and / or materials of layers of the gate dielectric 32 and / or the gate electrode 34 corresponding to the n-tub band 50B and / or the n-tub band 50C.

[0025] The gate stacks of the gate structures 130 are fabricated according to a gate-last process, a gate-first process, or a gate-last / gate-first hybrid process. In gate-last process implementations, one or more of the gate structures 130 contain dummy gate stacks, which are subsequently replaced by metal gate stacks. The dummy gate stacks contain, for example, an interface layer (containing, for example, silicon oxide) and a dummy gate electrode layer (containing, for example, polysilicon). In such implementations, the dummy gate electrode layer is removed to form openings (trenches) in which the gate dielectric 132 and / or the gate electrode 134 are subsequently formed. In some implementations, a dummy gate stack of at least one of the gate structures 130 is replaced by a metal gate stack, while a dummy gate stack of at least one of the gate structures 130 remains.For example, some or all of the gate structures may contain 130 polysilicon gate stacks. Gate-last and / or gate-first processes may implement deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. Deposition processes include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods, or combinations thereof.Lithographic structuring processes include resist coating (e.g., rotary coating), soft baking, mask alignment, exposure, post-exposure baking, resist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithographic exposure process is supported, implemented, or replaced by other methods, such as maskless lithography, electron beam writing, or ion beam writing. Etching processes include dry etching, wet etching, other etching processes, or combinations thereof. A CMP process can be performed to remove any excess material from the gate dielectric 132, the gate electrode 134, and / or the hard mask layer 136, thereby planarizing the gate structures 130.

[0026] The gate dielectric 132 is arranged over the fin 120 and the insulating feature 122, such that the gate dielectric 132 has a substantially uniform thickness. The gate dielectric 132 comprises a dielectric material, such as silicon oxide, a high k-value dielectric material, another suitable dielectric material, or combinations thereof. In the illustrated embodiment, the gate dielectric 132 comprises one or more high k-value dielectric layers, including, for example, hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, another suitable component, or combinations thereof. In some implementations, the one or more high k-value dielectric layers include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, another suitable high k-value dielectric material, or combinations thereof.A high k-value dielectric material generally refers to dielectric materials that have a high dielectric constant, for example, higher than that of silicon oxide (k ≈ 3.9). In some implementations, the gate dielectric 132 further includes an interface layer (containing a dielectric material, such as silicon oxide) arranged between the high k-value dielectric layer and the fins 120A and the insulating feature 122.

[0027] The gate electrode 134 is positioned above the gate dielectric 132. The gate electrode 134 contains an electrically conductive material. In some implementations, the gate electrode 134 contains multiple layers, such as one or more cover layers, working-functional layers, adhesive / barrier layers, and / or metal-filling (or mass) layers. A cover layer may contain a material that prevents or eliminates the diffusion and / or reaction of constituents between the gate dielectric 132 and other layers of the gate structures 130 (especially the gate layers containing metal). In some implementations, the cover layer contains a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W₂N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof.A working-functional layer can contain a conductive material tuned to exhibit a desired working function (such as an n-working function or a p-working function), such as n-working-functional materials and / or p-working-functional materials. p-working-functional materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, another p-working-functional material, or combinations thereof. n-working-functional materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, another n-working-functional material, or combinations thereof.An adhesive / barrier layer may contain a material that promotes adhesion between adjacent layers, such as the working functional layer and the metal filler layer, and / or a material that blocks and / or reduces diffusion between gate layers, such as the working functional layer and the metal filler layer. For example, the adhesive / barrier layer may contain a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, another suitable metal, or combinations thereof), metal oxides, metal nitrides (e.g., TiN), or combinations thereof. A metal filler layer may contain a suitable conductive material, such as Al, W, and / or Cu. The hard mask layer 136 is arranged over the gate electrode 134 and the gate electrode 132 and contains any suitable material, such as silicon, nitrogen, and / or carbon (e.g., silicon nitride or silicon carbide).

[0028] The gate spacers 138 are formed by any suitable process and contain a dielectric material. The dielectric material can contain silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer containing silicon and nitrogen, such as a silicon nitride layer, can be deposited over the substrate 110 and subsequently anisotropically etched to form the gate spacers 138. In some implementations, the gate spacers 138 contain a multilayer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide.In some implementations, the gate spacers 138 can contain more than one set of spacers, such as dense spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers formed adjacent to the gate stack. In such implementations, the different sets of spacers can contain materials exhibiting different etching properties. For example, a first dielectric layer containing silicon and oxygen can be deposited over the substrate 110 and subsequently anisotropically etched to form a first set of spacers adjacent to the gate stack, and a second dielectric layer containing silicon and nitrogen can be deposited over the substrate 110 and subsequently anisotropically etched to form a second set of spacers adjacent to the first set of spacers.Implantation, diffusion and / or annealing processes can be performed to create lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features (both of which are found in . Fig. 2A-2G are not shown) in Source / Drain (S / D) regions of the fins 120 before and / or after forming the Gate-Spacer 138.

[0029] The trough ribbon cell 50 further contains source features and drain features (referred to as source / drain features) arranged in source / drain regions of the fins 120, wherein the source / drain features are configured in the same or similar ways as the source / drain features of the n-FinFETs and / or p-FinFETs of the SRAM cells 20A, 20B. For example, a semiconductor material is epitaxially grown on the fins 120, forming the epitaxial source / drain features 140A on the fins 120 over the n-wells 112C, 112D (in other words, in regions of the well band cell 50 configured similarly to the p-FinFET regions containing the p-FinFETs of the SRAM memory cells 20A, 20B) and the epitaxial source / drain features 140B on the fins 120 over the p-well 114C (in other words, in regions of the well band cell 50 configured similarly to the n-FinFET regions containing the n-FinFETs of the SRAM memory cells 20A, 20B).In some implementations, a fin-removal process (e.g., a back-etching process) is performed on the source / drain regions of the fins 120, so that the epitaxial source / drain features 140A, 140B are grown from the lowest sections of the fins 120. In other implementations, the source / drain regions of the fins 120 are not subjected to a fin-removal process, so that the epitaxial source / drain features 140A, 140B are grown from and encircle at least one section of the upper active fin regions of the fins 120. The epitaxial source / drain features 140A, 140B can extend (grow) laterally along the y-direction (in some implementations essentially perpendicular to the fins 120), so that the epitaxial source / drain features 140A, 140B are fused epitaxial source / drain features spanning more than one fin 120.In some implementations, the epitaxial source / drain features 140A and / or the epitaxial source / drain features 140B contain partially fused sections (with breaks (or gaps) between the epitaxial material grown from adjacent fins 120) and / or fully fused sections (without breaks (or gaps) between the epitaxial material grown from adjacent fins 120).

[0030] An epitaxy process can implement CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxy process can utilize gaseous and / or liquid precursors that interact with the composition of the fins 120. The epitaxial source / drain features 140A and 140B are doped with n-type and / or p-type dopants. In some implementations, the n-well bands 50B, 50C and the p-FinFETs in memory cells 20 have the same doped epitaxial source / drain features, and the p-well band 50A and the n-FinFETs of memory cells 20 have the same doped epitaxial source / drain features.For example, the epitaxial source / drain features 140A of the n-tub bands 50B, 50C and the epitaxial source / drain features of the p-FinFETs in the memory cells 20 can contain epitaxial layers containing silicon and / or germanium, wherein the silicon-germanium-containing epitaxial layers are doped with boron, carbon, another p-dopant or combinations thereof (for example forming an epitaxial Si:Ge:B layer or an epitaxial Si:Ge:C layer).Further referring to the example, the epitaxial source / drain features 140B of the p-tub band 50A and the epitaxial source / drain features of the n-FinFETs in the memory cells 20 can contain epitaxial layers containing silicon and / or carbon, wherein the silicon-containing epitaxial layers or the silicon-carbon-containing epitaxial layers are doped with phosphorus, arsenic, another n-dopant or combinations thereof (for example, forming an epitaxial Si:P layer, an epitaxial Si:C layer, an epitaxial Si:As layer or an epitaxial Si:C:P layer). In some implementations, the n-well bands 50B, 50C and the p-FinFETs of memory cells 20 exhibit oppositely doped epitaxial source / drain features, and the p-well band 50A and the n-FinFETs of memory cells 20 exhibit oppositely doped epitaxial source / drain features.In some implementations, the epitaxial source / drain features 140A and 140B contain materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel regions. In some implementations, the epitaxial source / drain features 140A and 140B are doped during deposition by adding impurities to a starting material for the epitaxial process. In some implementations, the epitaxial source / drain features 140A and 140B are doped by an ion implantation process following a deposition process. In some implementations, annealing processes are performed to activate dopants in the epitaxial source / drain features 140A, 140B, and / or other source / drain features of Memory 10, such as HDD regions and / or LDD regions.

[0031] An MLI (multilayer interconnect) feature 150 is arranged above the substrate 110.The MLI feature 150 connects various devices (for example, the p-FinFETs in memory cells 20, the n-FinFETs in memory cells 20, the n-well bands in n-well band regions 50A, the p-well bands in p-well band region 50B, transistors, resistors, capacitors and / or inductors) and / or components (for example, gate structures of the p-FinFETs and / or n-FinFETs of memory cells 20, source / drain features (for example, the epitaxial source / drain features 140A, 140B and / or the epitaxial source / drain features of the p-FinFETs and / or the n-FinFETs of memory cells 20) and / or doped wells of well band 50 (for example, the n-wells 112C, 112D and / or the p-tub 114C) electrically interact with each other, so that the various devices and / or components can operate as specified by the design requirements of the memory 10.MLI feature 150 contains a combination of dielectric layers and electrically conductive layers (e.g., metal layers) configured to form various interconnection structures. The conductive layers are configured to form vertical interconnection features, such as device-level contacts and / or vias, and / or horizontal interconnection features, such as conductive traces. Vertical interconnection features typically connect horizontal interconnection features in different layers (or different levels) of MLI feature 150.During operation, the interconnection features are configured to route signals between the devices and / or components of the memory 10 and / or to distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the devices and / or components of the memory 10. For example, MLI feature 150 includes interconnection features configured to route a power supply or ground voltage to the p-tub tape 50A and / or the n-tub tapes 50B and 50C. It should be noted that, although MLI feature 150 is presented with a given number of dielectric and conductive layers, this disclosure also considers an MLI feature 150 with more or fewer dielectric and / or conductive layers.

[0032] The MLI feature 150 contains one or more dielectric layers, such as an interlayer dielectric layer (ILD-0) 152 arranged over the substrate 110 (in particular over the epitaxial source / drain features 140A, 140B, the gate structures 130 and the fins 120) and an interlayer dielectric layer 154 (ILD-1) arranged over the ILD layer 152. The ILD layers 152, 154 contain a dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low k-value dielectric material, another suitable dielectric material or combinations thereof.Examples of low-k dielectric materials include FSG, carbon-doped silicon dioxide, Black Diamond® (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK® (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In the illustrated embodiment, the ILD layers 152 and 154 are dielectric layers containing a low-k dielectric material (generally referred to as low-k dielectric layers). In some implementations, a low-k dielectric material generally refers to materials with a dielectric constant (k) less than 3. The ILD layers 152 and 154 may contain a multilayer structure with several dielectric materials.The MLI feature 150 may further include one or more contact etch stop layers (CESLs) arranged between the ILD layers 152 and 154, such as a CESL arranged between ILD layer 152 and ILD layer 154. In some implementations, a CESL is arranged between the substrate 110 and / or the insulating feature 122 and the ILD layer 152. The CESLs contain a material different from that of the ILD layers 152 and 154, such as a dielectric material different from the dielectric material of the ILD layers 152 and 154. For example, if the ILD layers 152 and 154 contain a dielectric material with a low k-value, the CESLs contain silicon and nitrogen, such as silicon nitride or silicon oxynitride.The ILD layers 152, 154 are formed over substrate 110 by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable processes, or combinations thereof. In some implementations, the ILD layers 152, 154 are formed by a flowable CVD (FCVD) process, which includes, for example, the deposition of a flowable material (such as a liquid compound) over substrate 110 and the conversion of the flowable material into a solid material by a suitable technique, such as thermal annealing and / or UV radiation treatment. Following the deposition of the ILD layer 152 and / or the CESL, a CMP process and / or another planarization process is carried out until a top surface of the gate stack of the gate structures 130 is reached (exposed).Following the deposition of the ILD layer 154 and / or the CESL, a CMP process and / or another planarization process can be carried out.

[0033] In Fig. 2A-2G are device-level contacts (such as the n-well contacts 160A and the p-well contacts 160B), vias, and / or conductive traces (collectively referred to as a metal-one (M1) layer of MLI feature 150) arranged in one or more of the ILD layers 152, 154 to form interconnect structures. The device-level contacts (such as the n-well contacts 160A and the p-well contacts 160B), the vias, and / or the conductive traces contain any suitable electrically conductive material, such as Ta, Ti, Al, Cu, Co, W, TiN, TaN, other suitable conductive materials, or combinations thereof.Various conductive materials can be combined to provide the device-level contacts (such as the n-well contacts 160A and the p-well contacts 160B), the vias, and / or the conductive lines with various layers, such as a barrier layer, an adhesion layer, a lining layer, a ground layer, another suitable layer, or combinations thereof. In some implementations, the device-level contacts (such as the n-well contacts 160A and the p-well contacts 160B) contain Ti, TiN, and / or Co; the vias contain Ti, TiN, and / or W; and the conductive lines contain Cu, Co, and / or Ru. The contacts at the device level (such as the n-well contacts 160A and the p-well contacts 160B), the vias and / or the conductive lines are formed by structuring the ILD layers 152, 154.The structuring of ILD layers 152 and 154 can include lithography and / or etching processes to create openings (trenches), such as contact openings, via openings, and / or conduction openings, in the respective ILD layers 152 and 154. In some implementations, the lithography processes include forming a resist layer over the respective ILD layers 152 and 154, exposing the resist layer to structured irradiation, and developing the exposed resist layer, thereby forming a structured resist layer that can be used as a masking element for etching one or more openings in the respective ILD layers 152-154. The etching processes include dry etching, wet etching, other etching processes, or combinations thereof. Subsequently, the opening(s) are filled with one or more conductive materials.The conductive material(s) can be deposited by PVD, CVD, ALD, electroplating, electroless deposition, another suitable deposition process, or a combination thereof. Subsequently, any excess conductive material can be removed by a planarization process, such as a CMP process, thereby planarizing the top surface of the ILD layers 152, 154, the device-level contacts (such as the n-well contacts 160A and the p-well contacts 160B), the vias, and / or the conductive traces.

[0034] The n-tub contacts 160A (also referred to as n-tub pickup regions) are arranged on the corresponding n-tubs 112C, 112D such that the n-tub contacts 160A electrically supply the n-tubs 112C, 112D with a supply voltage, such as the supply voltage V DD, connect; and the p-tub contacts 160B (also referred to as p-tub pickup regions) are arranged on the p-tub 114C such that the p-tub contacts 160B electrically connect the p-tub 114C to a supply voltage, such as the supply voltage V SSThe N-well contacts 160A and the p-well contacts 160B extend through the ILD layer 152, the ILD layer 154, and the insulating features 122, although the present disclosure also considers embodiments in which the n-well contacts 160A and / or the p-well contacts 160B extend through more or fewer ILD layers and / or CESLs of the MLI feature 150. In some implementations, one or more of the n-well contacts 160A and / or the p-well contacts 160B do not electrically connect the n-wells 112C, 112D, and / or the p-well 114A to another electrically conductive feature of the MLI feature 150, such as vias. In such implementations, one or more of the n-tub contacts 160A and / or the p-tub contacts 160B are dummy contacts, which have physical properties similar to non-dummy contacts in order to enable a substantially uniform processing environment.

[0035] In the illustrated embodiment, the p-well contacts 160B are arranged in the p-well strip 50A, and the n-well strips 50B, 50C are free of the p-well contacts 160B. Because the p-well strip 50A is free of an n-well, the p-well contacts 160B (p-well pickup regions) exhibit a reduced well-pickup resistance compared to conventional p-well strips, which typically have a doping configuration similar to the n-well strips 50B, 50C, such that the p-well contacts are arranged on two p-wells separated by an n-well. Further referring to the illustrated embodiment, the p-well strip 50A has more contacts than the n-well strips 50B, 50C. For example, the p-tub band range 50A contains nine p-tub contacts 160B, while the n-tub bands 50B, 50C each contain three n-tub contacts 160A.The present disclosure considers any configuration of the n-type cup contacts 160A and / or the p-type cup contacts 160B. For example, . Fig. 3 a simplified schematic view from above of another embodiment of a trough belt cell, sectionally or completely, such as the trough belt cell 50, which is located in the storage unit 10 of Fig. 1 is implemented, according to various aspects of the present revelation. In Fig. 3. The n-tub contacts 160A are arranged in an n-tub strip, such as the n-tub strip 50B. In such implementations, the n-tub strip 50C is free of the n-tub contacts 160A.

[0036] Fig. Figure 4 is a fragmentary top view of section 300 of the tub band column 40 according to various aspects of the present disclosure. In Fig. 4 Three trough tape cells 50 are arranged in a column between the columns of memory cells 20 (such as a column of memory arrangement 12A and a column of memory arrangement 12B). The trough tape column 40 contains an n-trough 312, which combines the n-troughs of the trough tape cells 50 and the SRAM cells 20 (for example, the n-troughs 112A, 112B as above with reference to Fig. 2A-2G described) and a p-tub 314, which is a combined p-tub of the tub band cells 50 and the SRAM cells 20 (for example, the p-tubs 114A-114C, as described above with reference to Fig. 2A-2G described) represents. Fig. 4. The n-trough 312 extends from the storage cells 20 into the n-trough bands 50B, 50C, but not the p-trough bands 50A, and the p-trough extends from the storage cells 20 into the n-trough bands 50B, 50C and the p-trough band 50A. Because the p-trough 314 is I-shaped in the trough band cells 50, the trough band column 40 contains a central section that is free of n-troughs along its entire length (here along the y-direction). Fig. For clarity, section 4 has been simplified to facilitate a better understanding of the concepts of the invention as presented in this disclosure. Additional features may be added to section 300 of the tub band gap 40, and some of the features described below may be replaced, modified, or eliminated in other embodiments of section 300 of the tub band gap 40.

[0037] Fig. Figure 5 is a circuit diagram of a single-terminal SRAM cell 400, which can be implemented in a memory cell of an SRAM, according to various aspects of the present disclosure. For example, the single-terminal SRAM cell 400 is implemented in one or more memory cells 20 of the memory 10 ( Fig. 1) The single-terminal SRAM cell 400 contains six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-1. The single-terminal SRAM cell 400 is thus alternatively referred to as a 6T SRAM cell. In operation, the pass-gate transistors PG-1 and PG-2 provide access to a memory section of the SRAM cell 400, which contains a cross-coupled pair of inverters, an inverter 410 and an inverter 420. Inverter 410 contains the pull-up transistor PU-1 and the pull-down transistor PD-1, and inverter 420 contains the pull-up transistor PU-2 and the pull-down transistor PD-2. Fig. For clarity, reference 5 has been simplified to facilitate a better understanding of the concepts of the invention as presented in this disclosure. Additional features may be added to the single-terminal SRAM cell 400, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the single-terminal SRAM cell 400.

[0038] In some implementations, the pull-up transistors PU-1 and PU-2 are configured as p-finFETs. For example, the pull-up transistors PU-1 and PU-2 each contain a gate structure arranged over a channel region of an n-fin structure (containing one or more n fins), such that the gate structure is connected between p-source / drain regions of the n-fin structure (for example, epitaxial p-source / drain features), with the gate structure and the n-fin structure arranged over an n-well region. and the pull-down transistors PD-1, PD-2 each contain a gate structure arranged over a channel region of a p-fin structure (which contains one or more p-fins), such that the gate structure is connected between n-source / drain regions of the p-fin structure (for example, epitaxial n-source / drain features), with the gate structure and the p-fin structure arranged over a p-well region.In some implementations, the pass-gate transistors PG-1 and PG-2 are also configured as n-finFETs. For example, each pass-gate transistor PG-1 and PG-2 contains a gate structure arranged over a channel region of a p-fin structure (containing one or more p-fins), such that the gate structure is connected between n-source / drain regions of the p-fin structure (for example, epitaxial n-source / drain features), with the gate structure and the p-fin structure arranged over a p-well region.

[0039] One gate of the pull-up transistor PU-1 is connected between a source (electrically coupled to a supply voltage (V)) DD )) and a first common drain (CD1) is connected and a gate of the pull-down transistor PD-1 is connected between a source (electrically coupled to a supply voltage (V) SS)) and the first common drain. A gate of the pull-up transistor PU-2 is connected between a source (electrically coupled to a supply voltage (V)). DD )) and a second common drain (CD2) is connected, and a gate of the pull-down transistor PD-2 is connected between a source (electrically coupled to a supply voltage (V)). SSThe first common drain (CD1) is a storage node (SN) that stores data in its original form, and the second common drain (CD2) is a storage node (SNB) that stores data in its complementary form. The gate of pull-up transistor PU-1 and the gate of pull-down transistor PD-1 are coupled to the second common drain, and the gate of pull-up transistor PU-2 and the gate of pull-down transistor PD-2 are coupled to the first common drain. A gate of pass-gate transistor PG-1 is connected between a source (electrically coupled to a bit line BL) and a drain that is electrically coupled to the first common drain.A gate of pass-gate transistor PG-2 is connected between a source (electrically coupled to a complementary bit line BLB) and a drain, which is electrically coupled to the second common drain. The gates of pass-gate transistors PG-1 and PG-2 are electrically coupled to a word line WL. In some implementations, pass-gate transistors PG-1 and PG-2 provide access to memory nodes SN and SNB during read and / or write operations. For example, pass-gate transistors PG-1 and PG-2 couple memory nodes SN and SN-B to bit lines BL and BLB in response to a voltage applied to the gates of pass-gate transistors PG-1 and PG-2 by the WLs.

[0040] Fig. Figure 6 is a fragmentary top view of an SRAM array 500, section by section or in its entirety, according to various aspects of the present disclosure. In some implementations, the SRAM array 500 represents a section of the memory 10, such as a section of the SRAM cells 20. In Fig. Figure 6 of the SRAM arrangement 500 contains a substrate 510 with various doped regions arranged therein, such as an n-well 512A, an n-well 512B, a p-well 514A, a p-well 514B, and a p-well 514C. The substrate 510, the n-wells 512A, 512B, and the p-wells 514A-514C are correspondingly similar to the substrate 110, the n-wells 112A, 112B, and the p-wells 114A-114C described above with reference to Fig. 2A-2G are described. The SRAM assembly 500 further includes various features arranged over the n-wells 512A, 512B and the p-wells 514A-514C, the various features being configured to achieve a desired functionality. For example, the SRAM assembly 500 includes the fins 520 (similar to the fins 120 described above with reference to Fig. 2A-2G are described), an insulation feature(s) (similar to insulation feature 222 described above with reference to Fig. 2A-2G is described), the gate structures 530 (similar to the gate structures 130 described above with reference to Fig. 2A-2G are described) (including, for example, a gate dielectric, a gate electrode, a hard mask and / or gate spacers similar to the gate dielectric 132, the gate electrode 134, the hard mask 136 and / or the gate spacers 138 described above with reference to Fig. 2A-2G are described), epitaxial source / drain features (similar to the epitaxial source / drain features 140A, 140B described above with reference to Fig. 2A-2G are described), an MLI feature (similar to MLI feature 150, which is described above with reference to Fig. 2A-2G is described), ILD layers (similar to ILD layers 152, 154, described above with reference to Fig. 2A-2G are described), device-level contacts (similar to the device-level contacts described above with reference to Fig. 2A-2G are described), vias (similar to the vias described above in relation to Fig. 2A-2G are described) and conductive lines (similar to the conductive lines described above with reference to Fig. (described in 2A-2G). The various features are configured to form an SRAM cell range containing one SRAM cell 560A, one SRAM cell 560B, one SRAM cell 560C, and one SRAM cell 560D. SRAM cells 560A-560D can be implemented in SRAM cells 20 of memory 10. In some implementations, SRAM cell 560B or SRAM cell 560D can be configured as SRAM cell 20A adjacent to the trough band 50 in Fig. 2. In some implementations, the SRAM cell 560A or the SRAM cell 560C can be implemented as the SRAM cell 20B adjacent to the tray belt 50 in Fig. 2 be implemented. Fig.For clarity, Section 6 has been simplified to facilitate a better understanding of the concepts of the invention as presented in this disclosure. Additional features may be added to the SRAM arrangement 500, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the SRAM arrangement 500.

[0041] The SRAM cells 560A-560D contain a single-terminal SRAM, a dual-terminal SRAM, an SRAM of another type, or combinations thereof. In the illustrated embodiment, the SRAM cells 560A-560D contain single-terminal SRAMs. For example, each of the SRAM cells 560A-560D contains six transistors: a pass-gate transistor PG-1, a pass-gate transistor PG-2, a pull-up transistor PU-1, a pull-up transistor PU-2, a pull-down transistor PD-1, and a pull-down transistor PD-1. Each of the SRAM cells 560A-560D contains an n-well arranged between p-wells. For example, the SRAM cells 560A, 560B each contain the n-well 512A arranged between the p-well 514A and the p-well 514B, with the pull-up transistors PU-1, PU-2 arranged across the n-well 512A and the pass-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 arranged across the p-well 514A or the p-well 514B.The SRAM cells 560C and 560D each contain the n-well 512B arranged between the p-well 514B and the p-well 514C, with the pull-up transistors PU-1 and PU-2 arranged across the n-well 512B and the pass-gate transistors PG-1 and PG-2 and the pull-down transistors PD-1 and PD-2 arranged across the p-well 514B or the p-well 514C, respectively. The pull-up transistors PU-1 and PU-2 are p-FinFETs, the pass-gate transistors PG-1 and PG-2 are n-FinFETs, and the pull-down transistors PD-1 and PD-2 are p-transistors. In some implementations, the pull-up transistors PU-1, PU-2 are configured as p-FinFETs, while the pass-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 are configured as n-FinFETs.For example, the pass-gate transistors PG-1, PG-2 and / or the pull-down transistors PD-1, PD-2 each contain a fin structure (containing one or more fins 520) arranged over a corresponding p-well and a corresponding gate structure 430 arranged over a channel region of the fin structure, such that the corresponding gate structure 430 is connected between source / drain regions of the fin structure. The fin structures of the pass-gate transistors PG-1, PG-2 and / or the pull-down transistors PD-1, PD-2 contain p-type dopants and are electrically connected to the p-wells. The fin structures of the pass-gate transistors PG-1, PG-2 and / or the pull-down transistors PD-1, PD-2 further contain epitaxial n-source / drain features (in other words, the epitaxial source / drain features of the pass-gate transistors PG-1, PG-2 and / or the pull-down transistors PD-1, PD-2 contain n dopants).The gate structures 430 and / or the epitaxial source / drain features of the pass-gate transistors PG-1, PG-2 and / or the pull-down transistors PD-1, PD-2 are electrically connected to a voltage source (e.g. V) by the MLI feature, such as the MLI feature 150. SS). Further referring to the example, the pull-up transistors PU-1 and PU-2 each contain a fin structure (containing one or more fins 520) arranged over a corresponding n-well and a corresponding gate structure 530 arranged over a channel region of the fin structure, such that the corresponding gate structure 530 is connected between source / drain regions of the fin structure. The fin structures of the pull-up transistors PU-1 and PU-2 contain n-type dopants and are electrically connected to n-wells. The fin structures of the pull-up transistors PU-1 and PU-2 also contain epitaxial p-source / drain features (in other words, the epitaxial source / drain features of the pull-up transistors PU-1 and PU-2 contain p-type dopants). The gate structures 530 and / or the epitaxial source / drain features of the pull-up transistors PU-1, PU-2 are electrically connected to a voltage source (e.g. V) via the MLI feature. DD). connected. In the present example, the pull-up transistors PU-1, PU-2, the pass-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 are single-fin FinFETs (in other words, the fin structures contain one fin), although the present disclosure also considers implementations in which one or more of the pull-up transistors PU-1, PU-2, the pass-gate transistors PG-1, PG-2 and the pull-down transistors PD-1, PD-2 are multi-fin FinFETs (in other words, the fin structures contain multiple fins).

[0042] The present disclosure provides for many different embodiments. Fin-based well bands and their fabrication methods are disclosed herein for improving the performance of memory arrangements, such as SRAM arrangements. An exemplary IC device includes a memory cell with a first well doping configuration comprising a first well region, a second well region, and a third well region arranged in a substrate. The second well region is located between the first and third well regions. The first and third well regions are doped with a dopant of a first type, and the second well region is doped with a dopant of a second type. The integrated circuit further includes a well band cell arranged adjacent to the memory cell.The trough-band cell has a first trough region, a second trough region, and a third trough region, with the second trough region positioned between the first and third trough regions. The first and third trough regions have the first type of trough doping configuration. The second trough region has a second type of doping configuration, which includes a fourth trough region doped with the first type dopant. The trough-band cell contains first trough pickup regions to the fourth trough region and second trough pickup regions to the second trough region. In some implementations, the first, third, and fourth trough regions are combined to form an I-shaped trough region in the trough-band cell doped with the first type dopant.In some implementations, the dopant of the first type is a p-dopant and the dopant of the second type is an n-dopant.

[0043] In some implementations, the first, second, third, and fourth well regions extend along a direction perpendicular to a gate longitudinal direction. In some implementations, the fourth well region has a width essentially equal to the width of the well band cell. In some implementations, the second well pickup regions are located in the second well region only in the first or third well band region. In some implementations, the first well pickup regions are connected to a first voltage, and the second well pickup regions are connected to a second voltage that differs from the first. In some implementations, the well band cell contains fins, gate structures, and epitaxial source / drain features configured as dummy FinFETs.

[0044] An exemplary trough-shaped cell is positioned between a first storage cell and a second storage cell. The trough-shaped cell contains a p-trough, a first n-trough, and a second n-trough arranged in a substrate. The p-trough, the first n-trough, and the second n-trough are configured within the trough-shaped cell such that a central portion of the trough-shaped cell is free of the first n-trough and the second n-trough along a gate longitudinal direction. The trough-shaped cell further contains p-trough pickup regions to the p-trough and n-trough pickup regions to the first n-trough, the second n-trough, or both. In some implementations, the p-trough has an I-shaped top view along the gate longitudinal direction.In some implementations, the sum of the width of the first n-trough, the width of the second n-trough, and a middle section of the trough band cell that is free of the first and second n-troughs along the gate longitudinal direction is essentially equal to the width of the trough band cell. In some implementations, the trough band cell is a fin-based trough band cell containing fins that extend along a direction perpendicular to the gate longitudinal direction.

[0045] In some implementations, the middle section of the trough band cell is located between a first edge section of the trough band cell and a second edge section of the trough band cell, wherein the middle section contains a first subregion of the p-trough; the first edge section contains the first n-trough located between a second subregion of the p-trough and a third subregion of the p-trough along the gate longitudinal direction, wherein the second subregion of the p-trough and the third subregion of the p-trough extend from the first subregion of the p-trough; and the second edge section contains the second n-trough located between a fourth subregion of the p-trough and a fifth subregion of the p-trough along the gate longitudinal direction, wherein the fourth subregion of the p-trough and the fifth subregion of the p-trough extend from the first subregion of the p-trough.In such implementations, the middle section can correspond to a p-tub band, the first edge section can correspond to a first n-tub band, and the second edge section can correspond to a second n-tub band. The p-tub band is positioned between the first n-tub band and the second n-tub band.

[0046] In some implementations, first gate structures are located in the central section of the trough belt cell, such that the first gate structures are positioned above the p-trough; second gate structures are located in the first boundary section of the trough belt cell, such that the second gate structures are positioned above the first n-trough, the second subregion of the p-trough, and the third subregion of the p-trough; and third gate structures are located in the second boundary section of the trough belt cell, such that the third gate structures are positioned above the second n-trough, the fourth subregion of the p-trough, and the fifth subregion of the p-trough. In some implementations, the p-trough pickup regions are located in the central section of the trough belt cell that is free of the first n-trough and the second n-trough along the gate longitudinal direction.In some implementations, at least one of the p-tub pickup regions is arranged between the first n-tub and the second n-tub along a direction perpendicular to the gate longitudinal direction.

[0047] An exemplary memory array contains a first column of memory cells and a second column of memory cells. Each cell in the first column and each cell in the second column has a first well doping configuration. The memory array further includes a well-band cell column located between the first and second columns. Each well-band cell in the well-band column contains a p-well band located between a first n-well band and a second n-well band. The first n-well band and the second n-well band have the first well doping configuration. The p-well band has a second well doping configuration that differs from the first well doping configuration. In some implementations, the first well doping configuration contains an n-well, and the second well doping configuration is devoid of an n-well.In some implementations, the p-tub belt contains the p-tub pickup regions arranged between an n-tub of the first n-tub belt and an n-tub of the second n-tub belt.

Claims

[1] Integrated circuit which includes the following: a storage cell (20A) with a first well doping configuration comprising a first well region (114A-1), a second well region (112A), and a third well region (114A-2) arranged in a substrate (110), wherein the second well region (112A) is located between the first well region (114A-1) and the third well region (114A-2), and wherein the first well region (114A-1) and the third well region (114A-2) are further doped with a dopant of a first type, and the second well region (112A) is doped with a dopant of a second type; and a trough belt cell (50) which is arranged adjacent to the storage cell (20A), wherein: - the trough belt cell (50) has a first trough belt area (50B), a second trough belt area (50A) and a third trough belt area (50C), wherein the second trough belt area (50A) is arranged between the first trough belt area (50B) and the third trough belt area (50C), - the first trough belt area (50B) and the third trough belt area (50C) have the first trough doping configuration, - the second trough band area (50A) has a second trough doping configuration which includes a fourth trough region (114C) doped with the dopant of the first type, and - the tub band cell (50) contains first tub pickup regions (160B) which are arranged on the fourth tub region (114C) and second tub pickup regions (160A) which are arranged on a fifth tub region (112C) which extends without interruption into the second tub region (112A). [2] Integrated circuit according to claim 1, wherein the first trough region (114A-1), the third trough region (114A-2) and the fourth trough region (114C) are combined to form an I-shaped trough region in the trough ribbon cell (50) doped with the dopant of the first type. [3] Integrated circuit according to claim 1 or 2, wherein the dopant of the first type is a p-type dopant and the dopant of the second type is an n-type dopant. [4] Integrated circuit according to one of the preceding claims, wherein the first well region (114A-1), the second well region (112A), the third well region (114A-2) and the fourth well region (114C) extend along a direction perpendicular to a gate longitudinal direction. [5] Integrated circuit according to one of the preceding claims, wherein the fourth trough region (114C) has a width that is substantially equal to the width of the trough band cell (50). [6] Integrated circuit according to one of the preceding claims, wherein the second tub pickup regions (160A) are arranged only in the first tub band region (50B) or the third tub band region (50C). [7] Integrated circuit according to one of the preceding claims, wherein the first tub pickup regions (160B) are connected to a first voltage and the second tub pickup regions (160A) are connected to a second voltage which differs from the first voltage. [8] Integrated circuit according to any of the preceding claims, wherein the trough ribbon cell (50) includes fins, gate structures and epitaxial source / drain features configured as dummy FinFETs, fin-like field-effect transistors. [9] Storage, having: a trough belt cell (50) arranged between a first storage cell (20A) and a second storage cell (20B), wherein the trough belt cell (50) comprises the following: - a p-trough (114C), a first n-trough (112C) and a second n-trough (112D) arranged in a substrate (110), wherein the p-trough (114C), the first n-trough (112C) and the second n-trough (112D) are arranged in the trough belt cell (50) such that a central section (50A) of the trough belt cell (50) is free from the first n-trough (112C) and the second n-trough (112D) along a gate longitudinal direction, - p-tub pickup regions (160B) to the p-tub (114C), and - n-tub pickup regions (160A) to the first n-tub (112C), the second n-tub (112D) or both. [10] Memory according to claim 9, wherein the p-tub (114C) has an I-shaped view from above along the gate longitudinal direction. [11] Storage device according to claim 9 or 10, wherein: the middle section (50A) of the trough band cell (50) is arranged between a first edge section (50B) of the trough band cell (50) and a second edge section (50C) of the trough band cell (50), wherein the middle section (50A) has a first subregion of the p-trough; the first boundary section (50B) has the first n-tub (112C) which is arranged between a second sub-region of the p-tub (114C) and a third sub-region of the p-tub (114C) along the gate longitudinal direction, the second sub-region of the p-tub (114C) and the third sub-region of the p-tub (114C) extending from the first sub-region of the p-tub (114C); and the second boundary section (50C) has the second n-trough (112D) which is located between a fourth sub-region of the p-trough (114C) and a fifth sub-region of the p-trough (114C) along the gate longitudinal direction, wherein the fourth sub-region of the p-trough (114C) and the fifth sub-region of the p-trough (114C) extend from the first sub-region of the p-trough (114C). [12] Storage device according to claim 11, wherein the middle section (50A) corresponds to a p-tub belt, the first edge section (50B) corresponds to a first n-tub belt and the second edge section (50C) corresponds to a second n-tub belt, wherein the p-tub belt is arranged between the first n-tub belt and the second n-tub belt. [13] Storage device according to claim 11 or 12, which further comprises: first gate structures which are arranged in the middle section of the trough band cell (50) such that the first gate structures are arranged above the p-trough (114C); second gate structures arranged in the first boundary section of the trough band cell (50) such that the second gate structures are arranged above the first n-trough (112C), the second subregion of the p-trough (114C) and the third subregion of the p-trough (114C); and third gate structures which are arranged in the second boundary section (50C) of the trough band cell (50) such that the third gate structures are arranged above the second n-trough (112D), the fourth subregion of the p-trough (114C) and the fifth subregion of the p-trough (114C). [14] Memory according to any one of the preceding claims 9 to 13, wherein the sum of a width of the first n-trough (112C), a width of the second n-trough (112D) and a middle section of the trough belt cell (50) that is free from the first n-trough (112C) and the second n-trough (112D) along the gate longitudinal direction is substantially equal to a width of the trough belt cell (50). [15] Memory according to any one of the preceding claims 9 to 14, wherein the p-well pickup regions (160B) are arranged in the central section (50A) of the well belt cell (50) which is free from the first n-well (112C) and the second n-well (112D) along the gate longitudinal direction. [16] Memory according to any one of the preceding claims 9 to 15, wherein at least one of the p-well pickup regions (160B) is arranged between the first n-well (112C) and the second n-well (112D) along a direction perpendicular to the gate longitudinal direction. [17] Memory according to any one of the preceding claims 9 to 16, wherein the trough belt cell (50) is a fin-based trough belt cell containing fins extending along a direction perpendicular to the gate longitudinal direction. [18] Storage arrangement which has the following features: a first memory cell column, wherein each memory cell (20) of the first memory cell column has a first trough doping configuration; a second memory cell column, wherein each memory cell (20) of the second memory cell column has the first trough doping configuration; and a trough-band cell column arranged between the first storage cell column and the second storage cell column, wherein each trough-band cell (50) in the trough-band cell column has a p-trough band arranged between a first n-trough band and a second n-trough band, and wherein the first n-trough band and the second n-trough band further have the first trough doping configuration, and the p-trough band has a second trough doping configuration different from the first trough doping configuration, wherein the first trough doping configuration includes a first p-trough, a second p-trough and an n-trough arranged between the first p-trough and the second p-trough, and the second trough doping configuration is free of an n-trough. [19] Storage arrangement according to claim 18, wherein the p-tub belt has p-tub pickup regions arranged between an n-tub of the first n-tub belt and an n-tub of the second n-tub belt.

Images