Proportional AC-coupled flank-enhancing transmission equalization for multi-stage pulse amplitude-modulated signaling

Abstract

Signaling system including: a pulse amplitude modulated transmitter or PAM transmitter coupled to a data track of a bus, wherein the transmitter is configured to generate N > 2 discrete voltage levels on the data track; and a plurality of N-1 equalizers coupled to the data track, each of the N-1 equalizers being assigned to a different signal eye of the data track, Each equalizer comprises a control and an edge detection stage to receive bits to be transmitted on the data track, an input stage to respond to a positive edge output and a negative edge output from the control and edge detection stage with a pull-up output and a pull-down output to an output stage coupled to the data track.

Description

BACKGROUND

[0001] In high-performance computing systems, the storage system and the connecting structures—that is, the data buses over which the components communicate—largely determine the system's computing capacity. A key performance characteristic of data buses is the rate at which data signals are transmitted between different components. The maximum transmission rate is determined by the bus clock frequency, the number of bus cycles per data transmission, and the number of bits transmitted per transmission period. Therefore, system performance can be improved by increasing the bus clock frequency, increasing the number of bits transmitted in each clock cycle, or increasing the bus width.

[0002] With faster and more complex computer systems, it is becoming increasingly important that the individual system components and devices are able to communicate securely and reliably at ever higher frequencies and over ever wider data buses.

[0003] The publication by Farjad-Rad, Ramin [et al.]: “An equalization scheme for 10 Gb / s 4-PAM signaling over long cables” (1997 URL: http: / / smirc.stanford.edu / papers / cancun97p-ramin.pdf) concerns simulation results for a serial 10 Gb / s connection. The serial connection consists of a transmitter, a copper coaxial cable, and a receiver. Multi-stage signaling (4-PAM) is used, along with pulse shaping at the transmitter and equalization at the receiver. BRIEF DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS

[0004] To make it easy to identify the discussion of a particular element or process, the leading number(s) of a reference sign refer to the figure in which that element is first introduced. Fig. 1 represents a data communication system 100 according to one embodiment. Fig. Figure 2 represents an embodiment of a serial PAM-4 connection 200. Fig. Figure 3 represents an embodiment of a PAM transmitter / receiver arrangement 300. Fig. Figure 4 represents an edge-enhanced auxiliary signaling system 400 with A / C-coupled edge amplification according to one embodiment. Fig. Figure 5 represents an equalizer 402 according to one embodiment. Fig. Figure 6 represents an equalizer input stage 502 according to one embodiment. Fig. Figure 7 represents an equalizer 402 according to one embodiment. Fig. Figure 8 represents a multi-stage PAM equalizer 800 according to one embodiment. Fig. Figure 9 represents a signal diagram 900 according to one embodiment. Fig. Figure 10 represents a PAM-4 control logic structure 1000 according to one embodiment. Fig. Figure 11 represents a PAM-8 control logic structure 1100 according to one embodiment. Fig. Figure 12 is a block diagram of a computer system 1200 in which the embodiments of PAM communication presented here can be designed or implemented. DETAILED DESCRIPTION

[0005] With reference to Fig. 1. A data communication system 100 comprises a transmission device such as a data processor 102, which has a processing core 110 and a PAM-4 transmitter 104. In some embodiments, the data processor 102 may include a graphics processing unit (GPU), a central processing unit (CPU), a system-on-a-chip (SoC), or other known data processing devices.

[0006] The data processor 102 communicates with a receiving device, such as a memory 108, via a bus, such as a memory bus 114. A PAM-4 receiver 106 receives the PAM-4 signals transmitted by the PAM-4 transmitter 104 via the memory bus 114 and transmits the data to the memory 108.

[0007] The data processor 102 uses an internal data bus 112 to transfer data bursts to and from the processing core 110 via a multi-track internal data bus 112. The PAM-4 transmitter 104 receives a data burst from the processing core 110 and sends the burst as PAM-4 symbols via the memory bus 114 to the PAM-4 receiver 106. The PAM-4 receiver 106 receives the symbols and sends them as data to the memory 108.

[0008] This is a simplified representation. In practice, there can be 114 additional elements at both ends of the memory bus, such as a data encoder and a data decoder.

[0009] Fig. Figure 2 represents a serial PAM-4 connection 200 for a single data track of a serial data bus in one embodiment. The serial PAM-4 connection 200 comprises a transmitter 202 for the least significant bit, a transmitter 204 for the most significant bit, a receiver 206, and a data track 208. The serial PAM-4 connection 200 uses the transmitter 202 for the least significant bit and the transmitter 204 for the most significant bit to generate a four-level symbol on the data track 208. Here, the term "symbol" refers to a voltage level generated by a line driver on a data track of a serial data bus, the voltage level representing the value of one or more data bits. Thus, "encoding a symbol" means the physical configuration of a line driver circuit of the serial data bus to drive the voltage on the data track to a specific value.

[0010] If, for example, the two data bits to be encoded in the symbol are (1,1), the outputs of transmitter 202 for the least significant bit and transmitter 204 for the most significant bit together generate a voltage of, for example, 1.2 V on data track 208, and the current on data track 208 is, for example, 0 mA due to the pull-up transistor Rt at receiver 206 (both ends of data track 208 are at the same potential). If the two data bits to be encoded in the symbol are (1,0), the outputs of transmitter 202 for the least significant bit and transmitter 204 for the most significant bit together generate a voltage of, for example, 1.0 V on data track 208 and a current on data track 208 of, for example, 5 mA. If the two data bits to be encoded in the symbol are (0,1), the outputs of the transmitter for the least significant bit and of transmitter 204 for the most significant bit together generate a voltage of, for example, 0.8 V on data track 208, and the current on data track 208 is, for example, 0.8 V.For example, 10 mA. If the two data bits to be encoded in the symbol are (0,0), the outputs of transmitter 202 for the least significant bit and of transmitter 204 for the most significant bit together generate a voltage of, for example, 0.6 V on data track 208, and the current on data track 208 is, for example, 15 mA. The 0.6 V can be referred to here as the base transmission voltage Vb, with which the other symbol voltage levels are determined by subtraction. The symbol value on a data track therefore corresponds to the current consumption of that data track during a data burst.

[0011] Fig. Figure 3 represents a transmitter / receiver arrangement 300 in one embodiment. A transmitter 302 and a receiver 304 communicate via a multi-track serial data bus 306 with a predetermined width (number of data tracks), represented by M. The line drivers 308 of the transmitter 302 encode PAM symbols S1-SM in parallel on the M data tracks of the multi-track serial data bus 306. The data word to be transmitted via the multi-track serial data bus 306 comprises a plurality of P bits. If N is the number of voltage levels used in the PAM encoding, e.g., N=4 for PAM-4, then a number of bits equal to log2(N) of each symbol on each data track of the multi-track serial data bus 306 is encoded.

[0012] In embodiments using data encoders and decoders, the transmitting device 302 may also include a control line driver 310 to transmit control information about the symbols on the data tracks to the receiving device 304 on an additional control line 312. The receiving device 304 includes input termination circuits 314 connected to the multi-track serial data bus 306 to receive the symbols transmitted on the multi-track serial data bus 306, typically with one termination circuit 314 for each data track. The receiving device 304 further includes an additional termination circuit 316 for receiving the control information transmitted on the control line 312. The received symbols represent bit combinations of length log2(N) (e.g., S1=00, S2=01, etc. for PAM-4).

[0013] A data eye is the interval of the communication clock cycle in which the signal values ​​transmitted over the data bus are stable and a receiving device can successfully resolve the signals at its inputs. The shape, height, and width of the data eye therefore visually represent the transmission quality and indicate how data signals transmitted over the data bus can be determined at the receiving device.

[0014] The vertical height and horizontal width of the signal eye at the receiver can be restricted due to intersymbol interference (ISI), which results from bandwidth limitations of the data bus and the transmit and receive circuitry. A combination of equivalent driver resistance, channel impedances, and parasitic effects at both ends of the bus causes frequency-dependent signal losses, leading to data-dependent ISI. The resulting signal eye can narrow considerably, for example, to a width of about 2 ns, even though the bus clock interval is 5 ns. Although the transmitter (in this example) has a 5 ns window in which each symbol on the data track can be communicated, the receiver only has 2 ns to resolve the symbol because the signal eye narrows due to frequency-dependent losses within the overall link.In some cases, the resulting signal eye may disappear completely, making reliable signal transmission between two electronic devices via the serial data bus impossible.

[0015] This problem is exacerbated in PAM-N (N>2) signaling due to the additional (>2) voltage levels used by the symbols within the overall signal range. For example, in PAM-4, each signal eye occupies 1 / 3 of the total signal voltage range, so signal eye closure effects affect a larger percentage of the voltage range within each PAM-4 voltage band. In higher-order communication technologies (e.g., PAM-8), these effects can be even greater.

[0016] Embodiments of the equalization scheme disclosed herein operate in parallel with the line drivers to inject energy at high frequencies onto the data tracks. This scheme effectively extends the frequency response of the received signal to reduce the ISI. The signal is equalized while maintaining impedance matching to the channel without reducing the DC amplitude of the signal. Embodiments of a multi-stage PAM equalizer for eliminating signal eye closure are described by way of example in Fig. 4 to Fig. 11 described.

[0017] With reference to Fig. 4 to Fig. 11 comprises an A / C-coupled, edge-amplified auxiliary signaling system 400, in one embodiment comprising a (non-zero-returning) NRZ transmitter 404 and an NRZ equalizer 402. The equalizer 402 comprises an equalizer input stage 502 and an equalizer output stage 504, as described in Fig. 5, Fig. 6 and Fig. Figure 7 shows that these can be combined with an edge detector 802 to form a multi-stage PAM equalizer 800 in an embodiment as shown in Figure 7. Fig. Figure 8 shows a signal diagram 900 for the multi-stage PAM equalizer 800, where N = 4. Fig. Figure 9 illustrates an exemplary series of symbols transmitted on a specific data track. The multi-stage PAM equalizer 800 can be configured according to the PAM-4 control logic structure 1000 as described in the embodiment of Fig. 10, according to the PAM-8 control logic structure 1100 according to the embodiment of Fig. 11 or according to other embodiments of a control logic depending on the number of PAM levels N.

[0018] The 802 edge detector can detect transitions of the signal eyes using NAND, NOR, or other general combinational gates. In PAM-4, each 802 edge detector monitors changes (corresponding to positive or negative edges) at the most significant and / or least significant data bit (MSB or LSB). An 8-PAM equalization scheme changes logical states depending on the most significant, intermediate, and least significant input data bit (MSB, ISB, and LSB, respectively). Similar truth tables can be easily created for multi-stage PAM signaling schemes with a varying number of voltage levels using common technical knowledge.

[0019] In the multi-stage PAM equalizer 800, each edge detector 802 receives the multiple bits of input data for a symbol and optionally clock and control signals. To equalize a PAM signaling scheme with N levels for encoding log2(N) bits, the multi-stage PAM equalizer 800 uses N-1 equalization components, which can be of similar size, with each equalizer assigned to a specific PAM signal eye. The pull-up and pull-down control signals for each equalization component are generated by an associated edge detector 802, which performs edge detection for the respective PAM signal eye in the digital domain. When the symbol on a data track changes state, the edge detector 802 toggles the pull-up and pull-down signals of the equalizer components assigned to the signal eyes traversed by the data track signal.This allows independent control of the equalizer components, where the number of components switched simultaneously within a given transmission interval is proportional to the number of PAM voltage levels by which the level changes within that interval, thus resulting in a proportional amount of charge being injected into the line. The multi-stage edge detection / control logic can be implemented using a variety of methods, including CMOS combination logic, a thermometer encoder, or a lookup memory control structure such as a table.

[0020] Signal diagram 900 shows exemplary waveforms for the transmitted data track voltage and equalizer outputs for a PAM-4 signaling scheme. The outputs of each equalizer (there are N-1=3 per data track) transition to either a pull-up or pull-down state due to changes in the multiple bits of the input data. This means that the polarity and the number of equalizer components switching states are proportional to the number of PAM voltage levels by which the level changes in a given transmission interval. For example, on the transition from 11→10, the equalizer component responsible for equalizing the upper signal eye (eye 3 EQ segment) switches from a pull-up to a pull-down state to inject a negative charge into the line and amplify the negative transition output signal edge.During the transition from 00→11, all equalizer components switch from a pulldown state to a pullup state to inject a positive charge into the line that is three times greater than in the example of a single-level transition. By assigning a specific equalizer of equal magnitude to each PAM signal eye, each individual equalizer operates in the correct logic state with respect to the output signal. The inner node of the coupling capacitor 702 is always pulled to the correct supply voltage (VDD or GND) to ensure an effective equalization level at the next signal transition, regardless of the current logic state.

[0021] With reference to Fig. 10 configures a PAM-4 control logic structure 1000 a first equalizer to perform a logical AND operation of a most significant bit and a least significant bit of each of the PAM-4 symbols, a second equalizer to pass the most significant bit of each of the symbols, and a third equalizer to perform a logical OR operation of the most significant bit and the least significant bit of each of the symbols. Fig. Figure 11 represents an exemplary PAM-8 control logic structure 1100 for PAM-8.

[0022] Fig.Figure 12 is a block diagram of an embodiment of a computer system 1200 in which one or more aspects of the disclosure can be implemented. The computer system 1200 comprises a system data bus 1232, a CPU 1202, input devices 1208, a system memory 1204, a graphics processing system 1206, and display devices 1210. In alternative embodiments, the CPU 1202, parts of the graphics processing system 1206, the system data bus 1232, or any combination thereof can be integrated into a single processing unit. Furthermore, the functionality of the graphics processing system 1206 can be contained in a chipset or in some other type of specialized processing unit or coprocessor.

[0023] As shown, the system data bus 1232 connects the CPU 1202, the input devices 1208, the system memory 1204, and the graphics processing system 1206. In alternative embodiments, the system memory 1204 can be directly connected to the CPU 1202. The CPU 1202 receives user input from the input devices 1208, executes programming instructions stored in the system memory 1204, and works with the data stored in the system memory 1204 to perform computational tasks. The system memory 1204 typically includes dynamic random access memory (DRAM) used to store program instructions and data. The graphics processing system 1206 receives the instructions transmitted by the CPU 1202 and processes them to, for example, implement aspects of the disclosed embodiments and / or to display and render graphics (e.g., images, tiles, video) on the display devices 1210.

[0024] As also shown, system memory 1204 contains an application program 1212, an API 1214 (Application Programming Interface), and a graphics processing unit driver 1216 (GPU driver). The application program 1212 makes calls to the API 1214 to generate a desired set of computational results. For example, the application program 1212 can transfer programs or functions from it to the API 1214 for processing within the graphics processing unit driver 1216.

[0025] The graphics processing system 1206 comprises a GPU 1218 (graphics processing unit), an on-chip GPU memory 1222, an on-chip GPU data bus 1236, a local GPU memory 1220, and a GPU data bus 1234. The GPU 1218 is configured to communicate with the on-chip GPU memory 1222 via the on-chip GPU data bus 1236 and with the local GPU memory 1220 via the GPU data bus 1234. The GPU 1218 can receive instructions transmitted by the CPU 1202, process these instructions, and store the results in the local memory of the GPU 1220. Subsequently, the GPU 1218 can display specific graphics stored in the local memory of the GPU 1220 on the display devices 1210.

[0026] The GPU 1218 includes one or more logic blocks 1224. The logic blocks 1224 can implement embodiments of the systems and methods disclosed herein. For example, the logic blocks 1224 can implement aspects of the encoding or decoding methods disclosed herein for improving signal quality on serial data buses.

[0027] The GPU 1218 can be equipped with any amount of on-chip GPU memory 1222 and local GPU memory 1220, or without it, and can use on-chip GPU memory 1222, local GPU memory 1220 and system memory 1204 in any combination for memory operations.

[0028] The on-chip GPU memory 1222 is configured to include a GPU programming interface 1228 and an on-chip buffer 1230. The GPU programming interface 1228 can be transferred from the graphics processing unit driver 1216 to the on-chip GPU memory 1222 via the system data bus 1232. The GPU programming interface 1228 can include logic blocks 1224.

[0029] The local GPU memory 1220 typically consists of less expensive dynamic random access memory (DRAM) located off-chip and is also used for storing data and programming for use by the GPU 1218. As shown, the GPU's local memory 1220 includes a frame memory 1226. The frame memory 1226 can, for example, store data such as an image, e.g., a graphical user interface, which can be used to control the display devices 1210. The frame memory 1226 can have more than one interface, so that the GPU 1218 can render one interface while a second interface is used to control the display devices 1210.

[0030] The display devices 1210 are one or more output devices capable of displaying a visual image in accordance with an input data signal. A display device can, for example, be equipped with a liquid crystal display or another suitable display system. The input data signals for the display devices 1210 are typically generated by reading the content of one or more images from image data stored in the image memory 1226.

[0031] The disclosed embodiments can be used in a variety of ways in the computer system 1200, e.g. for data transmission via the GPU data bus 1234, the on-chip GPU data bus 1236, the system data bus 1232 and / or one of the buses to or from any computing element (e.g. GPU 1218, CPU 1202) and another computing element, the system memory 1204 or a peripheral device.

[0032] The disclosed aspects can be used in conjunction with one or more of the buses of the Computer System 1200.

[0033] The embodiments described in this document can be extended for use in other multi-stage PAM signaling systems that use a different number of voltage levels. These embodiments can also be adapted for use in differential connections with equalizer components that operate with complementary versions of the multiple bits of input data. The embodiments can also be adapted for operation with high supply voltages using level shifters and cascoding transistors within the equalizer output stage to ensure circuit voltage compliance.

[0034] Implementations of the disclosed equalization scheme can be applied with line driver topologies other than the examples used here. The equalization scheme is an auxiliary function for the primary line drivers and operates in parallel with them.

[0035] The previously described specific voltages, currents, and other details serve only for illustration. The invention can be implemented using a variety of specific voltage levels, currents, resistances, etc. And while the invention was previously described, for example, in connection with a processor that transmits data to a memory, the signaling methods described here, PAM-4, etc., can be implemented in a variety of signaling systems in which data is sent from a transmitting device to a receiving device or between transmitting devices, etc.

[0036] The terms used here shall be allowed to have their usual meaning in the relevant field or the meaning indicated by their use in context, but where an explicit definition is given, that meaning shall prevail.

[0037] “Logic” here refers to machine memory circuits, non-volatile machine-readable media, and / or circuits that, due to their material and / or material energy configuration, include control and / or process signals and / or settings and values ​​(such as resistance, impedance, capacitance, inductance, current / voltage values, etc.) that can be used to influence the operation of a device. Electronic circuits such as controllers, field-programmable gate arrays, processors, and memory (both volatile and non-volatile) that includes instructions executable by the processor are examples of logic. Logic specifically excludes pure signals or software per se (but does not exclude machine memories that include software and thereby constitute configurations of matter).

[0038] Various logical function operations described here can be implemented in a logic that is referenced by a noun or noun phrase reflecting that operation or function. For example, an association operation can be performed by an "associator" or "correlator." Similarly, switching can be done by a "switch," selection by a "selector," and so on.

[0039] Those skilled in the art understand that logic can be distributed across one or more devices or components and / or may comprise combinations of memory, media, processing circuits and controls, other circuits, and so on. For the sake of clarity and accuracy, logic is therefore not always explicitly depicted in drawings of devices and systems, even though it is inherently present. The techniques and procedures described here can be implemented by logic distributed across one or more computing devices. The specific distribution and selection of logic varies depending on the implementation.

[0040] Within this disclosure, various entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This phrase—[unit] configured to perform [one or more tasks]—is used here to refer to a structure (i.e., something physical, such as an electronic circuit). More precisely, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. One can say that a structure is “configured” to perform a particular task even if the structure is not currently in operation. For example, a “credit distribution circuit configured to distribute credits to a plurality of processor cores” is said to beThis covers an integrated circuit that has a circuitry capable of performing this function during operation, even when the integrated circuit in question is not currently in use (e.g., when no power supply is connected to it). Thus, a unit described or quoted as being "designed to perform a task" refers to something physical, such as a device, a circuit, a memory that stores program instructions that can be executed to perform the task, etc. This expression is not used here to refer to something intangible.

[0041] The term "designed to" should not mean "configurable to". For example, an unprogrammed FPGA would not be considered "designed to" perform a specific function, even though it may be "configurable to" perform that function after programming.

[0042] The statement in the accompanying claims that a structure is "designed to" perform one or more tasks is expressly not intended to invoke 35 USC § 112(f) for that claim element. Accordingly, claims in this application that do not otherwise include the construct "means to" [perform a function] are not to be interpreted under 35 USC § 112(f).

[0043] As used here, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is to say, a determination may be based solely on specified factors, or on the specified factors as well as other, unspecified factors. Consider the phrase "determination A based on B." This sentence establishes that B is a factor used to determine A or that influences the determination of A. This sentence does not exclude the possibility that the determination of A may also be based on another factor, such as C. This sentence is also intended to cover an embodiment in which A is determined solely on the basis of B. This phrase "based on," as used here, is synonymous with the phrase "based at least partially on."

[0044] As used here, the phrase "depending on" describes one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, an effect may occur solely in response to these factors, or in response to the specified factors as well as other, unspecified factors. Consider the phrase "perform A depending on B." This phrase establishes that B is a factor that triggers the performance of A. This phrase does not exclude the possibility that the performance of A may also depend on another factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in dependence on B.

[0045] As used here, the terms "first," "second," etc., are used as labels for the nouns they precede and do not imply any kind of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified. For example, in a register file with eight registers, the terms "first register" and "second register" can be used to refer to any two of the eight registers, and not, for example, only to the logical registers 0 and 1.

[0046] When the term "or" is used in the claims, it is used as an inclusive or and not as an exclusive or. For example, the expression "at least one of x, y or z" means one of x, y and z, and any combination thereof.

Claims

[1] Signaling system comprising: a pulse amplitude modulated transmitter or PAM transmitter coupled to a data track of a bus, wherein the transmitter is configured to generate N > 2 discrete voltage levels on the data track; and a plurality of N-1 equalizers coupled to the data track, each of the N-1 equalizers being assigned to a different signal eye of the data track, Each equalizer comprises a control and an edge detection stage to receive bits to be transmitted on the data track, an input stage to respond to a positive edge output and a negative edge output from the control and edge detection stage with a pull-up output and a pull-down output to an output stage coupled to the data track. [2] Signaling system according to claim 1, wherein each of the N-1 equalizers has the same size. [3] Signaling system according to one of claims 1 or 2, wherein each equalizer converts log2(N) bits of data for transmission over the data track into a current which is fed onto or drawn from the data track. [4] Signaling system according to one of the preceding claims, wherein the transmitter comprises a PAM-4 transmitter and N = 4. [5] Signaling system according to claim 4, wherein a first equalizer performs a logical AND of a most significant bit and a least significant bit of a symbol for the data track, wherein a second equalizer allows the most significant bit of the symbol to pass, and wherein a third equalizer performs a logical OR of the most significant bit and the least significant bit of the symbol. [6] Signaling system according to any of the preceding claims, wherein the transmitter is a PAM-8 transmitter and N = 8. [7] Signaling system comprising: a serial data bus comprising a plurality of data tracks; and wherein each of the data tracks is coupled to a line driver in parallel to a plurality of N-1 equalizers of the same size, where N > 2 is a number of pulse amplitude modulation levels generated by the line driver. [8] Signaling system according to claim 7, wherein each equalizer is assigned to a signal eye for another of the N pulse amplitude modulation levels. [9] Signaling system according to claim 7 or 8, wherein each of the equalizers converts log2(N) bits into a pull-up output and a pull-down output for the data track. [10] Signaling system according to claim 9, wherein each of the equalizers converts log2(N) bits of data into a current which is fed onto or drawn from the data track. [11] Signaling system according to one of claims 7-10, wherein N = 4. [12] Signaling system according to one of claims 7-10, wherein N = 8. [13] Procedure encompassing: Operating a line driver to encode a plurality of log2(N) bits into one of N > 2 symbols on a data track of a serial data bus; and applying the plurality of bits to each of a plurality of N-1 equalizers coupled in parallel to the line driver with the data track, each of the N-1 equalizers being assigned to a different signal eye of the symbols, each of the N-1 equalizers converting the bits into a positive edge of an auxiliary voltage output or a negative edge of an auxiliary voltage output. [14] Method according to claim 13, wherein each of the equalizers has the same size. [15] Method according to claim 13 or claim 14, wherein each equalizer converts the bits into a current which is fed onto or subtracted from the data track. [16] Method according to any one of claims 13-15, further comprising a first equalizer of the N-1 equalizer which performs a logical AND of a most significant bit and a least significant bit of each of the symbols, a second equalizer of the N-1 equalizer which allows the most significant bit of each of the symbols to pass, and a third equalizer of the N-1 equalizer which performs a logical OR of the most significant bit and the least significant bit of each of the symbols. [17] Method according to any one of claims 13-16, wherein N = 4. [18] Method according to any one of claims 13-16, wherein N = 8.

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