METHOD AND SEMICONDUCER STRUCTURE

Abstract

Procedure, comprehensive: Picking up a workpiece (200), comprising: a first gate structure (206-1) which has a first cap layer (208) on it, a first source / drain contact (224-1) adjacent to the first gate structure (206-1), a second gate structure (206-2) which has a second cap layer (208) on it, a second source / drain contact (224-2), an etch stop layer (226) over the first source / drain contact (224-1) and the second source / drain contact (224-2) and a first dielectric layer over the etch stop layer; Forming a butt contact opening (230) to expose the first cap layer (208) and the first source / drain contact (224-1); Forming a butt contact (232) in the butt contact opening (230); after forming the butt contact (232), depositing a second dielectric layer; Forming a source / drain contact via opening (236) through the second dielectric layer, the etch stop layer (226) and the first dielectric layer to expose the second source / drain contact (224-2); and Forming a source / drain contact via (240) in the source / drain contact via opening (236).

Description

BACKGROUND

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Throughout IC development, functional density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This downward scaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0002] As IC device downscaling continues, the dimensions of contact vias, such as gate-to-gate and source / drain vias, are becoming increasingly smaller. While advanced lithography techniques enable the formation of high-aspect-ratio contact via orifices, filling these orifices with conductive material has proven challenging. Additionally, deposition of a metal filler layer on different metal surfaces can result in varying deposition rates, leading to unsatisfactory metal filling or porosity. While existing methods for forming contacts on transistors are adequate for their intended purpose, they are not satisfactory in all aspects.

[0003] US 2014 / 0361381 A1 describes a semiconductor structure with a butt contact that couples a gate and an S / D contact. Further prior art is known from DE 10 2013 104 236 A1, US 2016 / 0336 183 A1, US 2019 / 0287 851 A1, and US 2020 / 0135 912 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a flowchart of a method for manufacturing a general rail contact according to various aspects of the present disclosure. Fig. Figures 2-14 are fragmentary cross-sectional views of a workpiece at different manufacturing stages of the process in Fig. 1 according to various aspects of the present revelation. Fig. Figure 15 is a fragmentary top view of a semiconductor device having gate contacts, source / drain contact vias and butt contacts according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Spatially relative terms such as "underlying," "below," "under," "overlying," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] Furthermore, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to include numbers that lie within a reasonable range, taking into account variations that arise naturally during manufacturing, as is known to a person skilled in the art. For example, the number or range of numbers includes a reasonable range containing the described number, such as within + / -10% of the described number, based on known manufacturing tolerances associated with producing a feature with a property related to the number. For example, a material layer with a thickness of "about 5 nm" may contain a dimensional range from 4.25 nm to 5.75 nm, where a person skilled in the art knows that the manufacturing tolerances associated with depositing the material layer are + / -15%.Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not itself establish any relationship between the various embodiments and / or configurations discussed.

[0008] As semiconductor device dimensions continue to decrease, the use of a local interconnect structure to couple a gate structure and an adjacent source / drain contact is becoming common. In some examples, the gate structure is covered by a cap layer that differs in composition from the source / drain contact. During the formation of the local interconnect structure, a filler layer is deposited by chemical vapor deposition (CVD) or a selective deposition process. It is observed that the filler layer can be deposited more rapidly on the source / drain contact than over the cap layer. Additionally, prior to the metal-filling process for forming the local interconnect structure, the surfaces of the source / drain contact and the cap layer may be exposed to different oxidation or reduction atmospheres.Differences in the degree of reduction between different materials can also contribute to varying deposition rates. These varying deposition rates on different surfaces can result in poor contact between the local interconnect structure and the gate structure.

[0009] The present disclosure provides a method for forming a butt contact to couple a gate structure with an adjacent source / drain contact prior to the formation of a source / drain contact via and the formation of a gate contact. The butt contact opening has a low aspect ratio, and metal filling into the butt contact opening is performed using a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD). As a result, the cover areas of the source / drain contact via and the gate contact are higher than the cover area of ​​the butt contact. Embodiments of the present disclosure can reduce or eliminate problems associated with different deposition rates on different surfaces. The methods of the present disclosure reduce the possibility of porosity.

[0010] The various aspects of the present revelation will now be described in more detail with reference to the figures. In this respect, Fig. Figure 1 is a flowchart illustrating a method 100 for forming contact structures according to embodiments of the present disclosure. Method 100 is only an example and is not intended to limit the present disclosure to what is expressly illustrated in method 100. Additional steps may be provided before, during, and after method 100, and some of the described steps may be substituted, eliminated, or deferred for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail here. Method 100 is shown below in conjunction with Fig. 2 - 14 described the fragmentary cross-sectional views of a workpiece 200 in different manufacturing stages according to embodiments of the method 100 in Fig. 1 are. To avoid any doubt, the X, Y, and Z directions are in Fig. 2 - 14 perpendicular to each other and are continuously in Fig. References 2-14 are used. Since workpiece 200 is manufactured to form a semiconductor device or a semiconductor structure, workpiece 200 may here be referred to as a semiconductor device 200 or a semiconductor structure 200, depending on the context. In this disclosure, identical reference numerals denote identical features unless an exception applies.

[0011] With reference to Fig. 1 and Fig. Method 100 comprises a block 102 in which a workpiece 200 is received. The workpiece 200 has a substrate 202. In the illustrated embodiment, substrate 202 contains silicon (Si). Alternatively or additionally, substrate 202 can contain other elemental semiconductors, such as germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenic (AlInAs), aluminum gallium arsenic (AlGaAs), gallium indium arsenic (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenic phosphide (GaInAsP); or combinations thereof. In some implementations, substrate 202 contains one or more Group III-V materials, one or more Group II-VI materials, or combinations thereof.In some implementations, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. Semiconductor-on-insulator substrates can be fabricated using oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Substrate 202 can have various doped regions (not shown) configured according to the design requirements of semiconductor device 200, such as p-doped regions, n-doped regions, or combinations thereof. P-doped regions (for example, p-wells) contain p-dopers, such as boron (B), boron difluoride (BF₂), other p-dopers, or combinations thereof. N-doped regions (for example, n-wells) contain n-doping materials such as phosphorus (P), arsenic (As), other n-doping materials, or combinations thereof.An ion implantation process, a diffusion process, and / or another suitable doping process can be performed to form the various doped regions. Substrate 202 is shown in dotted lines in . Fig. 2 shown and omitted for simplicity Fig. 3 - 14.

[0012] As in Fig. As shown in Figure 2, the workpiece 200 features an active region 204 of a multi-gate device, such as a fin-type field-effect transistor (FinFET) or a multi-bridge channel transistor (MBC transistor). If the active region 204 is for a FinFET, it can be a fin element (or fin structure) extending lengthwise along the X direction. If the active region 204 is for an MBC transistor, it can be a vertical stack of channel elements, each extending lengthwise along the X direction. Because a gate structure of an MBC transistor is wrapped around each of the channel regions, an MBC transistor can also be referred to as a surrounding gate transistor (SGT) or a gate-all-around transistor (GAA). The channel elements take the form of nanostructures, such as nanosheets, nanowires, or nanorods.The active region 204 can be formed by structuring the substrate 202 or by one or more epitaxial layers deposited over the substrate 202. In the illustrated embodiment, the active region 204 is formed by structuring a section of the substrate 202 and contains silicon (Si). Although not explicitly shown in the figures, an insulating feature can be formed between the active region 204 and adjacent active regions (not explicitly shown). In some embodiments, the insulating feature can comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials.

[0013] As in Fig. As shown in Figure 2, workpiece 200 further comprises a first gate structure 206-1, a second gate structure 206-2, and a third gate structure 206-3, which are arranged over channel regions 10 of the active region 204. For ease of reference, the first gate structure 206-1, the second gate structure 206-2, and the third gate structure 206-3 can be collectively referred to as gate structures 206. The channel regions 10 of the active region 204 are intersected by source / drain regions 20. Each of the channel regions 10 inserts two source / drain regions 20. The gate structures 206 are looped over channel regions 10 of the active region 204. If the active region 204 has a vertical stack of channel elements, the gate structures 206 are looped around each of the channel elements. While not explicitly shown in the figures, each of the gate structures 206 has a gate dielectric layer and a gate electrode above the gate dielectric.The gate dielectric layer can comprise an interface layer and a high-k dielectric layer. In some cases, the interface layer may contain silicon oxide. The high-k dielectric layer is composed of dielectric materials with a high dielectric constant, for example, greater than the dielectric constant of silicon oxide (k ≈ 3.9).Exemplary high-k dielectric materials for the high-k dielectric layer include hafnium oxide (HfO), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), and combinations thereof. or other suitable material. In one embodiment, the high-k dielectric layer is formed from hafnium oxide (HfO). The gate electrode can have multiple layers, such as exit work layers, adhesive / barrier layers, and / or metal filler layers (or bulk layers).An exit work layer contains a conductive material tuned to have a desired exit work (such as an n-exit work or a p-exit work), such as n-exit work materials and / or p-exit work materials. P-exit work materials contain TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-exit work materials, or combinations thereof. N-exit work materials contain Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-exit work materials, or combinations thereof. An adhesive / barrier layer may contain a material that promotes adhesion between adjacent layers, such as the exit working layer and the metal filler layer, and / or a material that blocks and / or reduces diffusion between gate layers, such as the exit working layer and the metal filler layer.For example, the adhesive / barrier layer contains metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metal, or combinations thereof), metal oxides, metal nitrides (e.g., TiN), or combinations thereof. A metal filler layer can contain a suitable conductive material, such as aluminum (Al), copper (Cu), tungsten (W), ruthenium (Ru), titanium (Ti), a suitable metal, or a combination thereof. The metal filler layer can be omitted if the exit working materials accommodate all of the gate openings.

[0014] The sidewalls of each of the gate structures 206 are lined by a gate spacer 210. The gate spacer 210 can be a single layer or a multilayer. In some embodiments, the gate spacer 210 can contain silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. In some embodiments, a gate exchange or gate-loading process can be used to form the gate structures 206. In one example of a gate-loading process, dummy gate stacks are formed over channel regions 10 of the active region 204. The gate spacer 210 is then deposited over the workpiece 200, comprising sidewalls of the dummy gate stacks. An anisotropic etching process is then carried out to deepen the source / drain areas 20 to form source / drain trenches, leaving behind the gate spacer 210 extending along side walls of the dummy gate stack.After the source / drain trenches are formed, a first source / drain element 205-1 and a second source / drain element 205-2 are deposited into the source / drain trenches in the source / drain regions 20. The first source / drain element 205-1 and the second source / drain element 205-2 can be formed by vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD, molecular beam epitaxy (MBE), or other suitable epitaxial processes, or combinations thereof. The source / drain elements can also be referred to as epitaxial features. Depending on the design of the semiconductor device 200, the first source / drain element 205-1 and the second source / drain element 205-2 can be n or p. If they are n-type, they can contain silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As). If they are p-type, they can contain silicon germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron difluoride (BF₂).In some implementations, annealing processes can be performed to activate dopants in the first source / drain element 205-1 and the second source / drain element 205-2. In the illustrated embodiments, the first source / drain element 205-1 and the second source / drain element 205-2 can contain phosphorus-doped silicon (Si:P) or boron-doped silicon germanium (SiGe:B).

[0015] After the formation of the source / drain elements (such as the first source / drain element 205-1 and the second source / drain element 205-2), a contact etch stop layer (CESL) 212 and a first interlayer dielectric layer (ILD layer) 214 are deposited over the workpiece 200. In some embodiments, the CESL 212 may contain silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 212 may be deposited using atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition processes. The first ILD layer 214 can contain materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass or doped silicon oxide such as boron phosphosilicate glass (BPSG), quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG) and / or other suitable dielectric materials.The first ILD layer 214 can be deposited over the CESL 212 by CVD, flowable CVD (FCVD), spin-on coating, or another suitable deposition technique. The workpiece 200 is then planarized using a chemical-mechanical polishing (CMP) process to expose the dummy gate stacks. The dummy gate stacks are then removed and replaced with the gate structures 206, the composition of which is described above.

[0016] The gate structures 206 are covered with a cap layer 208. In some embodiments, the cap layer 208 can contain fluorine-free tungsten (FFW), which is deposited using chemical vapor deposition (CVD) or metal-organic chemical vapor deposition (MOCVD). As shown in Fig. As shown in Figure 2, the workpiece 200 can also have a self-aligned cap layer (SAC layer) 216 over the cap layer 208. In some embodiments, the SAC layer 216 can contain silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. The SAC layer 216 can be deposited using CVD, ALD, PEALD, or a suitable process.

[0017] With reference to Fig. 1 and Fig. Method 100 comprises a block 104 where a first source / drain contact 224-1 is formed to couple to the first source / drain element 205-1, and a second source / drain contact 224-2 is formed to couple to the second source / drain element 205-2. Block 104 includes the formation of source / drain contact openings over the source / drain regions 20 through the first ILD layer 214 and the CESL 212, and the formation of the first source / drain contact 224-1 and the second source / drain contact 224-2 within the source / drain contact openings. The formation of the source / drain contact opening may involve the use of lithography and / or etching processes. In some implementations, the lithography processes include forming a photoresist layer over the workpiece, exposing the photoresist layer with structuring radiation, and developing the exposed photoresist layer, thereby forming a structured photoresist layer.The workpiece 200 is then subjected to a dry etching process using the structured photoresist layer as a masking element to expose a section of the first source / drain element 205-1 and a section of the second source / drain element 205-2. The dry etching process in block 104 can involve the use of a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a hydrocarbon species (e.g., CH4), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. After the formation of the source / drain contact opening, a silicide layer 218 is formed in the source / drain contact openings. In some cases, the silicide layer 218 may contain titanium silicide, cobalt silicide, nickel silicide, tantalum silicide or tungsten silicide.Subsequently, a metal filler layer 222 is deposited over the silicide layer 218 using selective bottom-up CVD to form the first source / drain contact 224-1 over the first source / drain element 205-1 and the second source / drain contact 224-2 over the second source / drain element 205-2. It is noted that, due to the use of selective bottom-up CVD, no barrier layer is deposited prior to the deposition of the metal filler layer 222. Selective bottom-up CVD provides selective metal-on-metal deposition of metal, which has a slower deposition rate than regular CVD. The metal filler layer 222 can contain ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Co). In the illustrated embodiment, the metal filler layer 222 contains cobalt (Co).After deposition of the metal filler layer 222, a chemical-mechanical polishing process (CMP process) can be carried out to remove excess material and form the final shape of the first source / drain contact 224-1 and the second source / drain contact 224-2. After the CMP process, the surface of the workpiece 200 is essentially planar.

[0018] With reference to Fig. 1 and Fig. In section 4, the process 100 comprises a block 106 in which a middle etch stop layer (MESL) 226 and a second interlayer dielectric layer (ILD) 228 are deposited over the workpiece 200. In block 106, the MESL 226 and the second interlayer dielectric layer (ILD) 228 are deposited sequentially over the workpiece 200. In some embodiments, the composition and formation process of the MESL 226 may be similar to those of the CESL 212, and the composition and formation process of the second ILD 228 may be similar to those of the first ILD 214.

[0019] With reference to Fig. 1 and Fig. Procedure 100 comprises a block 108 where a butt contact opening 230 is formed to expose a cap layer 208 over the first gate structure 206-1 and the first source / drain contact 224-1. In an exemplary process, a structured photoresist layer can be formed over the workpiece 200 to expose the area directly above the first gate structure 206-1 and the first source / drain contact 224-1. The workpiece 200 is then anisotropically etched using the structured photoresist layer as an etching mask. Since the anisotropic etching in block 108 is selective for the second ILD layer 228, the MESL 226, and the SAC layer 216, the endpoint of the butt contact opening 230 can fall on a cover surface of the first source / drain contact 224-1 and a cover surface of the cap layer 208 above the first gate structure 206-1. As a result, the butt contact opening 230 is formed, which in Fig. Figure 5 illustrates this. The butt contact opening 230 not only exposes the first source / drain contact 224-1, but also the cap layer 208 over the first gate structure 206-1. The anisotropic etching process in block 108 can be a dry etching process using oxygen (O2), nitrogen (N2), a fluorine-containing gas (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a hydrocarbon species (e.g., CH4), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. In some embodiments, after the formation of the butt contact opening 230, a pre-cleaning process can be carried out to remove oxide from the first source / drain contact 224-1 and the cap layer 208.

[0020] With reference to Fig. 1 and Fig. 6 comprises method 100 comprising a block 110 in which a butt contact 232 is formed in the butt contact opening 230. Operations in block 110 include depositing a barrier layer 231 and a metal filler layer into the butt contact opening 230 and planarizing the workpiece 200 to remove excess metal material. In block 110, the barrier layer 231 can be deposited using physical vapor deposition (PVD), and a metal filler layer can be deposited over the barrier layer 231 using chemical vapor deposition (CVD). In some embodiments, the barrier layer 231 can contain a metal nitride, such as titanium nitride (TiN), and the metal filler layer over the barrier layer 231 can contain tungsten (W). It is noted that the deposition process of the butt contact 232 differs from the deposition of the source / drain contact.As described above, the source / drain contacts (such as the first source / drain contact 224-1) are deposited using selective bottom-up CVD and are barrier-free, while the butt contact 232 is deposited using CVD and has the barrier layer 231. After deposition of the metal material, the workpiece 200 is planarized, for example by a CMP process, until all the metal material above the second ILD layer 228 is removed. After planarization, the butt contact 232 is formed in the butt contact opening 230. The butt contact 232 (or the barrier layer 231 of the butt contact 232, to be precise) is in direct contact with the second ILD layer 228, the MESL 226, the metal filler layer 222 of the first source / drain contact 224-1, the gate spacer 210, the SAC layer 216 and the cap layer 208 over the first gate structure 206-1.Since the cap layer 208 is electrically conductive, the butt contact 232, which lands on the first source / drain contact 224-1 and the cap layer 208, is electrically coupled to the first source / drain contact 224-1 and the first gate structure 206-1.

[0021] With reference to Fig. 1 and Fig. Procedure 7 comprises a block 112 where a third ILD layer 234 is deposited over the workpiece 200. Like the first ILD layer 214 and the second ILD layer 228, the third ILD layer 234 can contain materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon dioxide such as boron phosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon dioxide (BSG), and / or other suitable dielectric materials. The third ILD layer 234 can be deposited over the second ILD layer 228 and the butt joint 232 by CVD, flowable CVD (FCVD), spin-on coating, or other suitable deposition techniques.

[0022] With reference to Fig. 1 and Fig. 8 comprises process 100, a block 114 where a source / drain contact via opening 236 is formed to expose the second source / drain contact 224-2. The formation of the source / drain contact via opening 236 can involve photolithography and etching processes. The photolithography processes form an etch mask that has an opening directly above the second source / drain contact 224-2. With reference to Fig. 8. A dry etching process is then carried out to etch completely through the third ILD layer 234, the second ILD layer 228, and the MESL 226 to expose a cover surface of the metal fill layer 222 of the second source / drain contact 224-2. An exemplary dry etching process in block 114 may involve the use of oxygen (O2), nitrogen (N2), hydrogen (H2), a fluorine-containing gas (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases, and / or plasmas, and / or combinations thereof. In one embodiment, the source / drain contact via opening 236 is etched using a nitrogen plasma, a hydrogen plasma or both.

[0023] With reference to Fig. 1 and Fig. 9. Method 100 comprises a block 116 where the second source / drain contact 224-2 is recessed. A selective wet etching process can be performed to selectively recess the metal filler layer 222 of the second source / drain contact 224-2 in order to enlarge the source / drain contact via opening 236 into the second source / drain contact 224-2. In some implementations, the selective wet etching process involves the use of deionized (DI) water, nitric acid (HNO3), hydrogen peroxide (H2O2), hydrochloride (HCl), or isopropyl alcohol (IPA). In one embodiment, the metal filler layer 222 is formed from cobalt (Co), and the recession in block 116 is performed using hydrogen peroxide (H2O2). As described in Fig. As shown in Figure 9, due to the isotropic property of the wet etching process, a cover surface of the metal filler layer 222 of the second source / drain contact 224-2 becomes concave or crater-shaped. In some embodiments, as shown in Figure 9, the cover surface of the metal filler layer 222 of the second source / drain contact 224-2 becomes concave or crater-shaped. Fig. 9, after the recess, a section of the source / drain contact via opening 236 can undercut the MESL 226 around the second source / drain contact 224-2. The recess in block 116 can improve adhesion and increase the interface area with the source / drain contact via 240 to be formed (which is described below).

[0024] With reference to Fig. 1 and Fig. Procedure 10 comprises a block 118 where a source / drain contact via 240 is formed in the source / drain contact via hole 236. Operations in block 118 may include metal deposition and surface planarization. In an exemplary process, a metal filler layer is deposited over the workpiece 200, containing in the source / drain contact via hole 236. In some embodiments, the metal filler layer may contain tungsten (W) or ruthenium (Ru). In the embodiment shown, the metal filler layer contains tungsten (W). In some implementations, the metal filler layer may be deposited using selective bottom-up CVD or a suitable deposition technique. After deposition of the metal filler layer, a CMP process is performed to planarize the workpiece 200 to remove excess material and form the source / drain contact via 240. As described in Fig. As shown in Figure 10, the source / drain contact via 240 extends through the third ILD layer 234, the second ILD layer 228, and MESL 226. Due to the indentation process in block 116, the source / drain contact via 240 extends partially into the metal-filled layer 222 of the second source / drain contact 224-2 and can undercut the MESL 226 around edges of the second source / drain contact 224-2. In some embodiments, shown in Fig. 10, a cover surface of the source / drain contact via 240 is higher than a cover surface of the butt contact 232 by a difference essentially equal to a thickness of the third ILD layer 234.

[0025] With reference to Fig. 1 and Fig. Procedure 11 comprises a block 120 where a fourth dielectric layer 242 is deposited over the workpiece 200. Like the first ILD layer 214 and the second ILD layer 228, the fourth ILD layer 242 can contain materials such as tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass, or doped silicon dioxide such as boron phosphosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon dioxide (BSG), and / or other suitable dielectric materials. The fourth ILD layer 242 can be deposited over the third ILD layer 234 and a cover surface of the source / drain via 240 by CVD, flowable CVD (FCVD), spin-on coating, or other suitable deposition techniques.

[0026] With reference to Fig. 1 and Fig. Method 100 comprises a block 122 where a gate contact opening 244 is formed to expose the cap layer 208 on the second gate structure 206-2. Formation of the gate contact openings 244 by the fourth ILD layer 242, the third ILD layer 234, the second ILD layer 228, the MESL 226, and the SAC layer 216 over the second gate structure 206-2 or the third gate structure 206-3 can involve the use of lithography and / or etching processes. The lithography processes include forming a photoresist layer over the fourth ILD layer 242, exposing the photoresist layer with structuring radiation, and developing the exposed photoresist layer, thereby forming a structured photoresist layer. The workpiece 200 is then etched in a dry etching process using the structured photoresist layer as an etching mask.An exemplary dry etching process for Block 122 may involve the use of oxygen (O2), nitrogen (N2), hydrogen (H2), a fluorine-containing gas (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases, and / or plasmas, and / or combinations thereof. Following the dry etching process, the structured photoresist layer may be removed by ashing. A wet cleaning process may be performed to remove particles on the cap layer 208 above the second gate structure 206-2 and the third gate structure 206-3. In some implementations, the wet cleaning process may involve the use of deionized (DI) water or isopropyl alcohol (IPA).

[0027] With reference to Fig. 1, Fig. 13 and Fig. Method 100 comprises a block 124 in which a gate contact 250 is formed in the gate contact opening 244. The gate contact 250 may have a metal filler layer 248. The metal filler layer 248 for the gate contact 250 may contain tungsten (W) or ruthenium (Ru) and may be deposited using selective bottom-up CVD. After the metal filler layer 248 has been deposited over the workpiece 200, as shown in Fig. As shown in Figure 13, the workpiece 200 is planarized in a CMP process to form the gate contacts 250, as shown in Fig. Figure 14 shows that planarization in block 124 is carried out until the cover surfaces of the gate contacts 250, the source / drain contact via 240, and the third ILD layer 234 are coplanar. The cover surfaces of the gate contacts 250, the source / drain contact via 240, and the third ILD layer 234 are all higher than the cover surface of the butt contact 232 by a thickness T of the third ILD layer 234. In some cases, the thickness T of the third ILD layer 234 can be Fig. 14 between approximately 5 nm and approximately 45 nm. If the thickness of the third ILD layer 234 is greater than 45 nm, the aspect ratios of the gate contact orifices 244 or the source / drain contact vias 236 may be too large for satisfactory metal filling. If the thickness of the third ILD layer 234 is less than 5 nm, the butt contact 232 may not be sufficiently insulated from overlying metal conductors or contact structures.

[0028] It will continue on Fig. 14 Referenced. According to the present disclosure, the butt contact 232 has a lower section extending into the SAC layer 216 above the first gate structure 206-1, and an upper section arranged above the first source / drain contact 224-1 and the lower section. The lower section of the butt contact 232 is arranged between two adjacent gate spacers 210 and is in contact with the cap layer 208 on the first gate structure 206-1. The upper section of the butt contact 232 is arranged in the MESL 226 and the second ILD layer 228. As in Fig. 14 shown, along the Z direction perpendicular to the substrate 202 (shown in Fig. 2) The lower section has a first height H1 and the upper section has a second height H2. In the illustrated embodiment, the first height H1 is essentially equal to the thickness of the SAC layer 216 and falls in a range between approximately 10 nm and approximately 25 nm. If the thickness of the SAC layer 216 is greater than 25 nm, the additional etching required to fracture the SAC layer 216 may punch through the first source / drain contact 224-1 when the butt contact opening 230 is formed. If the thickness of the SAC layer 216 is less than 10 nm, the butt contact opening 230 may expand laterally, resulting in undesired coupling to adjacent gate contacts. The second height H2 of the upper section is essentially equal to the combined thickness of the MESL 226 and the second ILD layer 228 and can be between approximately 30 nm and approximately 40 nm.If the second height H2 is less than 30 nm, the formation of the butt contact opening 230 can damage the first gate structure 206-1 and the cap layer 208. If the second height H2 is greater than 40 nm, the butt contact opening 230 may not satisfactorily expose the cap layer 208 above the first gate structure 206-1. The butt contact 232 has a third height H3, which is the sum of the first height H1 of the lower section and the second height H2 of the upper section. In some cases, the third height H3 may be between approximately 40 nm and 60 nm. The lower section has a first upper opening width W1 along the X direction, and the upper section has a second opening width W2 along the X direction. In some cases, the first upper opening width W1 may be between approximately 10 nm and approximately 25 nm, and the second upper opening width W2 may be between approximately 14 nm and approximately 40 nm.If the second upper aperture width W2 is less than 14 nm, the butt contact 232 may have a poor landing on the first source / drain contact 224-1. If the second upper aperture width W2 is greater than 40 nm, the butt contact 232 may come into contact with adjacent gate contacts, resulting in an undesired electrical connection. Overall, the butt contact 232 of the present disclosure has a nominal aspect ratio (i.e., the third height H3 divided by the second upper aperture width W2, or H3 / W2) between approximately 0.9 and approximately 2. It is evident that if a hypothetical butt contact also extends through the third ILD layer 234 of thickness T, its aspect ratio would be calculated as the sum of the third height H3 and the thickness T divided by the second aperture width W2.Such a hypothetical butt contact would have a nominal aspect ratio between approximately 1.5 and 3, which would hinder satisfactory metal filling in its lower section and could lead to pores and defects. Such pores and defects can increase the contact resistance.

[0029] Fig. Figure 14 shows that the butt contact 232, the source / drain contact via 240, and the gate contacts 250 are shown along the same cross-section. In some embodiments, while the shapes, depths, and relative vertical positions may remain the same, the butt contact 232, the source / drain contact via 240, and the gate contacts 250 may not be on the same cross-section. Fig. Figure 15 provides an example where the butt contacts 232, the source / drain vias 240, and the gate contacts 250 of a semiconductor device 200 do not necessarily appear on a single cross-section. The semiconductor device 200 in Fig. 15 has several gate structures 206 extending lengthwise along the Y-direction, several active regions 204 extending lengthwise along the X-direction, and several source / drain contacts 224 extending lengthwise along the Y-direction. The semiconductor device 200 has several butt contacts 232, several source / drain contact vias 240, and several gate contacts 250. Each of the butt contacts 232 spans a gate structure 206 and an adjacent source / drain contact 224 and is electrically coupled to it. Each of the source / drain contact vias 240 is located directly on a source / drain contact 224. Each of the gate contacts 250 is located directly above a gate structure 206 and is electrically connected to it. As in Fig.As shown in Figure 15, a cross-section that cuts along the X direction via a butt contact 232 does not cut through any of the source / drain contact vias 240 or any of the gate contacts 250.

[0030] The butt contact and the method of the present disclosure offer several advantages. For example, the butt contact opening, which exposes a gate structure and an adjacent source / drain contact, is not as deep as the source / drain contact via opening or the gate contact opening. As such, the butt contact opening has a smaller aspect ratio, which is conducive to satisfactory metal filling. The butt contact can be formed from tungsten (W) and can be deposited using a combination of PVD and CVD. The smaller aspect ratio and the two-stage metal filling improve the integrity of the butt contact and reduce contact resistance to the gate structure.

[0031] The present disclosure provides many different embodiments. In one embodiment, a method is provided. The method comprises picking up a workpiece having a first gate structure having a first cap layer thereon, a first source / drain contact adjacent to the first gate structure, a second gate structure having a second cap layer thereon, a second source / drain contact, an etch stop layer (ESL) over the first source / drain contact and the second source / drain contact, and a first dielectric layer over the ESL.The process further includes forming a butt contact opening to expose the first cap layer and the first source / drain contact, forming a butt contact in the butt contact opening, after forming the butt contact, depositing a second dielectric layer, forming a source / drain contact via opening through the second dielectric layer, the ESL layer and the first dielectric layer to expose the second source / drain contact, and forming a source / drain contact via in the source / drain contact via opening.

[0032] In some embodiments, the method may further include, after forming the source / drain contact via, depositing a third dielectric layer over the source / drain contact via, forming a gate contact via opening to expose the second cap layer, and forming a gate contact via in the gate contact via opening. In some embodiments, the method may further include, prior to forming the source / drain contact via, recessing the second source / drain contact. In some implementations, recessing the second source / drain contact involves the use of hydrogen peroxide. In some cases, the first cap layer and the second cap layer contain fluorine-free tungsten. In some embodiments, the first source / drain contact and the second source / drain contact contain cobalt.In some embodiments, the formation of the butt joint comprises depositing a barrier layer over the butt joint opening using physical vapor deposition (PVD), depositing a metal filler layer over the barrier layer using chemical vapor deposition (CVD), and planarizing the deposited metal filler layer. In some embodiments, after planarizing, a cover surface of the butt joint is coplanar with a cover surface of the first dielectric layer. In some implementations, the metal filler layer contains tungsten.

[0033] In another embodiment, a method is provided. The method comprises picking up a workpiece having a first gate structure, a first source / drain contact adjacent to the first gate structure, a second gate structure, a second source / drain contact, an etch stop layer (ESL) over the first source / drain contact and the second source / drain contact, and a first dielectric layer over the ESL.The process can further include forming a butt contact to couple the first gate structure and the first source / drain contact, depositing a second dielectric layer over the first dielectric layer and the butt contact, forming a source / drain contact via through the second dielectric layer, the first dielectric layer and the ESL layer to couple the second source / drain contact, depositing a third dielectric layer over the source / drain contact via and the second dielectric layer, and forming a gate contact through the third dielectric layer, the second dielectric layer, the first dielectric layer and the ESL layer to couple the second gate structure.

[0034] In some embodiments, the method may further include planarizing the workpiece after the gate contact has been formed, until a cover face of the gate contact is coplanar with a cover face of the source / drain contact via. In some implementations, the workpiece may further include a first cap layer over the first gate structure, a second cap layer over the second gate structure, a first self-aligned cap layer (SAC layer) over the first cap layer, and a second SAC layer over the second cap layer. In some embodiments, a portion of the butt contact extends through the first SAC layer to terminate on the first cap layer. In some implementations, the gate contact extends through the second SAC layer to terminate on the second cap layer.In some embodiments, the formation of the butt contact comprises forming an butt contact opening to expose a cover surface of the first source / drain contact and the first cap layer, depositing a barrier layer over the butt contact opening using physical vapor deposition (PVD), depositing a metal filler layer over the barrier layer using chemical vapor deposition (CVD), and planarizing the deposited metal filler layer. In some embodiments, the metal filler layer contains tungsten.

[0035] In a further embodiment, a semiconductor structure is provided. The semiconductor structure comprises a first gate structure having a first cap layer on it, a first source / drain contact adjacent to the first gate structure, a second gate structure having a second cap layer on it, a second source / drain contact, an etch stop layer (ESL) over the first source / drain contact and the second source / drain contact, a first dielectric layer over the ESL, a second dielectric layer over the first dielectric layer, a butt contact spanning the first gate structure and the first source / drain contact, wherein the butt contact is in contact with the first source / drain contact and the first cap layer, a source / drain contact via arranged over the second source / drain contact, and a gate contact arranged over the second cap layer.The second dielectric layer is positioned directly on a top surface of the butt contact. The butt contact has a lower height above the first cap layer than the gate contact and the source / drain via.

[0036] In some embodiments, the first source / drain contact and the second source / drain contact contain cobalt. In some cases, the first cap layer and the second cap layer contain fluorine-free tungsten. In some embodiments, the butt contact contains tungsten.

Claims

[1] Procedure, encompassing: Picking up a workpiece (200), comprising: a first gate structure (206-1) which has a first cap layer (208) on it, a first source / drain contact (224-1) adjacent to the first gate structure (206-1), a second gate structure (206-2) which has a second cap layer (208) on it, a second source / drain contact (224-2), an etch stop layer (226) over the first source / drain contact (224-1) and the second source / drain contact (224-2) and a first dielectric layer over the etch stop layer; Forming a butt contact opening (230) to expose the first cap layer (208) and the first source / drain contact (224-1); Forming a butt contact (232) in the butt contact opening (230); after forming the butt contact (232), depositing a second dielectric layer; Forming a source / drain contact via opening (236) through the second dielectric layer, the etch stop layer (226) and the first dielectric layer to expose the second source / drain contact (224-2); and Forming a source / drain contact via (240) in the source / drain contact via opening (236). [2] Method according to claim 1, further comprising: after forming the source / drain contact via (240), depositing a third dielectric layer over the source / drain contact via (240); Forming a gate contact via opening (244) to expose the second cap layer (208); and Forming a gate contact via in the gate contact via opening (244). [3] Method according to claim 1 or 2, further comprising: Before forming the source / drain contact via (240), deepening the second source / drain contact (224-2). [4] Method according to claim 3, wherein the deepening of the second source / drain contact (224-2) comprises the use of hydrogen peroxide. [5] Method according to any of the preceding claims, wherein the first cap layer (208) and the second cap layer (208) contain fluorine-free tungsten. [6] Method according to any of the preceding claims, wherein the first source / drain contact (224-1) and the second source / drain contact (224-2) contain cobalt and are free of a barrier layer. [7] Method according to any of the preceding claims, comprising forming the butt contact (232): Deposition of a barrier layer (231) over the butt joint opening (230) using physical vapor phase deposition; Deposition of a metal filler layer over the barrier layer (231) using chemical vapor deposition; and Planarizing the deposited metal filler layer. [8] Method according to claim 7, wherein after planarizing a cover surface of the butt contact (232) is coplanar with a cover surface of the first dielectric layer. [9] Method according to claim 7 or 8, wherein the metal filler layer contains tungsten. [10] Procedures, including: Picking up a workpiece (200), comprising: a first gate structure (206-1), a first source / drain contact (224-1) adjacent to the first gate structure (206-1), a second gate structure (206-2), a second source / drain contact (224-2), an etch stop layer (226) over the first source / drain contact (224-1) and the second source / drain contact (224-2) and a first dielectric layer over the etch stop layer; Forming a butt contact (232) to couple the first gate structure (206-1) and the first source / drain contact (224-1); Deposition of a second dielectric layer over the first dielectric layer and the butt joint (232); Forming a source / drain contact via (240) through the second dielectric layer, the first dielectric layer and the etch stop layer to couple the second source / drain contact (224-2); Deposition of a third dielectric layer over the source / drain contact via (240) and the second dielectric layer; and Forming a gate contact (250) through the third dielectric layer, the second dielectric layer, the first dielectric layer and the etch stop layer to couple the second gate structure (206-2). [11] Method according to claim 10, further comprising: After forming the gate contact (250), planarizing the workpiece (200) until a cover surface of the gate contact (250) is coplanar with a cover surface of the source / drain contact via (240). [12] Method according to claim 10 or 11, wherein the workpiece (200) further comprises: a first cap layer (208) over the first gate structure (206-1); a second cap layer (208) over the second gate structure (206-2); a first self-aligned cap layer (216) above the first cap layer (208); and a second self-aligned cap layer (216) above the second cap layer (208). [13] Method according to claim 12, wherein a section of the impact contact (232) extends through the first self-aligned cap layer (216) to land on the first cap layer (208). [14] Method according to claim 12 or 13, wherein the gate contact (250) extends through the second self-aligned cap layer (216) to land on the second cap layer (208). [15] Method according to any one of claims 12 to 14, comprising forming the butt contact (232): Forming a butt contact opening (230) to expose a cover surface of the first source / drain contact (224-1) and the first cap layer (208); Deposition of a barrier layer (231) over the butt joint opening (230) using physical vapor phase deposition; Deposition of a metal filler layer over the barrier layer (231) using chemical vapor deposition; and Planarizing the deposited metal filler layer. [16] Method according to claim 15, wherein the metal filling layer contains tungsten. [17] Semiconductor structure, having: a first gate structure (206-1) which has a first cap layer (208) on it; a first source / drain contact (224-1) adjacent to the first gate structure (206-1); a second gate structure (206-2) which has a second cap layer (208) on it; a second source / drain contact (224-2); an etch stop layer (226) over the first source / drain contact (224-1) and the second source / drain contact (224-2); a first dielectric layer over the etch stop layer (226); a second dielectric layer (234) over the first dielectric layer; a butt contact (232) spanning the first gate structure (206-1) and the first source / drain contact (224-1), wherein the butt contact (232) is in contact with the first source / drain contact (224-1) and the first cap layer (208); a source / drain contact via (240) arranged above the second source / drain contact (224-2); and a gate contact (250) which is arranged above the second cap layer (208), wherein the second dielectric layer (234) is arranged directly on a cover surface of the butt contact (232); wherein the butt contact (232) has a lower height above the first cap layer (208) than the gate contact (250) and the source / drain contact via. [18] Semiconductor structure according to claim 17, wherein the first source / drain contact (224-1) and the second source / drain contact (224-2) contain cobalt and are free of a barrier layer (231). [19] Semiconductor structure according to claim 17 or 18, wherein the first cap layer (208) and the second cap layer (208) contain fluorine-free tungsten. [20] Semiconductor structure according to claim 17, 18 or 19 wherein the butt contact (232) contains tungsten.

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