Semiconductor Device Structure and Its Manufacturing Process

Abstract

Semiconductor device structure (100d) comprising: a fin structure (110) formed over a substrate (102); a gate structure (150) formed over the fin structure (110), the gate structure (150) comprising: - a gate dielectric layer (152); - a first layer (154); and - a filler layer (158) over the first layer (154); and an electrically conductive protective layer (160) formed above the filler layer (158) of the gate structure (150), wherein the protective layer (160) is separated from the first layer (154) by the filler layer (158), wherein a first width of a lower surface of the protective layer (160) is equal to a second width of an upper surface of the filler layer (158), and a second layer (156) formed below the first layer (154), wherein the filler layer (158) is formed on the first layer (154) and the second layer (156), and wherein the first layer (154) and the second layer (156) have a U-shaped structure.

Description

GENERAL STATE OF THE ART Semiconductor devices are used in numerous electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by successively depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material onto a semiconductor substrate and structuring the various material layers using lithography to create circuit components and elements. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are separated by sawing between the integrated circuits along a scribed line. The individual dies are typically packaged separately, for example, in multi-chip modules or other types of packages. While the semiconductor industry has evolved into nanometer technology process nodes in the pursuit of higher device density, higher performance and lower costs, challenges from both manufacturing and design problems have led to the development of three-dimensional designs. Although existing semiconductor devices are generally adequate for their intended purpose, they are not entirely satisfactory in every respect. A semiconductor device and a corresponding fabrication method are known from US patent 2014 / 0110778A1. The semiconductor device comprises a gate insulating layer formed on the inner wall of a substrate depression, a release material layer formed on the gate insulating layer to exert a tensile or compressive stress on a channel of a MOS field-effect transistor, and a gate metal formed on the release material layer. The fabrication method comprises forming a working-function material layer on a gate insulating layer to exert a tensile or compressive stress on a channel of a MOS field-effect transistor, the gate insulating layer being formed on the inner wall of a substrate depression, and depositing a gate metal onto the working-function material layer.US Patent 2013 / 0214289A1 discloses a semiconductor structure comprising a semiconductor material having a conductivity type and a source that contacts the semiconductor material, wherein the source has a conductivity type opposite to the conductivity type of the semiconductor material.It further comprises a drain that contacts the semiconductor material, wherein the drain is arranged at a distance from the source and has a conductivity type opposite to the conductivity type of the semiconductor material, a channel region of the semiconductor material located between the source and the drain, a gate dielectric structure that contacts and lies above the channel region, a metal gate that contacts and lies above the channel region, a protective cap that contacts and lies above the metal gate, and a non-conductive sidewall spacer that contacts the gate dielectric structure and laterally surrounds both the metal gate and the protective cap. US Patent 2016 / 0079243A1 discloses a method for manufacturing a semiconductor device, which includes forming an insulating layer with a trench on a substrate and forming a first metal gate layer pattern along the side and bottom surfaces of the trench. The method further includes forming a second metal gate film on the first metal gate film pattern and the insulating film, and forming a second metal gate film pattern positioned on the first metal gate film pattern by removing the second metal gate film to expose at least a portion of the insulating film, and forming a barrier layer pattern on the second metal gate film pattern by oxidizing an exposed surface of the second metal gate film pattern. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Figures 1A-1K show perspective views of various stages for forming a semiconductor device structure according to some embodiments of the disclosure. Figure 2A shows a cross-sectional view of the semiconductor device structure along line AA', as shown in Figure 1I, according to some embodiments of the disclosure. Figure 2B shows a cross-sectional view of the semiconductor device structure along line BB', as shown in Figure 1I, according to some embodiments of the disclosure.Figure 3A shows a cross-sectional view of the semiconductor device structure along line AA', shown in Figure 1J, according to some embodiments of the disclosure. Figure 3B shows a cross-sectional view of the semiconductor device structure along line BB', shown in Figure 1J, according to some embodiments of the disclosure. Figure 4A shows a cross-sectional view of the semiconductor device structure along line AA', shown in Figure 1K, according to some unclaimed embodiments of the disclosure. Figure 4B shows a cross-sectional view of the semiconductor device structure along line BB', shown in Figure 1K, according to some unclaimed embodiments of the disclosure. Figures 5A-5K show cross-sectional views of various stages for forming the semiconductor device structure according to some unclaimed embodiments of the disclosure.Figures 6A-6C show cross-sectional views of various stages for forming a semiconductor device structure according to some unclaimed embodiments of the disclosure. Figures 7A-7E show cross-sectional views of various stages for forming the semiconductor device structure according to some unclaimed embodiments of the disclosure. Figures 8A-8I show cross-sectional views of various stages for forming a semiconductor device structure according to the invention according to some embodiments of the disclosure. Figures 9A-9E show cross-sectional views of various stages for forming a semiconductor device structure according to some unclaimed embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed. Several variations of the embodiments are described. The same reference numerals are used in the different views and illustrative embodiments to denote the same elements. It should be clear that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or eliminated by other embodiments of the method. The gate-all-around transistor (GAA) structures described below can be structured by any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual-structuring or multi-structuring processes. In general, dual-structuring or multi-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacing than would otherwise be obtainable with a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used to structure the GAA structure. Embodiments for forming a semiconductor device structure are provided. Figures 1A-1K show perspective views of various stages for forming a semiconductor device structure 100a according to some embodiments of the disclosure. The semiconductor device structure 100a is a gate-all-around (GAA) transistor structure. In some other embodiments, when the semiconductor device structure 100a is a FinFET device structure, a fin structure is formed over a substrate. The gate structure 150 (shown in Figure 5H) is formed over the fin structure. As shown in Fig. 1A, a substrate 102 is provided according to some embodiments of the invention. The substrate 102 can be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 can contain other elemental semiconductor materials such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 has an epitaxial layer. For example, the substrate 102 has an epitaxial layer that lies over a bulk semiconductor. A number of first semiconductor layers 104 and a number of second semiconductor layers 106 are sequentially and alternately formed on the substrate 102. The semiconductor layers 104 and 106 are vertically stacked to form a stacked nanowire structure (or stacked nanostructures). In some embodiments, the first semiconductor layers 104 and the second semiconductor layers 106 independently contain silicon (Si), germanium (Ge), silicon germanium (Si1-xGex, 0,1 <x<0,7, der Wert x ist der Atomprozentsatz von Germanium (Ge) im Siliziumgermanium), Indiumarsenid (InAs), Indiumgalliumarsenid (InGaAs), Indiumantimonid (InSb) oder ein anderes anwendbares Material. In manchen Ausführungsformen sind die erste Halbleiterschicht 104 und die zweite Halbleiterschicht 106 aus verschiedenen Materialien hergestellt. The first semiconductor layers 104 and the second semiconductor layers 106 are made of different materials with different lattice constants. In some embodiments, the first semiconductor layer 104 is made of silicon (Si) and the second semiconductor layer 106 is made of silicon germanium (Si1-xGex, 0.1). <x<0,7) hergestellt. In manchen anderen Ausführungsformen ist die erste Halbleiterschicht 104 aus Siliziumgermanium (Si1-xGex, 0,1 <x<0,7) hergestellt und die zweite Halbleiterschicht 106 ist aus Silizium (Si) hergestellt. In some embodiments, the first semiconductor layers 104 and the second semiconductor layers 106 are formed by a selective epitaxial growth process (SEG process), a chemical vapor deposition process (CVD process) (e.g., low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD)), a molecular epitaxial growth process, or another applicable process. In some embodiments, the first semiconductor layers 104 and the second semiconductor layers 106 are formed in situ in the same chamber. In some embodiments, the thickness of each of the first semiconductor layers 104 is in the range of about 1.5 nanometers (nm) to about 20 nm. Terms such as "about" in conjunction with a specific distance or size are to be interpreted in such a way as not to exclude an immaterial deviation from the specified distance or size and may, for example, include deviations of up to 20%. In some embodiments, the first semiconductor layers 104 are of substantially uniform thickness. In some embodiments, the thickness of each of the second semiconductor layers 106 is in the range of about 1.5 nm to about 20 nm. In some embodiments, the second semiconductor layers 106 are of substantially uniform thickness. Subsequently, as shown in Fig. 1B, the first semiconductor layers 104 and the second semiconductor layers 106 are structured to form a fin structure 110 according to the invention. Subsequently, as shown in Fig. 1C, an insulation structure 114 is formed over the substrate 102 according to some embodiments. The insulation structure 114 can be a trench insulation structure (STI structure) that surrounds the fin structure 110. The upper section of the fin structure 110 lies above the insulation structure 114. A lower section of the fin structure 110 is surrounded by the insulation structure 114, and an upper section of the fin structure 110 projects from the insulation structure 114. Subsequently, as shown in Fig. 1D, according to some embodiments, a dummy gate dielectric layer 116 is formed over the fin structure 110, and then a dummy gate electrode layer 118 is formed on the dummy gate dielectric layer 116. The dummy gate dielectric layer 116 and the dummy gate electrode layer 118 are then structured by a structuring process. The dummy gate structure 120 is constructed from the dummy gate dielectric layer 116 and the dummy gate electrode layer 118. The structuring process comprises a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, baking after exposure, photoresist development, rinsing, and drying (e.g., hard baking). The etching process includes either a dry or wet etching process. The dummy gate electrode layer 118 is formed to partially cover and extend over the fin structure 110. In some embodiments, the dummy gate electrode layer 118 is wrapped around the fin structure 110. The dummy gate dielectric layer 116 may be made of or contain silicon oxide. In some embodiments, the dummy gate dielectric layers 116 are formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), another applicable process, or a combination thereof. In some embodiments, the dummy gate electrode layer 118 is made of polycrystalline silicon (poly-Si) or polycrystalline silicon-germanium (poly-SiGe). In some embodiments, the dummy gate electrode layer 118 is formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), another applicable process, or a combination thereof. Then, as shown in Fig. 1E, according to some embodiments, a gate spacer layer 124 is formed on opposite side walls of the dummy gate electrode layer 118 and above the dummy gate dielectric layer 116. The gate spacer layer 124 can provide more protection to the dummy gate structure 120 during the following processes. In some embodiments, the gate spacer layer 124 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. In some embodiments, the gate spacer layer 124 is formed by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), another applicable process, or a combination thereof. Subsequently, as shown in Fig. 1F, according to some embodiments, a section of the first semiconductor layers 104 is removed to form an S / D trench 129. The S / D trench 129 lies between two adjacent second semiconductor layers 106. Subsequently, another section of the first semiconductor layers 104 directly beneath the gate spacer layer 124 is removed to form a cavity (not shown), and the cavity is exposed by the S / D trench 129. An internal spacer layer 136 is then formed within the cavity. The internal spacer layer 136 lies directly beneath the gate spacer layer 124. The internal spacer layer 136 acts as a barrier layer between an S / D structure 138 (formed later, Fig. 1G) and a gate structure 150 (formed later, as shown in Fig. 1K). The internal spacer layer 136 reduces the parasitic capacitance between the S / D structure 138 (formed later, Fig. 1G) and the gate structure 150 (formed later, as shown in Fig. 1K). Then, as shown in Fig. 1F, according to some embodiments an S / D structure 138 is formed in the S / D groove 129. The S / D structure 138 is in direct contact with the inner spacer layer 136. The S / D structure 138 can contain silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), or a combination thereof. The S / D structure 138 can be doped with one or more dopants. In some embodiments, the S / D structure 138 is silicon (Si) doped with phosphorus (P), arsenic (As), antimony (Sb), or another applicable dopant. Alternatively, the S / D structure 138 is silicon germanium (SiGe) doped with boron (B) or another applicable dopant. In some embodiments, the S / D structure 138 is formed by an epitaxy or epitactic process (epi-process). The epi-process may include a selective epitaxial growth process (SEG process), CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, or other suitable epi-processes. Subsequently, as shown in Fig. 1H, according to some embodiments, a contact etch stop layer (CESL) 140 is formed over the S / D structures 138, and an intermediate dielectric layer (ILD layer) 142 is formed over the CESL 140. A portion of the ILD layer 142 is then removed to expose the upper surface of the dummy gate electrode layer 118. In some embodiments, this portion of the ILD layer 142 is removed by a planarization process or a chemical-mechanical polishing (CMP) process. In some embodiments, CESL 140 is manufactured from silicon nitride, silicon oxynitride, and / or other applicable materials. CESL 140 can be formed by plasma-enhanced chemical vapor deposition (CVD), low-pressure CVD, atomic layer deposition (ALD), or other applicable processes. The ILD layer 142 can have multiple layers made of several dielectric materials, such as silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), low-k dielectric material, and / or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon dioxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), or polyimide. The ILD layer 142 can be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on coating process, or other applicable processes. Then, as shown in Fig. 1I, according to some embodiments, the dummy gate structure 120 is removed to form a trench 143 in the ILD layer 142. The dummy gate dielectric layer 116 and the dummy gate electrode layer 118 are removed by an etching process, such as a dry etching process or a wet etching process. Fig. 2A shows a cross-sectional view of the semiconductor device structure along line AA', shown in Fig. 1I, according to some embodiments of the disclosure. Fig. 2B shows a cross-sectional view of the semiconductor device structure along line BB', shown in Fig. 1I, according to some embodiments of the disclosure. As shown in Fig. 2A and Fig. 2B, the first semiconductor layers 104 and the second semiconductor layers 106 are exposed by the trench 143. Then, as shown in Fig. 1J, according to some embodiments, the first semiconductor layers 104 are removed to form a number of columns 145 of the disclosure. Each of the columns 145 is formed between two adjacent second semiconductor layers 106. Since the first semiconductor layers 104 and the second semiconductor layers 106 are made of different materials, they have different etch selectivity. Therefore, the first semiconductor layers 104 are removed, but the second semiconductor layers 106 remain. The remaining second semiconductor layers 106 are used as a channel region of the semiconductor device structure 100a. In some embodiments, the second semiconductor layers 106 can be referred to as “nanostructures”, “nanowires”, or “nanosheets”. Therefore, the first fin structure 110 has a number of nanostructures stacked in a vertical direction. Fig. 3A shows a cross-sectional view of the semiconductor device structure along line AA', shown in Fig. 1J, according to some embodiments of the disclosure. Fig. 3B shows a cross-sectional view of the semiconductor device structure along line BB', shown in Fig. 1J, according to some embodiments of the disclosure. As shown in Fig. 3A and Fig. 3B, the gaps 145 lie between two adjacent second semiconductor layers 106 and the gaps 145 are exposed by the trench 143. Subsequently, as shown in Fig. 1K, according to some embodiments of the disclosure, a gate dielectric layer 152, a first layer 154, a second layer 156, and a filler layer 158 are formed in the groove 143 and the gaps 145. A gate structure 150 is constructed by the gate dielectric layer 152, the first layer 154, the second layer 156, and the filler layer 158. A protective layer 160 is then formed on the filler layer 158, and an insulating layer 162 is formed over the protective layer 160. The first layer 154 and the second layer 156 are made of different materials. The insulating layer 162 has a protruding section in direct contact with the gate dielectric layer 152. Fig. 4A shows a cross-sectional view of the semiconductor device structure along line AA', shown in Fig. 1K, according to some embodiments of the disclosure. Fig. 4B shows a cross-sectional view of the semiconductor device structure along line BB', shown in Fig. 1K, according to some embodiments of the disclosure. As shown in Fig. 4A and Fig. 4B, the first layer 154 has a U-shaped structure, and the second layer 156 is formed over the first layer 154. The filler layer 158 is separated from the first layer 152 by the second layer 154, and the protective layer 160 is separated from the first layer 152 by the second layer 154 and the filler layer 158. The protective layer 160 is selectively formed on the filler layer 158 and the second layer 154, but not on the gate dielectric layer 152. Figures 5A-5K show cross-sectional views of various stages for the formation of the semiconductor device structure 100a according to some unclaimed embodiments of the disclosure. Figure 5A shows an enlarged area A of Figure 3B according to some embodiments of the disclosure. Figures 5A-5K show the individual processes for the formation of the gate structure 150 in the trench 143 and in the columns 145. As shown in Fig. 5A, the gate dielectric layer 152 is formed in the trench 143 and on the gate spacer layer 124. The trench 143 is not completely filled with the gate dielectric layer 152. In some embodiments, the gate dielectric layer 152 is a high-k dielectric layer. In some embodiments, the high-k gate dielectric layer is formed from one or more layers of a dielectric material such as HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer 152 is formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, another applicable process, or a combination thereof. Subsequently, as shown in Fig. 5B, the first layer 154 is formed above the gate dielectric layer 152 according to some embodiments of the disclosure. The first layer 154 is formed conformally in the trench 143. The first layer 154 is a conductive layer. The first layer 154 can be a single layer or a multiple layer. In some embodiments, the first layer 154 contains an n-exit work material. In some embodiments, the first layer 154 contains a silicon-containing material, an aluminum-containing material, or a combination thereof. In some embodiments, the silicon-containing material is made of TiSiN, TiSiC, TiSiAlC, or a combination thereof. In some embodiments, the aluminum-containing material is made of TiAlC, TaAlC, TiSiAlC, TiAlN, AlN, or a combination thereof. In some embodiments, the first layer 154 is formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, another applicable process, or a combination thereof. Then, as shown in Fig. 5C, according to some embodiments of the disclosure, a dummy layer 153 is formed above the first layer 154 and in the trench 143. The trench 143 is completely filled with the gate dielectric layer 152, the first layer 154, and the dummy layer 153. The dummy layer 153 is used to protect underlying layers. In some embodiments, the dummy layer 153 is formed from spin-on glass (SOG), spin-on carbon (SOC), antireflective coating (ARC), another applicable material, or a combination thereof. In some embodiments, the dummy layer 153 is formed using a chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, another applicable process, or a combination thereof. Then, as shown in Fig. 5D, according to some embodiments of the disclosure, a section of the dummy layer 153 is removed. As a result, a section of the first layer 154 is exposed. In some embodiments, the section of the dummy layer 153 is removed by an etching process, such as a wet etching process or a dry etching process. Then, as shown in Fig. 5E, according to some embodiments of the disclosure, a section of the first layer 154 is removed using the remaining dummy layer 153 as a mask to expose a section of the gate dielectric layer 152. The remaining first layer 154, which is covered by the dummy layer 153, is not removed. The upper surface of the first layer 154 is lower than the upper surface of the gate spacer layer 124. Subsequently, as shown in Fig. 5F, the dummy layer 153 is removed according to some embodiments of the disclosure. In some embodiments, the dummy layer 153 is removed by an etching process, such as a wet etching process or a dry etching process. As a result, the first layer 154 has a U-shaped structure. The trench 153 has a first depth D1. In some embodiments, the first depth D1 is in a range of approximately 30 nm to approximately 200 nm. The remaining first layer 154 has a second depth D2. In some embodiments, the second depth D2 is in a range of approximately 1 nm to approximately 10 nm. Subsequently, as shown in Fig. 5G, according to some embodiments of the disclosure, the second layer 156 is formed above the first layer 154 and in the trench 143, and the filler layer 158 is formed above the second layer 156 and the gate spacer layer 124. Then, a section of the second layer 156 and a section of the filler layer 158 outside the trench 143 are removed by a planarization process, a chemical-mechanical polishing (CMP) process. The second layer 156 is a conductive layer. The second layer 156 can be a single layer or a multiple layer. In some embodiments, the second layer 156 comprises a p-working material. In some embodiments, the second layer 156 is made of TiN, TaN, WCN, WSi, Ti, Ni, Co, or a combination thereof. In some embodiments, the second layer 156 is formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, another applicable process, or a combination thereof. The filler layer 158 is also a conductive layer. The filler layer 158 can be a single layer or a multiple layer. In some embodiments, the filler layer 158 is made of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the filler layer 158 is formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic vapor deposition (ALD) process, electroplating, another applicable process, or a combination thereof. Subsequently, as shown in Fig. 5H, according to some embodiments of the disclosure, a section of the gate dielectric layer 152, a section of the second layer 156, and a section of the filler layer 158 are removed. As a result, the upper surface of the filler layer 158 is lower than the upper surface of the gate spacer layer 124. In some embodiments, the upper surface of the filler layer 158 is essentially in the same plane as the upper surface of the second layer 156 and the upper surface of the gate dielectric layer 152. The filler layer 158 has a T-shaped structure. The section of the gate dielectric layer 152, the section of the second layer 156 and the section of the filler layer 158 are removed by an etching process, such as a wet etching process or a dry etching process. There is a third depth D3, measured from the top surface of the second layer 156 to the top surface of the first layer 154. In some embodiments, the third depth D3 is in a range of approximately 1 nm to approximately 20 nm. Subsequently, as shown in Fig. 5I, according to some embodiments of the disclosure, the protective layer 160 is formed on the filler layer 158 and on the second layer 156. The protective layer 160 is formed on the exposed upper surface of the filler layer 158 and the exposed upper surface of the second layer 156. The upper surface of the second layer 156 is in direct contact with the lower surface of the protective layer 160. The upper surface of the filler layer 158 is in direct contact with the lower surface of the protective layer 160. The filler layer 158 is surrounded by the second layer 156 and the protective layer 160. The surface treatment process is used to activate the upper surface of the filler layer 158 and the second layer 156. In some embodiments, the surface treatment process involves the use of hydrogen gas (H₂ gas). When hydrogen gas (H₂ gas) is used, the native metal oxide on the upper surface of layer 158 and the upper surface of the second layer 156 is removed, and hydrogen radicals are then formed on the upper surface. The dielectric gate spacer layer 124 is not reacted with hydrogen. Therefore, the hydrogen radicals are selectively formed on the upper surface of the filler layer 158 and the second layer 156 to facilitate the formation of the protective layer 160. The protective layer 160 is then formed by a deposition process. This process involves introducing a precursor only onto the upper surface of the filler layer 158 and the upper surface of the second layer 156, but not onto the dielectric gate spacer layer 124. In some embodiments, the precursor contains tungsten-containing material (W-containing material), such as tungsten hexafluoride (WF6) or tungsten hexachloride (WCl6). The precursor reacts with the hydrogen radicals to form the protective layer 160. The protective layer 160 is used as an etch stop layer to protect the underlying layers. Additionally, the protective layer 160 has a low gate resistance (Rg). If the protective layer 160 is too thin or not properly formed, its protective effect will be insufficient. It should be noted that the protective layer 160 is selectively formed on conductive material (such as the filler layer 158 and the second layer 156), but not on the insulating material (e.g., the gate dielectric layer 152). In some embodiments, the first layer 154 contains a silicon-containing material, an aluminum-containing material, or a combination thereof. In some embodiments, the protective layer 160 is not formed on the first layer 154 because the material of the first layer 154 is easily oxidized to become insulating (e.g., a metal oxide layer). Since the protective layer 160 is not formed on the first layer 154, if the first layer 154 is exposed after the process of Fig. 5H, the exposed first layer will be etched or damaged by the subsequent etching processes (to create an opening to form a contact structure). The first layer 154 is not exposed and is covered by the second layer 156 and the filler layer 158. The formation quality of the protective layer 160 is improved by using the filler layer 158 between the first layer 154 and the protective layer 160. Additionally, the protective layer 160 is separated from the first layer 154 by the second layer 156 and the filler layer 158. The filler layer 158 is separated from the first layer 154 by the second layer 156. The protective layer 160 has a first thickness T1. In some embodiments, the first thickness T1 is in a range of approximately 1 nm to approximately 20 nm. If the thickness is too small, the protective effect is insufficient. If the thickness is too large, the final gate height is too high, resulting in a large gate-to-source capacitance, which leads to a degradation of the alternating current (AC) performance of the device. Subsequently, as shown in Fig. 5J, according to some embodiments of the disclosure, the insulating layer 162 is formed in the groove 143 and on the protective layer 160 and on the gate dielectric layer 152. The insulating layer 162 has a protruding section in direct contact with the gate dielectric layer 152. In some embodiments, the insulating layer 162 is made of SiO2, Si3N4, SiON, SiOCN, SiOCH, or another applicable material. In some embodiments, the insulating layer 162 is formed by a chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, spin-on coating process, or other applicable processes. Subsequently, as shown in Fig. 5K, according to some embodiments of the disclosure, an etch stop layer 164 and a second dielectric layer 166 are formed on the gate spacer layer 124 and the insulating layer 162. An opening (not shown) is formed through the second dielectric layer 166, the etch stop layer 164, and the insulating layer 162, and then a barrier layer 168 and a conductive layer 170 are formed in the opening. A gate contact structure 172 has a U-shaped barrier layer 168 and the conductive layer 170, and the U-shaped barrier layer 168 is in direct contact with the protective layer 160. The gate contact structure 172 extends through the insulating layer 162, the etch stop layer 164, and the second dielectric layer 166. The gate contact structure 172 is electrically connected to the gate structure 150 through the protective layer 160. In some embodiments, the barrier layer 168 is made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), cobalt tungsten (CoW), or another applicable material. In some embodiments, the barrier layer 168 is made of Ti / TiN / W, and the tungsten (W) in the barrier layer 168 has a smaller grain size than the grain size of the conductive layer 170 when the conductive layer 168 is made of tungsten (W). In some embodiments, the barrier layer 168 is formed by a deposition process, such as a chemical vapor deposition process (CVD process), physical vapor deposition process (PVD process), atomic layer deposition process (ALD process), plating process or other deposition process. In some embodiments, the conductive layer 170 is made of tungsten (W), cobalt (Co), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), platinum (Pt), molybdenum (Mo), silver (Ag), manganese (Mn), zirconium (Zr), ruthenium (Ru), or another deposit material. In some embodiments, the conductive layer 170 is formed by a deposition process, such as a chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, plating process, or other deposition process. If there is no protective layer over the gate structure 150 when the opening is formed by the insulating layer 162, the gate structure 150 can be damaged. The protective layer provides an etch-stop function to protect the underlying gate structure 150 from damage. Since the protective layer 160 might not form on the first layer 154, the first layer 154 is separated from the protective layer 160 by the second layer 156 and the filler layer 158. The protective layer 160 is not in direct contact with the first layer 154 to ensure the quality of the protective layer 160's formation. It should be noted that the protective layer 160 is formed on the second layer 156 and the filler layer 158 to provide sufficient protection to prevent damage to the underlying gate structure 150 from an etching process. In some embodiments, the first width of the lower surface of the protective layer 160 is greater than the second width of the upper surface of the filler layer 158. The protective layer 160 is intended not only to provide protection but also to reduce the gate resistance (Rg). Therefore, the performance of the semiconductor device structure 100a is improved. Figures 6A-6C show cross-sectional views of various stages for forming a semiconductor device structure 100b according to some unclaimed embodiments of the disclosure. Processes and materials used to form the semiconductor device structure 100b may be similar to or identical with those used to form the semiconductor device structure 100a and are not repeated here. Fig. 6A is similar to Fig. 5G, the difference being that the second layer 156 in Fig. 6A is thicker than the second layer 156 in Fig. 5G. The second layer 156 has a bottom section and a side wall section, and the bottom section is in direct contact with the first layer 154. The bottom section is thicker than the side wall section. Subsequently, as shown in Fig. 6B, according to some unclaimed embodiments of the disclosure, a section of the gate dielectric layer 152, a section of the second layer 156, and a section of the filler layer 158 are removed. The filler layer 158 has a rectangular structure. Then, as shown in Fig. 6C, the gate contact structure 172 is formed on the protective layer 160. The gate contact structure 172 is electrically connected to the gate structure 150 via the protective layer 160. The protective layer 160 is separated from the first layer 154 by the second layer 156 and the filler layer 158. Figures 7A-7E show cross-sectional views of various stages for forming the semiconductor device structure 100c according to some unclaimed embodiments of the disclosure. Processes and materials used to form the semiconductor device structure 100c may be similar to or identical with those used to form the semiconductor device structure 100a and are not repeated here. As shown in Fig. 7A, according to some embodiments of the disclosure, the gate dielectric layer 152 is formed in the trench 143, and the first layer 154 is formed over the gate dielectric layer 152. Additionally, the hard mask layer 155 is formed on a section of the first layer 154. The hard mask layer 155 has a first section formed in the trench 143 and a second section over the gate dielectric layer 154. In some embodiments, the hard mask layer 155 is made of Ti, TiN, W, TaN, WN, or other applicable materials. In some embodiments, the hard mask layer 155 is formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, another applicable process, or a combination thereof. Then, as shown in Fig. 7B, according to some embodiments of the disclosure, the dummy layer 153 is formed in the trench 143 and above the first section of the hard mask layer 155. The dummy layer 153 is used to protect the underlying layers. Subsequently, as shown in Fig. 7C, according to some embodiments of the disclosure, a section of the hard mask layer 155 is removed. In particular, the second section of the hard mask layer 155 above the gate spacer layer 124 is removed. The first section of the hard mask layer 155 remains, as it is covered by the dummy layer 153. The dummy layer 153 is then removed by an etching process, such as a wet etching process or a dry etching process. Subsequently, as shown in Fig. 7D, according to some embodiments of the disclosure, a section of the first layer 154 is removed using the hard mask layer 155 as a mask. As a result, a section of the gate dielectric layer 154 is exposed. The first layer 154 has a U-shaped structure, and the hard mask layer 155 is formed in the recessed section of the U-shaped structure. Subsequently, as shown in Fig. 7E, the hard mask layer 155 is removed according to some embodiments of the disclosure. As a result, the first layer 154 has a U-shaped structure. The semiconductor device structure of Fig. 7E then undergoes the processes of Figs. 5G-5K or 6A-6C to obtain the semiconductor device structure 100c. The semiconductor device structure 100c is the same as or similar to the semiconductor device structure 100a or semiconductor device structure 100b. Figures 8A-8I show cross-sectional views of various stages for forming a semiconductor device structure 100d according to some embodiments of the invention as disclosed. Processes and materials used to form the semiconductor device structure 100d may be similar to or identical with those used to form the semiconductor device structure 100a and are not repeated here. As shown in Fig. 8A, according to some embodiments of the disclosure, the gate dielectric layer 152, the second layer 156, and the first layer 154 are formed successively in the trench 143. It should be noted that the first layer 154 is formed after and above the second layer 156. The trench 143 is not completely filled with the first layer 154. Then, as shown in Fig. 8B, according to some embodiments of the disclosure, the hard mask layer 155 is formed on the first layer 154. Then, as shown in Fig. 8C, according to some embodiments of the disclosure, a section of the second layer 156 and a section of the first layer 154 are removed using the hard mask layer 155 as a mask. The upper surface of the first layer 154 is essentially in the same plane as the upper surface of the second layer 156. The upper surface of the first layer 154 and the upper surface of the second layer 156 are essentially in the same plane as the upper surface of the hard mask layer 155. Then, as shown in Fig. 8D, the hard mask layer 155 is removed according to some embodiments of the disclosure. As a result, the first layer 154 and the second layer 156, respectively, have a U-shaped structure. The upper surface of the first layer 154 is in the same plane as the upper surface of the second layer 156. There is a fourth depth D4, measured from the upper surface of the second layer 156 to the lower surface of the second layer 156. In some embodiments, the fourth depth D4 is in a range of about 1 nm to about 10 nm. Then, as shown in Fig. 8E, the filling layer 158 is formed on the first layer 154 and the second layer 156 according to the invention. Subsequently, as shown in Fig. 8F, according to some embodiments of the disclosure, a section of the filler layer 158 and a section of the gate dielectric layer 154 are removed. As a result, the upper surface of the gate dielectric layer 152 is lower than the upper surface of the gate spacer layer 124, and the upper surface of the gate dielectric layer 152 is substantially in the same plane as the upper surface of the filler layer 158. Additionally, the upper surface of the filler layer 158 is higher than the upper surface of the first layer 152 and the upper surface of the second layer 156. The upper surface of the first layer 154 is covered by the filler layer 158. The filler layer 158 has a T-shaped structure with an upper horizontal section and a lower vertical section. The upper horizontal section has a second thickness T2. In some embodiments, the second thickness T2 is in a range of approximately 2 nm to approximately 20 nm. Then, as shown in Fig. 8G, according to some embodiments of the disclosure, the protective layer 160 is formed over the filler layer 158. The protective layer is formed selectively on the filler layer 158, but not on the gate dielectric layer 152. The protective layer 160 is not in direct contact with the first layer 154. The protective layer 160 is separated from the first layer 154 by the filler layer 158. Subsequently, as shown in Fig. 8H, according to some embodiments of the disclosure, the insulating layer 162 is formed on the gate dielectric layer 152 and the protective layer 160. The insulating layer 162 has a protruding section in direct contact with the side wall of the protective layer 160. Then, as shown in Fig. 8I, according to some embodiments of the disclosure, the gate contact structure 172 is formed on the protective layer 160. The gate contact structure 172 is electrically connected to the gate structure 150 through the protective layer 160. In some embodiments, a first width of the lower surface of the protective layer 160 is equal to a second width of the upper surface of the filler layer 158. Figures 9A-9E show cross-sectional views of various stages for forming a semiconductor device structure 100e according to some unclaimed embodiments of the disclosure. Processes and materials used to form the semiconductor device structure 100d may be similar to or identical with those used to form the semiconductor device structure 100a and are not repeated here. Fig. 9A is similar to Fig. 5A, the first layer 152 is formed over the gate dielectric layer 152 and the first layer 152 has a U-shaped structure. As shown in Fig. 9B, according to some embodiments of the disclosure, the filling layer 158 is formed above the first layer 152 and in the trench 143. As shown in Fig. 9C, according to some embodiments of the disclosure, a section of the filler layer 158 and a section of the gate dielectric layer 152 are removed. The section of the filler layer 158 and the section of the gate dielectric layer 152 are removed by an etching process, such as the dry etching process or the wet etching process. As shown in Fig. 9D, according to some embodiments of the disclosure, the protective layer 160 is selectively formed over the filler layer 158. The protective layer 160 is separated from the first layer 152 by the filler layer 158. The insulating layer 162 is formed over the protective layer 160 and is in direct contact with the gate dielectric layer 152. As shown in Fig. 9E, according to some embodiments of the disclosure, the gate contact structure 172 is formed above the gate structure 150. There is no second layer between the first layer 152 and the filler layer 158, but the first layer 152 is not in direct contact with the protective layer 160. The filler layer 158 covers the upper surface of the first layer 152 and is in direct contact with the protective layer 160. In particular, the upper surface of the filler layer 158 is in direct contact with the lower surface of the protective layer 160. Therefore, the protective layer 160 is selectively formed on the second layer 126 or the filler layer 158, but not on the first layer 152. The first layer 152 is covered by the second layer 156 or the filler layer 158. Therefore, the quality of the protective layer 160 can be improved. It should be noted that the protective layer 160 is in direct contact with the second layer 156 and the filler layer 158 in the semiconductor device structures 100a, 100b, and 100c. In the semiconductor device structures 100d and 100e, the protective layer 160 is in direct contact with the filler layer 158. Inventive embodiments for forming a semiconductor device structure and methods for forming the same are provided. According to the invention, the semiconductor structure comprises a gate structure formed over a fin structure. An electrically conductive protective layer is formed over the gate structure. The gate structure comprises a first layer, a second layer, and a filler layer. The first layer is separated from the protective layer by the filler layer. The protective layer is selectively formed on the filler layer to provide protection against etching or damage to the gate structure. Therefore, the performance of the semiconductor device structure is improved. In embodiments according to the invention, a semiconductor device structure is provided. The semiconductor device structure comprises a fin structure formed over a substrate and a gate structure formed over the fin structure. The gate structure comprises a first layer and a filler layer above the first layer. The gate structure comprises a protective layer formed over the filler layer of the gate structure, and the protective layer is separated from the first layer by the filler layer. In embodiments according to the invention, a semiconductor device structure is provided. The semiconductor device structure has a fin structure formed over a substrate, and the fin structure comprises several nanostructures. The semiconductor device structure has a gate structure formed over an uppermost nanostructure. The gate structure has a gate dielectric layer formed over the uppermost nanostructure and a first conductive layer formed over the gate dielectric layer. A second conductive layer is formed over the gate dielectric layer, and there is a filler layer over the first and second conductive layers. The semiconductor device structure has a protective layer formed over the filler layer and an insulating layer formed over the protective layer.The insulating layer has a protruding section in direct contact with the gate dielectric layer. According to the invention, a method for forming a semiconductor device structure is provided. The method comprises forming a fin structure over a substrate and forming a dummy gate structure over the fin structure. The method includes forming a dielectric layer over the gate structure and removing the dummy gate structure to form a trench in the dielectric layer. The method also includes forming a gate dielectric layer in the trench and forming a first layer over the gate dielectric layer. The method further comprises forming a filler layer over the first layer and forming a protective layer over the filler layer. The protective layer is separated from the first layer by the filler layer.

Claims

Semiconductor device structure (100d) comprising: a fin structure (110) formed over a substrate (102); a gate structure (150) formed over the fin structure (110), the gate structure (150) comprising: - a gate dielectric layer (152); - a first layer (154); and - a filler layer (158) over the first layer (154); and an electrically conductive protective layer (160) formed above the filler layer (158) of the gate structure (150), wherein the protective layer (160) is separated from the first layer (154) by the filler layer (158), wherein a first width of a lower surface of the protective layer (160) is equal to a second width of an upper surface of the filler layer (158), and a second layer (156) formed below the first layer (154), wherein the filler layer (158) is formed on the first layer (154) and the second layer (156), and wherein the first layer (154) and the second layer (156) have a U-shaped structure. Semiconductor device structure (100d) according to claim 1, wherein the fin structure (110) comprises multiple nanostructures. Semiconductor device structure (100d) according to claim 1 or 2, wherein the protective layer (160) is not in direct contact with the first layer (154). Semiconductor device structure (100d) according to one of claims 1 to 3, wherein the filler layer (158) is surrounded by the first layer (154), the second layer (156), the protective layer (160) and the gate dielectric layer (152). Semiconductor device structure (100d) according to one of the preceding claims, further comprising: an insulating layer (162) formed over the protective layer (160), wherein the insulating layer (162) is in direct contact with a side wall of the protective layer (160). Semiconductor device structure (100d) according to one of the preceding claims, wherein the first layer (154) is formed from a Si-containing material, an Al-containing material or a combination thereof. Semiconductor device structure (100d) according to one of the preceding claims, wherein the filler layer (158) has a T-shaped structure. Semiconductor device structure (100d) according to one of the preceding claims, wherein the protective layer (160) is not formed on the gate dielectric layer (152). Semiconductor device structure (100d) comprising: a fin structure (110) formed over a substrate (102), the fin structure (110) comprising multiple nanostructures; a gate structure (150) formed over a top nanostructure of the nanostructures, the gate structure (150) comprising: - a gate dielectric layer (152) formed over the top nanostructure of the nanostructures; - a first conductive layer (154) formed over the gate dielectric layer (152); - a second conductive layer (156) formed over the gate dielectric layer (152) and below the first conductive layer (154); and - a filler layer (158) on the first conductive layer (154) and the second conductive layer (156); a protective layer (160) formed over the filler layer (158);and an insulating layer (162) formed over the protective layer (160), wherein the insulating layer (162) has a protruding section that is in direct contact with the gate dielectric layer (152), wherein the first layer (154) and the second layer (156) have a U-shaped structure. Semiconductor device structure (100d) according to claim 9, wherein the protective layer (160) is separated from the first conductive layer (154) by the filler layer (158). Semiconductor device structure (100d) according to claim 9 or 10, further comprising: a gate contact structure (172) formed above the protective layer (160), wherein the gate contact structure (172) is electrically connected to the gate structure (150) through the protective layer (160). Semiconductor device structure (100d) according to one of claims 9 to 11, wherein the protective layer (160) is not formed on the gate dielectric layer (152). Semiconductor device structure (100d) according to one of claims 9 to 12, wherein an upper surface of the second conductive layer (156) lies in a plane with an upper surface of the first conductive layer (154). A method for forming a semiconductor device structure (100d), comprising: forming a fin structure (110) over a substrate (102); forming a dummy gate structure (120) over the fin structure (110); forming a dielectric layer over the gate structure (120); removing the dummy gate structure (120) to form a trench in the dielectric layer; forming a gate dielectric layer (152) in the trench; forming a second layer (156) over the gate dielectric layer (152); forming a first layer (154) over the second layer (156); forming a filler layer (158) on the first layer (154) and the second layer (156); forming a protective layer (160) over the filler layer (158), wherein the protective layer (160) is separated from the first layer (154) by the filler layer (158), wherein the first layer (154) and the second layer (156) have a U-shaped structure. Method for forming the semiconductor device structure (100d) according to claim 14, wherein the fin structure (110) comprises several first semiconductor layers and several second semiconductor layers, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately, wherein the method further comprises: removing the second semiconductor layers to form a gap (145), wherein the gate dielectric layer is formed in the gap (145). Method for forming the semiconductor device structure (100d) according to one of claims 14 to 15, further comprising: selectively forming the protective layer (160) on the filler layer (158), wherein the protective layer (160) is not formed on the gate dielectric layer (152).

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