Power semiconductor device

By dividing the power semiconductor device into cell and terminal regions with specific insulating layers and electrodes, and using a semi-insulating layer with controlled contact area, the device addresses charge carrier concentration variations, maintaining dielectric strength and reducing leakage current.

DE102021124741B4Active Publication Date: 2026-05-28MITSUBISHI ELECTRIC CORP
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
MITSUBISHI ELECTRIC CORP
Filing Date
2021-09-24
Publication Date
2026-05-28

AI Technical Summary

Technical Problem

The semi-insulating layer in power semiconductor devices causes variations in charge carrier concentration, inhibiting depletion layer propagation and reducing dielectric strength due to fixed charges.

Method used

The power semiconductor device is divided into a cell region and a terminal region, with a specific configuration of insulating layers and electrodes, and a semi-insulating layer that reduces contact area with the semiconductor base, using materials like silicon nitride and forming methods like plasma-CVD to suppress variations in charge carrier concentration.

Benefits of technology

This configuration suppresses variations in charge carrier concentration and maintains dielectric strength stability, reducing leakage current and ensuring dielectric strength.

✦ Generated by Eureka AI based on patent content.

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Abstract

Power semiconductor device comprising a cell region (1) and a terminal region (2) surrounding the cell region (1) in a top view: a semiconductor base (11) having a first principal surface (S1); a first insulating layer (5) which is formed on the first main surface (S1) in an inner circumferential end part region of the connection area (2); a second insulating layer (15) which is formed on the first main surface (S1) in an outer circumferential end part region of the connection area (2); a first electrode (10) formed on the first main surface (S1) and the first insulating layer (5) in the cell area (1); a second electrode (9) formed on the first main surface (S1) and the second insulating layer (15) in the outer circumferential end region of the connection area (2); and a semi-insulating layer (8) that has contact with the first electrode (10), the second electrode (9), the first insulating layer (5) and the second insulating layer (15) and has contact with the first main surface (S1) between the first insulating layer (5) and the second insulating layer (15), wherein the semiconductor base layer (11) has: a semiconductor substrate (3) of a first conductivity type; and one or more separate first diffusion layers (4) of a second conductivity type, which are formed on a surface layer on one side of the first main surface (S1) of the semiconductor substrate (3) in the connection area (2), the semiconductor base (11) further comprises at least one third insulating layer (25) formed on the first main surface (S1) of the semiconductor base (11) between the first insulating layer (5) and the second insulating layer (15), the semi-insulating layer (8) has contact with the third insulating layer (25) on the third insulating layer (25) and has contact with the first main surface (S1) in at least two areas where the third insulating layer (25) is not formed between the first insulating layer (5) and the second insulating layer (15), and a ratio of a contact area between the semi-insulating layer (8) and the first main surface (S1) of the semiconductor base (11) in the terminal area (2) to a distance from an inner circumferential end region of one of the one or more first diffusion layers (4) located in an innermost circumference of the terminal area (2) to an inner circumferential end region of the second electrode (9) is equal to or greater than 15% and equal to or less than 50%.
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Citation Information

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