Semiconductor device

Abstract

A semiconductor device (101) has a gate electrode embedded in each of a plurality of first trenches via an insulating film. The gate electrode comprises a first gate electrode (12) electrically connected to a first gate pad (30) and a second gate electrode (15) electrically connected to a second gate pad (31). A charge period and a discharge period of a gate capacitance parasitic at the second gate electrode (15) are shorter than a charge period and a discharge period of a capacitance parasitic at the first gate electrode (12), respectively.

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to a semiconductor device. Description of the background technology

[0002] Japanese Patent No. 5742672 discloses a semiconductor device in which a first gate electrode and a second gate electrode are arranged on a semiconductor substrate. In the semiconductor device described in Japanese Patent No. 5742672, at the time of turn-off, the second gate electrode is turned off earlier than the first gate electrode, and at the time of turn-on, the second gate electrode is turned on later than the first gate electrode. This reduces switching loss.

[0003] The semiconductor device described in Japanese Patent No. 5742672 does not consider that a parasitic gate capacitance at the second gate electrode is charged and discharged at a high rate. For this reason, there is a problem that a period during which the on-voltage is low is short and a conduction loss is large. Specifically, when the second gate electrode is turned on, an n-type accumulation layer is formed around the second gate electrode, and the accumulation layer serves as a hole barrier, so that the hole density in a drift layer can be increased to reduce the on-voltage. When the charge-discharge time of the second gate electrode is long, the period during which the second gate electrode is in an on-state is shortened, and there is a problem that the conduction loss deteriorates. SUMMARY

[0004] An object of the technology of the present disclosure is to improve the conduction loss in the semiconductor device having the first gate electrode and the second gate electrode.

[0005] A semiconductor device of the present disclosure includes a semiconductor substrate, an upper surface electrode, a lower surface electrode, a first gate pad, and a second gate pad. The semiconductor substrate has a first main surface and a second main surface opposite the first main surface. The upper surface electrode is formed on the first main surface of the semiconductor substrate. The lower surface electrode is formed on the second main surface of the semiconductor substrate. The second gate pad is controlled independently of the first gate pad. The semiconductor substrate has a drift layer of a first conductivity type, a base layer of a second conductivity type, a source layer of a first conductivity type, and a plurality of first trenches.The base layer is formed on the first main surface side of the drift layer. The source layer is formed on the first main surface side of the base layer. The plurality of first trenches penetrate the base layer from the source layer to reach the drift layer. The semiconductor device includes a gate electrode embedded in each of the plurality of first trenches via an insulating film. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode is electrically connected to the first gate pad. The second gate electrode is electrically connected to the second gate pad. A charging period and a discharging period of a parasitic gate capacitance at the second gate electrode are shorter than a charging period and a discharging period of a parasitic gate capacitance at the first gate electrode, respectively.

[0006] According to the semiconductor device of the present disclosure, the charge-discharge period of the parasitic gate capacitance at the second gate electrode is shorter than the charge-discharge period of the parasitic gate capacitance at the first gate electrode. Accordingly, the on-period of the second gate electrode can be extended. As a result, the period during which the on-voltage is low becomes longer, and the conduction loss is improved.

[0007] These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a semiconductor device according to a first preferred embodiment; Fig. 2 is a line AA in Fig. 1 is a sectional view illustrating the semiconductor device according to the first preferred embodiment; Fig. 3 is a view illustrating a timing of driving the semiconductor device; Fig. 4 is a sectional view illustrating a semiconductor device according to a first modification of the first preferred embodiment; Fig. 5 is a sectional view illustrating a semiconductor device according to a second modification of the first preferred embodiment; Fig. 6 is a sectional view illustrating a semiconductor device according to a third modification of the first preferred embodiment; Fig. 7 is a sectional view illustrating a semiconductor device according to a second preferred embodiment; Fig. 8 is a sectional view illustrating a semiconductor device according to a third preferred embodiment; Fig. 9 is a sectional view illustrating a semiconductor device according to a first modification of the third preferred embodiment; Fig. 10 is a sectional view illustrating a semiconductor device according to a second modification of the third preferred embodiment; Fig. 11 is a sectional view illustrating a semiconductor device according to a third modification of the third preferred embodiment; Fig. 12 is a sectional view illustrating a semiconductor device according to a fourth modification of the third preferred embodiment; Fig. 13 is a sectional view illustrating a semiconductor device according to a fifth modification of the third preferred embodiment; Fig. 14 is a sectional view illustrating a semiconductor device according to a sixth modification of the third preferred embodiment; Fig. 15 is a sectional view illustrating a semiconductor device according to a fourth preferred embodiment; Fig. 16 is a sectional view illustrating a semiconductor device according to a first modification of the fourth preferred embodiment; Fig. 17 is a plan view illustrating a semiconductor device according to a fifth preferred embodiment; Fig. 18 is a plan view illustrating a semiconductor device according to a first modification of the fifth preferred embodiment; Fig. 19 is a plan view illustrating a semiconductor device according to a sixth preferred embodiment; Fig. 20 is a line BB in Fig. 19 is a sectional view illustrating the semiconductor device according to the sixth preferred embodiment; Fig. 21 is a view illustrating a timing of driving the semiconductor device according to the sixth preferred embodiment; Fig. 22 is a sectional view illustrating a semiconductor device according to a first modification of the sixth preferred embodiment; Fig. 23 is a sectional view illustrating a semiconductor device according to a seventh preferred embodiment; Fig. Fig. 24 is a view illustrating a timing of driving the semiconductor device according to the seventh preferred embodiment; and Fig. 25 is a sectional view illustrating a semiconductor device according to a first modification of the seventh preferred embodiment; DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following description, the symbols n and p represent a conductivity type of a semiconductor. In the present disclosure, a first conductivity type is n-type, and a second conductivity type is p-type. However, the first conductivity type may be p-type, and the second conductivity type may be n-type. In addition, (n-) indicates that an impurity concentration is lower than n, and (n+) indicates that the impurity concentration is higher than n. Similarly, (p-) indicates that the impurity concentration is lower than p, and (p+) indicates that the impurity concentration is higher than p. <A. Erste bevorzugte Ausführungsform><A-1. Konfiguration>

[0009] Fig. 1 is a plan view illustrating a semiconductor device 101 according to a first preferred embodiment. However, in Fig. 1 an interlayer insulating film 2 and an emitter electrode 1 are not illustrated. Fig. 2 is a line AA in Fig. 1, illustrating the semiconductor device 101. The semiconductor device 101 forms an insulated gate bipolar transistor (IGBT).

[0010] As in Fig. As illustrated in FIG. 2, the semiconductor device 101 includes a semiconductor substrate 60. The semiconductor substrate 60 has a first main surface S1 and a second main surface S2, which is a main surface opposite the first main surface S1. The semiconductor substrate 60 includes an n+-type source layer 3, a p-type base layer 4, an n-type carrier accumulation layer 5, an n-type drift layer 6, an n-type buffer layer 7, and a p-type collector layer 8. The n-type carrier accumulation layer 5 is disposed on one side of the first main surface S1 of the n-type drift layer 6. The p-type base layer 4 is disposed on the side of the first main surface S1 of the n-type carrier accumulation layer 5. The (n+)-type source layer 3 is arranged on the side of the first main surface S1 of the p-type base layer 4.The n-type buffer layer 7 is arranged on the second main surface S2 side of the n-type drift layer 6. The p-type collector layer 8 is arranged on the second main surface S2 side of the n-type buffer layer 7.

[0011] A plurality of trenches 10 are formed, which penetrate from an upper surface of the n+-type source layer 3 through the n+-type source layer 3, the p-type base layer 4, and the n-type carrier accumulation layer 5 to reach the n-type drift layer 6. The plurality of trenches 10 extend as shown in Fig. 1 illustrates the same direction. Although in Fig. 1 four trenches 10 are illustrated, the number of trenches 10 is not limited to four.

[0012] Although in Fig. 2, a p+-type contact layer is also disposed on the p-type base layer 4. The n+-type source layer 3 and the p+-type contact layer are alternately disposed along an extension direction of each trench 10. The n+-type source layer 3 is a semiconductor layer containing, for example, arsenic or phosphorus as impurities or n-type impurities, respectively. The concentration of the n-type impurity in the n+-type source layer 3 is greater than or equal to 1.0 × 10 17 / cm 3 and less than or equal to 1.0 × 10 20 / cm 3 The p+-type contact layer is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p+-type contact layer is greater than or equal to 1.0 × 10 15 / cm 3 and less than or equal to 1.0 × 10 20 / cm 3 .

[0013] The n-type drift layer 6 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity. The concentration of the n-type impurity in the n-type drift layer 6 is greater than or equal to 1.0 × 10 12 / cm 3 and less than or equal to 1.0 × 10 15 / cm 3 .

[0014] The n-type carrier accumulation layer 5 is a semiconductor layer containing, for example, arsenic or phosphorus as n-type impurities. The concentration of the n-type impurity in the n-type carrier accumulation layer 5 is greater than or equal to 1.0 × 10 13 / cm 3 and less than or equal to 1.0 × 10 17 / cm 3However, the n-type carrier accumulation layer 5 is not an essential configuration or structure in the semiconductor device 101, and the p-type base layer 4 may be directly disposed on the n-type drift layer 6. The n-type carrier accumulation layer 5 reduces excitation loss when current flows. In the present description, the n-type carrier accumulation layer 5 and the n-type drift layer 6 may be referred to collectively as the drift layer.

[0015] The p-type base layer 4 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type base layer 4 is greater than or equal to 1.0 × 10 12 / cm 3 and less than or equal to 1.0 × 10 19 / cm 3The p-type base layer 4 is in contact with a first gate insulating film 11 of the trench 10. On the first main surface S1 side of the p-type base layer 4, the n+-type source layer 3 is disposed in contact with the first gate insulating film 11, and the p+-type contact layer is disposed in a remaining region. The n+-type source layer 3 and the p+-type contact layer constitute the first main surface of the semiconductor substrate. The p+-type contact layer is a region having a higher concentration of the p-type impurity than that of the p-type base layer 4. In the present specification, the p+-type contact layer and the p-type base layer 4 may sometimes be referred to collectively as the p-type base layer.

[0016] The n-type buffer layer 7 is a semiconductor layer having a higher concentration of n-type impurities than that of the (n-)-type drift layer 6. The n-type buffer layer 7 is provided to suppress punch-through through a depletion layer extending from the p-type base layer 4 toward the second main surface S2 side when the semiconductor device 101 is in an off-state. The n-type impurity in the n-type buffer layer 7 is, for example, phosphorus (P) and / or protons (H+). The concentration of the n-type impurity in the n-type buffer layer 7 is greater than or equal to 1.0 × 10 12 / cm 3 and less than or equal to 1.0 × 10 18 / cm 3The n-type buffer layer 7 is not an essential configuration or structure in the semiconductor device 101, and the p-type collector layer 8 may be directly disposed on the second main surface S2 side of the n-type drift layer 6. In the present description, the n-type buffer layer 7 and the n-type drift layer 6 may sometimes be referred to collectively as the drift layer.

[0017] The p-type collector layer 8 is disposed on the second main surface S2 side of the n-type buffer layer 7. That is, the p-type collector layer 8 is disposed between the n-type drift layer 6 and the second main surface S2. The p-type collector layer 8 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity in the p-type collector layer 8 is greater than or equal to 1.0 × 10 16 / cm 3and less than or equal to 1.0 × 10 20 / cm 3 . The p-type collector layer 8 configures or forms the second surface of the semiconductor substrate.

[0018] A first gate electrode 12 is embedded in some of the plurality of trenches 10 via the first gate insulating film 11. The first gate insulating film 11 is disposed on inner walls of these trenches 10. A second gate electrode 15 is embedded in remaining trenches 10 via a second gate insulating film 14. The second gate insulating film 14 is disposed on the inner walls of these trenches 10. As shown in Fig. As illustrated in Figure 1, the first gate electrode 12 is electrically connected to a first gate pad 30 via a first gate wiring 50. The second gate electrode 15 is electrically connected to a second gate pad 31 via a second gate wiring 51. The timings for turning on and off the first gate pad 30 and the second gate pad 31 are independently controlled by a controller (not illustrated).

[0019] When a gate driving voltage is applied to the first gate electrode 12 via the first gate pad 30, a channel is formed in the p-type base layer 4 in contact with the first gate insulating film 11, and an n-type accumulation layer is formed in the n-type carrier accumulation layer 5 and the (n-) type drift layer 6 in contact with the first gate insulating film 11. Similarly, when the gate driving voltage is applied to the second gate electrode 15 via the second gate pad 31, the channel is formed in the p-type base layer 4 contacting the second gate insulating film 14, and the n-type accumulation layer is formed in the n-type carrier accumulation layer 5 and the (n-) type drift layer 6 contacting the second gate insulating film 14.

[0020] The first gate electrode 12 and the second gate electrode 15 are formed by depositing polysilicon doped with n-type or p-type impurities. An impurity concentration of polysilicon in the first gate electrode 12 is greater than or equal to 1.0 × 10 17 / cm 3 and less than or equal to 1.0 × 10 22 / cm 3 . The impurity concentration of polysilicon in the second gate electrode 15 is higher than the impurity concentration of polysilicon in the first gate electrode 12. As a result, the semiconductor device 101 is characterized in that the resistivity of the second gate electrode 15 is lower than the resistivity of the first gate electrode 12. The impurity concentration of polysilicon in the second gate electrode 15 is, for example, greater than or equal to 1.0 × 10 19 / cm 3 and less than or equal to 1.0 × 10 22 / cm 3and desirably greater than or equal to 1.0 × 10 20 / cm 3 and less than or equal to 1.0 × 10 22 / cm 3 .

[0021] Although two first gate electrodes 12 and two second gate electrodes 15 in Fig. 1, the relationship between the first gate electrode 12 and the second gate electrode 15 is not limited to that shown in Fig. 1. Furthermore, the first gate electrode 12 and the second gate electrode 15 need not be arranged alternately.

[0022] As in Fig. 2, an interlayer insulating film 2 is arranged on the first gate electrode 12 and the second gate electrode 15. Although in Fig. 2, a barrier metal is formed on a region of the first main surface S1 where the interlayer insulating film 2 is not disposed and on the interlayer insulating film 2. For example, the barrier metal is a conductor containing titanium (Ti). The barrier metal is, for example, titanium nitride or TiSi obtained by alloying titanium or silicon (Si). The barrier metal is in ohmic contact with the n+-type source layer 3 and the p+-type contact layer, and is electrically connected to the n+-type source layer 3 and the p+-type contact layer.

[0023] The emitter electrode 1, as the upper surface electrode, is disposed on the barrier metal. For example, the emitter electrode 1 is formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si-based alloy). The emitter electrode 1 may be an electrode composed of a plurality of layers of metal films, in which a plating film is formed on an aluminum alloy film by electroless plating or electrolytic plating. At this point, for example, the plating film may be a nickel (Ni) plating film. If the emitter electrode 1 cannot be satisfactorily embedded in a narrow region such as between the adjacent interlayer insulating films 2, tungsten having better embeddability than the emitter electrode 1 may be disposed in the region, and the emitter electrode 1 may be disposed on the tungsten.

[0024] The emitter electrode 1 can be disposed directly on the n+-type source layer 3 and the p+-type contact layer without providing the barrier metal. Furthermore, the barrier metal can be disposed only on the n-type semiconductor layer, such as the n+-type source layer 3. In this specification, the barrier metal and the emitter electrode 1 may sometimes be referred to collectively as the emitter electrode.

[0025] A collector electrode 9 as a lower surface electrode is arranged on the second main surface S2 side of the p-type collector layer 8. Similar to the emitter electrode 1, the collector electrode 9 may be made of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 9 may have a configuration different from that of the emitter electrode 1. The collector electrode 9 is in ohmic contact with the p-type collector layer 8 and is electrically connected to the p-type collector layer 8. <A-2. Herstellungsprozess>

[0026] A method for manufacturing the semiconductor device 101 of the first preferred embodiment will be described. First, the semiconductor substrate 60 forming the n-type drift layer 6 is prepared. The semiconductor substrate 60 is, for example, a floating-zone FZ wafer manufactured by a zone melting (FZ) method or an MCZ (Magnetic Applied Czochralski) wafer manufactured by an MCZ method, and may be an n-type wafer containing n-type impurities. The semiconductor substrate 60 is, for example, a Si substrate. The concentration of the n-type impurity contained in the semiconductor substrate 60 is appropriately selected depending on the withstand voltage of the manufactured semiconductor device 101.For example, in the case where the semiconductor device 101 is manufactured with a withstand voltage of 1200 V, the concentration of the n-type impurity is adjusted so that a specific resistance of the (n-)-type drift layer 6 constituting the semiconductor substrate 60 is greater than or equal to about 40 Ω cm and less than or equal to 120 Ω cm. In a process for preparing the semiconductor substrate 60, the entire semiconductor substrate 60 is the (n-)-type drift layer 6. By implanting p-type or n-type impurity ions from the first main surface S1 side or the second main surface S2 side of the semiconductor substrate 60 and diffusing the impurity ions into the semiconductor substrate 60 by subsequent heat treatment or the like, the p-type or n-type semiconductor layer is formed to manufacture the semiconductor device 101.

[0027] Next, by implanting n-type impurities such as phosphorus (P) from the first main surface S1 side of the semiconductor substrate 60, the n-type carrier accumulation layer 5 is formed on the first main surface S1 side of the (n-)-type drift layer 6. Furthermore, by implanting p-type impurities such as boron (B) from the first main surface S1 side of the semiconductor substrate 60, the p-type base layer 4 is formed on the first main surface S1 side of the n-type carrier accumulation layer 5. The n-type carrier accumulation layer 5 and the p-type base layer 4 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment.Ions of the n-type impurity and the p-type impurity are implanted after mask processing is performed on the first main surface S1 of the semiconductor substrate 60, so that the n-type impurity and the p-type impurity are selectively formed on the first main surface S1 side of the semiconductor substrate 60. The mask processing is a process for forming a mask on the semiconductor substrate 60 by applying a resist to the semiconductor substrate 60 and forming an opening in a predetermined region of the resist using a photolithography technique. Ion implantation or etching is performed through the opening of the mask in a predetermined region of the semiconductor substrate 60.

[0028] Subsequently, after the mask processing is performed on the first main surface S1 of the semiconductor substrate 60, the n-type impurity is selectively implanted into the first main surface side of the p-type base layer 4 to form the (n+)-type source layer 3. For example, the implanted n-type impurity is arsenic (As) or phosphorus (P). After the mask processing is performed on the first main surface S1 of the semiconductor substrate 60, the p-type impurity is selectively implanted into the first main surface S1 side of the p-type base layer 4 to form the (p+)-type contact layer. For example, the implanted p-type impurity is boron (B) or aluminum (Al).

[0029] Subsequently, a plurality of trenches 10 are formed, penetrating the p-type base layer 4 from the first main surface S1 side of the semiconductor substrate 60 and reaching the n-type drift layer 6. The sidewalls of the plurality of trenches 10 penetrating the n+-type source layer 3 constitute a part of the n+-type source layer 3. After an oxide film such as SiO2 is deposited on the semiconductor substrate 60, mask processing is performed, etching is performed to form an opening in the oxide film at a portion where the trench 10 is formed, and the semiconductor substrate 60 is etched using the oxide film with the opening as a mask, whereby each trench 10 can be formed.

[0030] Subsequently, the semiconductor substrate 60 is heated in an oxygen-containing atmosphere to form the first gate insulating film 11 on the inner wall of the trench 10 and the first main surface S1 of the semiconductor substrate 60. The first gate insulating film 11 formed on the first main surface S1 of the semiconductor substrate 60 is removed in a later process.

[0031] Subsequently, polysilicon doped with the n-type or p-type impurity is deposited in the plurality of trenches 10 by chemical vapor deposition (CVD) or the like to form the first gate electrode 12.

[0032] Next, a mask is formed in which the trench to be filled with the second gate electrodes 15 is opened in the plurality of trenches 10 by the mask processing, and the first gate electrodes 12 are etched in the trench to be filled with the second gate electrodes 15. After that, the first gate insulating film 11 in the trench to be filled with the second gate electrode 15 is removed.

[0033] Thereafter, the semiconductor substrate 60 is heated in the oxygen-containing atmosphere, and the second gate insulating film 14 is formed on the inner wall of the trench to be filled with the second gate electrode 15 and the first main surface S1 of the semiconductor substrate 60. The second gate insulating film 14 formed on the first main surface S1 of the semiconductor substrate is removed in a later process.

[0034] Subsequently, polysilicon doped with the n-type or p-type impurity is deposited in the trench to be filled with the second gate electrode 15 by means of chemical vapor deposition (CVD) or the like to form the second gate electrode 15.

[0035] Subsequently, the interlayer insulating film 2 is formed on the trench 10. After that, the first gate insulating film 11 and the second gate insulating film 14 formed on the first main surface S1 of the semiconductor substrate 60 are removed. For example, the interlayer insulating film 2 is SiO2. A contact hole is then formed in the deposited interlayer insulating film 2 through mask processing. The contact hole is formed on the n+-type source layer 3 and the p+-type contact layer.

[0036] Subsequently, a barrier metal is formed on the first main surface S1 and the interlayer insulating film 2 of the semiconductor substrate 60, and the emitter electrode 1 is further formed on the barrier metal. The barrier metal is formed by depositing titanium nitride using physical vapor deposition (PVD) or CVD.

[0037] For example, the emitter electrode 1 is formed by depositing an aluminum-silicon alloy (Al-Si-based alloy) on the barrier metal by PVD such as sputtering or vapor deposition. Furthermore, a nickel alloy (Ni alloy) may be further formed on the aluminum-silicon alloy by electroless plating or electrolytic plating, and these two alloy layers may be used as the emitter electrode 1. As described above, a thick metal film can be easily formed as the emitter electrode 1 by plating, so that the heat capacity of the emitter electrode 1 can be increased to improve heat resistance. The nickel alloy plating treatment may be performed after the second main surface S2 side of the semiconductor substrate 60 is processed.

[0038] Subsequently, the second main surface S2 side of the semiconductor substrate 60 is ground to thin the semiconductor substrate 60 to a desired thickness. For example, the thickness of the ground semiconductor substrate 60 is greater than or equal to 80 µm and less than or equal to 200 µm.

[0039] Next, the n-type impurity is implanted from the second main surface S2 side of the semiconductor substrate 60 to form the n-type buffer layer 7. Furthermore, the p-type impurity is implanted from the second main surface S2 side of the semiconductor substrate 60 to form the p-type collector layer 8.

[0040] For example, the n-type buffer layer 7 is formed by implanting a phosphorus (P-) ion or a proton (H+), or both. The proton is injected from the second main surface S2 of the semiconductor substrate 60 to a deep position using a relatively low acceleration energy. Furthermore, the proton injection depth can be relatively easily changed by changing the acceleration energy. For this reason, if the proton is injected a plurality of times while changing the acceleration energy, the n-type buffer layer 7 can be formed with a larger width in the thickness direction of the semiconductor substrate 60 than that made of phosphorus.

[0041] Compared with the proton, phosphorus can increase the activation rate as an n-type impurity. Therefore, when the n-type buffer layer 7 is formed with phosphorus, punch-through of the depletion layer can be more reliably prevented even in the thinned semiconductor substrate 60. To further thin the semiconductor substrate 60, the n-type buffer layer 7 is preferably formed by injecting both the proton and phosphorus, and at this time, the proton is injected from the second surface S2 to a position deeper than the phosphorus.

[0042] The p-type collector layer 8 is formed, for example, by injecting boron (B). After ion implantation from the second main surface S2 side of the semiconductor substrate 60, the second main surface S2 is irradiated with a laser to perform laser annealing, so that implanted boron is activated to form the p-type collector layer 8. At this point, phosphorus for the n-type buffer layer 7, implanted in a relatively shallow position from the second main surface S2 of the semiconductor substrate 60, is also simultaneously activated. On the other hand, the proton is activated at a relatively low annealing temperature higher than or equal to 350°C and lower than or equal to 500°C, so care must be taken to ensure that the entire semiconductor substrate 60 does not become hotter than or equal to 350°C, except for a process for activating the proton after the proton injection.Only the vicinity of the second main surface S2 of the semiconductor substrate 60 can be heated to a high temperature, so that laser annealing can be used to activate the n-type impurity or the p-type impurity except the proton after proton injection.

[0043] Subsequently, the collector electrode 9 is formed on the second main surface S2 of the semiconductor substrate 60. The collector electrode 9 may be formed over the entire second main surface S2 of the semiconductor substrate 60. For example, the collector electrode 9 is formed by depositing an aluminum-silicon alloy (Al-Si-based alloy), titanium (Ti), or the like on the second main surface S2 of the semiconductor substrate 60 by means of PVD such as sputtering or vapor deposition. Alternatively, the collector electrode 9 may be formed by laminating a variety of metals such as an aluminum-silicon alloy, titanium, nickel, or gold. In addition, a metal film may be further formed on the metal film formed by PVD by means of electroless plating or electrolytic plating, and these two metal layers may serve as the collector electrode 9.

[0044] Through the above processes, the semiconductor device 101 is manufactured. A plurality of semiconductor devices 101 are formed in a matrix on an n-type wafer. Then, a cutting process is performed by laser dicing or blade dicing to obtain a semiconductor device 101. <A-3. Betrieb>

[0045] Fig. 3 is a view illustrating a timing of driving the semiconductor device 101. In Fig. 3, Vg1 represents the voltage applied to the first gate pad 30 and the first gate electrode 12, and Vg2 represents the voltage applied to the second gate pad 31 and the second gate electrode 15. The controller (not illustrated) controls so that the second gate pad 31 is turned on at a later timing than the first gate pad 30 and the second gate pad 31 is turned off at an earlier timing than the first gate pad 30. That is, the second gate pad 31 is turned on after the first gate pad 30 is turned on, and the first gate pad 30 is turned off after the second gate pad 31 is turned off. A period during which the turning-on of the second gate pad 31 is delayed with respect to the turning-on of the first gate pad 30 is referred to as a delay time. A period during which the turning off of the second gate pad 31 precedes the turning off of the first gate pad 30 is referred to as a lead period.

[0046] In the semiconductor device 101, the specific resistance of the second gate electrode 15 is lower than the specific resistance of the first gate electrode 12, so that a reduction in the gate current in the second gate electrode 15 can be reduced. As a result, the charge-discharge of the parasitic gate capacitance in the second gate electrode 15 can be accelerated. That is, as shown in Fig. As illustrated in Figure 3, the charge period and discharge period of the parasitic gate capacitance at the second gate electrode 15 can be set shorter than the charge period and discharge period of the parasitic gate capacitance at the first gate electrode 12, respectively. Accordingly, the on-period of the second gate electrode 15 becomes longer. When the second gate electrode 15 is turned on, an n-type accumulation layer is formed around the second gate electrode 15. The holes injected from the p-type collector layer 8 are hardly discharged from the emitter electrode 1 because the accumulation layer serves as a hole barrier, and the holes are accumulated in the n-type drift layer 6. As a result, conductivity modulation is promoted, and the on-voltage is reduced. <A-4. Modifikation>

[0047] Fig. Fig. 4 is a sectional view illustrating a semiconductor device 101A according to a first modification of the first preferred embodiment. The plan view of the semiconductor device 101A is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 4 is a sectional view of the semiconductor device 101A taken along the line AA in Fig. 1. In the semiconductor device 101A, the (n+)-type source layer 3 is in contact with the first gate insulating film 11, but not in contact with the second gate insulating film 14. The configuration of the semiconductor device 101A except for the (n+)-type source layer 3 is similar to that of the semiconductor device 101.

[0048] Fig. Fig. 5 is a sectional view illustrating a semiconductor device 101B according to a second modification of the first preferred embodiment. The plan view of the semiconductor device 101B is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 5 is a sectional view of the semiconductor device 101B taken along the line AA in Fig. 1. In the semiconductor device 101B, a trench emitter electrode 17 is embedded in some of the trenches 10 via an insulating film 16. That is, the semiconductor device 101B includes the trench 10 in which the first gate electrode 12 is embedded, the trench 10 in which the second gate electrode 15 is embedded, and the trench 10 in which the trench emitter electrode 17 is embedded. The trench emitter electrode 17 is electrically connected to the emitter electrode 1.

[0049] As in Fig. As illustrated in Figure 5, in the semiconductor device 101B, the semiconductor region adjacent to the second gate insulating film 14 may be insulated from the emitter electrode 1 by the interlayer insulating film 2 and need not be electrically connected to the emitter electrode 1. The remaining configurations of the semiconductor device 101B are similar to those of the semiconductor device 101.

[0050] Fig. Fig. 6 is a sectional view illustrating a semiconductor device 101C according to a third modification of the first preferred embodiment. The plan view of the semiconductor device 101C is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 6 is a sectional view of the semiconductor device 101C taken along the line AA in Fig. 1.

[0051] Semiconductor device 101C forms a reverse conducting IGBT (RC-IGBT). In semiconductor device 101C, an n-type cathode layer 21 is disposed on the second main surface S2 side of n-type buffer layer 7 in addition to p-type collector layer 8. The configuration of semiconductor device 101C, except for n-type cathode layer 21, is similar to that of semiconductor device 101.

[0052] According to the semiconductor device 101C, the electron is injected by turning on the second gate electrode 15 for a short time before a diode recovery operation, and the hole in the (n-)-type drift layer 6 can be reduced by recombination, so that recovery loss can be reduced. If the charge discharge of the second gate electrode 15 is slow, the electron injection becomes too large, and a snapback phenomenon is generated in which the current does not flow at a predetermined voltage. However, in this configuration, the charge discharge can be accelerated, so that the amount of electron injection when the second gate electrode 15 is turned on can be reduced to prevent the snapback phenomenon.

[0053] The semiconductor device 101 of the first preferred embodiment constitutes the IGBT. However, the semiconductor device 101 may not include the p-type collector layer 8 and may constitute a metal-oxide-semiconductor field-effect transistor (MOSFET). As an effect contributing to the unipolar MOSFET, a parasitic gate capacitance in the first gate electrode 12 can be shared by the second gate electrode 15, and the effective gate capacitance at the time of turn-on can be reduced, thus reducing switching loss. Furthermore, the charge-discharge of the second gate electrode 15 can be accelerated so that a period during which the on-resistance is low can be extended to reduce conduction loss.

[0054] Amorphous silicon can be used as the material for the second gate electrode 15 instead of polysilicon. Compared to polysilicon, amorphous silicon can reduce surface irregularities. Therefore, when the second gate electrode 15 is made of amorphous silicon, the surface area of ​​the second gate electrode 15 in contact with the second gate insulating film 14 is reduced. As a result, the parasitic gate capacitance at the second gate electrode 15 is reduced, and the charge-discharge of the gate capacitance is accelerated, so that the low-on voltage period becomes longer, thus improving conduction loss.

[0055] Amorphous silicon can be used as the material of the first gate electrode 12 instead of polysilicon.

[0056] A metal can be used as the material of the second gate electrode 15 instead of polysilicon. When the second gate electrode 15 is made of metal, the resistivity of the second gate electrode 15 becomes low. Therefore, the charge-discharge of the parasitic gate capacitance in the second gate electrode 15 is accelerated, and the period during which the on-voltage is low becomes longer, thus improving conduction loss.

[0057] As the semiconductor substrate 60, a substrate made of a wide band-gap semiconductor such as SiC, GaN, or Ga2O3 can be used instead of the Si substrate. In this case, the gate capacitance, which is inversely proportional to the thickness of the gate oxide film, tends to be larger than that of Si because, due to the difference in physical properties, the thickness of the gate oxide film can become about half that of Si. For this reason, the effective effect of reducing the gate capacitance by the configuration of the present disclosure is large, and switching loss is reduced. In addition, the charge-discharge of the gate capacitance is accelerated, so the period during which the on-resistance is low becomes longer to reduce conduction loss. <B. Zweite bevorzugte Ausführungsform>

[0058] Fig. Fig. 7 is a sectional view illustrating a semiconductor device 102 according to a second preferred embodiment. The top view of the semiconductor device 102 is similar to the top view of the semiconductor device 101 in Fig. 1, and the sectional view of Fig. 7 is a sectional view of the semiconductor device 102 taken along the line AA in Fig. 1.

[0059] In the semiconductor device 102, the second gate insulating film 14 is thicker than the first gate insulating film 11. The configuration of the semiconductor device 102 except for the thickness of the second gate insulating film 14 is similar to that of the semiconductor device 101. In the semiconductor device 102, similar to the semiconductor device 101, the specific resistance of the second gate electrode 15 can be made lower than the specific resistance of the first gate electrode 12 by setting the impurity concentration of polysilicon in the second gate electrode 15 higher than the impurity concentration of the polysilicon in the first gate electrode 12.

[0060] In the semiconductor device 102, the second gate insulating film 14 is thicker than the first gate insulating film 11, so that the parasitic gate capacitance at the second gate electrode 15 is smaller than the parasitic capacitance at the first gate electrode 12.

[0061] For example, the thickness of the first gate insulating film 11 is greater than or equal to 50 nm and less than or equal to 150 nm. The thickness of the second gate insulating film 14 is, for example, greater than or equal to 150 nm and less than or equal to 500 nm, and desirably greater than or equal to 300 nm and less than or equal to 500 nm. When the thickness of the second gate insulating film 14 is greater than or equal to 2 times, preferably greater than or equal to 3 times, the thickness of the first gate insulating film 11, the parasitic gate capacitance at the second gate electrode 15 can be sufficiently reduced. This accelerates the charge-discharge of the parasitic gate capacitance at the second gate electrode 15, so that the period during which the on-voltage is low becomes longer to improve the conduction loss.

[0062] Here, "the parasitic gate capacitance in the second gate electrode 15" or "the parasitic gate capacitance in the first gate electrode 12" refers to a sum of a gate-emitter capacitance Cge and a gate-collector capacitance Cgc. However, in the semiconductor device 102, the parasitic gate capacitance Cge at the second gate electrode 15 may be smaller than the parasitic gate-emitter capacitance Cge at the first gate electrode 12. Furthermore, the parasitic gate-collector capacitance Cgc at the second gate electrode 15 may be smaller than the parasitic gate-collector capacitance Cgc at the first gate electrode 12.

[0063] In Fig. 7, the number of trenches 10 containing the first gate electrodes 12 is the same as the number of trenches 10 containing the second gate electrodes 15. However, the number of gate trenches 10 is not limited to the same number. For example, to reduce the parasitic capacitance at the second gate electrode 15, the number of trenches 10 containing the second gate electrode 15 may be fewer than the number of trenches 10 containing the first gate electrode 12. <C. Dritte bevorzugte Ausführungsform><C-1. Konfiguration>

[0064] Fig. Fig. 8 is a sectional view illustrating a semiconductor device 103 according to a third preferred embodiment. The top view of the semiconductor device 103 is similar to the top view of the semiconductor device 101 in Fig. 1, and the sectional view of Fig. Fig. 8 is a sectional view of the semiconductor device 103 taken along the line AA in Fig. 1.

[0065] In semiconductor device 103, the electrode within each trench 10 has a two-stage structure consisting of the first gate electrode 12 of an upper stage and the second gate electrode 15 of a lower stage. Such a structure of trench 10 is referred to as a split gate. The first gate electrode 12 and the second gate electrode 15 are insulated by a barrier insulating film 13. The configuration of semiconductor device 103, except for the split gate, is similar to that of semiconductor device 101.

[0066] Since the electrode on the lower stage side of the split gate becomes an emitter potential, an accumulation layer is generally not formed around the lower electrode, and the on-voltage is high. On the other hand, in the semiconductor device 103 of the third preferred embodiment, the second gate electrode 15 is arranged on the lower stage side of the split gate, and the accumulation layer is formed around the second gate electrode 15. For this reason, the electron injected through the channel formed by the first gate insulating film 11 on the upper stage side and the p-type base layer 4 is passed with low resistance through the accumulation layer formed around the second gate electrode 15, so the on-voltage is reduced.

[0067] In the above description, the semiconductor device 103 was described as having a configuration in which the split gate is applied to the semiconductor device 101 of the first preferred embodiment. However, the semiconductor device 103 may have a configuration in which the split gate is applied to the semiconductor device 102 of the second preferred embodiment. Fig. 8, the second gate insulating film 14 is formed thicker than the first gate insulating film 11. In any configuration, the charge-discharge of the parasitic gate capacitance in the second gate electrode 15 can be accelerated and the period during which the on-voltage is low can be extended to improve the conduction loss. <C-2. Modifikation>

[0068] Fig. 9 is a sectional view illustrating a semiconductor device 103A according to a first modification of the third preferred embodiment. The plan view of the semiconductor device 103A is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 9 is a sectional view of the semiconductor device 103A taken along the line AA in Fig. 1. In the semiconductor device 103A, both the upper stage side and the lower stage side of the split gate in some of the trenches 10 are the second gate electrodes 15. The remaining configurations of the semiconductor device 103A are similar to those of the semiconductor device 103. With such a configuration, the gate-emitter capacitance Cge parasitic in the first gate electrode 12 is reduced, so that the turn-on loss is reduced.

[0069] Fig. Fig. 10 is a sectional view illustrating a semiconductor device 103B according to a second modification of the third preferred embodiment. The plan view of the semiconductor device 103B is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view of Fig. 10 is a sectional view of the semiconductor device 103B taken along the line AA in Fig. 1.

[0070] In the semiconductor device 103B, the upper stage side of the split gate in some of the trenches 10 is the trench emitter electrode 17. The trench emitter electrode 17 is electrically connected to the emitter electrode. The insulating film 16 is formed between the trench emitter electrode 17 and the inner wall of the trench 10. The other configurations of the semiconductor device 103B are similar to those of the semiconductor device 103. With such a configuration, the parasitic gate-emitter capacitance Cge in the first gate electrode 12 is reduced, so that the turn-on loss is reduced. Moreover, the parasitic gate-emitter capacitance Cge in the second gate electrode 15 is smaller than that in the semiconductor device 103A, so that the charge-discharge of the parasitic gate-emitter capacitance Cge in the second gate electrode 15 can be accelerated.As a result, the period during which the on-voltage is low becomes longer and the conduction loss is improved.

[0071] Fig. Fig. 11 is a sectional view illustrating a semiconductor device 103C according to a third modification of the third preferred embodiment. The plan view of the semiconductor device 103C is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 11 is a sectional view of the semiconductor device 103C taken along the line AA in Fig. 3.

[0072] In the semiconductor device 103C, in some of the trenches 10, the upper stage side of the split gate is filled with an insulator 18. According to the configuration of the semiconductor device 103B, the gate-emitter capacitance Cge is generated between the trench emitter electrode 17 and the second gate electrode 15. According to the configuration of the semiconductor device 103C, the gate-emitter capacitance Cge is generated between the second gate electrode 15 and the p-type base layer 4, but can be made smaller than the gate-emitter capacitance Cge generated between the trench emitter electrode 17 and the second gate electrode 15 in the semiconductor device 103B. Accordingly, the charge-discharge of the gate-emitter capacitance Cge parasitic in the second gate electrode 15 can be accelerated, and the low on-voltage period can be extended.

[0073] In the above description, the configuration in which the split gates are formed in all the trenches 10 was described. However, as illustrated in the following modification, a configuration in which the split gate and a normal gate (hereinafter also referred to as a "single-stage gate") other than the split gate are combined may be adopted. Fig. Fig. 12 is a sectional view illustrating a semiconductor device 103D according to a fourth modification of the third preferred embodiment. The plan view of the semiconductor device 103D is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 12 is a sectional view of the semiconductor device 103D taken along the line AA in Fig. 1.

[0074] In the semiconductor device 103D, a split gate including the upper-level first gate electrode 12 and the lower-level second gate electrode 15 is formed in some of the trenches 10. In the split gate, the first gate insulating film 11 is disposed between the first gate electrode 12 and the inner wall of the trench 10, and the second gate insulating film 14 is disposed between the second gate electrode 15 and the inner wall of the trench 10. The barrier insulating film 13 is disposed between the first gate electrode 12 and the second gate electrode 15 to insulate the first gate electrode 12 and the second gate electrode 15 from each other. On the other hand, in the remaining trenches 10, the first gate electrode 12 is formed over the first gate insulating film 11.

[0075] In the case where the second gate electrode 15 is arranged on the lower stage side of the split gate, when the second gate pad 31 is turned off, the accumulation layer is not formed around the second gate electrode 15, and the electron injection efficiency decreases. For this reason, the on-voltage becomes high during the period until the first gate pad 30 is turned off. In particular, when the off-voltage of the second gate pad 31 on the negative side is large, the p-type inversion layer is formed around the second gate electrode 15 on the lower stage side, so there is a specific problem that even when the first gate electrode 12 on the upper stage side is turned on, electron injection is greatly suppressed to increase the on-voltage.On the other hand, in the semiconductor device 103D, the on-voltage in the period until the first gate pad 30 is turned off can be reduced by combining the split gate and the single-stage gate.

[0076] Fig. Fig. 13 is a sectional view illustrating a semiconductor device 103E according to a fifth modification of the third preferred embodiment. The plan view of the semiconductor device 103E is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 3 is a sectional view of the semiconductor device 103E taken along the line AA in Fig. 1.

[0077] In the semiconductor device 103E, the lower-stage split-gate side is the trench emitter electrode 17, and the single-stage gate electrode is the second gate electrode 15. The insulating film 16 is formed between the trench emitter electrode 17 and the inner wall of the trench 10. The second gate insulating film 14 is formed between the second gate electrode 15 and the inner wall of the trench 10. The other configurations of the semiconductor device 103E are similar to those of the semiconductor device 103D. In the semiconductor device 103E, the single-stage gate electrode is the second gate electrode 15, so the electron is efficiently injected from the first gate electrode 12 on the upper-stage split-gate side even after the second gate pad 31 is turned off. In addition, an increase in the on-voltage after the second gate pad 31 is turned off is prevented.

[0078] Fig. Fig. 14 is a sectional view illustrating a semiconductor device 103F according to a sixth modification of the third preferred embodiment. The plan view of the semiconductor device 103F is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 14 is a sectional view of the semiconductor device 103F taken along the line AA in Fig. 1.

[0079] In the semiconductor device 103F, the upper stage side of the split gate is the second gate electrode 15, and the single-stage gate electrode is the first gate electrode 12. The second gate insulating film 14 is formed between the second gate electrode 15 and the inner wall of the trench 10, and the first gate insulating film 11 is formed between the first gate electrode 12 and the inner wall of the trench 10. The other configurations of the semiconductor device 103F are similar to those of the semiconductor device 103E. In the semiconductor device 103F, even after the second gate pad 31 is turned off, more electrons are injected from the single-stage gate where the accumulation layer is formed. For this reason, the increase in the on-voltage after the second gate pad 31 is turned off is prevented. <D. Vierte bevorzugte Ausführungsform><D-1. Konfiguration>

[0080] Fig. 15 is a sectional view illustrating a semiconductor device 104 according to a fourth preferred embodiment. The top view of the semiconductor device 104 is similar to the top view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 15 is a sectional view of the semiconductor device 104 taken along the line AA in Fig. 1.

[0081] In the semiconductor device 104, the cross-sectional area of ​​the second gate electrode 15 is larger than the cross-sectional area of ​​the first gate electrode 12. Specifically, a depth d and / or a width w of the second gate electrode 15 are / is larger than those of the first gate electrode 12. As the cross-sectional area of ​​the second gate electrode 15 is increased, the resistivity of the second gate electrode 15 becomes smaller, so the charge-discharge of the parasitic gate capacitance in the second gate electrode 15 is accelerated. As a result, the period during which the on-voltage is low becomes longer, and the conduction loss is improved. <D-2. Modifikation>

[0082] Fig. Fig. 16 is a sectional view illustrating a semiconductor device 104A according to a first modification of the fourth preferred embodiment. The plan view of the semiconductor device 104A is similar to the plan view of the semiconductor device 101 in Fig. 1, and the sectional view in Fig. 16 is a sectional view of the semiconductor device 104A taken along the line AA in Fig. 1.

[0083] In the semiconductor device 104A, the surface area of ​​the second gate electrode 15 is smaller than the surface area of ​​the first gate electrode 12. Specifically, the depth d and / or the width w of the second gate electrode 15 are / is smaller than those of the first gate electrode 12. The parasitic gate capacitance in the second gate electrode 15 can be reduced by reducing the surface area of ​​the second gate electrode 15. As a result, the charge-discharge of the parasitic gate capacitance at the second gate electrode 15 is accelerated, and the period during which the on-voltage is low is extended to improve the conduction loss. <E. Fünfte bevorzugte Ausführungsform><E-1. Konfiguration>

[0084] Fig. 17 is a plan view illustrating a semiconductor device 105 according to a fifth preferred embodiment. The first gate electrode 12 is electrically connected to the first gate pad 30 via the first gate wiring 50 and a first built-in gate resistor 60. The second gate electrode 15 is electrically connected to the second gate pad 31 via the second gate wiring 51 and a second built-in gate resistor 61. The second built-in gate resistor 61 is smaller than the first built-in gate resistor 60. Accordingly, the charge-discharge of the parasitic gate capacitance in the second gate electrode 15 can be accelerated, the period during which the on-voltage is low becomes longer, and the conduction loss is improved. <E-2. Modifikation>

[0085] Fig. 18 is a plan view illustrating a semiconductor device 105A according to a first modification of the fifth preferred embodiment. Unlike the semiconductor device 105, the semiconductor device 105A does not include the first built-in gate resistor 60 and the second built-in gate resistor 61. In the semiconductor device 105A, the cross-sectional area of ​​the second gate wiring 51 is larger than the cross-sectional area of ​​the first gate wiring 50. Specifically, the width of the second gate wiring 51 is larger than the width of the first gate wiring. Thus, the specific resistance of the second gate wiring 51 becomes lower than the specific resistance of the first gate wiring 50. As a result, the resistance value formed by the second gate wiring 51 becomes lower than the resistance value formed by the first gate wiring 50.Accordingly, the charge-discharge of the parasitic gate capacitance in the second gate electrode 15 can be accelerated, the period during which the on-voltage is low becomes longer, and the conduction loss is improved. <F. Sechste bevorzugte Ausführungsform><F-1. Konfiguration >

[0086] Fig. 19 is a plan view illustrating a semiconductor device 106 according to a sixth preferred embodiment. Fig. 20 is one along the line BB in Fig. 19 is a sectional view illustrating the semiconductor device 106.

[0087] The semiconductor device 106 includes a third gate pad 32, a third gate insulating film 19, and a third gate electrode 20 in addition to the configuration of the semiconductor device 101 of the first preferred embodiment.

[0088] Among the plurality of trenches 10, the first gate electrode 12 is embedded in some of the trenches 10 via the first gate insulating film 11, the second gate electrode 15 is embedded in some other of the trenches 10 via the second gate insulating film 14, and the third gate electrode 20 is embedded in some other of the trenches 10 via the third gate insulating film 19.

[0089] The specific resistance of the third gate electrode 20 is lower than the specific resistance of the second gate electrode 15. Alternatively, the parasitic gate capacitance at the third gate electrode 20 is lower than the parasitic gate capacitance at the second gate electrode 15. Accordingly, the charge period and the discharge period of the parasitic gate capacitance at the third gate electrode 20 are shorter than the charge period and the discharge period of the parasitic gate capacitance at the second gate electrode 15, respectively.

[0090] The third gate electrode 20 is electrically connected to the third gate pad 32 via a third gate wiring 52. The timings for turning on and off the first gate pad 30, the second gate pad 31, and the third gate pad 32 are independently controlled by a controller (not shown). That is, the semiconductor device 106 has a triple-gate structure.

[0091] Fig. 21 is a view illustrating the timing of driving the semiconductor device 106. In Fig. In Fig. 21, Vg3 represents the voltage applied to the third gate pad 32 and the third gate electrode 20. The third gate pad 32 is controlled by the controller (not shown) so that the third gate pad 32 is turned off at an earlier timing than that of the first gate pad 30 and the third gate pad 32 is turned on at an earlier timing than that of the second gate pad 31. That is, the second gate pad 31 is turned on after the third gate pad 32 is turned on, and the first gate pad 30 is turned off after the third gate pad 32 is turned off. The turning-on and turning-off timings of the first gate pad 30 and the second gate pad 31 are similar to those in the first preferred embodiment.

[0092] When the third gate pad 32 is turned off at an earlier time than the first gate pad 30, only the parasitic gate capacitance at the first gate electrode 12 becomes the off-state gate capacitance, so the gate capacitance becomes smaller to reduce the off-state loss. When the third gate pad 32 is turned on at an earlier time than the second gate pad 31, the channel density is increased by the channel formed by the third gate electrode 20 and the amount of electron injection is increased, so the temporal change of the current is accelerated to reduce the on-state loss. <F-2. Modifikation>

[0093] Fig. 22 is a sectional view illustrating a semiconductor device 106A according to a first modification of the sixth preferred embodiment. The semiconductor device 106A adopts a split-gate structure in the semiconductor device 106 having the triple-gate structure. In the trench 10, the second gate electrode 15 is embedded in the lower stage via the second gate insulating film 14, and the first gate electrode 12 is embedded in the upper stage via the first gate insulating film 11, or the third gate electrode 20 is embedded in the upper stage via the third gate insulating film 19.

[0094] Since the second gate insulating film 14 is not in contact with the p-type base layer 4, in the semiconductor device 106A, the second gate electrode 15 does not contribute to an increase in channel density. Therefore, when the second gate electrode 15 is turned on with a delay compared to the first gate electrode 12 and the third gate electrode 20, the turn-on speed can be increased by the parasitic gate capacitance at the second gate electrode 15, and the turn-on loss can be reduced. <G. Siebte bevorzugte Ausführungsform><G.1 Konfiguration>

[0095] Fig. 23 is a sectional view illustrating a semiconductor device 107 according to a seventh preferred embodiment. The semiconductor device 107 adopts a double-sided gate structure in the semiconductor device 101 of the first preferred embodiment. In the semiconductor device 107, in the semiconductor substrate 60, in addition to the trench 10 formed in the n-type drift layer 6 from the first main surface S1, a trench 40 is formed, which penetrates the p-type collector layer 8 and the n-type buffer layer 7 from the second main surface S2 of the semiconductor substrate 60 to reach the n-type drift layer 6. To distinguish between the two trenches, the trench 10 may sometimes be referred to as the first trench, and the trench 40 may be referred to as the second trench.

[0096] The first gate insulating film 11 is formed on the inner wall of the trench 10, and the first gate electrode 12 is embedded in the trench 10 via the first gate insulating film 11. The second gate insulating film 14 is formed on the inner wall of the trench 40, and the second gate electrode 15 is embedded in the trench 10 via the second gate insulating film 14. As described above, the semiconductor device 107 also has the gate structure on the second main surface S2 side (back surface side) of the semiconductor substrate 60.

[0097] Fig. 24 is a view illustrating the timing of driving the semiconductor device 107. In Fig. 24, Vg1 represents the voltage applied to the first gate pad 30 and the first gate electrode 12, and Vg2 represents the voltage applied to the second gate pad 31 and the second gate electrode 15. During turn-off, the second gate pad 31 is controlled by the controller (not shown) so that the second gate pad 31 is turned on at an earlier time than the first gate pad 30 is turned off. That is, the first gate pad 30 is turned off after the second gate pad 31 is turned on.

[0098] In the double-sided gate structure, when the second gate pad 31 is turned on during turn-off, the electron is discharged through the channel formed on the back surface side, so that the electron density on the back surface side is reduced. Accordingly, the turn-off loss is reduced because the hole density decreases to maintain the charge neutral. On the other hand, since the hole density decreases, so that the on-voltage increases, the charge period of the parasitic gate capacitance at the second gate pad 31 is desirably shortened, that is, the turn-on timing of the second gate pad 31 is delayed.

[0099] In the semiconductor device 107, similar to the semiconductor device 101 of the first preferred embodiment, the resistivity of the second gate electrode 15 is set lower than the resistivity of the first gate electrode 12. Alternatively, in the semiconductor device 107, similar to the semiconductor device 102 of the second preferred embodiment, the parasitic gate capacitance at the second gate electrode 15 is set lower than the parasitic gate capacitance at the first gate electrode 12. Accordingly, in the semiconductor device 107, the charging of the parasitic gate capacitance at the second gate electrode 15 can be accelerated, so that the turn-on timing of the second gate pad 31 can be delayed.As described above, according to the semiconductor device 107, the period during which the hole density is high, that is, the period during which the on-voltage is low, can be extended and the conduction loss can be improved. <G-2. Modifikation>

[0100] Fig. 25 is a sectional view illustrating a semiconductor device 107A according to a first modification of the seventh preferred embodiment. In the semiconductor device 107A, the gate structure on the back surface of the semiconductor device 107 is not a trench type but a planar type. By forming the gate structure on the back surface side as a planar type, the manufacturing process of the trench 40 on the back surface, which is very difficult to manufacture, can be reduced, and manufacturing costs can be reduced.

[0101] Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described preferred embodiments and the like, and various modifications and substitutions can be made to the above-described preferred embodiments and the like without departing from the scope described in the claims. Furthermore, the features of the semiconductor devices according to the respective preferred embodiments can be appropriately combined.

[0102] Various aspects of the present disclosure are described collectively herein as appendices. (Appendix 1)

[0103] A semiconductor device comprising: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; an upper surface electrode formed on the first main surface of the semiconductor substrate; a lower surface electrode formed on the second main surface of the semiconductor substrate; a first gate pad; and a second gate pad controlled independently of the first gate pad, wherein the semiconductor substrate a drift layer of a first conductivity type, a base layer of a second conductivity type formed on one side of the first main surface of the drift layer, a source layer of a first conductivity type formed on the first main surface side of the base layer, a plurality of first trenches penetrating the base layer from the source layer to reach the drift layer, and a gate electrode embedded in each of the plurality of first trenches via an insulating film, the gate electrode a first gate electrode electrically connected to the first gate pad, and a second gate electrode electrically connected to the second gate pad, and a charge period and a discharge period of a parasitic gate capacitance at the second gate electrode are shorter than a charge period and a discharge period of a parasitic gate capacitance at the first gate electrode. (Appendix 2)

[0104] The semiconductor device described in Appendix 1, wherein a specific resistance of the second gate electrode is lower than a specific resistance of the first gate electrode. (Appendix 3)

[0105] The semiconductor device described in Appendix 2, wherein an impurity concentration of a semiconductor material forming the second gate electrode is higher than an impurity concentration of a semiconductor material forming the first gate electrode. (Appendix 4)

[0106] The semiconductor device described in Appendix 2, wherein a cross-sectional area of ​​the second gate electrode is larger than a cross-sectional area of ​​the first gate electrode. (Appendix 5)

[0107] The semiconductor device described in Appendix 2, wherein the second gate electrode is made of metal. (Appendix 6)

[0108] The semiconductor device described in Appendix 1, wherein the parasitic gate capacitance at the second gate electrode is smaller than the parasitic gate capacitance at the first gate electrode. (Appendix 7)

[0109] The semiconductor device described in Appendix 6, wherein a second gate insulating film, which is the insulating film formed between the second gate electrode and the inner wall of the first trench, is thicker than a first gate insulating film, which is the insulating film formed between the first gate electrode and the inner wall of the first trench. (Appendix 8)

[0110] The semiconductor device described in Appendix 6, wherein a surface area of ​​the second gate electrode is smaller than a surface area of ​​the first gate electrode. (Appendix 9)

[0111] The semiconductor device described in Annex 6, wherein the second gate electrode is made of amorphous silicon. (Appendix 10)

[0112] The semiconductor device described in Annex 1, further comprising: a first built-in gate resistor disposed between the first gate electrode and the first gate pad; and a second built-in gate resistor arranged between the second gate electrode and the second gate pad, where the second built-in gate resistor is smaller than the first built-in gate resistor. (Appendix 11)

[0113] The semiconductor device described in Annex 10, wherein the first built-in gate resistor comprises a first gate wiring connecting the first gate electrode and the first gate pad, the second built-in gate resistor comprises a second gate wiring connecting the second gate electrode and the second gate pad, and a specific resistance of the second gate wiring is lower than a specific resistance of the first gate wiring. (Appendix 12)

[0114] The semiconductor device described in any one of Appendices 1 to 11, wherein in at least one first trench among the plurality of first trenches, the second gate electrode is embedded in a lower stage, the first gate electrode is embedded in an upper stage, and a barrier insulating film insulating the first gate electrode and the second gate electrode from each other is disposed between the first gate electrode and the second gate electrode. (Appendix 13)

[0115] The semiconductor device described in any one of Annexes 1 to 12, wherein the second gate pad is turned on after the first gate pad is turned on, and the first gate pad is turned off after the second gate pad is turned off. (Appendix 14)

[0116] The semiconductor device described in any one of Appendices 1 to 13, further comprising a third gate pad controlled independently of the first gate pad and the second gate pad, wherein the gate electrode has a third gate electrode electrically connected to the third gate pad and a charge period and a discharge period of the parasitic gate capacitance at the third gate electrode are shorter than a charge period and a discharge period of the parasitic gate capacitance at the second gate electrode. (Appendix 15)

[0117] The semiconductor device described in Annex 14, wherein the second gate pad is turned on after the third gate pad is turned on, and the first gate pad is turned off after the third gate pad is turned off. (Appendix 16)

[0118] The semiconductor device described in any one of Annexes 1 to 11, wherein the semiconductor substrate has at least one second trench reaching the drift layer from the second main surface, and the second gate electrode is embedded inside the second trench instead of the first trench. (Appendix 17)

[0119] The semiconductor device described in Appendix 16, wherein the first gate pad is turned off after the second gate pad is turned on. (Appendix 18)

[0120] The semiconductor device described in any one of Annexes 1 to 17, wherein the semiconductor device is an RC-IGBT. (Appendix 19)

[0121] The semiconductor device described in any one of Annexes 1 to 17, wherein the semiconductor device is a MOSFET. (Appendix 20)

[0122] The semiconductor device described in any one of Annexes 1 to 19, wherein the semiconductor substrate is made of a wide band gap semiconductor.

[0123] While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations may be devised. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 5742672 [0002, 0003]

Claims

[1] A semiconductor device comprising: a semiconductor substrate (60) having a first main surface (S1) and a second main surface (S2) opposite the first main surface (S1); an upper surface electrode (1) formed on the first main surface (S1) of the semiconductor substrate (60); a lower surface electrode (9) formed on the second main surface (S2) of the semiconductor substrate (60); a first gate pad (30); and a second gate pad (31) controlled independently of the first gate pad (30), wherein the semiconductor substrate (60) a drift layer (6) of a first conductivity type, a base layer (4) of a second conductivity type formed on one side of the first main surface (S1) of the drift layer (6), a source layer (3) of a first conductivity type formed on the side of the first main surface (S1) of the base layer (4), a plurality of first trenches (10) penetrating the base layer (4) from the source layer (3) to reach the drift layer (6), and a gate electrode (12, 15, 20) embedded in each of the plurality of first trenches (10) via an insulating film, the gate electrode (12, 15, 20) a first gate electrode (12) electrically connected to the first gate pad (30), and a second gate electrode (15) electrically connected to the second gate pad (31), and a charge period and a discharge period of a parasitic gate capacitance at the second gate electrode (15) are shorter than a charge period and a discharge period of a parasitic gate capacitance at the first gate electrode (12). [2] A semiconductor device according to claim 1, wherein a specific resistance of the second gate electrode (15) is lower than a specific resistance of the first gate electrode (12). [3] A semiconductor device according to claim 2, wherein an impurity concentration of a semiconductor material constituting the second gate electrode (15) is higher than an impurity concentration of a semiconductor material constituting the first gate electrode (12). [4] A semiconductor device according to claim 2, wherein a cross-sectional area of ​​the second gate electrode (15) is larger than a cross-sectional area of ​​the first gate electrode (12). [5] A semiconductor device according to claim 2, wherein the second gate electrode (15) is made of metal. [6] A semiconductor device according to claim 1, wherein the parasitic gate capacitance at the second gate electrode (15) is smaller than the parasitic gate capacitance at the first gate electrode (12). [7] The semiconductor device according to claim 6, wherein a second gate insulating film (14) which is the insulating film formed between the second gate electrode (15) and an inner wall of the first trench (10) is thicker than a first gate insulating film (11) which is the insulating film formed between the first gate electrode (12) and the inner wall of the first trench (10). [8] A semiconductor device according to claim 6, wherein a surface area of ​​the second gate electrode (15) is smaller than a surface area of ​​the first gate electrode (12). [9] A semiconductor device according to claim 6, wherein the second gate electrode (15) is made of amorphous silicon. [10] The semiconductor device according to claim 1, further comprising: a first built-in gate resistor (60) disposed between the first gate electrode (12) and the first gate pad (30); and a second built-in gate resistor (61) arranged between the second gate electrode (15) and the second gate pad (31), wherein the second built-in gate resistor (61) is smaller than the first built-in gate resistor (60). [11] A semiconductor device according to claim 10, wherein the first built-in gate resistor (60) comprises a first gate wiring (50) connecting the first gate electrode (12) and the first gate pad (30), the second built-in gate resistor (61) comprises a second gate wiring (51) connecting the second gate electrode (15) and the second gate pad (31), and a specific resistance of the second gate wiring (51) is lower than a specific resistance of the first gate wiring (50). [12] A semiconductor device according to any one of claims 1 to 11, wherein in at least one first trench (10) of the plurality of first trenches (10), the second gate electrode (15) is embedded in a lower stage, the first gate electrode (12) is embedded in an upper stage, and a barrier insulating film (13) isolating the first gate electrode (12) and the second gate electrode (15) from each other, is arranged between the first gate electrode (12) and the second gate electrode (15). [13] A semiconductor device according to any one of claims 1 to 12, wherein the second gate pad (31) is switched on after the first gate pad (30) is switched on, and the first gate pad (30) is turned off after the second gate pad (31) is turned off. [14] A semiconductor device according to any one of claims 1 to 13, further comprising a third gate pad (32) controlled independently of the first gate pad (30) and the second gate pad (31), wherein the gate electrode (12, 15, 20) has a third gate electrode (20) electrically connected to the third gate pad (32) and a charge period and a discharge period of the parasitic gate capacitance at the third gate electrode (20) are shorter than a charge period and a discharge period, respectively, of the parasitic gate capacitance at the second gate electrode (15). [15] A semiconductor device according to claim 14, wherein the second gate pad (31) is turned on after the third gate pad (32) is turned on, and the first gate pad (30) is turned off after the third gate pad (32) is turned off. [16] A semiconductor device according to any one of claims 1 to 11, wherein the semiconductor substrate (60) has at least one second trench (40) which reaches the drift layer (6) from the second main surface (S2), and the second gate electrode (15) is embedded inside the second trench (40) instead of the first trench (10). [17] A semiconductor device according to claim 16, wherein the first gate pad (30) is turned off after the second gate pad (31) is turned on. [18] A semiconductor device according to any one of claims 1 to 17, wherein the semiconductor device is an RC-IGBT. [19] A semiconductor device according to any one of claims 1 to 17, wherein the semiconductor device is a MOSFET. [20] A semiconductor device according to any one of claims 1 to 19, wherein the semiconductor substrate is made of a wide band gap semiconductor.

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