RGBZ pixel cell unit for an RGBZ image sensor

Abstract

Device comprising: an image sensor (100) comprising a pixel matrix with a unit cell (402; 600) comprising photodiodes (203) for visible light and an infrared photodiode (303), wherein the photodiodes (203) for visible light and the infrared photodiode (303) are coupled to a specific column of the pixel matrix, and the unit cell (402; 600) has a first capacitor (201) coupled to the photodiodes (203) for visible light to store charge from each of the photodiodes (203) for visible light, wherein the unit cell (402; 600) has a readout circuit to provide the voltage of the first capacitor (201) at the specific column, and the unit cell (402; 600) has a second capacitor (301) coupled to the infrared photodiode (303) via a transfer gate transistor (Q2). is to absorb charge from the infrared photodiode (303) during a time-of-flight exposure, wherein the unit cell (402;600) comprises a reverse flow transistor (Q4) coupled to the infrared photodiode (303), and wherein the unit cell (402; 600) comprises a reset transistor coupled to both the first (201) and second (301) capacitors to quench corresponding charge from the first capacitor (201) and the second capacitor (301).

Description

Field of invention

[0001] The field of the invention relates generally to imaging technology and in particular to an RGBZ pixel unit cell for an RGBZ image sensor. General state of the art

[0002] Fig. Figure 1 shows the basic elements of an image sensor 100. As can be seen in Fig. The image sensor 100 comprises a pixel matrix 101 with individual pixel cells 102. A row decoder 103 with outputs that connect to rows of pixel cells 102 is coupled to the pixel matrix 101. Detection amplifiers 104 are also coupled to the column outputs of the pixel matrix 101. The image sensor 100 also includes analog-to-digital circuits 105, which are connected downstream of the detection amplifiers 104. The image sensor 100 also includes timing and control circuits 106, which are responsible for generating clock and control signals that dictate the operation of the image sensor 100.

[0003] US 2014 / 0217474A1 discloses a unit pixel of an image sensor comprising a photoelectric conversion region, a floating diffusion region, and a transfer gate. The photoelectric conversion region is located in an active region defined by an isolation region of a semiconductor substrate. The photoelectric conversion region generates electrical charges corresponding to the incident light. The transfer gate transfers the electrical charges to the floating diffusion region.

[0004] EP 2 148 514 A1 discloses an imaging method and a device. The device can include an image sensor that may contain multiple pixels. At least one pixel contains a light detector element and a filter that directs a selected visible light component to the light detector element and a selected non-visible light component to the light detector element.

[0005] US 2012 / 0268566A1 relates to a three-dimensional color image sensor containing color pixels and depth pixels. A semiconductor substrate is provided with a depth region that extends adjacent to a surface of the semiconductor substrate. Within the depth region, a two-dimensional array of spaced-apart color regions is provided. Each of the color regions contains a variety of different color pixels (e.g., red, blue, and green pixels), and each color pixel within each of the spaced-apart color regions is spaced from all other color pixels within other color regions. Brief description

[0006] A device according to claims 1 to 8, a method according to claims 9 to 13 and a computer system according to claims 14 to 20 is disclosed. Figures

[0007] The following description and accompanying drawings are used to illustrate embodiments of the invention. The drawings show: Fig. Figure 1 shows a representation of an image sensor (state of the art); Fig. Figure 2 shows a representation of a pixel cell for visible light; Fig. Figure 3 shows a representation of a Z-pixel cell; Fig. Figure 4 shows a representation of a pixel matrix with one RGBZ pixel; Fig. Figure 5 shows a first Venn diagram for a first RGBZ pixel unit cell design; Fig. Figure 6 shows an embodiment of an RGBZ pixel unit cell that corresponds to the Venn diagram of Fig. 5 corresponds to; The Fig. 7a and Fig. Figure 7b shows layout implementation forms for the RGBZ pixel unit cell of Fig. 6; Fig. Figure 8 shows a second Venn diagram for a second RGBZ pixel unit cell design; Fig. Figure 9 shows a first embodiment of an RGBZ pixel unit cell, which corresponds to the Venn diagram of Fig. 8 corresponds to; The Fig. 10a and Fig. Figure 10b shows layout implementation forms for the RGBZ pixel unit cell of Fig. 9; Fig. Figure 11 shows a second embodiment of an RGBZ pixel unit cell, which corresponds to the Venn diagram of Fig. 8 corresponds to; The Fig. 12a and Fig. Figure 12b shows layout implementation forms for the RGBZ pixel unit cell of Fig. 11; Fig. Figure 13 shows a third embodiment of an RGBZ pixel unit cell, which corresponds to the Venn diagram of Fig. 8 corresponds to; The Fig. 14a and Fig. Figure 14b shows layout implementation forms for the RGBZ pixel unit cell of Fig. 13; Fig. Figure 15 shows a method carried out by an RGBZ pixel unit cell; The Fig. 16a to Fig. Figure 16g shows a method for manufacturing an RGBZ pixel cell; Fig. Figure 17 shows an embodiment of a camera system; Fig. Figure 18 shows an embodiment of a computer system. Detailed description

[0008] Fig. Figure 2 shows a circuit design 202 for a pixel for visible light. As can be seen in Fig. 2. Initially, the negative charge of a capacitor 201 is cleared by switching on a reset transistor Q1 (which reduces the capacitor voltage to a supply voltage (V_pixel)). When the negative charge of the capacitor is cleared and a transfer gate transistor Q2 is switched off, an exposure time begins, during which a light-sensitive photodiode 203 generates and accumulates negative charge (electrons) as a function of the intensity of the light it receives over the exposure time and the length of the exposure time.

[0009] After the exposure time, the transfer gate transistor Q2 is switched on, transferring the negative charge accumulated in photodiode 203 to capacitor 201. The transfer of negative charge to capacitor 201 affects the capacitor's voltage (the more negative charge capacitor 201 holds, the lower its voltage). Once the negative charge from the photodiode has been transferred to capacitor 201, a series selector control signal is activated, which switches on a series selector transistor Q3. This allows a detection amplifier, coupled behind the column output of the pixel cell, to detect the capacitor voltage. The capacitor voltage reading is then digitized and used as an indicator of the light intensity received by photodiode 203. The entire process then repeats.

[0010] Typically, the row selection signal activates the row selection transistor Q3 for each pixel cell along an equal row in the pixel matrix. The row selection signal "scrolls" through the rows of the matrix to acquire the entire matrix image. In a "global shutter" mode, the exposure times for all pixel cells in the matrix occur simultaneously (and the image should not exhibit any motion-related artifacts). In a "rolling shutter" mode, the exposure times of the pixel cells are staggered, for example, on a row-by-row basis (which can allow for the presence of motion artifacts).

[0011] The existence of the storage capacitor 201 allows the exposure timing to be decoupled from the timing of the series selection activation and the readout of the storage capacitor 201. In other words, after an exposure and the charge transfer into the storage capacitor 201, the voltage of the storage capacitor can remain for a certain period before it is read out. Consequently, an image sensor architecture that supports multiple exposure times per storage capacitor readout is possible. That is, as just one example, an image sensor can be designed that has three exposures with three corresponding charge transfers into the storage capacitor 201 for each readout of the storage capacitor 201 according to its series selection activation.

[0012] Fig. Figure 3 shows a circuit design for a "Z" pixel 302 for image sensors that acquire depth information using "time-of-flight" techniques. In the case of time-of-flight imaging, a light source typically emits infrared (IR) light from a camera system onto an object and measures, for each of several pixel cells in a pixel matrix, the time between the emission of the light and the reception of its reflection at the pixel matrix. The image produced by the time-of-flight pixels corresponds to a three-dimensional profile of the object, as indicated by a unique depth measurement (z) at each of the distinct (x, y) pixel positions.

[0013] As can be seen in Fig. The Z-pixel design 302 comprises a storage capacitor 301, reset transistor Q1, transfer gate transistor Q2, a photodiode 303, and a series selector transistor Q3, which operate similarly to those described above with respect to the visible light pixel cell 202. The transfer gate transistor Q2 is switched on and off during the exposure time by a clock signal. Controlling the transfer gate transistor Q2 with a clock signal during the exposure time of the Z-pixel 301 is an artifact of the transit-time measurement. In a common approach, the same Z-pixel 302 is equipped with four different clocks (each separated in phase by 90°) over four different reset, exposure-time, and readout sequences. The four different readouts of the charge collection are then combined to calculate the transit-time depth value for the pixel.

[0014] During the exposure time itself, as mentioned above, the transfer gate transistor Q2 switches on and off under the control of a clock signal. As such, charge is transferred from photodiode 303 to storage capacitor 301 several times during the exposure sequence. When the transfer gate transistor Q2 is off during the half-clock cycles, a "reverse flow" transistor Q4 is on to cause charge to flow from photodiode 304 to the supply node V_Pixel-. The clock that controls the reverse flow transistor Q4 is 180° out of phase with the clock that controls the transfer gate transistor Q2, so that while one is on, the other is off.

[0015] As such, charge flow from the photodiode alternates direction back and forth between flowing through the transfer gate transistor Q2 and flowing through the reverse flow transistor Q4 during the exposure time. However, it should be noted that the switching on and off of the transfer gate transistor Q2 during the exposure time of the Z-pixel cell is functionally similar to certain visible pixel cell implementations mentioned previously, where there are multiple exposures and corresponding charge transfers into the storage capacitor 201 per row selection readout.

[0016] Fig. Figure 4 shows an embodiment of a pixel matrix 401 with a pixel unit cell 402 comprising the visible light pixels R, G, and B and a Z pixel. Although this particular embodiment shows red (R), blue (B), and green (G) pixels as the visible light pixels, other embodiments may use differently colored pixel schemes (e.g., cyan, purple, and yellow). For the sake of simplicity, the remainder of this application largely refers to an RGB pixel scheme for visible light.

[0017] One challenge in the layout design of the 402 unit cell is to increase the area of ​​the photodiodes (to improve optical sensitivity) while preserving enough semiconductor area space to accommodate the transistors associated with the pixel unit cell circuitry near or within the unit cell (e.g., where such proximity is appropriate or necessary). That is, the more space these transistors occupy, the less space there will be for light collection, and conversely, the more space there is for light collection, the less space there is for transistors.

[0018] An additional problem is that the storage capacitor used for a visible light pixel design should be smaller to reduce noise during readout, while the storage capacitor design used for a Z-pixel should be larger to promote a greater infrared detection pixel capacity.

[0019] One solution is to have the visible-light pixels share the same storage capacitor and introduce a second storage capacitor for the Z-pixel. By having the visible-light pixels share the same storage capacitor, the space that would otherwise be consumed by the eliminated storage capacitors is preserved. The shared-memory pixel can also be made small to reduce readout signal noise for the visible-light pixels. Additionally, the second storage capacitor for the Z-pixel can be made larger than the visible-light storage capacitor to achieve a greater infrared detection pixel capacity.

[0020] Fig. Figure 5 shows a Venn diagram 500 for an RGBZ pixel unit cell design that corresponds to this approach. As can be seen in Fig. In equation 5, each of the R, G, and B pixels uses the same storage capacitor C1. In contrast, the Z pixel has its own storage capacitor C2, which has a larger capacitance than capacitor C1.

[0021] Fig. Figure 6 shows an embodiment of a design for an RGBZ pixel unit cell 600, which corresponds to the Venn diagram 500 of Fig. 5 corresponds. As can be seen in Fig. 6 represents the corresponding transfer gate transistor Q2_R, Q2_G, Q2_B for each of the R, G, and B photodiodes, coupled to the same storage capacitor C1. Apart from the combined RGB pixel circuit 601, a separate, distinct Z pixel circuit 602 exists. The combined RGB pixel circuit 601 and the Z pixel circuit 602 each have their own corresponding readout circuits, which are coupled to the same matrix column 603. Thus, for example, the same detection amplifier can detect the readout voltage from both pixel circuits 601 and 602.

[0022] The voltage readings of capacitors C1 and C2 are performed at different times (i.e., they cannot be read simultaneously). Additionally, due to the division of capacitor C1, readings for the visible light photodiodes are performed at different times for the different colors. Visible light readings can be performed sequentially, such as first a red reading, then a green reading, then a blue reading, and then the process repeats. The charge collected by the R, G, and B photodiodes can be accumulated simultaneously (or serially).

[0023] Charge transfer from any visible light photodiode to capacitor C1 is isolated (i.e., if any of the RGB transfer gate transistors Q2_R, Q2_G, or Q2_B is on for the purpose of measuring incident light, then the other two transfer gate transistors are off). Therefore, charge transfers in C1, such as readouts from C1, are performed sequentially rather than in parallel. Charge accumulated in a visible light photodiode can be cleared by activating both its transfer gate transistor and its reset transistor Q1_RGB. In this case, multiple visible light photodiodes can be cleared simultaneously by activating each of transistors Q2_R, Q2_G, Q2_B, and the reset transistor Q1_RGB.

[0024] According to one embodiment, the following timing scheme is implemented for the RGB pixel circuit. First, the charge of capacitor C1 is cleared by activating the reset transistor while the series selector transistor is off. Charge within one or more visible light photodiodes can be cleared simultaneously with C1 by activating the corresponding transfer gate transistor of each photodiode to be cleared. During the exposure time of a particular visible light photodiode, its transfer gate transistor is off. Then, charge is transferred from the photodiode into C1 by activating its transfer gate transistor while the other transfer gate transistors and the reset and series selector transistors are off. The voltage across C1 from the first photodiode is then detected by activating the series selector transistor Q3_RGB, with the reset transistor Q1_RGB off (all three transfer gate transistors can also be off).The charge at C1 is then cleared via a reset, and the process is repeated two more times for each of the other photodiodes. The entire process then repeats.

[0025] According to one embodiment, the following timing scheme is implemented for the Z-pixel circuit 602. The voltage across capacitor C2 is cleared by activating the reset transistor Q1_Z, while the series selector transistor Q3_Z is off. One of the transfer gate or reverse flow transistors Q2_Z or Q4_Z may also be on to clear any charge in the Z-photodiode. An exposure time then begins, during which a first clock signal is applied to the gate of the transfer gate transistor Q2_Z and a second clock signal, phase-shifted by 180° relative to the first, is applied to the gate of the reverse flow transistor Q4_Z. For these segments (e.g., 50%) of the first clock cycle, corresponding to a logic level that activates the transfer gate transistor Q2_Z, charge is transferred from the Z-photodiode to C2.For the remaining sections, where the second clock signal corresponds to a logic level that activates the backflow transistor Q4_Z, charge is transferred from the Z photodiode to the voltage supply terminal Vpix.

[0026] After the exposure time, both clock signals are suppressed to turn off both the transfer gate transistor Q2_Z and the reverse flow transistor Q4_Z, leaving the reset transistor Q1_Z off. The series selector transistor Q3_Z is then turned on, allowing the voltage across capacitor C2 to be measured. This process is repeated three more times, resulting in four different instances of the first clock signal (and the corresponding second clock signal) with phases of 0°, 90°, 180°, and 270° being applied to the Z-pixel circuit. The readings from capacitor C2 for the four different phases are then processed to determine a depth value for the Z-pixel. The entire process is then repeated for the next set of clock signals at 0°, 90°, 180°, and 270° to obtain the next Z-pixel depth value.

[0027] In operation, the RGB pixel cell circuit 601 and the Z pixel cell circuit 602 can operate in series or parallel, as long as their corresponding readouts are performed at different times. Likewise, R, G, and B pixel values ​​can be generated at the same rate as Z pixel values ​​or at different rates. In a higher-power embodiment, however, R, G, and B pixel values ​​are generated more frequently than Z pixel values ​​due to the longer Z pixel exposure times (multiple R, G, and B pixel readouts are performed during the Z exposure time). If the R, G and B pixels need to be read out at the same or slower rate as the Z pixel, the corresponding transfer gate transistors Q2_R, Q2_G, Q2_B for the R, G and B pixels can also be used as reverse flow transistors to allow charge to flow away from the R, G and B photodiodes, which may accumulate, for example, during the long Z exposure.Here, both the RGB transfer gate transistors Q2_R, Q2_G, Q2_B and the RGB reset transistor Q1_RGB are activated to force the voltage at capacitor C1 to a supply voltage level Vpix and to allow charge to flow from a photodiode into capacitor C1.

[0028] The Fig. 7a and Fig. Figure 7b shows two different layout configurations for the R, G, B, and Z photodiodes, as well as the transfer gate transistors Q2_R, Q2_G, Q2_B, and Q2_Z, the reverse flow transistor Q4, and the capacitors C1 and C2. Since the transfer gate and reverse flow transistors are directly coupled to a photodiode, they are typically integrated within the same semiconductor area as the photodiodes. The other transistors of the RGB pixel circuit and the Z pixel circuit can be located, for example, around the perimeter of the pixel matrix or around the perimeter of a macrocell (e.g., a group of RGBZ unit cells) within the area of ​​the pixel matrix. One or more of the other transistors can also be integrated within the RGBZ unit cell at the expense of photodiode area.

[0029] As can be seen in the Fig. 7a and Fig. In diagram 7b, the transfer gate transistors Q2_R, Q2_G, and Q2_B for the cell's RGB pixel circuit are located at the corners facing the R, G, and B photodiodes, respectively. Capacitor C1 is located in a region that exists at, directly outside, or near the active regions for each of the three transfer gate transistors Q2_R, Q2_G, and Q2_B. The transfer gate and reverse flow transistors Q2_Z and Q4 for the Z photodiode are located at corners of the Z photodiode other than the corner facing C1 and the RGB transfer gate transistors. C2 is located in a region that exists at, directly outside, or near the active region of the Z transfer gate transistor.

[0030] As can be seen in the Fig. 7a and Fig. 7b The gate electrode for transistors Q2_R, Q2_G, Q2_B, Q2_Z, and Q4 can be arranged near or at the edges of their corresponding photodiodes. In one embodiment, a first source / drain region for each of these transistors is spatially integrated with its corresponding photodiode (e.g., by having its implantation located within the photodiode). In an identical or different embodiment, a second source / drain region of these transistors is spatially integrated with C1, C2, or Vpix, depending on the specific transistor. In the case of a transistor coupled to C1 or C2, the source / drain region of the transistor is located within an implantation used to form C1 and C2, and / or it receives a contact that serves as an electrode for C1 or C2.In the case of a transistor coupled to Vpix, the source / drain region of the transistor receives a contact that is bound to the supply voltage potential Vpix.

[0031] The Fig. 7a and Fig. 7b differ in that which two of the three “available” (i.e., not facing the RGB transfer gate transistors and C1) corners of the Z-pixel are consumed by the Z-pixel transfer gate transistor Q2_Z and the reverse flow transistor Q4_Z. Another embodiment (not shown) corresponds to the embodiment of Fig. 7a, wherein the positions of the transfer gate transistor Q2_Z and the capacitor C2 are interchanged with the position of the reverse flow transistor Q4. A further embodiment (also not shown) corresponds to the embodiment of Fig. 7b, where the positions of the transfer gate transistor Q2_Z and the capacitor C2 are swapped with the position of the return flow transistor Q4.

[0032] In various embodiments, both capacitors C1 and C2 can be formed, at least partially, as diffusion capacitances. C2 can be made larger than C1 by having any implantation different from that of C1, by having a larger surface area than C1, or by having more (e.g., more extensive, elaborate, larger) metal structures formed on top of it than C1, so that it essentially has a larger electrode plate area than C1.

[0033] Fig. Figure 8 shows a Venn diagram 800 for another RGBZ pixel unit cell, in which the visible light pixels share the same capacitor C1 and introduce a second capacitor C2 for the Z pixel. In contrast to the approach shown in Fig. As can be seen in section 5, the Z-pixel in the approach of Fig. However, component 8 not only has its own larger capacitor C2, but it also shares the use of capacitor C1 or is at least somehow coupled to capacitor C1. In designs where the Z pixel actually uses C1 as a storage node for the charge from the Z photodiode, only a single readout circuit can be used (i.e., both the RGB and Z pixel circuits use the same readout circuit because the circuits are coupled at the storage capacitance node).

[0034] Fig. Figure 9 shows an embodiment 900 of an RGBZ pixel unit cell, which corresponds to the Venn diagram of Fig. 8 corresponds. As can be seen in Fig. In diagram 9, the corresponding transfer gate transistors Q2_R, Q2_G, and Q2_B for each of the R, G, and B photodiodes are coupled to the same storage capacitor C1. Apart from the combined circuit consisting of the RGB photodiode, transfer gate, and capacitor C1, there is a separate, distinct circuit consisting of the Z photodiode, transfer gate, and capacitor C2. However, the combined RGB circuit and the Z circuit are coupled by transistor Q5, allowing the charge from the Z photodiode to be transferred to both capacitors C2 and C1 during exposure of the Z pixel. This effectively increases the capacitance for the Z pixel to C1 + C2. In one embodiment, C2 has a larger capacitance than C1. In another embodiment, C1 and C2 have approximately the same capacitance.

[0035] The coupling between the RGB and Z circuits via transistor Q5 allows the two pixel circuits to share the same readout circuit. Here, transistor Q5 is essentially used to establish a common node between capacitors C1 and C2 during Z-pixel exposure and Z-pixel readout. As such, in one embodiment, transistor Q5 is on during Z-pixel exposure and Z-pixel readout (but is otherwise off).

[0036] The RGB pixel cell largely functions as described above with regard to Fig. 6. However, it should be noted that the use of capacitor C1 by the Z-pixel circuit causes an additional reset of capacitor C1 by the RGB reset transistor. Specifically, after the voltage across capacitor C1 has been read for a visible light pixel, capacitor C1 is reset to prepare it to accept charge from the Z-photodiode (this reset does not exist in the embodiment of Fig. 6) After resetting, charge is drawn into capacitor C1 by the Z-photodiode, and the voltage across capacitors C1 and C2 is read. Capacitor C1 is then reset again to prepare it to draw charge from a visible light photodiode.

[0037] The Z-pixel cell also functions largely as described above with regard to Fig. 6. However, as just mentioned, during the exposure of the Z-pixel, transistor Q5 is also activated to allow charge transfer from the Z-photodiode to capacitor C1. Transistor Q5 remains activated until the voltage across capacitors C1 and C2 has been read.

[0038] Due to the coupling between the RGB pixel cell and the Z pixel cell, the two cells are less able to operate in parallel and in isolation from each other compared to the circuit of Fig. 6. That is, while the RGB and Z pixel circuits 601, 602 of Fig. 6 can operate completely simultaneously and without reference to each other (except that they cannot be read simultaneously), compared to the approach of Fig. 9. Charge from the R, G, or B photodiodes during Z-pixel exposure is not transferred to C1. Since Z-exposure can take a longer period of time (because exposures are made at four different clock phases), the reverse flow transistors Q4_R, Q4_G, Q4_B are coupled to each of the R, G, and B photodiodes, respectively, to allow charge to flow off that they may accumulate during Z-pixel exposure. Thus, in one embodiment, transistors Q4_R, Q4_G, Q4_B are off during R-, G-, and B-pixel exposure, but on during Z-pixel exposure.

[0039] The Fig. 10a and Fig. Figure 10b shows RGBZ unit cell layout implementation forms for the circuit of Fig. 9. As a point of comparison with the embodiments of the Fig. 7a and Fig. 7b for the circuit of Fig. Figure 6 shows the embodiments of the Fig. 10a and Fig. 10b further details the backflow transistors Q4_R, Q4_G, Q4_B for the pixels for visible light. The transistor Q5 is not directly coupled to a photodiode and can therefore be arranged on the perimeter of the matrix, the perimeter of a macro element, or within the unit cell with a proportional loss of photodiode area size.

[0040] The Fig. 10a and Fig. 10b differ in that which two of the three “available” (i.e., not facing the RGB transfer gate transistors and C1) corners of the Z-pixel are consumed by the Z-pixel transfer gate transistor Q2_Z and the four return flow transistors Q4_R, Q4_G, Q4_B, Q4_Z. Another embodiment (not shown) corresponds to the embodiment of Fig. 10a, wherein the positions of the four return-flow transistors Q2_Z and capacitor C2 are interchanged with the position of the return-flow transistor Q4_R, Q4_G, Q4_B, Q4_Z. A further embodiment (also not shown) corresponds to the embodiment of Fig. 10b, wherein the positions of the backflow transistor Q4_R, Q4_G, Q4_B, Q4_Z and capacitor C2 are swapped with the position of the backflow transistor Q4.

[0041] It should be noted that in the embodiment of Fig. 10a the pixel unit cell can be viewed as having “inner halves” of two distinct physical nodes Vpix located on opposite sides of the cell. That is, each physical node Vpix is ​​shared by two adjacent pixel unit cells. In comparison, in the embodiment of Fig. 10b The pixel unit cell can be viewed as having “inner quarters” of four distinct physical nodes Vpix located at four different corners of the pixel unit cell. That is, each physical node Vpix is ​​shared by four distinct pixel unit cells.

[0042] Fig. Figure 11 shows another embodiment, which corresponds to the Venn diagram of Fig. 8 corresponds. As can be seen in Fig. 11. The use of capacitor C1 by the Z-pixel cell is achieved through the backflow transistor Q4. However, here, capacitor C1 is not used as a storage node for the Z-photodiode, but rather as a supply voltage node Vpix. As such, capacitor C1 is used to support the backflow transistor Q4 according to its normal / traditional operation during Z-exposure. Capacitor C1 can be brought to the voltage level Vpix by activating the reset transistor Q1_RGB of the RGB pixel cell circuit. Therefore, in one embodiment of Fig. 11 The RGB reset transistor Q1_RGB is not only activated to reset C1 before an R, G or B exposure, but it is also activated during the Z exposure to force capacitor C1 to act as voltage node Vpix to assist the operation of the Z pixel backflow transistor Q4.

[0043] Limitations regarding when the visible RGB photodiodes can transfer charge to capacitor C1 and when capacitor C1 can be read out are the above in relation to Fig. 9 described similarly. That is, the RGB pixel cell and the Z pixel cell are limited in how they can operate simultaneously in isolation from each other. Specifically, the charge of an R, G, or B photodiode cannot be transferred to capacitor C1 during the Z exposure. However, using C1 as the voltage node Vpix during the Z exposure eliminates the additional reset sequence of capacitor C1 (described above in relation to Fig. (as described in section 9) to clear the charge from the Z photodiode. That is, if the capacitor voltage is set to Vpix during the Z exposure, capacitor C1 effectively remains at a reset level during the Z exposure and is therefore ready to accept charge from an R, G, or B pixel immediately after the Z pixel exposure and charge transfer to C2.

[0044] The embodiment of Fig. Figure 11 features separate readouts for the pair of capacitors C1 and C2, as the former is used to accept charge from RGB photodiodes, and the latter is used to store charge from the Z photodiode. In contrast to the approach of Fig. 9 does not require every RGB photodiode to be used in the approach of Fig. 11. Backflow transistors, since any excess charge accumulated by an RGB photodiode during Z-exposure can be tapped into capacitor C1 by its corresponding transfer gate transistor. As such, the RGB transfer gate transistors Q2_R, Q2_G, Q2_B act not only as transfer gate transistors but also as backflow transistors. In one embodiment, therefore, the RGB transfer gate transistors Q2_R, Q2_G, Q2_B are active not only during charge transfer for their corresponding photodiode but also during Z-exposure.

[0045] The Fig. 12a and Fig. Figure 12b shows different RGBZ pixel cell layout implementation forms for the circuit design of Fig. 11. Since the approach of Fig. 11, which does not include a backflow transistor coupled to a specially generated supply voltage node Vpix, in contrast to the preceding embodiments, includes the layout approach of Fig. 12a and Fig. 12b has no voltage node Vpix. Additionally, the backflow transistor Q4 for the Z photodiode is directly coupled to capacitor C1. Note that the Z transfer gate Q2_Z can occupy any of the three corners of the Z photodiode that is not consumed by the backflow transistor Q4.

[0046] It can be seen that the different activation / deactivation schemes for different of the above with regard to the circuit design implementation forms of the Fig. 6, Fig. 9 and Fig. The transistors described in section 11 can be implemented by an image sensor timing and control circuit coupled to it, which provides the control signals to each of these transistors to establish their on / off state.

[0047] It should also be noted that the RGBZ unit cell should appropriately filter light into its corresponding pixels. That is, in one embodiment, the R photodiode should receive red light by forming a filter structure over it that essentially only allows red light to pass through, the G photodiode should receive green light by forming a filter structure over it that essentially only allows green light to pass through, the B photodiode should receive blue light by forming a filter structure over it that essentially only allows blue light to pass through, and the Z photodiode should receive infrared light by forming a filter structure over it that essentially only allows infrared light to pass through.

[0048] Fig. Figure 13 shows two embodiments 1301, 1302 of an RGBZ pixel unit cell design approach that corresponds to the Venn diagram of Fig. 8 corresponds. As can be seen in Fig. 13, both embodiments 1301 and 1302 include a second transfer gate transistor Q2_Z_2 to increase the amount of charge collected during Z exposure. That is, it is worth recalling that in a typical implementation, the Z photodiode is coupled to a transfer gate transistor and a reverse flow transistor. During Z exposure, a first clock signal is applied to the transfer gate transistor and a second clock signal is applied to the reverse flow transistor, with the first and second clocks phase-shifted by 180°. When the first clock is applied, the transfer gate transistor charge is transferred to a storage capacitor, which is later read to detect the received optical intensity. In contrast, the reverse flow transistor charge is transferred to a supply node when the second clock is applied.

[0049] The charge flow in the supply nodes can be considered a signal loss that reduces the sensitivity of the Z pixel. In comparison, embodiments 1301 and 1302 of Fig. 13. The first and second clock signals are applied to the first and second transfer gate transistors Q2_Z_1 and Q2_Z_2, respectively, which are coupled to capacitors C2 and C1. Thus, during Z-exposure, the charge that would traditionally flow back to a supply node during the return flow would instead flow into capacitor C1 when the second clock signal, Q2_Z_2, is activated. As a result, more charge is accumulated during Z-exposure, leading to a more sensitive Z-pixel.

[0050] During readout, the voltage across C1 is detected, followed by the voltage across C2 (or first C2, then C1). Downstream (e.g., using analog-to-digital or mixed-signal circuitry, after the detection amplifiers), the two voltage readings are combined to produce a single read for the pair of clock signals applied during the Z-exposure. The process is then repeated, for example, with clock pairs that are 90° out of phase with the first and second clock signal pairs just applied. In one embodiment, the capacitance C1 is approximately equal to the capacitance C2, so that equal voltage readings from the pair of capacitors C1 and C2 correspond to equal amounts of charge absorbed.

[0051] Regarding the readout, the first embodiment 1301 differs from the second embodiment 1302 in that the first embodiment 1301 has a single readout circuit, while the second embodiment 1302 has separate readout circuits for each of capacitor C1 and capacitor C2. The first embodiment 1301 includes transistor Q5 to couple C2 to the readout circuit when the voltage across capacitor C2 is detected. The first embodiment 1301 also includes a single reset transistor Q1 to reset both C1 and C2. C1 and C2 can be reset simultaneously by holding Q5 active during the reset process (e.g., after both have been read out following a Z-exposure).

[0052] In one embodiment, the first embodiment 1301 keeps transistor Q5 switched off during Z-exposure. During Z-exposure, the pair of clock signals is applied to Q2_Z_1 and Q2_Z_2 to alternatively transfer charge to C2 and C1. Additionally, the RGB transfer gate transistors are switched off and the RGB return flow transistors Q4_R, Q4_G, Q4_B are switched on to prevent overexposure of the RGB pixels during Z-exposure.

[0053] When the Z-exposure is complete, Q5 remains off while the voltage across C1 is detected by activating the series select (RS) signal of the readout circuit. After the voltage across C1 has been detected, transistor Q5 is switched on to couple C2 to the readout circuit. The voltage across C2 is then detected. Once the voltages across C1 and C2 have been detected, Q5 remains on to couple both C1 and C2 to the reset transistor Q1. The reset transistor Q1 is then activated to clear the charge across both C1 and C2. Transistors Q2_Z_2 and Q5 are then switched off to decouple the Z-pixel from the RGB pixels, for example, in preparation for RGB exposure.

[0054] During RGB exposure, both Z transfer gate transistors Q2_Z_1 and Q2_Z_2 are off, and the Z return transistor Q4_Z is on. The RGB transfer gate transistors are activated and the return transistors deactivated according to the embodiments described above. In one embodiment, one RGB pixel is exposed while the other two RGB pixels are not. That is, the return transistor is off and the transfer gate transistor is on for the RGB pixel being exposed, while for the other two pixels that are not being exposed, the return transistor is on and the transfer gate transistor is off. The charge from the exposed photodiodes is transferred to C1, and the voltage across C1 is read. The voltage across C1 is then cleared, and, for example, either another RGB exposure can occur (for one of the pixels that was not exposed) or a Z exposure can be performed.

[0055] In the case of the second embodiment 1302, transistor Q5 is eliminated due to the separate read and reset circuits. During Z exposure, the gate transistor Q2_Z_1 is controlled by the first clock signal, and charge flows from the Z photodiode into C2. Additionally, the transfer gate transistor Q2_Z_2 is controlled by the second clock signal, and charge flows from the Z photodiode into C1. After Z exposure, one of the read circuits is activated to detect the voltage across one of the capacitors (the other read circuit is deactivated). After the first read, the other read circuit is activated (the first is deactivated) to detect the voltage across the second capacitor (the first capacitor may be reset at this point). After both capacitors have been read, the voltages across the latter, or across both capacitors, are reset.Otherwise, the process is carried out as described above for the first embodiment.

[0056] The Fig. 14a and Fig. Figure 14b shows layout configurations for the embodiments 1301 and 1302 described above. Fig. 13. As can be seen in Fig. In 14, R, G, and B transfer transistor gates are coupled between the R, G, and B photodiodes and C1 as in previous layout embodiments. In contrast to previous embodiments, a second Z-pixel transfer transistor gate Q2_Z_2 is coupled between the Z photodiode and C1. This specific layout approach is achievable at least with the second embodiment. The other apparent layout features have been described in previous layout embodiments.

[0057] Fig. Figure 15 shows a methodology implemented by the RGBZ pixel unit cell implementations described above. The method comprises transferring a first charge from a first photodiode, which has received visible light of a first type, into a storage capacitor and reading a first voltage of the storage capacitor at pixel matrix column 1501. The method also comprises transferring a second charge from a second photodiode, which has received visible light of a second type, into the storage capacitor and reading a second voltage of the storage capacitor at pixel matrix column 1502. The method also comprises transferring a third charge from a third photodiode, which has received visible light of a second type, into the storage capacitor and reading a third voltage of the storage capacitor at pixel matrix column 1503.The procedure also includes transferring charge from a fourth photodiode, which has received infrared light, to a second storage capacitor and reading a fourth voltage of the second storage capacitor at pixel matrix column 1504.

[0058] The Fig. 16a to Fig. 16e discloses a method for manufacturing an image sensor which performs any of the above-mentioned functions with regard to the Fig. 4 to Fig. 15 described RGB unit cell design strategies, and further includes an RGBZ filter structure that corresponds to these designs. Fig. Figure 16a shows a cross-sectional segment of an image sensor along an axis of the pixel matrix with a pair of pixels for visible light (R and G, as can be seen in Fig. 16a). Here, the semiconductor substrate 1601 shows the general location of the light-sensitive regions of the R and G photodiodes. The metallization 1602 deposited on the substrate forms the transistor gates and source / drain contacts, and the metallization deposited above the substrate forms the transistor and circuit coupling structure that connects to the pixel unit cell designs and other image sensor circuits. The metallization and transistor structures can be combined into any of the various configurations shown above with respect to the Fig. 4 to Fig. The characteristics described in 14a, b are formed.

[0059] Following the formation of the coupling structure metallization, as can be seen in Fig. 16b, a mordent or transparent layer 1603 is formed over the surface above the underlying structure. Then filters for visible light 1604 of a first kind (e.g., a red-colored “R” filter as shown in Fig. 16b), in the Mordant or Transparent layer 1603 by staining the layer with the appropriate color in the appropriate region. Specifically, as can be seen in Fig. 16b, the R-pixel regions of the mordent / transparent layer are colored red. The coloring can be implemented by heat transferring a mordent dye through a photoresist mask into a mordent layer and then removing the mask, or by absorbing a dye into a transparent layer through a photoresist mask and then removing the mask. Here, the photoresist and the mask are structured such that the regions of interest (the R-pixel regions) are exposed, while the other regions (GB and Z regions) are blocked. Specifically, photoresist is deposited onto or coated with the mordent / transparent layer. The photoresist is then exposed with a mask that has the features of the R-pixel regions. The photoresist is then etched to expose the underlying transparent / mordent layer in the R-regions of the pixel matrix.

[0060] As can be seen in Fig. 16c become filters for visible light of a second type 1605 (e.g. a green-tinted “G” filter, as can be seen in Fig. 16c) formed above the coupling structure metallization by, for example, green coloring of the suitable (G) pixel regions of the mordent / transparent layer 1403 by the techniques described above. Fig. Figure 16d shows the cross-sectional segment of an image sensor along another axis of the pixel matrix with pixels for visible light of a third kind (B) and a Z-pixel after forming the B filters 1606 according to the same techniques used to form the R and G pixels described above (the already formed R and G filters in the background are not shown for the sake of simplicity).

[0061] As can be seen in Fig. In Figure 16e, the infrared filters 1607 are formed in the Z-pixel regions of the image sensor. The infrared filters allow IR light to pass through and essentially block visible light. The infrared filters 1607 can be formed by forming a photoresist layer over the transparent / mordent layer 1603 and then exposing the photoresist with a mask that includes the Z-pixel regions of the pixel matrix. The photoresist layer is then etched to expose the transparent / mordent layer in the Z-pixel regions. The underlying transparent / mordent layer can also be etched in the Z-pixel regions, and a material that essentially only allows IR light to pass through can be deposited in the exposed regions. The resulting structure is described in Figure 16e. Fig. Figure 16e shows this. Alternatively, the underlying mordent or transparent layer can remain in the Z-pixel regions and the infrared filter can be deposited on top of the layer using photomasking techniques such as those described above.

[0062] In embodiments where the infrared filter is formed within the same layer as the RGB filters, the four pixel types can be formed in any order.

[0063] After the infrared filter, as can be seen in Fig. In a structure formed as shown in 16f, an IR reduction filter layer 1608 is deposited or coated onto the underlying structure and etched over the Z-pixel regions (e.g., using photoresist and masking techniques). As such, an IR reduction filter is essentially positioned over the R, G, and B pixel locations. The IR reduction filter layer 1608 is made of a material that essentially blocks infrared light. In various embodiments, the IR reduction layer 1608 is beneficial because traditional RGB filters do not essentially block infrared light, and in the context of an RGBZ image sensor for use in a time-of-flight system, without an IR reduction filter, the RGB pixels can respond to the infrared light from the time-of-flight illuminator. As such, the IR reduction filters help to isolate the imaging systems for visible light and time-of-flight.

[0064] Additionally, the IR reduction filters help prevent the RGB pixels from saturating during the Z-exposure process. This can also reduce the need for RGB pixel backflow during Z-exposure, prevent overexposure (where oversaturated pixels allow charge to flow into adjacent pixels), or at least simplify any RGB reset that occurs after a Z-exposure. It should be noted that, to the extent that overexposure remains a concern, the RGB filters can be coupled to some or all of the RGB photodiodes described in various embodiments. As such, the embodiments of Fig. 6, Fig. 7a, Fig. 7b and Fig. 11, Fig. 12a, Fig. 12b, for example, additionally includes backflow transistors for the RGB photodiode and therefore the backflow structures that are in the Fig. 10a and Fig. 10b are evident, include.

[0065] As can be seen in Fig. 16g, microlenses 1609 are formed over the filters. Here, a transparent layer, such as the microlenses, can be formed by any number of different processes, such as: 1) Coating and firing one or more photoresist layers onto the underlying structure, structuring the photoresist layers into, for example, circles / cylinders representing the microlens matrix, and then melting the photoresist circles / cylinders into the shape of the microlenses; 2) Performing the preceding process of 1) on a layer on a transparent layer (e.g., silica glass) and using the molten photoresist as a mask for RIE etching into the transparent layer (which completes the shape of fuller microlenses into the transparent layer); 3) Micro-extrusion of droplets directed toward the underlying structure in the matrix pattern and solidification of the droplets.

[0066] Fig. Figure 17 shows an integrated traditional camera and a time-of-flight imaging system 1700. The system 1700 has a connector 1701 for making electrical contact, for example, with a larger system / mainboard, such as the system / mainboard of a laptop computer, tablet computer, or smartphone. Depending on the layout and implementation, the connector 1701 may connect to the system / mainboard via a flexible cable, for example, by making an actual connection, or the connector 1701 may make direct contact with the system / mainboard.

[0067] The 1701 connector is attached to a baseboard 1702, which can be implemented as a multilayer structure of alternating conductive and insulating layers. The conductive layers are structured to form electronic traces that support the internal electrical connections of the 1700 system. The 1701 connector receives commands from the larger host system, such as configuration commands that read / write configuration information to / from configuration registers within the 1700 camera system.

[0068] An RGBZ image sensor 1703 is mounted on the baseboard 1702 beneath a receiving lens 1704. The RGBZ image sensor 1703 comprises a pixel matrix, which includes an RGBZ unit pixel cell. The RGB pixel cells are used to support traditional visible image acquisition (2D) functions. The Z pixel cells are IR-sensitive and are used to support 3D depth profiling using runtime techniques. The RGBZ unit pixel cell may include RGB pixel cells that have the same storage capacitor and / or some of the other features described above with respect to the Fig. 4 to Fig. 16. Although one basic embodiment includes RGB pixels for capturing a visible image, other embodiments may use different colored pixel schemes (e.g., cyan, purple, and yellow).

[0069] The 1703 image sensor can also include ADC circuits for digitizing the signals from the image sensor and timing and control circuits to generate clocking and control signals for the pixel matrix and the ADC circuits.

[0070] The 1702 baseboard can include signal traces to carry digital information provided by the ADC circuits to connector 1701 for processing by a higher end component of the host computer system, such as an image signal processing pipeline (which is integrated, for example, into an application processor).

[0071] A camera lens module 1704 is integrated above the RGBZ image sensor 1703. The camera lens module 1704 contains a system of one or more lenses to focus received light onto the image sensor 1703. Since the camera lens module's reception of visible light can interfere with the reception of IR light by the time-of-flight pixel cells of the image sensor, and conversely, the camera module's reception of IR light can interfere with the reception of visible light by the image sensor's RGB pixel cells, one or both of the image sensor's pixel matrix and the lens module 1703 can contain a system of filters designed to essentially block IR light intended to be received by the RGB pixel cells and essentially block visible light intended to be received by the time-of-flight pixel cells.

[0072] An illuminator 1705, consisting of a light source matrix 1707 under an aperture 1706, is also mounted on the base board 1701. The light source matrix 1707 can be implemented on a semiconductor chip attached to the base board 1701. A light source driver is coupled to the light source matrix to cause it to emit light with a specific intensity and modulated waveform.

[0073] In one embodiment, the integrated system supports 1700 of Fig. 17 Three operating modes: 1) 2D mode; 3) 3D mode; and 4) 2D / 3D mode. In 2D mode, the system behaves like a traditional camera. As such, the illuminator 1705 is deactivated, and the image sensor is used to receive visible images through its RGB pixel cells. In 3D mode, the system acquires time-of-flight depth information of an object within the field of view of the illuminator 1705. As such, the illuminator 1705 is activated and emits IR light (e.g., in an on-off-on-off-... sequence) onto the object. The IR light is reflected by the object, received by the camera lens module 1504, and captured by the Z pixels of the image sensor. In 2D / 3D mode, the 2D and 3D modes described above are active simultaneously.

[0074] Fig. Figure 18 shows a representation of an exemplary computer system from 1800, such as a personal computer system (e.g., desktop or laptop) or a mobile or handheld computer system such as a tablet or smartphone. As in Fig. As can be seen, the basic computer system can include a central processing unit 1801 (which may, for example, comprise several general-purpose processor cores) and a main memory controller 1817, arranged on an application processor or multi-core processor 1850, system memory 1802, a display 1803 (e.g., touchscreen, flat panel), a local wired point-to-point connection 1804 (e.g., USB), various network I / O functions 1805 (such as an Ethernet interface and / or a cellular modem subsystem), a wireless local area network connection 1806 (e.g., WiFi), a wireless point-to-point connection 1807 (e.g., Bluetooth), and a global positioning system connection 1808, various sensors 1809_1 to 1809_N, one or more cameras 1810, a battery 1811, a power management control unit 1812, a loudspeaker, and a microphone. 1813 and an audio encoder / decoder 1814.

[0075] An application processor or multi-core processor 1850 can include one or more general-purpose processor cores 1815 within its CPU 1801, one or more graphics processing units 1816, a main memory controller 1817, an I / O control function 1818, and one or more image signal processing pipelines 1819. The general-purpose processor cores 1815 typically run the computer system's operating system and application software. The graphics processors 1816 typically perform intensive graphics functions, such as generating graphic information displayed on the display 1803. The memory control function 1817 is connected to the system memory 1802. The image signal processing pipelines 1819 receive image information from the camera and process the raw image information for downstream uses. The power management control unit 1812 generally controls the power consumption of the system 1800.

[0076] The touchscreen displays 1803, the communication interfaces 1804 to 1807, the GPS interface 1808, the sensors 1809, the camera 1810, and the speaker / microphone codecs 1813, 1814 can each be considered as different I / O (input and / or output) forms relative to the overall computer system, including, where applicable, an integrated peripheral device (such as the one or more cameras 1810). Depending on the implementation, various of these I / O components may be integrated into the application processor / multi-core processor 1850, or they may be located outside the chip or package of the application processor / multi-core processor 1850.

[0077] In one embodiment, one or more cameras 1810 comprise an RGBZ image sensor with an RGBZ unit cell in which the pixel cells for visible light share an identical storage capacitor and / or in which the RGBZ unit cell includes any of the other features described above with respect to the Fig. 4 to Fig. The features described in section 16 are included. Application software, operating system software, device driver software and / or firmware running on a general-purpose CPU core (or other functional block having an instruction execution pipeline to execute program code) by an application processor or another processor can send commands to the camera system and receive image data from it.

[0078] In the case of commands, the commands can include entering or exiting any of the 2D, 3D, or 3D / 2D system states described above.

[0079] Embodiments of the invention can comprise various processes as described above. The processes can be embodied in machine-executable instructions. The instructions can be used to instruct a general-purpose or specialized processor to execute specific processes. Alternatively, these processes can be executed by specific hardware components containing hard-wired logic to execute the processes, or by any combination of programmed computer components and user-defined hardware components.

[0080] Elements of the present invention can also be provided as a machine-readable medium for storing machine-executable instructions. The machine-readable medium may include, but is not limited to, floppy disks, optical disks, CD-ROMs and magneto-optical disks, FLASH memory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, propagation media, or other types of media / machine-readable media suitable for storing electronic instructions. The present invention can, for example, be downloaded as a computer program that can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by means of data signals encoded in a carrier signal or other propagation medium over a communication link (e.g., a modem or a network connection).

[0081] In the foregoing description, the invention has been described with reference to specific exemplary embodiments thereof. However, it is obvious that various modifications and changes can be made to it without deviating from the broader meaning and scope of the invention as set forth in the appended claims. The specification and drawings should therefore be regarded as illustrative rather than limiting.

Claims

[1] Device comprising: an image sensor (100) comprising a pixel matrix with a unit cell (402; 600) comprising photodiodes (203) for visible light and an infrared photodiode (303), wherein the photodiodes (203) for visible light and the infrared photodiode (303) are coupled to a specific column of the pixel matrix, and the unit cell (402; 600) has a first capacitor (201) coupled to the photodiodes (203) for visible light to store charge from each of the photodiodes (203) for visible light, wherein the unit cell (402; 600) has a readout circuit to provide the voltage of the first capacitor (201) at the specific column, and the unit cell (402; 600) has a second capacitor (301) coupled to the infrared photodiode (303) via a transfer gate transistor (Q2). is to absorb charge from the infrared photodiode (303) during a time-of-flight exposure, wherein the unit cell (402;600) comprises a reverse flow transistor (Q4) coupled to the infrared photodiode (303), and wherein the unit cell (402; 600) comprises a reset transistor coupled to both the first (201) and second (301) capacitors to quench corresponding charge from the first capacitor (201) and the second capacitor (301). [2] Device according to claim 1, wherein the second capacitor (301) is coupled to the readout circuit and the readout circuit also provides the voltage of the second capacitor (301) at the specified column. [3] Device according to claim 1, wherein the photodiodes (203) for visible light are coupled with corresponding transfer gate transistors (Q2) and corresponding backflow transistors. [4] Device according to claim 1, wherein the photodiodes (203) for visible light are coupled with corresponding transfer gate transistors and corresponding return flow transistors. [5] Device according to claim 1, wherein the second capacitor (301) is larger than the first capacitor (201). [6] Device according to claim 1, wherein the unit cell (402; 600) further comprises a second readout circuit coupled to the second capacitor (301), and the second readout circuit provides the voltage of the second capacitor (301) at the specified column. [7] Device according to claim 1, wherein the backflow transistor is coupled to the first capacitor (201). [8] Device according to claim 1, wherein the first capacitor (201) is coupled to the second capacitor (301) by a transistor. [9] Procedures, comprehensive: Transfer of a first charge from a first photodiode (203), which has received visible light of a first kind, into a storage capacitor (201) and reading of a first voltage of the storage capacitor (201) at a pixel matrix column; Transferring a second charge from a second photodiode (203), which has received visible light of a second type, into the storage capacitor (201) and reading a second voltage of the storage capacitor (201) at the pixel matrix column; Transferring a third charge from a third photodiode (203), which has received visible light of a third type, into the storage capacitor (201) and reading a third voltage of the storage capacitor (201) at the pixel matrix column; Transferring a fourth charge from a fourth photodiode (303), which has received infrared light during a time-of-flight exposure, into a second storage capacitor (301) and reading a fourth voltage from the second storage capacitor (301) at the pixel matrix column; and Clearing the first, second and third voltages from the first capacitor (201) and clearing the fourth voltage from the second capacitor (301) with an identical reset transistor. [10] Method according to claim 9, further comprising transferring the fourth charge during an exposure time of the fourth photodiode (303) and performing the transfer of any of the first, second and third charges during the exposure time. [11] Method according to claim 9, further comprising transferring the fourth charge during an exposure time of the fourth photodiode (303) and allowing a fifth charge from any of the first, second and third photodiodes (203) to flow into a supply node during the exposure time. [12] Method according to claim 9, further comprising transferring the fourth charge during an exposure time of the fourth photodiode (303) and performing the readout of any of the first, second and third voltages during the exposure time. [13] Method according to claim 9, further comprising reading the first, second, third and fourth voltages with an identical reading circuit. [14] Computer system, comprising: an application processor (1850) with several processor cores (18151, 18152, 1815) coupled to a memory controller (1817) N ), wherein the memory controller (1817) is coupled to a system memory (1802); a camera system (1810) coupled to the application processor (1850), wherein the camera system (1810) comprises an image sensor (100), and the image sensor (100) comprises a pixel matrix with a unit cell (402; 600) comprising photodiodes (203) for visible light and an infrared photodiode (303), and the photodiodes (203) for visible light and the infrared photodiode (303) are coupled to a specific column of the pixel matrix, and the unit cell (402; 600) has a first capacitor (201) coupled to the photodiodes (203) for visible light to store charge from each of the photodiodes (203) for visible light, wherein the unit cell (402; 600) has a readout circuit to provide the voltage of the first capacitor (201) at the specific column, and the unit cell (402;600) has a second capacitor (301) coupled to the infrared photodiode (303) via a first transfer gate transistor (Q2) to absorb charge from the infrared photodiode (303) during a transit-time exposure, wherein the unit cell (402; 600) comprises a reverse flow transistor (Q4) coupled to the infrared photodiode (303), and wherein the unit cell (402; 600) comprises a reset transistor coupled to the first (201) and second (301) capacitors to quench corresponding charge from the first capacitor (201) and the second capacitor (301). [15] Computer system according to claim 14, wherein the second capacitor (303) is coupled to the readout circuit and the readout circuit also provides the voltage of the second capacitor (303) at the specified column. [16] Computer system according to claim 15, wherein the photodiodes (203) for visible light are coupled with corresponding transfer gate transistors (Q2) and corresponding backflow transistors. [17] Computer system according to claim 14, wherein the photodiodes (203) for visible light are coupled with corresponding transfer gate transistors and corresponding backflow transistors. [18] Computer system according to claim 14, wherein the backflow transistor is coupled to the first capacitor (201). [19] Computer system according to claim 14, wherein the second capacitor (303) is coupled to the first capacitor (201) by a transistor. [20] Computer system according to claim 14, wherein the second capacitor(303) is larger than the first capacitor (201).

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