Power semiconductor module, method for manufacturing the same and power conversion device

Abstract

Power semiconductor module (1, 1b, 1c), comprising: a plurality of connections (11, 12, 13, 14, 15) comprising a first connection (11) and a second connection (12) spaced apart from the first connection (11); a power semiconductor chip (20); a chip capacitor (27) having a first electrode (28a) and a second electrode (28b); an electronic element (25) which differs in type from the chip capacitor (27); and a sealing element (40) to seal the power semiconductor chip (20), the chip capacitor (27) and the electronic element (25), wherein the power semiconductor chip (20) is connected to at least one of the terminals (11, 12, 13, 14, 15), wherein the electronic element (25) is connected to the first terminal (11) by a first electrically conductive bonding region (35) which contains a first content of an electrically conductive filler, and wherein the first electrode (28a) and the second electrode (28b) of the chip capacitor (27) are connected to the first terminal (11) and the second terminal (12) respectively by a second electrically conductive bonding area (37) which is a hardened, electrically conductive adhesive and contains a second content of the electrically conductive filler, wherein the second content is greater than the first content.

Description

Technical area

[0001] The present invention relates to a power semiconductor module, a method for manufacturing the same and a power conversion device. State of the art

[0002] The published Japanese patent application JP 2012-104633A (PTL 1) discloses a semiconductor device comprising, in an injection-molded package: a terminal frame; a power chip mounted on the terminal frame; an IC chip mounted on the terminal frame to drive the power chip; and a bootstrap capacitor connected to the IC chip. The bootstrap capacitor is connected to the terminal frame via an insulating adhesive. List of patent literature

[0003] PTL 1: Published Japanese patent application JP 2012 - 104 633 A Overview of the invention Technical problem

[0004] One objective of the present invention is to provide a power semiconductor module that exhibits high reliability. Another objective of the present invention is to provide a power conversion device that exhibits high reliability. Solution to the problem

[0005] To solve the technical problem, a power semiconductor module with the features of claims 1 and 2, a power conversion device with the features of claim 18, and a method with the features of claim 19 are proposed. Advantageous embodiments of the power semiconductor module are described by the features of dependent claims 3 to 17. A power semiconductor module according to one embodiment comprises a plurality of terminals, a chip capacitor, and an electronic element. The terminals comprise a first terminal and a second terminal spaced apart from the first terminal. The chip capacitor comprises a first electrode and a second electrode. The electronic element is connected to one of the terminals by a first electrically conductive bonding region containing a first amount of an electrically conductive filler.The first electrode and the second electrode of the chip capacitor are connected to the first terminal and the second terminal, respectively, by a second electrically conductive bonding area which contains a second amount of the electrically conductive filler, the second amount being greater than the first amount.

[0006] A power semiconductor module according to the second aspect of the present invention comprises a plurality of terminals, a chip capacitor, and an electronic element. The terminals comprise a first terminal and a second terminal spaced apart from the first terminal. The chip capacitor comprises a first electrode and a second electrode. The electronic element is connected to one of the terminals by a first electrically conductive bonding region containing a first electrically conductive filler. The first electrode and the second electrode of the chip capacitor are connected to the first terminal and the second terminal, respectively, by a second electrically conductive bonding region containing a second electrically conductive filler. The second electrically conductive bonding region has a lower electrical resistance than the first electrically conductive bonding region.

[0007] A method for fabricating a power semiconductor module according to the present invention comprises connecting a power semiconductor chip to at least one of a plurality of terminals. The terminals comprise a first terminal and a second terminal spaced apart from the first terminal. The method for fabricating a power semiconductor module according to the present invention comprises connecting an electronic element to one of the terminals by means of a first electrically conductive bonding region. The first electrode and the second electrode of the chip capacitor are connected to the first terminal and the second terminal, respectively, by means of a second electrically conductive bonding region containing a second electrically conductive filler. The second electrically conductive bonding region has a lower specific electrical resistance than the first electrically conductive bonding region.

[0008] A method for manufacturing a power semiconductor module according to the present invention comprises connecting a power semiconductor chip to at least one of a plurality of terminals. The terminals comprise a first terminal and a second terminal spaced apart from the first terminal. The method for manufacturing a power semiconductor module according to the present invention comprises connecting an electronic element to one of the terminals by means of a first electrically conductive bonding region. The first electrically conductive bonding region contains a first component of an electrically conductive filler. The method for manufacturing a power semiconductor module according to the present invention comprises supplying an electrically conductive adhesive to a plurality of first regions in the first terminal and to a plurality of second regions in the second terminal.The method for fabricating a power semiconductor module according to the present invention comprises placing a first electrode of a chip semiconductor onto the electrically conductive adhesive in the first areas and placing a second electrode of the chip semiconductor onto the electrically conductive adhesive in the second areas. The chip semiconductor is of a different type than the electronic element. The method for fabricating a power semiconductor module according to the present invention comprises curing the electrically conductive adhesive to form a second electrically conductive bonding area that connects the first electrode and the second electrode of the chip capacitor to the first terminal and the second terminal, respectively. The second electrically conductive bonding area contains a second amount of the electrically conductive filler, the second amount being greater than the first amount.The method for manufacturing a power semiconductor module of the present invention comprises sealing the power semiconductor chip, the chip capacitor and the electronic element by means of a sealing element.

[0009] A power conversion device of the present invention comprises: a main conversion circuit for converting received electrical power and outputting converted electrical power, wherein the main conversion circuit comprises the power semiconductor module of the present invention; and a control circuit for outputting a control signal to the main conversion circuit for controlling the main conversion circuit. Advantageous effects of the invention

[0010] According to the power semiconductor module of the first aspect of the present invention and the method for fabricating a power semiconductor module of the present invention, the second content of the electrically conductive filler in the second electrically conductive bonding region is greater than the first content of the electrically conductive filler in the first electrically conductive bonding region. According to the power semiconductor module of the second aspect of the present invention, the specific electrical resistance of the second electrically conductive bonding region is lower than that of the first electrically conductive bonding region. This allows for a greater difference between the electrical resistance in the second electrically conductive bonding region and the permissible electrical resistance required in the interconnection region of the chip semiconductor.Even if the stress acting on the second electrically conductive bonding region leads to partial delamination and / or cracking in the second electrically conductive bonding region, the increase in electrical resistance in the second electrically conductive bonding region can be reduced. The reliability of the electrical connection of the second electrically conductive bonding region can be improved. The power semiconductor module of the first and second aspects of the present invention exhibits high reliability. According to the method for fabricating a power semiconductor module of the present invention, a power semiconductor module with high reliability can be produced.

[0011] The power conversion device of the present invention comprises a main conversion circuit which includes the power semiconductor module of the present invention. The power conversion device of the present invention exhibits high reliability. Brief description of the drawings Fig. Figure 1 is a schematic top view of a power semiconductor module according to the first embodiment. Fig. 2 is a schematic, partially enlarged top view of an area II, which is in Fig. 1 shown, of the power semiconductor module according to the first embodiment. Fig. Figure 3 is a schematic, partially enlarged cross-sectional view along a cross-sectional line III-III, which is shown in Fig. 1 shown, of the power semiconductor module according to the first embodiment. Fig. Figure 4 is a diagram showing a circuit in an electronic element included in the power semiconductor module of the first embodiment. Fig. Figure 5 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. Fig. Figure 6 is a diagram showing a flowchart of a method for manufacturing the power semiconductor module according to the first embodiment. Fig. Figure 7 is a diagram showing a flowchart of the process for manufacturing the power semiconductor module according to the first embodiment. Fig. Figure 8 is a schematic top view showing one step of the process for manufacturing the power semiconductor module according to the first embodiment. Fig. Figure 9 is a schematic, partially enlarged cross-sectional view along a cross-sectional line IX-IX in step 2, which is in Fig. Figure 8 shows the method for manufacturing the power semiconductor module of the first embodiment. Fig. Figure 10 is a schematic, partially enlarged top view of a step of the method for manufacturing the power semiconductor module according to the first embodiment. Fig. Figure 11 is a schematic, partially enlarged top view of a power semiconductor module of a comparative example. Fig. Figure 12 is a schematic top view showing a step that follows the step that is in Fig. Figure 8 shows the method for creating the power semiconductor module according to the first embodiment. Fig. Figure 13 is a schematic, partially enlarged cross-sectional view along a cross-sectional line XIII-XIII in the step that is in Fig. Figure 12 shows the method for manufacturing the power semiconductor module according to the first embodiment. Fig. Figure 14 is a schematic, partially enlarged top view of a step of a method for manufacturing a power semiconductor module according to a modification of the first embodiment. Fig. Figure 15 is a diagram showing a flowchart of the process for manufacturing the semiconductor device according to the first embodiment. Fig. Figure 16 is a schematic cross-sectional view of a power semiconductor module according to the second embodiment. Fig. Figure 17 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. Fig. Figure 18 is a schematic cross-sectional view of a power semiconductor module according to the third embodiment. Fig. Figure 19 is a block diagram showing a configuration of a power conversion system according to the fourth embodiment. Description of embodiments

[0012] Embodiments of the present invention are described below. Identical configurations are designated with the same reference numerals and their descriptions are not repeated. First embodiment

[0013] With reference to the Fig. 1, Fig. 2, Fig. 3 to Fig. Section 4 below describes a power semiconductor module 1 of the first embodiment. The power semiconductor module 1 essentially comprises a plurality of terminals, a power semiconductor chip 20, a chip capacitor 27, an electronic element 25, and a sealing element 40. The power semiconductor module 1 may further comprise a controlling semiconductor chip 23.

[0014] The majority of connections further comprise a first connection 11, a second connection 12, a third connection 13, a fourth connection 14 and a fifth connection 15. The first connection 11, the second connection 12, the third connection 13, the fourth connection 14 and the fifth connection 15 are spaced apart from each other.

[0015] Multiple ports can also comprise multiple pads (for example, a first pad 11a, a second pad 12a, a third pad 14a, and a fourth pad 15a). The first port 11 can comprise a first pad 11a, which is a widely extended region of the first port 11. The second port 12 can comprise a second pad 12a, which is a widely extended region of the second port 12. The fourth port 14 can comprise a third pad 14a, which is a widely extended region of the fourth port 14. The fifth port 15 can comprise a fourth pad 15a, which is a widely extended region of the fifth port 15. The fifth port 15 comprises a stepped region 15b between the fourth pad 15a and a third projecting region 15c.The stepped area 15b comprises a first end area connected to the fourth pad 15a and a second end area located on the side opposite the first end area. The second end area is positioned higher than the first end area.

[0016] At least one region of the connection comprises a plurality of projecting regions extending from the sealing element 40. The projecting regions are curved. For example, the connection 11 comprises a first projecting region 11c extending from the sealing element 40. The first projecting region 11c comprises a first projecting region 11d extending horizontally away from the first connection 11a, and a second projecting region 11e extending upwards from the first projecting region 11d. The second connection 12 comprises a second projecting region 12c extending from the sealing element 40. The second projecting region 12c comprises a third projecting region 12d extending horizontally from the second pad 12a, and a fourth projecting region 12e extending upwards from the third projecting region 12d.The fifth terminal 15 comprises a third projecting area 15c, which projects from the sealing element 40. The third projecting area 15c comprises a fifth projecting area 15d, which extends horizontally from the second end area of ​​the stepped area 15b, and a sixth projecting area 15e, which extends upwards from the fifth projecting area 15d. Electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, electronic element 25) are packaged in the semiconductor module 1 in a dual in-line package (DIP) configuration.

[0017] The majority of terminals are each formed from an electrically conductive material, such as copper. At least one region of the majority of terminals may be covered with a plated area 17, such as a silver-plated area. The plated area 17 may be formed from a material that is less prone to oxidation than the material of the majority of terminals. The material that is less prone to oxidation than the material of the majority of terminals is a noble metal, such as silver. The plated area 17 may, for example, be formed on an innermost region of the first terminal 11. The plated area 17 may be formed on the innermost region of the second terminal 12. The plated area 17 may be formed on a portion of the fourth pad 15a of the fifth terminal 15.

[0018] The first terminal 11 may also have a first through-hole 16a. In the present embodiment, the first through-hole 16a is located outside the chip capacitor 27 (on the side of the first projecting area 11c). The first through-hole 16a may be located inside the chip capacitor 27 (on the side opposite the first projecting area 11c), or it may be located both outside and inside the chip capacitor 27. The second terminal 12 may also have a second through-hole 16b. In the present embodiment, the second through-hole 16b is located outside the chip capacitor 27 (on the side of the second projecting area 12c).The second through-hole 16b can be provided inside the chip capacitor 27 (on the side opposite the second projecting area 12c), or it can be arranged both outside and inside the chip capacitor 27.

[0019] The power semiconductor chip 20 can be, for example, a reverse-conducting IGBT (RC-IGBT), an insulated-gate bipolar transistor (IGBT), a freewheeling diode (FBD), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a diode. The power semiconductor chip 20 has, for example, a rated current of 1 A or more and a rated voltage of 100 V or more. The power semiconductor chip 20 can be made of a semiconducting material such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). The power semiconductor module 1 can comprise one power semiconductor chip 20, or it can comprise a plurality of power semiconductor chips 20. In the present embodiment, the power semiconductor module 1 comprises the high-voltage power semiconductor chip 20 and the low-voltage power semiconductor chip 20. The high-voltage power semiconductor chip 20 is connected to the fourth pad 15a of the fifth terminal 15.

[0020] The power semiconductor chip 20 is connected to at least one of the plurality of terminals (fifth terminal 15). At least one of the plurality of terminals (the fifth terminal 15) to which the power semiconductor chip 20 is connected is different from the first terminal 11, the second terminal 12, the third terminal 13, and the fourth terminal 14. The power semiconductor chip 20 is connected to the fourth pad 15a (in particular to the plated area 17) of the fifth terminal 15 by a solder joint 30. The solder joint 30 can effectively transfer the heat generated by the power semiconductor chip 20 to the fifth terminal 15. The power semiconductor chip 20 is connected to the plurality of terminals (in particular to the plated area 17) via an electrically conductive wire 29.

[0021] The controlling semiconductor chip 23 is configured to control the power semiconductor chip 20. The controlling semiconductor chip 23 forms part of a control circuit that controls the power semiconductor chip 20. For example, the controlling semiconductor chip 23 can be configured to control the gate voltage of the power semiconductor chip 20. The controlling semiconductor chip 23 can be configured to detect the current flowing through the power semiconductor chip 20. The power semiconductor module 1 is an intelligent power module (IPM) that includes the power semiconductor chip 20 and the controlling semiconductor chip 23, which is configured to control the power semiconductor chip 20. The controlling semiconductor chip 23 is connected to the power semiconductor chip 20 via an electrically conductive wire 29. The controlling semiconductor chip 23 is electrically connected to the first terminal 11 and the second terminal 12 via an electrically conductive wire 29.

[0022] The power semiconductor module 1 can comprise a controlling semiconductor chip 23, or it can comprise a plurality of controlling semiconductor chips 23. In the present embodiment, the power semiconductor module 1 comprises: the high-voltage controlling semiconductor chip 23, which is configured to control the high-voltage power semiconductor chip 20; and the low-voltage controlling semiconductor chip 23, which is configured to control the low-voltage power semiconductor chip 20.

[0023] The controlling semiconductor chip 23 is connected to at least one of the plurality of connections (the fourth connection 14). At least one of the plurality of connections (the fourth connection 14) to which the controlling semiconductor chip 23 is connected is different from the first connection 11, the second connection 12, the third connection 13, and the fifth connection 15. The controlling semiconductor chip 23 is connected to the third pad 14a of the fourth connection 14 by an electrically conductive connection area 33. The electrically conductive connection area 33 can be a solder joint area, or it can be a first electrically conductive connection area 35, which is described below.

[0024] The electronic element 25 is an electronic component of a different type than the chip capacitor 27. The electronic element 25 forms part of the control circuit that controls the power semiconductor chip 20. The electronic element 25 can be a passive electronic component. Examples of passive electronic components include a diode 25a, such as a chip diode, or a resistor 25b, such as a chip resistor. As an example of a passive electronic component, the diode 25a has, for instance, a rated current of less than 1 A and a rated voltage of less than 100 V.

[0025] In the present embodiment, the electronic element 25 is a rectifying semiconductor chip. As in Fig. As shown in Figure 4, the rectifying semiconductor chip includes a resistor 25b in addition to the diode 25a. The rectifying semiconductor chip, which includes the resistor 25b and the chip capacitor 27, can form a bootstrap circuit. The electronic element 25 can be a bootstrap diode (BSD). The bootstrap circuit serves as a circuit that provides gate-driven power on the P-side only, while providing gate-driven power on the N-side. The bootstrap circuit consists of a rectifying semiconductor chip and a capacitor connected to a gate-driven circuit. The bootstrap circuit differs from a snubber circuit, which is located on the output side (between a drain and a source, between a collector and an emitter) of a switching element (for example, a power semiconductor chip 20).The electronic element 25 can be electrically connected to control the semiconductor chip 23 via the electrically conductive wire 29 and the first terminal 11. The electronic element 25 can also be electrically connected to the third terminal 13 (in particular the plated area 17) via the electrically conductive wire 29.

[0026] The electronic element 25 is connected to one of the several terminals by the first electrically conductive bonding region 35. In particular, the electronic element 25 is connected to the first terminal 11 by the first electrically conductive bonding region 35. The first electrically conductive bonding region 35 contains a first component of an electrically conductive filler. The first electrically conductive bonding region 25 contains a first resin and the first electrically conductive filler dispersed within the first resin. The first electrically conductive filler can be made of one or more electrically conductive materials selected from the group consisting, for example, of silver, nickel, and copper. In the present description, the electrically conductive filler also contains conductive particles. The first resin can, for example, be an epoxy resin.

[0027] The chip capacitor 27 can be a surface-mount ceramic multilayer capacitor. The chip capacitor 27 forms part of the control circuit that regulates the power of the semiconductor chip 20. The chip capacitor 27 can be a bootstrap capacitor (BSC), which is part of a bootstrap circuit. The capacitance of the chip capacitor 27 is appropriately set according to the power consumption of the controlling semiconductor chip 23, the gate capacitance of the power semiconductor chip 20, and the charging and discharging times of the chip capacitor 27. The chip capacitor 27 comprises a first electrode 28a and a second electrode 28b. The chip capacitor 27 is the tallest component among the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) that are connected to the majority of terminals.

[0028] The first electrode 28a and the second electrode 28b of the chip capacitor 27 are connected to the first terminal 11 and the second terminal 12, respectively, by electrically conductive bonding regions 37. The second electrically conductive bonding region 37 contains a second resin and an electrically conductive filler dispersed within the second resin. The electrically conductive filler can be made of one or more electrically conductive materials, selected, for example, from the group consisting of silver, nickel, and copper. In the present embodiment, the material of the second electrically conductive filler contained in the second electrically conductive bonding region 37 can be the same as, or different from, the material of the first electrically conductive filler contained in the first electrically conductive bonding region 35. The second resin can, for example, be an epoxy resin.The material of the second resin can be the same as the material of the first resin, or it can be different.

[0029] The second electrically conductive bonding region 37 has a lower specific electrical resistance than the first electrically conductive bonding region 35. If the second electrically conductive filler is formed from the same material as the first electrically conductive filler, the second electrically conductive bonding region 37 contains a second amount of electrically conductive filler, and this second amount is greater than the first amount. The first amount may be 65 wt.% or less, or it may be 60 wt.% or less. The second amount may, for example, be 75 wt.% or more, or it may be 80 wt.% or more.

[0030] In this description, the first content, expressed in wt.%, represents the ratio of the weight of the first electrically conductive filler to the weight of the first electrically conductive bonding region 35. In this description, the second content, expressed in wt.%, represents the ratio of the weight of the electrically conductive filler contained in the second electrically conductive bonding region 37 to the weight of the second electrically conductive bonding region 37. The difference between the second content and the first content can be 10 wt.% or more, 15 wt.% or more, or 20 wt.% or more. Since the first content of the electrically conductive filler in the first electrically conductive bonding region 35 is relatively low, the first electrically conductive bonding region 35 can lead to reduced costs.

[0031] During the use of the power semiconductor module 1, the power semiconductor chip 20 and the like generate heat. Therefore, the second electrically conductive bonding area 37 is subjected to thermal stresses resulting from the different coefficients of thermal expansion of the first terminal 11, the second terminal 12, and the chip capacitor 27. The second electrically conductive bonding area 37 may also be subjected to mechanical stresses during the use of the power semiconductor module 1 or during the manufacturing steps of the power semiconductor module 1. Regarding the first terminal 11 and the second terminal 12, variations in the size of the terminal frame 10 (see Figure 1) may occur. Fig. 8) during manufacturing or the difference in bending between the first terminal 11 and the second terminal 12, a height difference between the first terminal 11 and the second terminal 12 (a difference in position between the first terminal 11 and the second terminal 12 in the direction perpendicular to the plane of the drawing) Fig. 8) cause. The chip capacitor 27 can be connected to the first terminal 11 and the second terminal 12 in the state in which the first terminal 11 and the second terminal 12 have different heights. If, as in Fig. As shown in Figure 13, the terminal frame 10, to which the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) are connected, is clamped by a form 45. The first terminal 11 and the second terminal 12 are aligned at the same height, and the second electrically conductive bonding area 37 can be subjected to mechanical stresses. Such thermal and mechanical stresses lead to partial delamination and / or cracking in the second electrically conductive bonding area 37, thereby increasing the electrical resistance in the second electrically conductive bonding area 37.

[0032] The second electrically conductive bonding region 37, however, exhibits a lower specific electrical resistance than the first electrically conductive bonding region 35. If the second electrically conductive filler is made of the same material as the first electrically conductive filler, the second content of electrically conductive filler in the second electrically conductive bonding region 37 is greater than the first content of electrically conductive filler in the first conductive bonding region 35. This allows for an increased difference between the second electrical resistance in the second electrically conductive bonding region 37 and the permissible electrical resistance required for the connecting region of the chip capacitor 27.Even if partial delamination occurs in the second electrically conductive bonding region 37, the increase in electrical resistance in the second electrically conductive bonding region 37 can be reduced. Therefore, the reliability of the electrical connection of the second electrically conductive bonding region 37 can be improved.

[0033] The first and second grades are obtained according to the following procedures. The sealing element 40, the electronic element 25, and the terminals (first terminal 11, second terminal 12) are removed from the power semiconductor module 1, and the electrically conductive bonding region (first electrically conductive bonding region 35, second electrically conductive bonding region 37) is extracted. The weight of the electrically conductive bonding region is then measured. The electrically conductive bonding region is heat-treated at a temperature lower than the melting point of the electrically conductive filler (first electrically conductive filler, second electrically conductive filler). For example, if the electrically conductive filler is made of silver, which has a melting point of 962 °C, the electrically conductive bonding region can be heat-treated at 800 °C.This process volatilizes the resin contained in the electrically conductive bonding region, extracting the electrically conductive filler contained within that region. The weight of the extracted electrically conductive filler is measured. The ratio of the weight of the electrically conductive filler to the weight of the electrically conductive bonding region is calculated. This yields the first and second content values.

[0034] The specific electrical resistance of the first electrically conductive bonding region 35 and the specific electrical resistance of the second electrically conductive bonding region 37 are obtained according to the following procedure. First, the sealing element 40, the electronic element 25, and the terminals (first terminal 11, second terminal 12) are removed from the power semiconductor module 1, and the electrically conductive bonding region (first electrically conductive bonding region 35, second electrically conductive bonding region 37) is extracted. The resistance of the electrically conductive bonding region is determined by a four-point measurement. The contact area and the thickness of the electrically conductive bonding region are measured. The electrical resistance is multiplied by the contact area and then divided by the thickness.In this way, the specific electrical resistance of the first electrically conductive bonding region 35 and the specific electrical resistance of the second electrically conductive bonding region 37 are obtained.

[0035] The specific electrical resistivity of the first electrically conductive bonding region 35 and the specific electrical resistivity of the second electrically conductive bonding region 37 are also obtained by another method. First, a portion is cut out of the power semiconductor module 1. This cut-out portion of the power semiconductor module 1 comprises: the electrically conductive bonding region (first electrically conductive bonding region 35, second electrically conductive bonding region 37); a portion of the terminal (first terminal 11, second terminal 12); and at least a portion of the electronic component (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25).Then, the electrical resistance of the terminal portion and the electronic circuit portion are subtracted from the electrical resistance in the power semiconductor module 1 to calculate the electrical resistance of the conductive bonding region. The bonding area and the thickness of the conductive bonding region are measured. The electrical resistance is multiplied by the bonding area and then divided by the thickness. In this way, the resistivity of the first conductive bonding region is 25 and the resistivity of the second conductive bonding region is 37.

[0036] The first electrically conductive bonding region 35 can further contain insulating particles made of an insulating inorganic material. The insulating particles are each formed from one or more inorganic materials selected from the group consisting, for example, of silicon dioxide, aluminum oxide, and aluminum nitride. The addition of insulating particles to the first electrically conductive bonding region 35 leads to the first and second effects, which are described below. In the first effect, the insulating particles serve to reduce the volume of the area of ​​the first electrically conductive bonding region 35 through which current can flow, thereby increasing the electrical resistance in the electrically conductive bonding region 35.In the second effect, the insulating particles serve to increase the content of the first electrically conductive filler in the area of ​​the electrically conductive bonding region 35 through which a current can flow, for example, to increase the contact between the first electrically conductive filler, thereby reducing the electrical resistance of the first electrically conductive bonding region 35.

[0037] In the present embodiment, insulating particles are added to the first electrically conductive bonding region 35, so that the second effect occurs to a greater extent than the first. The insulating particles thus serve to reduce the electrical resistance in the first electrically conductive bonding region 35. Even if the first content of the electrically conductive filler in the first electrically conductive bonding region 35 is relatively low, the insulating particles can improve the reliability of the electrical connection of the first electrically conductive bonding region 35. For example, if the insulating particles are silicon dioxide particles, the first electrically conductive bonding region 35 can contain 3.5 wt.% or more, or 6 wt.% or more, of silicon dioxide particles. The first electrically conductive bonding region 35 can contain 18 wt.% or less, or 12 wt.% or less, of silicon dioxide particles.Since the content of electrically conductive filler is higher, the second effect occurs to a lesser extent. The insulating particles are not added to the second electrically conductive bonding region 37, but they can be added to the first electrically conductive bonding region 35 at will.

[0038] The insulating particles also serve to increase the elastic modulus of the first electrically conductive bonding region 35 and to decrease its coefficient of linear expansion. Consequently, the curvature of the first connection is reduced. The height difference between the first connection 11 and the second connection 12 is reduced. Furthermore, the delamination and fractures introduced into the second electrically conductive bonding region 37 are also reduced. Thus, the reliability of the electrical connection of the second electrically conductive bonding region 37 can be improved.

[0039] The first terminal 11 has a first surface 11s that corresponds to the first electrode 28a. The first surface 11s can be made of copper or tin. The second terminal 12 has a second surface 12s that corresponds to the second electrode 28b. The second surface 12s can also be made of copper or tin. The first surface 11s of the first terminal 11 and the second surface 12s of the second terminal 12 can be exposed to the plated area 17, which is made of the material that is less likely to oxidize. Thus, the first surface 11s of the first terminal 11 and the second surface 12s of the second terminal 12 are more likely to oxidize than the plated area 17. However, the second electrically conductive bonding area 37 has a relatively low electrical resistance.Even if the first surface 11s of the first terminal 11 and the second surface 12s of the second terminal 12 are not each provided with the plated area 17, an electrical connection that is reliable and has low resistance can still be created via the second electrically conductive bonding area 37 between the first terminal 11 and the chip capacitor 27, as well as via the second electrically conductive bonding area 37 between the second terminal 12 and the chip capacitor 27.

[0040] The first electrode 28a and the second electrode 28b of the chip capacitor 27 can each be made of gold, silver, palladium, nickel, copper, or tin. In other words, the surface of the first electrode 28a and the surface of the second electrode 28b need not be made of a material such as silver, which is less likely to oxidize. The surface of the first electrode 28a and the surface of the second electrode 28b are more prone to oxidation than the plated area 17. However, the second electrically conductive bonded area 37 exhibits a relatively low electrical resistance.Even if the first electrode 28a and the second electrode 28b are each made of copper or tin, a reliable low-resistance electrical connection can thus be provided between the first terminal 11 and the chip capacitor 27 via the first electrically conductive bonding area 35 and also between the second terminal 12 and the chip capacitor 27 via the second electrically conductive bonding area 37.

[0041] The electronic element 25 and the chip capacitor 27 can be connected to the first terminal 11. This reduces the first distance between the electronic element 25 and the chip capacitor 27. The wiring resistance between the electronic element 25 and the chip capacitor 27 can be reduced. Furthermore, the first distance between the electronic element 25 and the chip capacitor 27 can be smaller than the second distance between the chip capacitor 27 and the power semiconductor chip 20. The harmful effects of electromagnetic interference and heat generated by the power semiconductor chip 20 via the chip capacitor 27 are reduced. The operation of the electrical circuit (for example, a bootstrap circuit) that includes the electronic element 25 (for example, a rectifying semiconductor chip containing the diode 25a and the resistor 25b) and the chip capacitor 27 is stabilized.

[0042] The sealing element seals a portion of the terminals of the power semiconductor chip 20, the control semiconductor chip 23, the chip capacitor 27, the electronic element 25, and the electrically conductive wire 29. The sealing element 40 exhibits electrical insulation properties. The sealing element 40 can be made of cast resin. The sealing element 40 can be made of a resin material selected, for example, from the group consisting of epoxy resin, polyimide resin, polyamide resin, a polyamide-imide resin, a fluorine-based resin, an isocyanate resin, silicone resin, and a combination thereof.

[0043] The first projecting area 11c extends from an area 41a of the sealing element 40. The shortest distance between an area 41a of the sealing element 40 and the chip capacitor 27 can be equal to or less than five times the thickness of the first terminal 11. The thickness of the first terminal 11 can be, for example, 0.2 mm or greater. The thickness of the first terminal 11 can be 2 mm or less. The second projecting area 12c extends from an area 41b of the sealing element 40. The shortest distance d between an area 41b of the sealing element 40 and the chip capacitor 27 can be equal to or less than five times the thickness t of the second terminal 12. The thickness t of the second terminal 12 can be, for example, 0.2 mm or greater. The thickness t of the second terminal 12 can be 2.0 mm or less.

[0044] In that step (see Fig. 6, Fig. 12 and Fig. 13) By sealing the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) with the sealing element 40, the length of the first terminal 11 extending in a space 45a within the shape 45 can be reduced. When a load is applied to a plate element having a fixed end, the degree of deflection of the plate element is generally proportional to the cube of the length of the plate element extending from the fixed end and inversely proportional to the cube of the thickness of the plate element. As the length of the first terminal extending in the space 45a of the shape 45 decreases, the degree of deflection of the first terminal 11 decreases.As the length of the second terminal 12, which extends within space 45a of the mold, decreases, the degree of bending of the second terminal 12 also decreases. This reduces the height difference between the first terminal 11 and the second terminal 12. Consequently, the occurrence of partial detachment and cracking in the second electrically conductive bonding region 37 is suppressed, thus improving the reliability of the electrical connection of the second electrically conductive bonding region 37.

[0045] The first through-hole 16a of the first connection 11 and the second through-hole 16b of the second connection 12 are filled with the sealing element 40. Even if the first connection 11 and the second connection 12 are deformed due to the difference between the thermal expansion of the sealing element 40 and the coefficients of thermal expansion of the first connection 11 and the second connection 12, respectively, the first connection 11 and the second connection 12 are deformed into substantially the same shape, starting from the first through-hole 16a and the second through-hole 16b, respectively. This suppresses the formation of partial detachment and cracks in the second electrically conductive bonding area 37, thereby improving the reliability of the electrical connection of the electrically conductive bonding material 37.

[0046] By inserting the sealing element 40 into the first through-hole 16a and the second through-hole 16b, the sealing element 40 located above the first terminal 11 and the second terminal 12 is integrated with the sealing element 40 located below the first terminal 11 and the second terminal 12. The sealing element 40 inserted into the first through-hole 16a and the second through-hole 16b acts as an anchor against the force that pulls the first terminal 11 and the second terminal 12 out of the sealing element 40. This prevents the first terminal 11 and the second terminal 12 from being pulled out of the sealing element 40 and also suppresses the effect of shear stress on the second electrically conductive bonding region 37.The occurrence of partial detachment and cracks in the second electrically conductive bonding area 37 is also suppressed, so that the reliability of the electrical connection of the second electrically conductive bonding area 37 can be improved.

[0047] With reference to Fig. Section 5 below describes a semiconductor device of the present embodiment. The semiconductor device 2 comprises a power semiconductor module 1 and a printed circuit board 51, which includes a plurality of conductors (for example, conductors 54 and 55) and a plurality of through-holes (for example, through-holes 52 and 53). The printed circuit board 51 has a first main surface 51a and a second main surface 51b on the side opposite the first main surface 51a. The first main surface 51a is associated with the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25). The plurality of through-holes extends from the first main surface 51a to the second main surface 51b. The plurality of conductors is formed on the second main surface 51b.

[0048] The majority of the connections are inserted into the through-holes of the circuit board 51. Protruding areas of the majority of the connections are connected to the conductors by solder joint areas (for example, solder joint areas 57 and 58). In particular, the second protruding area 11e (see Fig. 1) The first terminal 11 is inserted into a through-hole (not shown) in the circuit board 51. The second protruding section 11e of the first terminal 11 is connected to a conductor (not shown) via a solder joint area (not shown). The fourth protruding section 12e of the second terminal 12 is inserted into the through-hole 52. The fourth protruding section 12e of the second terminal 12 is connected to the conductor 54 via the solder joint area 87. The sixth protruding section 15e of the fifth terminal 15 is inserted into the through-hole 53. The sixth protruding section 15e of the fifth terminal 15 is connected to the conductor 55 via the solder joint area 58.

[0049] With reference to the Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. 10 and the Fig. 12, Fig. 13 to Fig. 14 A method for manufacturing the power semiconductor module 1 of the first embodiment is described below.

[0050] With reference to the Fig. 6, Fig. 7, Fig. 8 to Fig. Section 9 comprises the method for manufacturing the power semiconductor module 1, which involves connecting electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) to the terminal frame 10 (S1). In particular, the terminal frame 10 is prepared. The terminal frame 10 comprises a frame area 10a and a plurality of terminals. The plurality of terminals includes a first terminal 11, a second terminal 12, a third terminal 13, a fourth terminal 14, and a fifth terminal 15. The plurality of terminals extends from the frame area 10a to the interior of an opening 10b in the frame area 10a. The terminal frame 10 may also have a terminal connection area 18. Inside the opening 10b of the frame, the terminal connection area 18 connects the plurality of terminals to each other and also connects the plurality of terminals to the frame area 10a.The connecting area 18 suppresses the bending of the opening 10b of the frame area 10a.

[0051] Then the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) are connected to the conductor frame 10. As in Fig. As shown in Figure 7, the power semiconductor chip 20 is connected to the fifth terminal 15, one of the plurality of terminals, via the solder joint area 30 (S1a). The controlling semiconductor chip 23 is connected to the fourth terminal 14, one of the plurality of terminals, via the electrically conductive connection area 33 (S1b). The electrically conductive connection area 33 can be a solder joint area or it can be the first electrically conductive bonding area 35. The electronic element 25, such as a rectifying semiconductor chip, is connected to the first terminal 11, one example of the plurality of terminals, via the first electrically conductive bonding area 35 (S1c).

[0052] The first electrode 28a and the second electrode 28b of the chip capacitor 27 are connected by the second electrically conductive bonding region 37 to the first terminal 11 and the second terminal 12, respectively, which are contained in the plurality of terminals (S1d). As in Fig. Figure 10 shows in particular the application of an electrically conductive adhesive 37a to the first surface 11s of the first terminal 11 and the second surface 12s of the second terminal 12 (S1e) by a screen printing process or a distribution process, such as an inkjet process. The electrically conductive adhesive 37a contains the second resin and the second electrically conductive filler, which is dispersed in the second resin.

[0053] The first electrode 28a and second electrode 28b of the chip capacitor 27 are then positioned at the first terminal 11 and the second terminal 12, respectively (S1f). The electrically conductive adhesive 37a is pressed through the chip capacitor 27 and expanded. The electrically conductive adhesive 37a cures to form the second electrically conductive bonding region 37, which connects the first electrode 28a and the second electrode 28b of the chip capacitor 27 to the first terminal 11 and the second terminal 12, respectively (S1g). The second electrically conductive bonding region 37 (the electrically conductive adhesive 37a) contains a second proportion of the electrically conductive filler. The second proportion is greater than the first.

[0054] As in Fig. As shown in Figure 9, the second electrically conductive bonding region 37 can extend to a first edge region 11b of the first terminal 11 and a second edge region 12p of the second terminal 12. The second electrically conductive bonding region 37 does not extend beyond the first region 11p of the first terminal 11 and the second edge region 12p of the second terminal 12. The first edge region 11p of the first terminal 11 and the second edge region 12p of the second terminal 12 are arranged such that they face each other and, in a top view of the first surface 11s of the first terminal 11 and the second surface 12s of the second terminal 12, are located below the chip capacitor 27.

[0055] The second electrically conductive bonding region 37 on the first region 11r and the second region 12r is connected to a main body region of the chip capacitor 27, with the exception of the first electrode 28a and the second electrode 28b. The first region 11r is a region of the first surface 11s of the first terminal 11 facing the chip capacitor 27, and this region is located between the first electrode 28a and the first edge region 11b of the first terminal 11. The second region 12r is a region of the second surface 12s of the second terminal 12 facing the chip capacitor 27, and this region is located between the second electrode 28b and the second edge region 12p of the second terminal 12. The first region 11r and the second region 12r are located below the main body region of the chip capacitor 27.

[0056] Step S1e can comprise the application of the electrically conductive adhesive 37a to the majority of first areas on the first surface 11s of the first terminal 11 and the majority of second areas on the second surface 12s of the second terminal 12, as shown in Fig. Figure 10 shows that step S1f can involve arranging the first electrode 28a of the chip capacitor 27 on the electrically conductive adhesive 37a at first regions and placing the second electrode 28b of the chip semiconductor 27 on the electrically conductive adhesive 37a at second regions. The chip capacitor 27 presses and expands the electrically conductive adhesive 37a. Since the electrically conductive adhesive 37a is supplied to the first regions at the first terminal 11 and to the second regions at the second terminal 12, the electrically conductive adhesive 37a is prevented from extending beyond the first edge region 11p and the second edge region 12p when the chip capacitor 27 presses and expands the electrically conductive adhesive 37a. The second electrically conductive bonding region 37 is prevented from extending beyond the first edge region 11p and the second edge region 12p.Therefore, the deterioration of insulation reliability can be prevented even more reliably.

[0057] At the in Fig. In contrast, in the power semiconductor module shown in Figure 11 of a comparative example, the electrically conductive bonding area 37 (electrically conductive adhesive 37a) extends beyond the first edge area 11p or the second edge area 12p. Due to an excessively small minimum distance G between the second electrically conductive bonding area 37 at the first terminal 11 and the second electrically conductive bonding area 37 at the second termination 12, the insulation reliability of the power semiconductor module decreases.

[0058] The electrically conductive conductor 29 is then bonded to the power semiconductor chip 20, the plurality of terminals including the first termination 11, the second termination 12 and the third termination 13, the controlling semiconductor chip 23 and the electronic element 25. The electrically conductive conductor 29 is bonded using a conductor bonder.

[0059] With reference to the Fig. 6 , Fig. 12 and Fig. Figure 13 comprises the method for manufacturing the power semiconductor module 1, which includes sealing the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) by the sealing element 40 (S2). Specifically, the conductor frame 10, to which the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) are connected, is placed in the mold 45. A sealing resin is introduced into the cavity 45a of the mold 45 using an injection molding or compression molding process. The electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) are sealed by the sealing element 40.The frame area 10a, the connection connection area 18 and the foreground areas (for example, first foreground area 11c, second foreground area 12c and third foreground area 15c) of the majority of connections are exposed on the sealing element 40.

[0060] The shortest distance between a region 46a of form 45, from which the first terminal 11 protrudes, and the chip capacitor 27 can be equal to or less than five times the thickness of the first terminal 11. The shortest distance d between a region 46b of form 45, from which the second terminal 12 protrudes, and the chip capacitor 27 can be equal to or less than five times the thickness t of the second terminal 12. When a force is applied to a plate element having a fixed end, the deflection of the plate element is generally proportional to the cube of the length of the plate element extending from the fixed end and inversely proportional to the cube of the thickness of the plate element. As the length of the first terminal 11 extending into the space 45a of form 45 decreases, the deflection of the first terminal 11 decreases.Since the length of the second connection 12, which extends into the space 45a of the shape 45, decreases, the bending of the second connection 12 decreases. This suppresses the occurrence of delamination and cracking in the second electrically conductive bonding area 37, thus improving the reliability of the electrical connection of the second electrically conductive bonding area 37.

[0061] With reference to Fig. Section 6 of the method for manufacturing the power semiconductor module 1 includes processing the conductor frame 10 (S3). In particular, the frame section 10a and the connection section 18 are removed. A portion of the majority of the protruding sections of the majority of connections (for example, a portion of the protruding section of the third connection 13 and the fourth connection 14) may be further removed. A portion of the majority of the protruding sections (for example, the first protruding section 11c, the second protruding section 12c, and the third protruding section 15c of the majority of connections) are bent. In this way, the Fig. 1 power semiconductor module 1 shown.

[0062] In a modification of the present invention, the following is covered, as in Fig. Figure 14 shows that the electrically conductive bonding region 37 covers 80% or more and 100% or less of the first region 11r of the first terminal 11, which exists below the chip capacitor 27, and it covers 80% or more and 100% or less of the second region 12r of the second terminal 12, which exists below the chip capacitor 27. In the present description, 80% or more and 100% or less of the first region 11r means that 80% or more and 100% or less of the area of ​​the first region 11r in a top view of the first surface 11s of the first terminal 11, which faces the chip capacitor 27. Likewise, 80% or more and 100% or less of the second area 12r of the second terminal 12 means 80% or more and 100% or less of the area of ​​the second area 12r in top view of the second surface 12s of the second terminal 12 facing the chip capacitor 27.

[0063] The second electrically conductive bonding region 37 can cover 90% or more and 100% or less of the first region 11r of the first terminal 11 located below the chip capacitor 27, and it can cover 90% or more and 100% or less of the second region 12r of the second terminal 12 located below the chip capacitor 27. The second electrically conductive bonding region 37 can cover the entire first region 11r of the first terminal 11 located below the chip capacitor 27, and it can cover the entire second region 12r of the second terminal 12 located below the chip capacitor 27.

[0064] The second electrically conductive bonding region 37 of the first region 11r and the second region 12r is connected to the main body part of the chip capacitor 27, with the exception of the first electrode 28a and the second electrode 28b. The second electrically conductive bonding region 37 does not extend beyond the first edge region 11p and the second edge region 12p.

[0065] Thermal stresses arising from the difference between the coefficient of thermal expansion of the second electrically conductive bonding region 37 and the coefficient of thermal expansion of the sealing element 40 act on the second electrically conductive bonding region 37. These thermal stresses are generated, for example, when the sealing element 40 is cooled after the step of casting the sealing resin to form the sealing element 40. The second electrically conductive bonding region 37 at the first region 11r and the second region 12r is connected to the main body region of the chip capacitor 27, with the exception of the first electrode 28a and the second electrode 28b, but is not in contact with the sealing element 40.Thus, the electrically conductive bonding region 37, the first region 11r, and the second region 12r increase the volume of the electrically conductive bonding region 37 without increasing the thermal stresses. Therefore, the thermal stresses per unit volume of the second electrically conductive bonding region 37 decrease. The occurrence of cracks in the second electrically conductive bonding region 37 is suppressed. Thus, the reliability of the electrical connection of the second electrically conductive bonding region 37 can be increased.

[0066] As in the modification of the present embodiment, the second electrically conductive bonding area 37, which covers 80% or more and 100% or less of the first area 11r and 80% or more and 100% or less of the second area 12r and which does not extend beyond the first edge area 11p and the second edge area 12p, can be simply formed by supplying the electrically conductive adhesive 37a to the first areas at the first 11s of the first terminal 11 and to the second areas at the second surface 12s of the second terminal 12, as shown in Fig. 10 is shown.

[0067] With reference to Fig. Section 15 below describes a method for manufacturing the semiconductor device 2 of the present embodiment. The method for manufacturing the semiconductor device 2 comprises preparing the power semiconductor module 1 (S11). The power semiconductor module 1 is prepared by the method for manufacturing the power semiconductor module 1 of the present invention.

[0068] The method for manufacturing the semiconductor device 2 comprises mounting the power semiconductor module 1 onto the printed circuit board 51 (S12). In particular, the two aforementioned areas of the plurality of connections (for example, the fourth aforementioned area 12e of the second connection 12 and the sixth aforementioned area 15e of the fifth connection 15) are inserted into the plurality of through-holes (for example, through-holes 52 and 53) in the printed circuit board 51. In the power semiconductor module 1, the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) are packaged in a dual in-line package (DIP) configuration.Therefore, the foreground areas of the majority of connections (for example, the fourth foreground area 12e of the second connection 12 and the sixth foreground area 15e of the fifth connection 15) are soldered to the majority of conductors (for example, conductors 54 and 55) on the circuit board 51. In this way, the Fig. 5 Semiconductor device 2 shown.

[0069] The following is an explanation of the effect of the power semiconductor module 1 of the present invention and the method for its manufacture.

[0070] The power semiconductor module 1 of the present invention comprises a plurality of terminals, the power semiconductor chip 20, the chip capacitor 27, the electronic element 25 of a type different from the chip capacitor 27, and the sealing element 40. The plurality of terminals comprises the first terminal 11 and the second terminal 12, which is spaced apart from the first terminal. The chip capacitor 27 comprises the first electrode 28a and the second electrode 28b. The sealing element 40 seals the power semiconductor chip 20, the chip capacitor 27, and the electronic element 25. The power semiconductor chip 20 is connected to at least one of the plurality of terminals (for example, the fifth terminal 15). The electronic element 25 is connected to one of the plurality of terminals (for example, the first terminal 11) through the first electrically conductive bonding region 35.The first electrically conductive bonding region 35 contains a first amount of electrically conductive filler. The first electrode 28a and the second electrode 28b of the chip capacitor 27 are connected to the first terminal 11 and the second terminal 12, respectively, by the second electrically conductive bonding region 37. The second electrically conductive bonding region 37 contains a second amount of electrically conductive filler. The second amount is greater than the first amount.

[0071] The power semiconductor module 1 of the present invention comprises a plurality of terminals, the power semiconductor chip 20, the chip capacitor 27, the electronic element 25 of a type different from the chip capacitor 27, and the sealing element 40. The plurality of terminals includes the first terminal 11 and the second terminal 12, which is spaced apart from the first terminal 11. The chip capacitor 27 comprises the first electrode 28a and the second electrode 28b. The sealing element 40 seals the power semiconductor chip 20, the chip capacitor 27, and the electronic element 25. The power semiconductor chip 20 is connected to at least one of the plurality of terminals (for example, the fifth terminal 15). The electronic element 25 is connected to one of the plurality of terminals (for example, the first terminal 11) through the first electrically conductive bonding region 35.The electrically conductive bonding region 35 contains the first electrically conductive filler. The first electrode 28a and the second electrode 28b of the chip capacitor 27 are connected to the first terminal 11 and the second terminal 12, respectively, by the second electrically conductive bonding region 37. The second electrically conductive bonding region 37 contains the second electrically conductive filler. The second electrically conductive bonding region has a specific electrical resistance that is lower than that of the first electrically conductive bonding region.

[0072] The second electrically conductive bonding region 37 has a lower specific electrical resistance than the first electrically conductive bonding region 35. If the second electrically conductive filler is made of the same material as the first electrically conductive filler, the second content of electrically conductive filler in the second electrically conductive bonding region 37 is greater than the first content of electrically conductive filler in the first electrically conductive bonding region 35. This allows for a greater difference between the electrical resistance of the second electrically conductive bonding region 37 and the permissible electrical resistance required for the connection area of ​​the chip capacitor 27.Even if stresses applied to the second electrically conductive bonding region 37 cause partial delamination and / or cracking in the second electrically conductive bonding region 37, the increase in electrical resistance in the second electrically conductive bonding region 37 can be reduced. Thus, the reliability of the electrical connection of the second electrically conductive bonding region 37 can be improved. The power semiconductor module 1 of the present embodiment exhibits high reliability.

[0073] Since the first content of the electrically conductive filler in the electrically conductive bonding region 35 is lower than the second content of the electrically conductive filler in the second electrically conductive bonding region 37, the first electrically conductive bonding region 35 is also more cost-effective. According to the power semiconductor module 1 of the present embodiment, the power semiconductor module 1 has reduced costs.

[0074] The tallest chip capacitor 27 among the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25), which is connected to the majority of terminals, is connected to the first terminal 11 and the second terminal 12 via the second electrically conductive bonding area 37 without using electrically conductive conductors 29. Thus, the height of the power semiconductor module 1 can be reduced. According to the power semiconductor module 1 of the present invention, the power semiconductor module 1 can have a reduced size.

[0075] In the power semiconductor module 1 of the present embodiment, the second electrically conductive bonding region 37 covers 80% or more and 100% or less of the first region 11r of the first terminal 11, which exists below the chip capacitor 27, and it covers 80% or more and 100% or less of the second region 12r of the second terminal 12, which exists below the chip capacitor 27. The first region 11r is a region of the first surface 11s of the first terminal 11, which faces the chip capacitor 27, and this region is arranged between the first electrode 28a and the first edge region 11p of the first terminal 11. The second area 12r is an area of ​​the second surface 12s of the second terminal 12 facing the chip capacitor 27, and it is an area located between the second electrode 28b and the edge area 12p of the second terminal 12.The first edge region 11p and the second edge region 12p are arranged facing each other and are located below the chip capacitor 27, as seen from a top view of the first surface 11s of the first terminal 11 and the second surface 12s of the second terminal 12. The second electrically conductive bonding region 37 of the first region 11r and the second region 12r is connected to the main body region of the chip capacitor 27, except for the first electrode 28a and the second electrode 28b. The second electrically conductive bonding region 37 does not extend beyond the first edge region 11b and the second edge region 12p.

[0076] Thermal stresses per unit volume of the second electrically conductive bonding area 37 are then reduced. These stresses arise from the difference between the coefficient of thermal expansion of the second electrically conductive bonding area 37 and the coefficient of thermal expansion of the sealing element 40. The formation of cracks in the second electrically conductive bonding area 37 is suppressed. Therefore, the deterioration of the reliability of the power semiconductor module 1 can be prevented. The reliability of the electrical connection of the second electrically conductive bonding area 37 can be improved.

[0077] The method for manufacturing a power semiconductor module according to the present invention comprises connecting the power semiconductor chip to at least one of the plurality of terminals (S1a). The plurality of terminals comprises the first terminal 11 and the second terminal 12, which is spaced apart from the first terminal 11. The method for manufacturing a power semiconductor module according to the present invention comprises connecting the electronic element 25 to one of the plurality of terminals through the first electrically conductive bonding region 35 (S1c). The first electrically conductive bonding region 35 contains the first portion of the electrically conductive filler. The method for manufacturing a power semiconductor module according to the present invention comprises supplying the electrically conductive adhesive 37a to the first regions of the first terminal 11 and the second regions of the second terminal 12 (S1e).The method for manufacturing a power semiconductor module of the present invention comprises arranging the first electrode 28a of the chip capacitor 27 on the electrically conductive adhesive 37 at the first regions and arranging the second electrode 28b of the chip capacitor 27 on the electrically conductive adhesive 37a at the second regions (S1f). The chip capacitor 27 is of a different type than the electronic element 24. The method for manufacturing a power semiconductor module of the present invention comprises curing the electrically conductive adhesive 37a to form the second electrically conductive bonding region 37, which connects the first electrode 28a and the second electrode 28b of the chip capacitor 27 to the first terminal 11 and the second terminal 12, respectively (S1g). The second electrically conductive bonding region 37 contains the second amount of electrically conductive filler. The second amount is greater than the first amount.The method for manufacturing a power semiconductor module of the present embodiment comprises sealing the power semiconductor chip 20, the chip capacitor 27 and the electronic element 25 by the sealing element 40 (S2).

[0078] The second electrically conductive bonding region 37 can be easily formed at half or more of the first region 11r and half or more of the second region 12r, provided that the second electrically conductive bonding region 37 does not extend beyond the first edge region 11p and the second edge region 12p. This more reliably prevents the deterioration of the insulation reliability of the power semiconductor module 1 and improves the reliability of the electrical connection of the second electrically conductive bonding region 37. Second embodiment

[0079] With reference to Fig. Section 16 describes a power semiconductor module 1b of the second embodiment below. The power semiconductor module 1b of the present embodiment is similar to the power semiconductor module 1 of the first embodiment in terms of its configuration and function, but differs from it essentially in the following respects.

[0080] In the power semiconductor module 1b, at least some of the multiple terminals comprise protruding areas that extend beyond the sealing element 40. These protruding areas are each curved in the shape of a gull's wing. For example, the first terminal 11 comprises the protruding area 11c (in Fig. 16 (not shown), which projects from the delay element 40. The second connection 12 comprises a second projecting area 12c, which projects from the sealing element 40. The fifth connection 15 comprises a third projecting area 15c, which projects from the sealing element 40. The first projecting area 11c, second projecting area 12c, and third projecting area 15c are each curved in the shape of a gull's wing.

[0081] The plurality of terminals comprises a plurality of terminal areas extending along a plurality of pads (for example, a first pad 11a, a second pad 12a, a third pad 14a, a fourth pad 15a). For example, the first projecting area 11c of the first terminal 11 further comprises a seventh projecting area (not shown), in addition to the first projecting area 11d and the second projecting area 11e (see Fig. 1) The seventh projecting section extends from the second projecting section 11e in the direction opposite to the first projecting section 11d and in the direction horizontal to the first projecting section 11d. The seventh projecting section is curved relative to the second projecting section 11e. The seventh projecting section acts as the first connection section of the first connection 11. The second projecting section 12c of the second connection 12 further comprises an eighth projecting section 12f, in addition to the third projecting section 12d and the fourth projecting section 12e. The eighth projecting section 12f extends from the fourth projecting section 12e in the direction opposite to the third projecting section 12d and in the direction horizontal to the third projecting section 12d. The eighth projecting section 12f is curved relative to the fourth projecting section 12e.The eighth preceding area 12f acts as the second connection area of ​​the second connection 12.

[0082] The third projecting region 15c of the fifth terminal 15 further comprises a ninth projecting region 15f, in addition to the fifth projecting region 15d and the sixth projecting region 15e. The ninth projecting region 15f extends from the sixth projecting region 15e in the direction opposite to the fifth projecting region 15d and in the direction horizontal to the fifth projecting region 15d. The ninth projecting region 15f is curved relative to the sixth projecting region 15e. The ninth projecting region 15f acts as the third terminal region of the fifth terminal 15. In the power semiconductor module 1b, the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) are packaged in a small outline package (SOP). The power semiconductor module 1b is a surface-mount module.

[0083] The method for fabricating the power semiconductor module 1b of the present embodiment comprises the same steps as the method for fabricating the power semiconductor module 1 of the first embodiment (see Fig. 6), however, differs from this with respect to the following points. According to the method for manufacturing the semiconductor module 1b, in step (S3) of processing the conductor frame 10, the protruding areas (for example, the first protruding area 11c, the second protruding area 12c, and the third protruding area 15c) of the plurality of terminals are each bent into a gull wing shape. A plurality of terminal areas (for example, the seventh protruding area, the eighth protruding area 12f, and the ninth protruding area 15f) are formed on the protruding areas of the plurality of terminals. The plurality of terminal areas extends along the pads (for example, the first pad 11a, the second pad 12a, the third pad 14a, and the fourth pad 15a). In this way, the Fig. 16 power semiconductor module 1b shown.

[0084] With reference to Fig. Section 17 describes below a semiconductor device 2b of the second embodiment. The semiconductor device 2b of the present embodiment is similar in configuration under the influence of the semiconductor device 2 of the first embodiment, but differs from it essentially in the following points.

[0085] The semiconductor device 2b comprises a power semiconductor module 1b and a printed circuit board 51 having a plurality of conductors (for example, conductors 54 and 55). The plurality of conductors are formed on a first main surface 51a of the printed circuit board 51. The connection areas of the plurality of connections are connected to the conductors by solder joint areas. In particular, the seventh projecting area (not shown) of the first connection 11 is connected to a conductor (not shown) by a solder joint area (not shown). The eighth projecting area 12f of the second connection 12 is connected to the conductor 54 by a connection area 57. The ninth projecting area 15f of the fifth connection 15 is connected to the conductor 55 by a solder joint area 58.

[0086] The following is an explanation of a method for manufacturing the semiconductor device 2b of the present embodiment. The method for manufacturing the semiconductor device 2b of the present embodiment comprises the same steps as the method for manufacturing the semiconductor device 2 of the first embodiment (see Fig. 15), however, differs from this in essential respects with regard to the following points.

[0087] In the power semiconductor module 1b, the electronic components (power semiconductor chip 20, control semiconductor chip 23, chip capacitor 27, and electronic element 25) are packaged in a Small Outline Package (SOP). When the power semiconductor module 1b is mounted on the printed circuit board 51 by reflow soldering, the majority of the connection areas (for example, the eighth protruding area 12f and the ninth protruding area 15f) are soldered to the conductors (for example, conductors 54 and 55) on the printed circuit board 51. In this way, the Fig. The semiconductor device 2b shown in Figure 17 is obtained. Reflow soldering in the present embodiment results in the package reaching a higher temperature during soldering, and the soldering process taking longer than in the first embodiment. When the power semiconductor module 1b is mounted on the circuit board 51 by reflow soldering, greater thermal stresses are exerted on the second electrically conductive bonding area 37.

[0088] The second electrically conductive bonding region 37, however, exhibits a lower specific electrical resistance than the first electrically conductive bonding region 35. If the second electrically conductive filler is made of the same material as the first electrically conductive filler, the content of the second electrically conductive filler in the second electrically conductive bonding region 37 is greater than the content of the first electrically conductive filler in the first electrically conductive bonding region 35. This allows for an increase in the difference between the electrical resistance in the second electrically conductive bonding region 37 and the permissible electrical resistance that is generally required for the connection area of ​​the chip capacitor 27.Even if the stresses applied to the second electrically conductive bonding region 37 cause partial delamination and / or cracking in the second electrically conductive bonding region 37, the increase in electrical resistance in the second electrically conductive bonding region 37 can be reduced. The reliability of the electrical connection of the second electrically conductive bonding region 37 can be improved. The power semiconductor module 1b of the present embodiment exhibits high reliability. Third embodiment

[0089] With reference to Fig. Section 18 describes a power semiconductor module 1c of the third embodiment below. The power semiconductor module 1c of the present embodiment is similar to the power semiconductor module 1 of the first embodiment in terms of configuration and function, but differs from it mainly in the following points.

[0090] The power semiconductor module 1c further comprises a heat distribution plate 60. At least one of the plural terminals (the fifth terminal 15) comprises a third surface 15s facing the power semiconductor chip 20 and a fourth surface 15t on a side opposite the third surface 15s. The heat distribution plate 60 is attached to the fourth surface 15t. The heat distribution plate 60 is made of a material, such as copper or aluminum, which has high thermal conductivity. The heat distribution plate 60 has a heat distribution surface 61 that is exposed on the sealing element 40. The heat distribution surface 61 serves to efficiently distribute heat generated in the power semiconductor chip 20 to the outside of the power semiconductor module 1c. The heat distribution surface 61 can be flush with a surface 42 of the sealing element 40.The majority of surfaces of the heat distribution plate 60, which differ from the heat distribution surface 61, can face the sealing element 40.

[0091] The heat distribution plate 60 is integrated with the sealing element 40. For example, the heat distribution plate 60 can be integrated with the sealing element 40 by encapsulating the heat distribution plate 60 together with the electronic components (power semiconductor chip 20, controlling semiconductor chip 23, chip capacitor 27, electronic element 25) and the majority of connections within the sealing element 40. Alternatively, the heat distribution plate 60 can be integrated with the sealing element 40 by fitting the heat distribution plate 60 into a recessed area formed in the sealing element 40. The heat distribution plate 60 can also be integrated with the sealing element 40 by attaching the heat distribution plate 60 to the sealing element 40 using a fixing element, such as a screw.

[0092] In particular, the power semiconductor module 1c can further comprise an insulating layer 62. The heat distribution plate 60 can be attached to the fourth surface 15t by interposing the insulating layer 62. The insulating layer 62 can be an insulating resin layer in which insulating particles with high thermal conductivity are distributed. The insulating particles can each be made of an inorganic material, such as silicon dioxide, aluminum oxide, or aluminum nitride. The insulating resin layer can also be, for example, an epoxy resin layer. The heat distribution plate 60 can be insulated at the majority of its connections by the sealing element 40 and the insulating layer 62.

[0093] The following is an explanation of the effect of the power semiconductor module 1c of the present embodiment.

[0094] The power semiconductor module 1c of the present embodiment further comprises the heat distribution plate 60. At least one of the plurality of terminals (the fifth terminal 15) comprises the third surface 15s, which is assigned to the power semiconductor chip 20, and the fourth surface 15t on the side opposite the third surface 15s. The heat distribution plate 60 is attached to the fourth surface 15t. The heat generated by the power semiconductor chip 20 is thus efficiently transferred to the outside of the power semiconductor module 1c via the heat distribution plate 60.

[0095] The power semiconductor chip 20 and at least one of the plurality of connections (the fifth connection 15) exist between the sealing element 40 and the heat distribution plate 60. The sealing element 40 and the heat distribution plate 60 have different coefficients of thermal expansion. In the power semiconductor module 1c of the present embodiment, the number of connections therefore bends more than in the power semiconductor module 1 of the first embodiment, and greater thermal stresses are exerted on the second electrically conductive bonding area 37.

[0096] However, the second electrically conductive bonding region 37 exhibits a lower specific electrical resistance than the first electrically conductive bonding region 35. In the case where the second electrically conductive filler is made of the same material as the first electrically conductive filler, the content of the second electrically conductive filler in the second electrically conductive bonding region 37 is greater than the required content of the first electrically conductive filler in the first electrically conductive bonding region of the chip semiconductor 27. Even if voltages applied to the second electrically conductive bonding region 37 cause delamination and / or cracking in the second electrically conductive bonding region 37, the increase in electrical resistance in the second electrically conductive bonding region 37 can be reduced.The reliability of the electrical connection of the second electrically conductive bonding region 37 can be improved. The power semiconductor module 1c of the present embodiment exhibits high reliability. Fourth embodiment

[0097] The present embodiment is obtained by applying the power semiconductor modules 1, 1b and 1c according to one of embodiments 1 to 3 to a power conversion device. Although the power conversion device 200 of the present embodiment is not specifically restricted, a three-phase inverter is used in the following explanation.

[0098] A in Fig. The power conversion system shown in Figure 19 consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a direct current (DC) power supply and provides DC power to the power conversion device 200. The power supply 100 is not restricted in any particular way and could, for example, consist of a DC system, a solar cell, or a storage battery; or it could consist of a rectifier circuit connected to an alternating current (AC) system; or it could consist of an AC / DC converter. The power supply 100 could consist of a DC / DC converter that converts DC power output by the DC system into DC power.

[0099] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load. The power conversion device 200 converts the DC power supplied by the power supply 100 into AC power and supplies the converted AC power to the load 300. As shown in Fig. As shown in Figure 19, the power conversion device 200 comprises: a main conversion circuit 201, which converts DC power to AC power and outputs the converted AC power, and a control circuit 203, which outputs a control signal to the main conversion circuit 201 for controlling the main conversion circuit 201.

[0100] The Load 300 is a three-phase electric motor powered by AC power supplied by the Power Conversion Device 200. The Load 300 is not specifically limited in its application; it is an electric motor that can be installed in and used in various electrical devices, such as hybrid vehicles, electric vehicles, rail vehicles, elevators, or air conditioning systems.

[0101] The following is an explanation of the details of the power conversion device 200. The main conversion circuit 201 comprises a switching element and a freewheeling diode (neither of which are shown). By switching the voltage supplied by the power supply 10, the main conversion circuit 201 converts the DC power supplied by the power supply 100 into AC power and supplies the converted AC power to the load 300. While the specific circuit configuration of the main conversion circuit 201 can be of various types, the main conversion circuit 201 according to the present embodiment is a three-phase full-bridge circuit configured in two planes, and it can be formed from six switching elements and six freewheeling diodes connected antiparallel to the respective six switching elements.The power semiconductor modules 1, 1b, and 1c can be applied in any of the switching elements and freewheeling diodes of the main conversion circuit 201, according to any of the preceding embodiments 1 to 3. The six switching elements are configured such that two switching elements are connected in series to form an upper arm and a lower arm. Each pair of upper and lower arms forms a corresponding phase (a U-phase, a V-phase, and a W-phase) of a full bridge circuit. The output terminals of the upper and lower arms, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0102] As described in the first embodiment above, the main conversion circuit 201 includes the driver circuit, since a driver circuit (e.g., the controlling semiconductor chip 23) that drives each of the switching elements is contained in a power semiconductor module 202. The driver circuit generates a driver signal to drive each switching element contained in the main conversion circuit 201 and supplies the generated driver signal to the control electrode of each switching element in the main conversion circuit 201. In accordance with the control signal from the control circuit 203, in particular the driver signal to bring each switching element into an ON state and the driver signal to bring each switching element into an OFF state are output to the control electrode of each switching element.When the switching element is held in an ON state, the driver signal is a voltage signal (an ON signal) that is equal to or greater than a threshold voltage of the switching element. When the switching element is held in an OFF state, the driver signal is a voltage signal (ON / OFF signal) that is equal to or less than the threshold voltage of the switching element.

[0103] The control circuit 203 controls each switching element in the main conversion circuit 201 to supply the desired electrical power to the load 300. Specifically, the time (ON time) at which each switching element of the main conversion circuit 201 is to be switched to the ON state is calculated based on the electrical power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by pulse width modulation (PWM) to modulate the ON time of each switching element according to the output voltage. A control command (control signal) is then issued to the driver circuit contained in the main conversion circuit 201, so that an ON signal is issued to the switching element to be switched to the ON state at any given time, and an OFF signal is issued to the switching element to be switched to the OFF state at any given time.In accordance with this control signal, the driver circuit outputs an ON signal or an OFF signal as a driver signal to the control electrode of each switching element.

[0104] In the power conversion circuit 200 according to the present embodiment, the power semiconductor modules 1, 1b and 1c according to one of embodiments 1 to 3 are applied to the power semiconductor module 202, which is included in the main conversion circuit 201. Thus, the power conversion circuit 200 according to the present embodiment exhibits high reliability.

[0105] The present embodiment has been described with reference to the examples in which the present invention is applied to a three-phase converter configured in two levels; however, the present invention is not limited thereto and can be applied to various types of power converter devices. In the present embodiment, the power converter device is configured in two levels, but the power converter device can be configured in three levels or more. Even in the case where the power converter device supplies electrical power to a single-phase load, the present invention can be applied to a single-phase converter. In the case where the power converter device supplies electrical power to a DC load or the like, the present invention is also applicable to a DC / DC converter or an AC / DC converter.

[0106] The power conversion device to which the present invention is applied is not limited to cases where the load is limited to an electric motor; rather, it can be used in a power supply device for an electric discharge machine or a laser beam machine, or it can be used in a power supply device for an induction heating cooking machine or a contactless power supply system. The power conversion device to which the present invention is applied can also be used as a power controller for a solar power generation system, a power storage system, or the like. Reference symbol list 1, 1b, 1c Power semiconductor module; 2, 2b Semiconductor device; 10 connection frames; 10a Framework area; 10b Opening; 11 first connection; 11a first pad; 11c first preceding section; 11d first preceding section; 11e second preceding section; 11p first edge area; 11r first area; 11s first surface; 12 second connection; 12a second pad; 12c second preceding section; 12d third preceding section; 12e fourth preceding section; 12f eighth preceding area; 12p second edge area; 12r second area; 12s second surface; 13 third connection; 14 fourth connection; 14a third pad; 15 fifth connection; 15a fourth connection; 15b tiered area; 15c third preceding section; 15d fifth preceding section; 15e sixth preceding section; 15f ninth preceding section; 15s third surface; 15t fourth surface; 16a first through hole; 16b second through hole; 17 plated area; 18 Connection area; 20 power semiconductor chips; 23 controlling semiconductor chip; 25 electronic element; 25a Diode; 25Ω resistance; 27 Chip capacitor; 28a first electrode; 28b second electrode; 29 electrically conductive conductor; 30 solder joint area; 33 electrically conductive connection area; 35 first electrically conductive bonding area; 37 second electrically conductive bonding area; 37a electrically conductive adhesive; 40 sealing element; 41a, 41b area; 42 surface area; 45 Form; Sections 46a and 46b; 51 printed circuit board; 51a first main surface; 51b second main surface; 52, 53 Through hole; 54, 55 ladder; 57, 58 Solder joint area; 60 Heat distribution plate; 61 Heat distribution surface; 62 Insulating layer; 100 Benefit provision; 200 power conversion device; 201 Main conversion circuit; 202 Power semiconductor module; 203 Control circuit; 300 Last.

Claims

[1] Power semiconductor module (1, 1b, 1c), comprising: a plurality of connections (11, 12, 13, 14, 15) comprising a first connection (11) and a second connection (12) spaced apart from the first connection (11); a power semiconductor chip (20); a chip capacitor (27) having a first electrode (28a) and a second electrode (28b); an electronic element (25) which differs in type from the chip capacitor (27); and a sealing element (40) to seal the power semiconductor chip (20), the chip capacitor (27) and the electronic element (25), wherein the power semiconductor chip (20) is connected to at least one of the terminals (11, 12, 13, 14, 15), wherein the electronic element (25) is connected to the first terminal (11) by a first electrically conductive bonding region (35) which contains a first content of an electrically conductive filler, and wherein the first electrode (28a) and the second electrode (28b) of the chip capacitor (27) are connected to the first terminal (11) and the second terminal (12) respectively by a second electrically conductive bonding area (37) which is a hardened, electrically conductive adhesive and contains a second content of the electrically conductive filler, wherein the second content is greater than the first content. [2] Power semiconductor module (1, 1b, 1c), comprising: a plurality of connections (11, 12, 13, 14, 15) comprising a first connection (11) and a second connection (12) spaced apart from the first connection (11); a power semiconductor chip (20); a chip capacitor (27) having a first electrode (28a) and a second electrode (28b); an electronic element (25) which differs in type from the chip capacitor (27); and a sealing element (40) to seal the power semiconductor chip (20), the chip capacitor (27) and the electronic element (25), wherein the power semiconductor chip (20) is connected to at least one of the terminals (11, 12, 13, 14, 15), wherein the electronic element (25) is connected to the first terminal (11) by a first electrically conductive bonding region (35) which contains a first electrically conductive filler, wherein the first electrode (28a) and the second electrode (28b) of the chip capacitor (27) are connected to the first terminal (11) and the second terminal (12) respectively by a second electrically conductive bonding area (37) which is a hardened, electrically conductive adhesive and contains a second electrically conductive filler, and wherein the second electrically conductive bonding region (37) has a lower specific electrical resistance than the first electrically conductive bonding region (35). [3] Power semiconductor module (1, 1b, 1c) according to claim 1 or 2, wherein the first electrically conductive bonding region (35) further contains insulating particles made of an insulating inorganic material. [4] Power semiconductor module (1, 1b, 1c) according to claim 3, wherein the insulating particles are each made of one or more inorganic materials selected from the group consisting of silicon oxide, aluminum oxide and aluminum nitride. [5] Power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 4, wherein the first terminal (11) has a first through-hole (16a), wherein the second connection (12) has a second through-hole (16b), and wherein the first through-hole (16a) and the second through-hole (16b) are filled with the sealing element (40). [6] Power semiconductor module (1, 1b, 1c) according to claim 1, wherein the second content is 75 wt.% or more. [7] Power semiconductor module (1, 1b, 1c) according to claim 1, wherein the first content is 65 wt.% or less. [8] Power semiconductor module (1, 1b, 1c) according to claim 1, wherein the electrically conductive filler is made of one or more electrically conductive materials selected from the group consisting of silver, nickel and copper. [9] Power semiconductor module (1, 1b, 1c) according to claim 2, wherein the first electrically conductive filler is made of one or more electrically conductive materials selected from the group consisting of silver, nickel and copper, and wherein the second electrically conductive filler is formed of one or more electrically conductive materials selected from the group consisting of silver, nickel and copper. [10] Power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 9, wherein the first terminal (11) has a first surface (11s) that is assigned to the first electrode (28a), and the second terminal (12) has a second surface (12s) that is assigned to the second electrode (28b), and wherein the first surface (11s) and the second surface (12s) are made of copper or tin. [11] Power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 10, wherein the first electrode (28a) and the second electrode (28b) are made of copper or tin. [12] Power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 11, wherein the electrical element (25) is a rectifying semiconductor chip. [13] Power semiconductor module (1, 1b, 1c) according to claim 12, wherein the rectifying semiconductor chip includes a resistor (25b), and wherein the rectifying semiconductor chip containing the resistor (25b) and the chip capacitor (27) form a bootstrap circuit. [14] Power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 13, wherein the second connection (12) comprises a projecting area (12c) that projects from an area (41b) of the sealing element (40), and wherein a shortest distance between the area (41b) of the sealing element (40) and the chip capacitor (27) is equal to or less than five times the thickness of the second terminal (12). [15] Power semiconductor module (1b) according to any one of claims 1 to 13, wherein at least part of the terminals (11, 12, 13, 14, 15) comprise a plurality of projecting areas (11c, 12c) that project from the sealing element (40), and wherein the projecting areas (11c, 12c) are each bent into a gull wing shape. [16] Power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 9, wherein the second electrically conductive bonding area (37) covers 80% or more and 100% or less of a first area (11r) of the first terminal (11) that exists below the chip capacitor (27), and 80% or more and 100% or less of a second area (12r) of the second terminal (12) that exists below the chip capacitor (27), wherein the first region (11r) is a region contained in a first surface (11s) of the first terminal (11) facing the chip capacitor (27) and located between the first electrode (28a) and a first edge region (11p) of the first terminal (11), wherein the second region (12r) is a region contained in a second surface (12s) of the second terminal (12) which faces the chip capacitor (27) and is located between the second electrode (28b) and a second edge region (12p) of the second terminal (12), wherein the first edge region (11p) and the second edge region (12p) are arranged such that they assign to each other and, as seen in a top view of the first surface (11s) of the first terminal (11) and the second surface (12s) of the second terminal (12), are arranged below the chip capacitor (27), wherein the second electrically conductive bonding region (37) is connected to the first region (11r) and the second region (12r) with a region of the chip capacitor (27) excluding the first electrode (28a) and the second electrode (28b), and wherein the second electrically conductive bonding region (37) does not extend beyond the first edge region (11p) and the second edge region (12p). [17] Power semiconductor module (1c) according to any one of claims 1 to 16, further comprising a heat distribution plate (60), wherein at least one of the terminals (11, 12, 13, 14, 15) has a third surface (15s) facing the power semiconductor chip (20) and a fourth surface (15t) on a side opposite the third surface (15s), and wherein the heat distribution plate (60) is attached to the fourth surface (15t). [18] Power conversion device (200), comprising: a main conversion circuit (201) for converting received electrical power and outputting the converted electrical power, wherein the main conversion circuit (201) comprises the power semiconductor module (1, 1b, 1c) according to any one of claims 1 to 17; and a control circuit (203) to output a control signal to the main conversion circuit (201) for controlling the main conversion circuit (201). [19] Method for manufacturing a power semiconductor module (1, 1b, 1c) comprising: Connecting a power semiconductor chip (20) to at least one of a plurality of terminals (11, 12, 13, 14, 15), wherein the terminals (11, 12, 13, 14, 15) comprise a first terminal (11) and a second terminal (12) spaced apart from the first terminal (11); Connecting an electronic element (25) to the first terminal (11) by means of a first electrically conductive bonding area (35) which contains a first content of electrically conductive filler; Supplying an electrically conductive adhesive (37a) to a plurality of first areas at the first terminal (11) and a plurality of second areas at the second terminal (12); Arranging a first electrode (28a) of a chip capacitor (27) on the electrically conductive adhesive (37a) at the first areas and arranging a second electrode (28b) of the chip capacitor (27) on the electrically conductive adhesive (37a) at the second areas, wherein the chip capacitor (27) is different in type from the electronic element (25); Curing of the electrically conductive adhesive (37a) to form a second electrically conductive bonding area (37) that connects the first electrode (28a) and the second electrode (28b) of the chip capacitor (27) to the first terminal (11) and the second terminal (12), respectively, wherein the second electrically conductive bonding region (37) contains a second content of the electrically conductive filler, the second content being greater than the first content; and Sealing the power semiconductor chip (20), the chip capacitor (27) and the electronic element (25) by a sealing element (40).

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