Semiconductor structure and method for producing a resistive storage device with vertically predefined filament

Abstract

Method for producing a semiconductor structure (100) containing at least one resistive memory cell (802), wherein the method comprises: Forming a dielectric layer (702) on inner sidewalls of a cell contact hole (302) over a cavity (602) in a semiconductor structure, wherein a rim (704) is formed in the dielectric layer between the inner sidewalls of the cell contact hole, wherein the rim is doped with conductive material; Forming a lower electrode (902) within a portion of the cavity, wherein the lower electrode is in contact with an upper surface of an electrical target contact (124) and with a lower surface of the dielectric layer and a lower surface of the rim; and Forming an upper electrode (1004) above the dielectric layer and in direct contact with an upper surface of the dielectric layer and an upper surface of the rim.

Description

BACKGROUND

[0001] The present invention relates generally to the field of semiconductors and in particular to a method for manufacturing resistive memory units.

[0002] Resistive random access memory (ReRAM) is a type of non-volatile memory whose operating principle is based on a resistance difference between on and off states. Conductive bridging memory (CBRAM) is another type of non-volatile memory whose operating principle is based on a resistance difference between on and off states. In this type of non-volatile memory, a high resistance and a low resistance are defined depending on the physical connection of several nanoscale filaments between an upper and a lower electrode of each memory cell.

[0003] One problem with this type of non-volatile memory, such as ReRAM or CBRAM, is that it is impossible to predict where and how many filaments will form in each memory cell. Therefore, the operation of such non-volatile memory can be uneven and unpredictable from cell to cell, resulting in poor overall performance. Due to the uncertainty of filament formation in each memory cell compared to another, the operational reliability of the non-volatile memory is significantly impaired.

[0004] In this context, several documents already exist. Document US 2016 / 0196874A1 describes random access memory cells in the form of RRAM cells for storing information with a plurality of programmable cell states. Document US 2011 / 0193044A1 describes a resistive memory and its fabrication, including a filament. Additionally, document US 9570678B1 describes a non-volatile memory device with multiple dielectrics and a second electrode containing half-particles capable of diffusing into a boundary region. Additionally, document US 2014 / 0217482A1 describes a method for fabricating an integrated circuit with a dielectric interlayer over a dummy gate stack. Furthermore, document US 2019 / 0229264A1 describes a random access storage device with a conductive bridge (CBRAM - Conductive Bridge Random Access Memory).

[0005] Nevertheless, the problem of unpredictable filament formation in the memory cell, as described above, persists. The task remains to solve this problem. BRIEF SUMMARY OF THE INVENTION

[0006] This problem is solved by the manufacturing processes according to claims 1 and 18, and by the semiconductor structure according to claim 12. Further embodiments are specified by the respective dependent claims.

[0007] Various embodiments of the present invention include fabricating a semiconductor structure containing at least one resistive memory cell (also referred to as a resistive memory element). For example, a method and a structure include forming at least one resistive memory cell in a semiconductor structure. The method comprises: forming a sacrificial layer on and in contact with an electrical contact of a transistor; forming a first dielectric layer over and in contact with the sacrificial layer; forming a cell contact hole through the first dielectric layer and exposing a first portion of the sacrificial layer; forming an access contact hole through the first dielectric layer and exposing a second portion of the sacrificial layer; and removing the remaining portion of the sacrificial layer to form a cavity directly connecting a lower opening of the cell contact hole and a lower opening of the access contact hole.Forming a second dielectric layer on the inner sidewalls of the first contact hole above the cavity, wherein a rim or gap is formed in the second dielectric layer between the inner sidewalls of the cell contact hole; forming a lower electrode within a portion of the cavity, wherein the lower electrode is in contact with an upper surface of the electrical contact and with a lower surface of the second dielectric layer and a lower surface of the rim; and forming an upper electrode above the dielectric layer and in direct contact with an upper surface of the second dielectric layer and an upper surface of the rim.

[0008] In various embodiments, a semiconductor structure comprises at least one memory cell containing a transistor and a resistor. The semiconductor structure includes: a transistor comprising a drain, a gate, and a source; and a vertical resistive element of the memory having first and second electrical contacts. The first or the second of the electrical contacts is electrically connected to the drain of the transistor.

[0009] The vertical resistive element of the memory according to an exemplary embodiment includes a vertically oriented rim located near a central region along the length of the vertical resistive element of the memory, extending from the first electrical contact to the second electrical contact. In an exemplary embodiment, the vertically oriented rim comprises a conductive filament extending from the first electrical contact to the second electrical contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying figures, in which the same reference numerals denote identical or functionally similar elements in the different views, and which are included in the description along with the detailed description below and form a part thereof, serve to further illustrate various embodiments and to explain various basic ideas and advantages according to the present invention, wherein: Fig. 1 a lateral sectional view of an exemplary semiconductor structure at a first point of an exemplary manufacturing process, such as for the manufacture of resistive memory units, according to an embodiment of the present invention; Fig. 2 a side sectional view of the exemplary semiconductor structure of Fig. 1 at a subsequent point of the exemplary manufacturing process; Fig. 3 A side sectional view of the exemplary semiconductor structure of Fig. 2 at a subsequent step of the exemplary manufacturing process after forming a vertical cell contact hole; Fig. 4 A side sectional view of the exemplary semiconductor structure of Fig. 3 at a subsequent step of the exemplary manufacturing process after forming a vertical access contact hole; Fig. 5 a top view of the in Fig. The semiconductor structure shown in section 4 is; Fig. 6 A side sectional view of the exemplary semiconductor structure of Fig. 4 at a subsequent step of the exemplary manufacturing process after removal of the a-Si layer; Fig. 7 A side sectional view of the exemplary semiconductor structure of Fig. 6 at a subsequent step of the exemplary manufacturing process after performing atomic layer deposition of dielectric material that fills the vertical cell contact hole and forms a rim; Fig. 8 a side sectional view of the exemplary semiconductor structure of Fig. 7 at a subsequent point of the exemplary manufacturing process; Fig. 9 a side sectional view of the exemplary semiconductor structure of Fig. 8 at a subsequent step of the exemplary manufacturing process after forming a lower electrode of a resistive storage cell; Fig. 10 A side sectional view of the exemplary semiconductor structure of Fig. 9 at a subsequent step of the exemplary manufacturing process after forming an upper electrode of the resistive storage cell; and Fig. 11 is a workflow plan illustrating an exemplary manufacturing process for producing a semiconductor structure containing a resistive memory cell according to an embodiment of the present invention. DETAILED DESCRIPTION

[0011] It should be noted that the present invention is described with reference to illustrative, exemplary manufacturing processes for the fabrication of semiconductor structures containing field-effect transistor semiconductor units and / or other types of transistors. However, other semiconductor architectures, structures, substrate materials, and process elements and steps can be varied within the scope of the present invention.

[0012] The inventors have discovered that it is highly desirable to have a resistive memory (ReRAM), including a conductive bridging memory (CBRAM), which forms a single filament at a predetermined position in a resistive memory cell.

[0013] Various embodiments of the present invention include a new and novel architecture for a semiconductor structure comprising at least one non-volatile memory unit. The memory unit comprises, for example, a plurality of resistive memory cells (hereinafter also referred to as resistive memory elements) on the same semiconductor substrate on a wafer. This structure can be used, for example, to fabricate non-volatile CMOS memory units in an integrated circuit.

[0014] It is important to note that when an element such as a layer, area, or substrate is described as "on," "above," or "on top" of another element, it may be located directly "on," "above," or "on top" of the other element, but there may also be elements in between. A similar but reversed meaning applies to an element such as a layer, area, or substrate described as "under" or "below" another element. It may be located directly "under" or "below" the other element, but there may also be elements in between. Conversely, when an element is described as "directly on," "directly above," or "directly top" of another element, or alternatively, "directly under" or "directly below" another element, there are no elements in between.Furthermore, it should be noted that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to that other element, or there may be intervening elements. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0015] The present embodiments can include a design for a chip with an integrated circuit, which can be generated in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard disk, or virtual hard disk, such as in a storage access network). If the designer does not manufacture chips or the photolithographic masks used for chip production, the designer can transmit the resulting design directly or indirectly to such entities by physical means (e.g., by providing a copy of the storage medium containing the design) or electronically (e.g., via the internet). The stored design is then converted into the appropriate format (e.g.,GDSII) is converted for the production of photolithographic masks, which typically contain multiple copies of the corresponding blueprint for the chip to be formed on a wafer. The photolithographic masks are used to define areas of the wafer (and / or the layers on it) to be etched or otherwise processed.

[0016] The methods described herein can be used as part of a process in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (i.e., a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic substrate with traces attached to a motherboard or other higher-level support) or in a multi-chip package (such as a ceramic substrate having one or both of surface or buried interconnects). In each case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing units as part of (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input device and a central processing unit.

[0017] In the description, references to "an embodiment" or "a form of embodiment" of the present basic ideas, as well as other variations thereof, mean that a particular element, structure, feature, and so forth, described in connection with the embodiment, is included in at least one embodiment of the present basic ideas. Thus, the appearance of the expression "in an embodiment" or "according to an embodiment," as well as any other variations, at different points in the description does not necessarily always refer to the same embodiment.

[0018] It should be noted that the various layers and / or regions shown in the accompanying drawings are not to scale, and that one or more layers and / or regions of a type commonly used in complementary metal-oxide-semiconductor (CMOS), field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and / or other semiconductor devices need not be explicitly shown in any given drawing. This does not mean that the layers and / or regions not explicitly shown are omitted in the actual devices. Furthermore, certain elements may be omitted in certain views for the sake of clarity and / or simplicity, where explanations are not necessarily focused on the omitted elements.Furthermore, the same or similar reference numerals are used in the drawings to denote the same or similar features, elements or structures, so that a detailed explanation of the same or similar features, elements or structures is not repeated for each of the drawings.

[0019] The semiconductor devices and methods for manufacturing them according to various embodiments of the present invention can be used in applications in hardware and / or electronic systems. Suitable electronic hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state storage devices, functional circuits, etc. Systems and hardware containing the semiconductor devices and structures are considered embodiments of the invention.

[0020] Various embodiments of the present invention can be implemented in conjunction with semiconductor devices and related semiconductor fabrication processes that may employ CMOS, MOSFET, and / or FET technology. Non-limiting examples of semiconductor devices may include, but are not limited to, CMOS, MOSFET, and FET devices and / or semiconductor devices that employ CMOS, MOSFET, and / or FET technology.

[0021] As used herein, "vertical" means a direction perpendicular to a substrate in any of the sectional and three-dimensional views shown herein. Current may be described herein as flowing in a vertical direction (e.g., between a lower electrode of a vertically oriented resistive storage cell and an upper electrode of the vertically oriented resistive storage cell, positioned above the lower electrode). As used herein, "horizontal" means a direction parallel to a substrate in any of the sectional and three-dimensional views shown herein.

[0022] As used herein, “thickness”, “thick” or the like refers to a size of an element (e.g., a layer, trench, hole, etc.) in a sectional view, measured from a bottom surface to an top surface or from a left side surface to a right side surface of the element and / or measured relative to a surface directly adjacent to and in contact with the element (e.g., a surface on which the element is directly placed).

[0023] Furthermore, the terms "width" or "width value" and the like denote a distance from a starting point on a structure to an endpoint on the same structure in a critical dimension. For example, a width value could be measured horizontally along a critical dimension from a starting point of a vertical contact metal structure to an endpoint of the same vertical contact metal structure.

[0024] Unless otherwise specified, when used herein, "height" or "height above a substrate" refers to the vertical dimension of an element (e.g., a layer, trench, hole, etc.) in a sectional view, measured from a top surface of the substrate to a top surface of the element. An element's thickness may be equal to its height if the element is positioned directly on the substrate.

[0025] As used herein, the terms “side”, “side side”, “side surface” refer to a side surface of an element (e.g., a layer, an opening, a side wall spacer, etc.), such as a left or right side surface in a sectional view shown herein.

[0026] Now we turn to the drawings Fig. 1, Fig. 2, Fig. 3 to Fig. References are made to Figure 4, in which identical reference numbers represent identical or similar elements and the side sectional views of the depicted semiconductor structure 100 are at selected points of an exemplary manufacturing process. The in Fig. The line 5-5 shown in section 4 runs over a part of the depicted semiconductor structure 100 and corresponds to one in Fig. 5 Top view of the depicted semiconductor structure 100. Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. Figure 10 shows lateral sectional views of the semiconductor structure 100 shown at the following selected points of the exemplary manufacturing process.

[0027] The in Fig. The exemplary semiconductor structure 100 shown in Figure 1 is used in the present explanation to illustrate an exemplary semiconductor manufacturing process according to different embodiments of the invention.

[0028] As in Fig. As shown in Figure 1, in an exemplary semiconductor manufacturing process, a transistor integration manufacturing process forms a transistor supported on a circuit carrier substrate 102. The transistor contains a gate stack which, as shown in Figure 1, forms a transistor on a circuit carrier substrate 102. Fig. Figure 1 shows that the transistor is arranged between and adjacent to a corresponding plurality of source / drain stacks. The gate stack and the plurality of source / drain stacks are formed in a dielectric layer 108, which is supported by the circuit carrier substrate 102. It should be noted that a transistor is a non-limiting example of a type of memory cell selector unit used in non-volatile working memories to select at least one memory cell. Other types of memory cell selector units can also be used according to various embodiments of the invention. For example, a diode can also be used as a memory cell selector unit.

[0029] According to various embodiments, the substrate 102 comprises at least one material selected from the following set of materials consisting of: silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), III-V compound semiconductor or II-V compound semiconductor, an organic semiconductor, a layered semiconductor, a silicon-on-insulator, a SiGe-on-insulator, amorphous material, polycrystalline material, single-crystal material or a hybrid-oriented (HOT) semiconductor material or a combination of the materials in this set.

[0030] Each source / drain stack contains a corresponding epitaxial active region 104, 106 in the substrate 102. Each source / drain stack contains a source / drain metal 114, 116 and an upper metal contact 118, 120 arranged above the corresponding source / drain metal 114, 116.

[0031] The gate stack can be arranged above a corresponding ribbed channel in the substrate 102. For example, the ribbed channel is in Fig. 1 is arranged in the substrate 102 below the gate stack and adjacent to and in contact with the two epitaxial active regions 104, 106, and forms a path for the horizontal flow of electric current between the two epitaxial active regions 104 of a transistor. The gate stack in the Fig. The example shown in Figure 1 includes a high K-value dielectric layer 112 and a gate metal contact 110, which is arranged on and in contact with the upper surface of the high K-value dielectric layer 112. Fig. The example shown is representative of an NFET or a PFET transistor. It should be noted that the explanations herein provide non-limiting examples to illustrate various manifestations of the invention. The exemplary transistor described herein does not necessarily represent a real circuit design. The explanation of the exemplary transistor is given merely to illustrate that an exemplary process flow according to an embodiment of the invention could function on one or both NFET and PFET circuit elements.

[0032] A target metal contact (also referred to as an electrical target contact) 124, formed in an interlayer dielectric (ILD) layer 122, is electrically connected in the example to a first drain / source metal contact 114 or a second drain / source metal contact 116, or in various embodiments to a combination of the first set of drain / source metal contacts 114 and 118 or a combination of the second set of drain / source metal contacts 116, 120. In the present example, the target metal contact 124 is connected to a drain contact 116 (e.g., of the second set of drain / source metal contacts 116, 120) of the Fig. The active drain region 106 of the transistor shown in Figure 1 is electrically connected. The target metal contact 124 in this description of an exemplary manufacturing process can also be referred to as the drain contact 124. However, it should be clear that in various embodiments, any combination of metal contacts of the transistor can be electrically coupled to the target metal contact 124.

[0033] Furthermore, a transistor, as explained above, is an exemplary type of memory selector unit that can be used in various embodiments. Other types of selector units can also be used alternatively or additionally to select at least one memory cell in a non-volatile memory unit. In general, a selector unit contact will be electrically connected to the target metal contact 124. The selector unit can be electrically controlled to select a specific memory cell in a non-volatile memory unit.

[0034] Fig. Figure 1 illustrates one step in the exemplary semiconductor fabrication process, in which a semiconductor material stack 102, 108, 122, containing the substrate 102, the gate stack, and the plurality of drain / source stacks, has been provided. Subsequently, as shown in Fig. Figure 1 shows that a sacrificial layer 126 of amorphous silicon (a-Si) is deposited on the ILD layer 122, which is arranged on the dielectric layer 108, followed by a planarization process, such as a chemical and / or mechanical planarization (CMP) step, or an etching step, which removes excess material from a top surface of the a-Si sacrificial layer in the semiconductor structure 100 and, optionally, excess material from a top surface of a wafer. The a-Si layer 126 can also be referred to as a sacrificial layer 126, since this a-Si layer 126 will be removed in subsequent steps of the fabrication process.

[0035] The a-Si layer 126 is then processed as in Fig. 2 shown structured into a circular (or rectangular or other) shape. A silicon dioxide (SiO2) layer 202, which can also be referred to as an ILD layer 202 or as a first dielectric layer 202, is structured as shown in Fig. 2 shown deposited on an upper surface of the structured a-Si layer 126 and in contact with it. The first dielectric layer 202 comprises, in various embodiments, at least one dielectric material selected from the following set of dielectric materials: silicon nitride (SiN), silicon carbide (SiC), SiCO, silicon oxide, silicon dioxide (SiO2), carbon-doped silicon oxide (SiCOH), one or more silicon-based materials in which some or all of the Si is replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon-based materials, organo-inorganic materials, such asCentrifugally cast glasses and materials based on silsesquioxane, diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H), or any of the aforementioned materials in porous form or in a form which changes during processing to or from porous and / or permeable to non-porous and / or impermeable.

[0036] As in Fig. As shown in Figure 3, a vertically oriented cell contact hole 302, which may also be referred to as a vertical cell contact hole 302 or the like, is formed in the SiO2 layer 202 (also referred to as an ILD layer 202) extending over and down to a lower surface of the a-Si layer 126 or extending slightly through the a-Si layer 126. A vertically oriented etching process, such as, but not limited to, a dry etching process or a reactive ion etching (RIE) process using a fluoride-based chemistry, or another etching method, may be used to form the vertically oriented cell contact hole 302. In this example, the vertically oriented cell contact hole 302 exposes the drain contact 124 within the vertical cell contact hole 302. The cell contact hole 302 is located above the drain contact 124, but not necessarily directly above it (e.g. vertically aligned with the drain contact 124).The cell contact hole 302 can be arranged in the a-Si layer 126 at a horizontal position that is close to, but not necessarily directly above, the horizontal position of the drain contact 124.

[0037] As in Fig. As shown in Figure 4, in the manufacturing process a vertically oriented access contact hole 402, which may also be referred to herein as a vertical access contact hole 402 or the like, is subsequently structured in the SiO2 layer 202 (which may also be referred to as the ILD layer 202 or the first dielectric layer 202 or the like) directly above a lower surface of the a-Si sacrificial layer 126 and partially into or through it. The horizontal critical dimension (CD) of the vertically oriented access contact hole 402 can be much larger than the horizontal CD of the vertically oriented cell contact hole 302. The vertically oriented access contact hole 402 can be structured by a vertical etching process, such as…, but not limited to, a dry etching process or a reactive ionic etching (RIE) process using a fluoride-based chemistry or another etching process.

[0038] The vertically oriented access contact hole 402 creates an access opening into the a-Si sacrificial layer 126, wherein the access opening 402 can have a horizontal CD that is much larger than the horizontal CD of the vertically oriented cell contact hole 302. This vertically oriented access contact hole 402 can be used, for example, to enable an etching process for removing the a-Si sacrificial layer 126, in order to, after removal of the a-Si sacrificial layer 126, as in Fig. Figure 6 shows a cavity opening or hollow space 602. The vertically oriented access contact hole 402 also allows access to the cavity opening or hollow space 602 in subsequent steps of the manufacturing process. As explained in more detail below, in various embodiments, the vertically oriented access contact hole 402 allows access to the cavity opening or hollow space 602 to insert a lower electrode 902 of a vertical storage cell 802 (see Figure 6). Fig. 8, Fig. 9 and Fig. 10), which is formed in the vertically oriented cell contact hole 302.

[0039] It should be noted that the formation of the vertically oriented access contact hole 402 and the formation of the vertically oriented cell contact hole 302 are described separately above, but the formation of these two holes 302, 402 can be carried out simultaneously or separately in different embodiments.

[0040] Fig. Figure 5 shows a top view of the semiconductor structure 100 at this point in the exemplary semiconductor manufacturing process. In this example, the vertical access contact hole 402 and the vertical cell contact hole 302 are located horizontally close to each other, with both situated directly above the a-Si sacrificial layer 126.

[0041] As in Fig. As shown in Figure 6, in the exemplary semiconductor fabrication process, the a-Si sacrificial layer 126 is subsequently completely removed by a selective isotropic etching process. A selective wet etching process can be performed, for example, by an isotropic etching process. If necessary, the etching could be carried out by another suitable wet or dry etching process. The selective etching leaves a cavity 602 (which can also be referred to as a void 602 or the like) from which material of the a-Si sacrificial layer 126 has been removed. This void 602 connects a lower opening of the vertically oriented cell contact hole 302 and a lower opening of the vertically oriented access contact hole 402.

[0042] As in Fig. As shown in Figure 7, the exemplary semiconductor fabrication process continues with the atomic layer deposition (ALD) of dielectric material 702 onto exposed surfaces (e.g., the dielectric material 702 is deposited and formed on the inner sidewalls of the vertical cell contact hole 302) of the semiconductor structure 100. Successive thin films of the dielectric material 702, each approximately 15 nm thick in one example, are progressively deposited and formed onto the exposed surfaces of the semiconductor structure 100. In this example, the formed dielectric material 702 fills the vertical cell contact hole 302. See also Fig. 8.

[0043] The dielectric material 702, which in this example fills the vertical cell contact hole 302, contains a vertical rim 704 near a central region (horizontally centered with respect to the side walls of the vertically oriented cell contact hole 302) of a vertical memory cell 802 (see e.g. Fig. 8 and Fig. 10, which represent the manufacture of the vertical memory cell 802, which is in Fig. 10 having an upper electrode 1004 and a lower electrode 902). The dielectric material 702 (which may also be referred to as a second dielectric layer 702) may, for example, comprise a metal with an oxide. As another example, the second dielectric layer 702 may comprise a metal with a nitride. In various embodiments, the second dielectric layer 702 comprises at least one dielectric material selected from the following set of dielectric materials consisting of: metal oxide, metal nitride, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), carbon-doped silicon nitride (SiCN), and boron-doped silicon carbonitride (SiBCN), or any combination of the aforementioned dielectric materials.

[0044] As in Fig. As shown in Figure 7, in the present example, the dielectric material 702 is deposited as a thin film onto exposed surfaces in the cavity 602, onto exposed surfaces in the vertical cell contact hole 302 (e.g., onto inner sidewalls of the vertical cell contact hole 302), onto exposed surfaces in the vertical access contact hole 402 (e.g., onto inner sidewalls of the vertical access contact hole 402), and onto exposed surfaces on the upper surfaces of the semiconductor structure 100 using an ALD process. The thickness of each thin film of dielectric material 702 deposited by an ALD process can be approximately 15 nm in this example. However, other layer thicknesses can be applied in various embodiments. The thin films of dielectric material 702 are progressively deposited and formed successively onto the exposed surfaces of the semiconductor structure 100.In this example, after the successive deposition of thin films, the thickness of the total deposited thin film of dielectric material 702 will increase until it reaches a total thin film thickness that is more than about half the diameter of the vertical cell contact hole 302. The thin-film deposition process adds layer upon layer of dielectric material 702 until it blocks further deposition of thin films of dielectric material 702 in the vertical cell contact hole 302. Furthermore, this thin-film deposition process forms a vertical rim 704 in the layer of dielectric material 702 in the vertical cell contact hole 302.

[0045] As a result of the ALD process and / or another thin-film deposition process, a vertical rim 704 is formed in the second dielectric layer 702 in the vertical cell contact hole 302, filling the vertical cell contact hole 302 with progressively deposited, successive layers of dielectric material 702. In this example, the vertical rim 704 is formed near a central region (horizontally centered with respect to the side walls of the vertically oriented cell contact hole 302) of the dielectric material 702 to fill the vertical cell contact hole 302. See also the in Fig. 8 shown vertical memory cell 802, which contains the centrally arranged vertical seam 704.

[0046] In the present example, an ALD process is used because it reliably forms a uniform rim in the center of the vertical cell contact hole 302. While in the present example, as explained above, an ALD process is used to deposit the thin films of dielectric material 702 and to form the vertical rim 704, alternatively or additionally, other thin-film deposition processes can be used to deposit thin films of the dielectric material 702 and / or to form the vertical rim 704. One example of a deposition process that can be used is a chemical vapor deposition (CVD) process. Another example of a deposition process that can be used is a physical vapor deposition (PVD) process.

[0047] An ALD process that can be used for the progressive deposition of successive layers of dielectric material 702 filling the vertical cell contact hole 302 can, for example, be a thermal ALD process. As another example, the ALD process can be a plasma-assisted ALD process. In various embodiments, the layer of dielectric material 702 filling the vertical cell contact hole 302 comprises at least one dielectric material selected from the following set of dielectric materials: metal oxide, metal nitride, silicon dioxide (SiO2), silicon nitride (SiN), carbon-doped silicon oxide nitride (SiOCN), carbon-doped silicon nitride (SiCN), boron- and carbon-doped silicon nitride (SiBCN), or any combination of the aforementioned dielectric materials.

[0048] The vertical rim 704 is formed by the ALD process near a central region (horizontally centered with respect to the side walls of the vertically oriented cell contact hole 302) of the dielectric material 702, which in this example fills the vertical cell contact hole 302. In various embodiments, this vertical rim 704 can be doped with conductive material to form a single conductive (e.g., resistive) filament at a known position running vertically inside from an upper electrode 1004 to a lower electrode 902 of a vertical storage cell 802 (see Fig. 8 and Fig. 10, which show the manufacture of the vertical memory cell 802, which is in Fig. 10 contains an upper electrode 1004 and a lower electrode 902).

[0049] This arrangement with a single conductive (resistive) filament can confer significant advantages to non-volatile memory, e.g., resistive RAM (ReRAM), including conductive bridging RAM (CBRAM). In various embodiments, a non-volatile memory unit can be manufactured such that the operation from memory cell to memory cell across the memory cells in the non-volatile memory unit is reliably uniform. This results in improved overall performance of the non-volatile memory unit. The arrangement with a single filament for each vertical memory cell 802 (see Fig. 8 and Fig. 10) provides certainty regarding filament formation and the operation of the unit in a non-volatile memory device. The operational reliability of such a non-volatile memory device, e.g., a ReRAM memory device, is significantly improved. This, in turn, substantially increases the marketability of this type of resistive non-volatile memory device and the associated semiconductor manufacturing process.

[0050] As in Fig. As shown in Figure 8, in the exemplary semiconductor fabrication process, the excess dielectric material 702 is subsequently removed, if necessary, from the cavity 602, from the vertical access contact hole 402, and from the upper surfaces of the semiconductor structure 100. An isotropic dry or wet etching process, or a combination of dry and wet etching processes, can be used to remove the excess dielectric material 702. The dielectric material 702 that filled the vertical cell contact hole 302 is not removed. As shown in Fig. As shown in Figure 8, an upper surface and a lower surface of the vertical rim 704 are exposed near a central region (horizontally centered with respect to the side walls of the vertically oriented cell contact hole 302) of the vertical memory cell 802 at an upper opening and a lower opening of the vertical cell contact hole 302. In various embodiments, this vertical rim 704 can be doped with conductive material to form a single conductive (e.g., resistive) filament at a known position within the vertical memory cell 802 (see Figure 8). Fig. 8) to form in the vertical cell contact hole 302.

[0051] Doping of the 704 filament with a mobile element (e.g., a metallic mobile species), such as copper (Cu) or silver (Ag), can be performed to improve the switching characteristics of the 704 filament in the vertical memory cell 802. This doping can, for example, inject metallic mobile species into the 704 filament to promote its formation. There are various methods for performing the doping of the 704 filament. For example, doping can be carried out using a dopant-containing electrode 902 or 1004.

[0052] As a further example, doping can also be performed according to the exemplary manufacturing process. Fig. 9 and before Fig. 10 will be carried out. With regard to Fig. 10. Dopant material can be deposited after the formation of the dielectric plug material 1002 and forced into the seam 704 by heat annealing. After the dopant has been forced into the seam 704, the dopant is removed from the surface to leave dopant only in the seam 704.

[0053] As below with reference to Fig. As explained in section 10, an upper electrode 1004 (see Fig. 10) of the vertical storage cell 802 directly on and in contact with an upper surface of the vertical storage cell 802 and an upper surface of the vertical rim (and filament) 704. In various embodiments, the upper electrode 1004 can also be a dopant for doping a mobile element (e.g., metallic mobile species) into the vertical rim (and filament) 704. For example, in certain embodiments, after depositing and contacting a metal, such as copper (Cu), on and with the upper surface of the vertical rim (and filament) 704 to form an upper electrode 1004 for the vertical storage cell 802, copper atoms can diffuse downwards and migrate from the upper electrode 1004 into the vertical rim (and filament) 704.

[0054] As in Fig. As shown in Figure 9, conductive material 902 can be deposited in the vertically oriented access contact hole 402 to fill the cavity 602 under the vertical storage cell 802 (see Figure 9). Fig. 8) to fill and come into contact with a lower surface of the vertical memory cell 802 and the vertical rim 704 to form a lower electrode 902 for the vertical memory cell 802. The lower electrode 902 for the vertical memory cell 802 is formed directly on and in contact with an upper surface of the target metal contact 124 (e.g., the drain contact 124 of the transistor). The conductive material 902 can partially (or completely) fill the vertical access contact hole 402, and excess conductive material 902 can, as shown in Fig. 9, shown, can be deposited directly onto and in contact with the upper surfaces of the semiconductor structure 100. The deposition of the conductive material 902 can be carried out by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, another conductive material deposition method, or a combination of methods that allows the conductive material 902 to fill the cavity 602 beneath the vertical memory cell 802 (see Figure 9). Fig. 8) fills and thereby forms the lower electrode 902 for the vertical storage cell 802.

[0055] As in Fig. As shown in Figure 10, in the exemplary semiconductor fabrication process, the conductive material 902 is subsequently removed from the vertical access contact hole 402 and from the upper surfaces of the semiconductor structure 100. For example, a dry etching process, such as a reactive ion etching (RIE) process using a fluoride-based chemistry, can etch the conductive material 902 vertically from the vertical access contact hole 402. The dry etching process, optionally in combination with a suitable wet etching process, can be used to remove the conductive material 902 from the upper surfaces of the semiconductor structure 100. A gap filler of dielectric material in the vertical access contact hole 402 forms a plug of dielectric material 1002 that fills the vertical access contact hole 402.The lower electrode 902 remains in electrical contact with the lower surface of the vertical memory cell 802, with the lower surface of the vertical rim 704 and with an upper surface of the target metal contact 124 (e.g., the drain contact 124 of the transistor).

[0056] As in Fig. As shown in Figure 10, in the exemplary semiconductor fabrication process, the subsequent deposition of conductive material is carried out, optionally followed by structuring, which forms an upper electrode 1004 above the dielectric layer 702 and above and in direct contact with an upper surface of the vertical rim 704 (see the in Figure 10). Fig. 8 shown vertical memory cell 802). In the exemplary manufacturing process, the upper electrode 1004 is in contact with an upper surface of the vertical rim (and filament) 704 near a central area (horizontally centered with respect to side walls of the vertically oriented cell contact hole 302) of the vertical memory cell 802.

[0057] The upper electrode 1004 (see Fig. 10) The vertical storage cell 802, which is formed directly on and in contact with an upper surface of the vertical seam (and filament) 704, can also serve as a dopant for adding a mobile element (e.g., a metallic mobile species) to the vertical seam (and filament) 704. For example, in certain embodiments, after deposition of conductive material, such as, but not limited to, copper (Cu) or silver (Ag) or another metal, onto the upper surface of the vertical rim (and filament) 704 to form the upper electrode 1004, the atoms of conductive material (e.g., copper atoms) can diffuse downwards and migrate from the upper electrode 1004 into the vertical rim (and filament) 704 to dope the vertical rim (and filament) 704 with atoms of conductive material (e.g., copper atoms).

[0058] In addition to using the upper electrode 1004 (and / or the lower electrode 902) as the dopant, a conductive material can be used as a dopant for doping the vertical slit (and filament) 704 in a doping process. The conductive material can be added as part of an overall semiconductor fabrication process as the dopant for doping the vertical slit (and filament) 704 by a separate doping process, as explained above. By way of example, and not limited to, conductive material for doping the vertical slit (and filament) 704 can comprise a mobile element (e.g., metallic mobile species) or a non-stoichiometric compound by adding reactive elements, or a combination thereof.A non-stoichiometric compound is a compound containing amounts of reactants that are not present in a simple integer ratio or in the ratio expected from an ideal formula or equation. For example, TiO₂ is a stoichiometric titanium dioxide. In contrast, TiOx, where x is less than or greater than 2, is considered a non-stoichiometric titanium oxide.

[0059] As a further example, the vertical seam 704 can be doped with a conductive material selected from the following set of materials: metal oxide, non-conductive metal nitride, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), and lanthanum (La). The seam 704 can accordingly contain material selected from the following set of materials: metal oxide, non-conductive metal nitride, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), and lanthanum (La). As a further example, the seam 704 can be doped with at least one mobile element and a non-stoichiometric compound by adding reactive elements.

[0060] In various embodiments, the second dielectric layer 702, formed by the ALD process in the vertically oriented cell contact hole 302 to create a vertical resistive element of the memory 802, comprises at least one material selected from the following set of materials: metal oxide, non-conductive metal nitride, silicon oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, silicon oxycarbonitride (SiOCN), carbon-doped silicon nitride (SiCN), and silicon-boron-carbon nitride (SiBCN), or any combination of the aforementioned materials. The second dielectric layer 702 formed may also comprise a material selected from the following set of materials: metal oxide, non-conductive metal nitride, aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), silicon (Si), germanium (Ge), copper (Cu), and lanthanum (La).

[0061] In various embodiments, at least one of the upper electrode 1004 and the lower electrode 902 (see Fig. 10) a conductive material selected from the following set of conductive materials consisting of: copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), nickel (Ni), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conductive metallic composite material, and a conductive metal alloy containing at least one of the aforementioned conductive materials. In various embodiments, the vertical rim 704 may comprise a single conductive filament 704 extending from the upper electrode 1004 to the lower electrode 902.

[0062] Fig.Figure 11 illustrates an exemplary method 1100 for fabricating a semiconductor structure comprising a vertical memory cell electrically connected to a transistor unit on a substrate. Different embodiments of the invention may include some, but not necessarily all, of the process steps in the illustrative example.

[0063] The exemplary fabrication process begins at step 1102 and proceeds immediately to step 1104 to obtain a semiconductor substrate material stack containing a substrate 102 supporting a gate stack and a first and second source / drain stack of a transistor. The gate stack is located adjacent to and between the first and second source / drain stacks in a dielectric layer 108. The gate stack contains a gate metal contact 110. The first source / drain stack contains a drain metal contact 116, 120. The second source / drain stack contains a source metal contact 114, 118. An ILD layer 122 is located directly above the dielectric layer 108. A target metal contact 124 is located in the ILD layer 122.

[0064] The semiconductor fabrication process continues in step 1106 with the deposition of an a-Si layer 126 directly onto and in contact with the upper surface of the ILD layer 122. The a-Si layer is then structured to form a structured a-Si layer 126 directly onto and in contact with an upper surface of the target metal contact 124 of the transistor. In this example, the target metal contact 124 contains, and is thus electrically coupled to, at least one of the drain metal contacts 116, 120 and the source metal contact 114, 118. A first dielectric layer 202 is then deposited onto the a-Si layer 126. Vertical, direction-dependent etching is then performed to structure both a vertical cell contact hole 302 and a vertical access contact hole 402 through the first dielectric layer 202 and into the a-Si layer 126.In this example, the vertical cell contact hole 302 and the vertical access contact hole 402 are arranged horizontally close to each other directly above the a-Si layer 126.

[0065] The semiconductor fabrication process proceeds at step 1108 with the removal of the a-Si layer 126. Subsequently, ALD (Automatic Laser Deposition) of dielectric material 702 is performed to fill the vertical cell contact hole 302 and form a vertical rim 704 near a central region of a memory cell 802 formed in the vertical cell contact hole 302. The ALD process further deposits dielectric material 702 onto other exposed surfaces in the dielectric structure 100. The semiconductor fabrication process then proceeds with isotropic etching to remove excess dielectric material 702 from the semiconductor structure 100, exposing the rim 704 and leaving a cavity 602 from which the a-Si layer 126 has been removed. The semiconductor fabrication process performs doping of mobile metal species into the rim 704.Conductive material 902 is then deposited into the cavity 602, followed by isotropic etching to form a lower electrode 902 of the memory cell 802. The lower electrode 902 is electrically connected to the upper surface of the target metal contact 124, to the lower surface of the memory cell 802, and to the lower surface of the rim 704.

[0066] The semiconductor manufacturing process continues in step 1110 by depositing a dielectric gap-filling material into the vertical access contact hole 402 to form a dielectric plug 1002. The process then deposits a conductive material layer 1004 onto and into contact with an upper surface of the memory cell 802 and an upper surface of the rim 704, followed by structuring to form an upper electrode 1004 of the memory cell 802.

[0067] The manufacturing process then ends at step 1112.

[0068] The structure of a resistive non-volatile memory unit, e.g., a ReRAM memory unit, according to various embodiments, comprises a plurality of vertical memory cells 802, each memory cell 802 containing a single vertical conductive filament 704. This can significantly improve the operational reliability of the non-volatile memory unit. The operation from memory cell to memory cell can be reliably and uniformly generated across the memory cells in the non-volatile memory unit, resulting in improved overall performance of the non-volatile memory unit. The arrangement with a single filament for each vertical memory cell 802 ensures reliable filament generation and unit operation within the non-volatile memory unit. In various embodiments, this can also reduce defects in the manufacturing process and lower the manufacturing costs of the semiconductor product.This in turn significantly increases the marketability of this type of resistive non-volatile memory device and the associated semiconductor manufacturing process.

Claims

[1] Method for producing a semiconductor structure (100) containing at least one resistive memory cell (802), wherein the method comprises: Forming a dielectric layer (702) on inner sidewalls of a cell contact hole (302) over a cavity (602) in a semiconductor structure, wherein a rim (704) is formed in the dielectric layer between the inner sidewalls of the cell contact hole, wherein the rim is doped with conductive material; Forming a lower electrode (902) within a portion of the cavity, wherein the lower electrode is in contact with an upper surface of an electrical target contact (124) and with a lower surface of the dielectric layer and a lower surface of the rim; and Forming an upper electrode (1004) above the dielectric layer and in direct contact with an upper surface of the dielectric layer and an upper surface of the rim. [2] Method according to claim 1, further comprising: Forming a sacrificial layer (126) on and in contact with the electrical target contact; Forming a second dielectric layer (202) above and in contact with the sacrificial layer; Formation of the cell contact hole through the second dielectric layer and exposure of a first part of the sacrificial layer; Forming an access contact hole (402) through the second dielectric layer and exposing a second part of the sacrificial layer; and Removing remaining portions of the sacrificial layer to form the cavity that directly connects a lower opening of the cell contact hole and a lower opening of the access contact hole. [3] Method according to claim 1, wherein the dielectric layer is formed by atomic layer deposition of dielectric material onto the inner side walls of the cell contact hole above the cavity, and wherein the rim in the dielectric layer is formed by atomic layer deposition of the dielectric material. [4] Method according to claim 1, wherein the hem is vertically oriented and formed near a central region of the dielectric layer between the inner side walls of the cell contact hole above the cavity. [5] Method according to claim 1, wherein the dielectric layer comprises at least one material selected from the following set of materials consisting of metal oxide, non-conducting metal nitride, silicon oxide, silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, carbon-doped silicon nitride and silicon-boron-carbon nitride or any combination of the above-mentioned materials. [6] Method according to claim 1, wherein the dielectric layer comprises at least one material selected from the following set of materials consisting of metal oxide, non-conductive metal nitride, aluminium, hafnium, zirconium, titanium, silicon, germanium, copper and lanthanum. [7] Method according to claim 1, further comprising: Doping the rim with a mobile element or a non-stoichiometric compound by adding reactive elements. [8] Method according to claim 1, wherein the conductive material is selected from a set of conductive materials consisting of: copper, titanium, aluminium, hafnium and lanthanum. [9] Method according to claim 1, wherein the hem has a conductive filament extending from the upper electrode to the lower electrode. [10] Method according to claim 1, wherein a resistive memory cell is produced. [11] Method according to claim 1, wherein at least one of the upper electrode and the lower electrode comprises a conductive material selected from a set of conductive materials consisting of copper, cobalt, aluminium, tungsten, titanium, tantalum, ruthenium, hafnium, zirconium, nickel, platinum, tin, silver, gold, a conductive metallic composite material and a conductive metal alloy containing at least one of the aforementioned conductive materials. [12] Semiconductor structure containing at least one memory cell consisting of a transistor and a resistor, wherein the semiconductor structure has: a target metal contact; and a vertical resistive element of the memory, having first and second electrical contacts and containing a vertically oriented rim extending from the first electrical contact to the second electrical contact, wherein the vertically oriented rim comprises conductive material, wherein one of the first and second electrical contacts is electrically connected to the target metal contact, wherein the vertically oriented rim comprises a conductive material, wherein the conductive material comprises a doped mobile element or a doped non-stoichiometric compound, wherein the semiconductor structure is manufactured according to any one of claims 1 to 11. [13] Semiconductor structure according to claim 12, wherein the vertically oriented rim is arranged near a central region of a length of the vertical resistive element of the memory extending from the first electrical contact to the second electrical contact, and wherein the target metal contact is electrically connected to a memory cell selector unit. [14] Semiconductor structure according to claim 12, wherein the vertically oriented rim comprises at least one material selected from a set of materials consisting of metal oxide, non-conductive metal nitride, copper, titanium, aluminium, hafnium and lanthanum. [15] Semiconductor structure according to claim 12, wherein the vertical resistive element of the memory comprises at least one material selected from a set of materials consisting of metal oxide, non-conductive metal nitride, aluminum, hafnium, zirconium, titanium, silicon, germanium, copper and lanthanum. [16] Semiconductor structure according to claim 12, wherein the vertical resistive element of the memory comprises at least one material selected from a set of materials consisting of metal oxide, metal nitride, silicon dioxide, silicon nitride, silicon oxycarbonitride, carbon-doped silicon nitride or boron-doped silicon carbonitride or any combination of the above-mentioned materials. [17] Semiconductor structure according to claim 12, wherein the vertically oriented rim comprises a single conductive filament extending from the first electrical contact to the second electrical contact. [18] Method for producing a semiconductor structure containing at least one resistive memory cell, wherein the method comprises: Providing a stack of semiconductor material comprising: a substrate (102); a gate stack containing a gate metal contact; a first source-drain stack that has an initial source / drain metal contact; and a second source-drain stack having a second source / drain metal contact, wherein the substrate supports the gate stack and the first and second source-drain stacks; Performing the deposition of a layer (126) of amorphous silicon, a-Si, directly onto and in contact with an upper surface of a target metal contact, wherein the target metal contact is connected with at least one of the first source / drain metal contact or is electrically connected to the second source / drain metal contact; Performing the deposition of an interlayer dielectric layer, ILD layer (122), directly onto and in contact with an upper surface of the a-Si layer; Performing vertical direction-dependent etching in the ILD layer from an upper surface thereto downwards to at least one lower surface thereto to form a vertical cell contact hole in the ILD layer that exposes the a-Si layer in the vertical cell contact hole; Performing vertical direction-dependent etching in the ILD layer from an upper surface thereto downwards to at least one lower surface thereto to form a vertical access contact hole in the ILD layer and to expose the a-Si layer in the vertical access contact hole, wherein the vertical access contact hole is arranged horizontally near the vertical cell contact hole; Performing isotropic etching to remove the a-Si layer and leave a cavity (602) for it; Performing atomic layer deposition of dielectric material that fills the vertical cell contact hole in the ILD layer and forms a vertical rim near the center of a vertical storage cell formed in the vertical cell contact hole, wherein the rim is doped with conductive material; Performing the deposition of conductive material in the vertical access contact hole, filling the vertical access contact hole and the cavity to form a lower electrode of the vertical memory cell directly on and in contact with an upper surface of the target metal contact and in contact with a lower surface of the vertical memory cell and the vertical rim; and Performing the deposition of conductive material on and in contact with an upper surface of the vertical storage cell and the vertical rim to form an upper electrode of the vertical storage cell. [19] Method according to claim 18, wherein the conductive material is selected from a set of conductive materials consisting of: copper, titanium, aluminium, hafnium and lanthanum.

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