Electronic device

Abstract

Electronic device The present description relates to a method for manufacturing an electronic device (10) comprising an interconnection substrate (12) comprising, on the side of an upper connection face (12s), an electrically insulating protective layer (16s), the electrically insulating protective layer (16s) comprising openings leaving accessible metallic electrical connection pads (18s) intended to be soldered or brazed to a connection element (26), the method comprising a step of forming alignment marks (30s) on the surface of the electrically insulating protective layer (16s) of the interconnection substrate (12), on the side of the upper face of the electrically insulating protective layer (16s). Figure for abstract: Fig. 1B

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more specifically to packages for electronic chips. Prior art

[0002] An electronic chip may be mounted in a package comprising an interconnect substrate, on which the chip is mechanically fixed and electrically connected. The mounting of the electronic chip on the interconnect substrate is assisted by an alignment tool, which uses alignment marks formed in the substrate, in order to position the chip precisely at a previously defined location.

[0003] It would be desirable to improve at least in part certain aspects of known electronic devices. Summary of the invention

[0004] For this, one embodiment provides a method for manufacturing an electronic device comprising an interconnection substrate comprising, on the side of an upper connection face, an electrically insulating protective layer, the electrically insulating protective layer comprising openings leaving accessible metallic electrical connection pads intended to be welded or soldered to a connection element, the method comprising a step of forming alignment marks on the surface of the electrically insulating protective layer of the interconnect substrate, on the side of the upper face of the electrically insulating protective layer.

[0005] According to one embodiment, the alignment marks are gold or white.

[0006] According to one embodiment, the alignment marks have a dimension comprised between 150 pm and 500 pm.

[0007] According to one embodiment, the alignment marks are formed by screen printing on and in contact with the electrically insulating protective layer.

[0008] According to one embodiment, the alignment marks are adhesive and in which the formation of the alignment marks comprises a step of transferring a support film, comprising on the side of a lower face the alignment marks, onto the electrically insulating protective layer and a step of removing the support film while leaving on the surface of the electrically insulating protective layer the adhered alignment marks.

[0009] According to one embodiment, the alignment marks are deposited on the surface of the electrically insulating protective layer by taking the alignment marks and then placing them on and in contact with the electrically insulating protective layer.

[0010] According to one embodiment, the formation of the alignment marks comprises a step of transferring a support film, in and / or on which the alignment marks are formed, onto the electrically insulating protective layer, the support film comprising openings making it possible to leave the surface of the interconnection substrate free of access for mounting the connection element.

[0011] According to one embodiment, the method comprises a step of mechanically fixing an electronic chip on the upper connection face of the interconnection substrate.

[0012] According to one embodiment, the method comprises a step of electrically connecting the electronic chip to the interconnection substrate via the electrical connection metal pads and the connection element.

[0013] According to one embodiment, during the step of mechanically fixing the electronic chip, the electronic chip is aligned on the upper connection face of the interconnection substrate using the alignment marks.

[0014] According to one embodiment, the method comprises a step of cutting the electronic device so as to obtain a plurality of electronic components, each electronic component comprising an electronic chip.

[0015] Another embodiment provides an electronic device comprising: - an interconnection substrate comprising, on the side of an upper connection face, an electrically insulating protective layer, the electrically insulating protective layer comprising openings leaving accessible metallic electrical connection pads intended to be welded or soldered to a connection element; and - alignment marks formed on the surface of the electrically insulating protective layer, on the side of the upper face of the electrically insulating protective layer.

[0016] According to one embodiment, the device comprises an electronic chip fixed on the upper connection face of the interconnection substrate and electrically connected to the interconnection substrate via the electrical connection metal pads and the connection element. Brief description of the drawings

[0017] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0018] [Fig.lA], [Fig.lB] and [Fig.lC] are partial and schematic views of an example of an electronic device according to one embodiment;

[0019] [Fig.2A], [Fig.2B], [Fig.3A] and [Fig.3B] are views illustrating steps of an example of a method of manufacturing the electronic device of FIGS. 1A, 1B and 1C;

[0020] [Fig.4A], [Fig.4B], [Fig.5A], [Fig.5B], [Fig.6A] and [Fig.6B] are views illustrating steps of another example of a method of manufacturing the electronic device of FIGS. 1A, 1B and 1C;

[0021] [Fig.7A], [Fig.7B], [Fig.8], [Fig.9A] and [Fig.9B] are views illustrating steps of yet another example of a method of manufacturing the electronic device of FIGS. 1A, 1B and 1C; and

[0022] [Fig.lOA], [Fig.lOB], [Fig.l1A], [Fig.llB], [Fig.l2A] and [Fig.l2B] are views illustrating steps of yet another example of a method of manufacturing the electronic device of Figs. 1A, 1B and 1C. Description of the embodiments

[0023] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the interconnection substrate and its manufacture have not been detailed. Furthermore, the electronic chip and its manufacture have not been detailed, the described embodiments being compatible with all electronic chips.

[0025] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0027] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0028] [Fig.lA], [Fig.lB] and [Fig.lC] are partial and schematic views of an example of an electronic device 10 according to one embodiment.

[0029] More particularly, [Fig.lA] is a top view of the electronic device 10, [Fig.lB] is a sectional view of the electronic device 10 and [Fig.lC] is a bottom view of the electronic device 10, [Fig.lB] being a view along the section plane BB of figures 1A and 1C.

[0030] The electronic device 10 comprises an interconnection substrate 12. The substrate 12 comprises an upper connection face 12s and a lower connection face 12i, opposite the upper connection face 12s. These two faces are for example substantially planar. By way of example, the substrate 12 comprises a polymer material, for example a resin, for example of the epoxy type. By way of example, the substrate 12 further comprises fiberglass, mixed with the polymer material.

[0031] The substrate 12 has, for example, a rectangular shape. The substrate 12 has, for example, dimensions of between 30 mm by 10 mm and 800 mm by 150 mm, for example of between 100 mm by 40 mm and 400 mm by 70 mm, for example of the order of 216 mm by 58 mm.

[0032] The substrate 12 comprises, for example, electrical conductors 14 passing through the polymer material and electrically connecting the upper face 12s to the lower face 12i of the substrate 12. By way of example, the electrical conductors 14 comprise metal levels corresponding to horizontal conductive tracks (in the orientation of [Fig.lB]) and vertical conductive vias. By way of example, the electrical conductors 14 of the substrate 12 are made of copper.

[0033] The substrate 12 comprises, for example, on the side of its lower 12i and upper 12s faces, electrically insulating protective layers 16. The substrate 12 thus comprises a protective layer 16i flush with its lower 12i face and another electrically insulating protective layer 16s flush with its upper 12s face.

[0034] The protective layers 16, also called solder masks or resist varnishes, correspond for example to layers making it possible to protect the upper metal levels of the electrical conductors 14 from oxidation. The protective layers 16 extend for example over the entire surface of the substrate 12. The protective layers 16 are for example locally open, leaving electrical connection conductive pads 18 accessible.

[0035] By way of example, electrical connection pads 18i are present on the side of the lower face 12i of the substrate 12. Similarly, other electrical connection pads 18s are present on the side of the upper face 12s of the substrate 12.

[0036] The electrical connection pads 18 are for example electrically connected to the electrical conductors 14 of the substrate 12. The connection pads 18s of the face upper face 12s of the substrate 12 are thus electrically connected to the connection pads 18i of the lower face 12i of the substrate 12. The electrical connection pads 18 are, for example, made of metal, for example gold.

[0037] The conductive pads 18s make it possible, for example, to electrically connect at least one external element, for example an electronic chip, to the upper face 12s of the substrate 12.

[0038] An electronic chip 20 is for example fixed on the substrate 12 on the side of its upper face 12s. For example, the chip 20 has, in top view, a substantially square shape. Alternatively, the chip 20 has, in top view, a round or rectangular shape. The chip 20 has for example dimensions between 0.2 mm by 0.2 mm and 10 mm by 10 mm, for example between 0.5 mm by 0.5 mm and 5 mm by 5 mm, for example of the order of 1.5 mm by 1.5 mm.

[0039] The chip 20 is for example an integrated circuit chip. The chip 20 comprises for example a semiconductor substrate, for example made of silicon, in and for example on which electronic components are formed.

[0040] The chip 20 is for example mechanically fixed to the substrate 12, for example using a fixing layer 22. The fixing layer 22 corresponds for example to a layer of glue, for example an electrically insulating glue. The fixing layer 22 extends for example under and in contact with the entire lower surface of the chip 20.

[0041] The chip 20 is for example electrically connected to the substrate 12. The electrical connection between the chip 20 and the substrate 12 is for example made by wire bonding between conductive pads 18s, formed on the upper face 12s of the substrate 12, and connection pads 24 of the chip 20 located on the side of the upper face of the chip 20. For example, the connection pads 24 are flush with the upper face of the chip 20. For example, the pads 24 and the pads 18s are connected by electrical cables, or wires, 26. The wires 26 therefore extend from the upper face 12s of the substrate 12 to the upper face of the chip 20. The wires 26 are for example made of gold, silver or copper.

[0042] By way of example, the electronic device 10 is divided into several units 32, at the right of the upper face 12s of the substrate 12, each unit 32 comprising a chip 20. The units 32 are for example all identical. By way of example, [Fig.lB] illustrates a part of the device 10 corresponding to a single unit 32 in sectional view. In figures 1A and 1C, the units 32 have been delimited and represented by a dotted line. Each unit 32 has for example dimensions between 1 mm by 1 mm and 30 mm by 30 mm, for example between 3 mm by 3 mm and 10 mm by 10 mm, for example of the order of 6.5 mm by 6.5 mm.

[0043] The units 32 are for example organized according to a matrix of rows and columns in the device 10. In figures 1A and 1C, fifteen units 32 have been shown in full and three have been shown partially. In practice, the device 10 may comprise a number of units 32 greater than what has been shown.

[0044] The units 32 each correspond, for example, to an electronic component after their individualization. Each component is, for example, intended to be soldered or welded to an external device, not shown, for example a printed circuit, for example, of the PCB (Printed Circuit Board) type. For example, the substrate 12 is, for example, of the BGA (Bail Grid Array) type, that is to say that the electrical connection between the components and the external device is made by means of solder balls 28 arranged on the lower face 12i of the substrate 12. For example, the balls 28 are arranged in regular rows and columns on all or part of the face 12i of the substrate 12. The balls 28 are, for example, made of a metallic material.

[0045] By way of example, the balls 28 are formed in contact with the areas 18i of the lower face 12i of the substrate 12.

[0046] The electronic device 10 further comprises alignment marks 30. Among the alignment marks 30, certain alignment marks 30s make it possible to ensure the alignment of the chip 20, during its transfer, on the upper face 12s of the substrate 12. The alignment marks 30s are formed on the surface of the protective layer 16s, on the side of the upper face of the protective layer 16s. For example, each alignment mark 30s is associated with a single unit 32. Each unit 32 comprises, on the side of the upper face 12s of the substrate 12, several alignment marks 30s, for example four alignment marks 30s. For example, each unit 32 comprises, at each of its corners, on the upper face of the protective layer 16s, an alignment mark 30s.

[0047] By way of example, among the alignment marks 30, other alignment marks 30i make it possible to ensure the alignment of the balls 28, during their formation, on the lower face 12i of the substrate 12. The alignment marks 30i are formed on the surface of the protective layer 16i, on the side of the lower face of the protective layer 16i. By way of example, the alignment marks 30i are formed outside the units 32 and are, for example, associated with several neighboring units 32. By way of example, each unit 32 is associated with several alignment marks 30i, for example four alignment marks 30i.

[0048] By way of example, the alignment marks 30 are made of a material having, with the protective layer 16, a contrast allowing an alignment tool to detect the alignment marks 30 on the protective layer 16.

[0049] For example, the alignment marks 30 are gold. Alternatively, the alignment marks 30 are white.

[0050] In Figures 1A and 1B, the alignment marks 30 have the shape of a cross. Alternatively, the alignment marks 30 may have a different shape, for example a round shape, a square shape, a triangular shape or a rectangular shape. The alignment marks 30 have, for example, a dimension between 150 μm and 500 μm.

[0051] [Fig.2A], [Fig.2B], [Fig.3A] and [Fig.3B] are views illustrating steps of an example of a method of manufacturing the electronic device 10 of FIGS. 1A, 1B and 1C.

[0052] More particularly, Figures 2A and 3A are sectional views and Figures 2B and 3B are top views illustrating steps of an example of a method for manufacturing the electronic device 10 of Figures 1A, 1B and 1C, [Fig.2A] being a view along the section plane AA of [Fig.2B] and [Fig.3A] being a view along the section plane AA of [Fig.3B].

[0053] During the steps of FIGS. 2A, 2B, 3A and 3B, it is proposed to form the alignment marks 30s by screen printing on the upper face 12s of the substrate 12.

[0054] Figures 2A and 2B illustrate a starting structure corresponding to the interconnection substrate 12 comprising the electrical conductors 14, the pads 18 and the protective layers 16. In [Fig.2A], the substrate 12 is represented schematically by a white rectangle without the electrical conductors 14, the protective layer 16 and the pads 18 being represented.

[0055] The structure illustrated in [Fig.2A] and 2B further comprises other alignment marks 34. The alignment marks 34 make it possible to ensure the correct positioning of the alignment marks 30s on the upper face 12s of the substrate 12. In other words, the alignment marks 34 correspond to the alignment marks for the alignment marks 30s.

[0056] The alignment marks 34 are for example formed in the substrate 12. The alignment marks 34 extend for example over only a part of the thickness of the substrate 12.

[0057] For example, the alignment marks 34 are formed in the same metal level as the connection pads 18s. The alignment marks 34 for example are formed at the same time as the pads 18s. The alignment marks 34 are for example made of gold.

[0058] Alternatively, the alignment marks 34 are formed in the same level as one of the conductive tracks of the electrical conductors 14, for example the same metal level as the last track (i.e. the highest track) of the electrical conductors 14. The alignment marks 34 are flush, for example, with the upper face 12s of the interconnection network of the substrate 12. The alignment marks 34 are for example formed at the same time as one of the tracks of the electrical conductors 14. The alignment marks 34 are for example made of copper.

[0059] The alignment marks 34 are formed before the formation of the protective layer 16s. The alignment marks are for example covered by the protective layer 16s. Alternatively, it can be provided that the layer 16s is open opposite all or part of the alignment marks 34, the alignment marks 34 are then not covered or only partly covered by the protective layer 16s. For example, when the alignment marks 34 are at least partly covered by the layer 16s, they are in contact, by their upper faces, with the lower face of the protective layer 16s.

[0060] The alignment marks 34 are, for example, distributed over the entire surface of the device 10 and are, for example, formed outside the units 32.

[0061] Figures 3A and 3B illustrate a structure obtained at the end of a step of screen printing the 30s alignment marks on the upper face of the structure illustrated in [Fig.2A].

[0062] During this step, the alignment marks 30s are formed by screen printing on and in contact with the upper face of the protective layer 16s. This step is for example assisted by an alignment tool so that the position of the alignment marks 30s on the surface of the layer 16 is defined relative to the position of the alignment marks 34.

[0063] For example, the alignment marks 30s are formed by localized deposition of an ink. For example, the ink is gold in color. For example, the ink comprises a gold pigment. The ink comprises, by weight, for example between 1% and 30% gold pigment, for example between 10% and 20% gold pigment, for example of the order of 8% gold pigment. Alternatively, the ink is white in color.

[0064] At the end of the step of forming the alignment marks 30s, the electronic chips 20 are for example transferred onto the upper face of the protective layer 16s using the alignment marks 30s.

[0065] [Fig.4A], [Fig.4B], [Fig.5A], [Fig.5B], [Fig.6A] and [Fig.6B] are views illustrating steps of another example of a method of manufacturing the electronic device 10 of FIGS. 1A, 1B and 1C.

[0066] More particularly, Figures 4A, 5A and 6A are sectional views and Figures 4B, 5B and 6B are top views illustrating steps of another example of a method for manufacturing the electronic device 10 of Figures 1A, 1B and 1C, [Fig.4A] being a view along the section plane AA of [Fig.4B], [Fig.5A] being a view along the section plane AA of [Fig.5B] and [Fig.6A] being a view along the section plane AA of [Fig.6B].

[0067] During the steps of Figures 4A, 4B, 5A, 5B, 6A and 6B, it is planned to form the alignment marks 30s by self-adhesive decal, that is to say by transfer adhesive alignment marks 30s, from a support film 36, on the interconnect substrate 12.

[0068] Figures 4A and 4B illustrate a structure identical to the structure illustrated in Figures 2A and 2B.

[0069] Figures 5A and 5B illustrate a support film 36 on the surface of which the alignment marks 30s are formed. The alignment marks 30s are, in [Fig.5A], formed on the underside of the support film 36. For example, the alignment marks 30s have an adhesive underside.

[0070] The support film 36 comprises, for example, alignment marks 38, which, with the alignment marks 34, ensure the correct positioning of the alignment marks 30s. The alignment marks 38 make it possible, for example, during a subsequent step, to position and align the support film 36 on the structure illustrated in FIGS. 4A and 4B by making the alignment marks 38 of the support film 36 coincide in top view with the alignment marks 34 of the structure illustrated in FIGS. 4A and 4B.

[0071] For example, the alignment marks 38 are formed in the support film 36. Alternatively, the alignment marks 38 are formed on the surface of the support film 36, in contact with the lower face of the support film 36 or in contact with the upper face of the support film 36.

[0072] The alignment marks 38 are for example formed by screen printing or by engraving. The alignment marks 38 are for example gold or white.

[0073] The support film 36 is for example made of a polymer material, for example epoxy.

[0074] Figures 6A and 6B illustrate a structure obtained at the end of a step of transferring the support film 36 onto the structure illustrated in Figures 2A and 2B. More precisely, during this step, the lower face of the structure illustrated in [Fig.4A] is brought into contact with the upper face of the structure illustrated in [Fig.5A]. Even more precisely, during this step, the two structures are transferred onto each other by making the alignment marks 34 and 38 coincide, in top view.

[0075] For example, at the end of this transfer step, the support film 36 is removed, leaving the alignment marks 30s bonded by adhesion to the upper face of the protective layer 16s.

[0076] Similar to what was described at the end of the steps of FIGS. 2A, 2B, 3A and 3B, at the end of the removal of the support film 36, the electronic chips 20 are for example transferred to the upper face of the protective layer 16s using the alignment marks 30s.

[0077] [Fig.7A], [Fig.7B], [Fig.8], [Fig.9A] and [Fig.9B] are views illustrating steps of yet another example of a method of manufacturing the electronic device 10 of FIGS. 1A, 1B and 1C.

[0078] More particularly, Figures 7A and 9A are sectional views and Figures 7B, 8 and 9B are top views illustrating steps of yet another example of a method of manufacturing the electronic device 10 of Figures 1A, 1B and 1C, [Fig.7A] being a view along the section plane AA of [Fig.7B] and [Fig.9A] being a view along the section plane AA of [Fig.9B].

[0079] During the steps of figures 7A, 7B, 8, 9A and 9B, it is planned to form the alignment marks 30s by taking the alignment marks 30s from a ribbon 39 and then placing the latter on the upper face 12s of the interconnection substrate 12.

[0080] Figures 7A and 7B illustrate a structure identical to the structure illustrated in Figures 2A and 2B.

[0081] [Fig. 8] illustrates a ribbon 39, for example a ribbon from a reel, on which the alignment marks 30s are formed. The alignment marks 30s are for example organized on the ribbon 39 in a line and are for example regularly spaced. For example, the ribbon is made of an adhesive material so that the alignment marks 30s are adhered to the ribbon 39.

[0082] Figures 9A and 9B illustrate a structure obtained at the end of a step of transferring the alignment marks 30s present on the ribbon 39 of [Fig.8], onto the upper face 12s of the substrate 12 of the structure illustrated in [Fig.7A].

[0083] During this step, the alignment marks 30s are for example taken from the ribbon 39 illustrated in [Fig.8] then placed on the upper face 12s of the substrate 12 and more particularly, the upper face of the protective layer 16s. This step is for example assisted by an alignment tool making it possible to position the alignment marks 30s using the alignment marks 34.

[0084] At the end of the placement of all the alignment marks 30s on the upper face 12s of the substrate 12 and similarly to what was described at the end of the steps of FIGS. 2A, 2B, 3A and 3B, the electronic chips 20 are for example transferred to the upper face 12s of the substrate 12, so as to form the device 10 illustrated in FIGS. 1A to 1C, using the alignment marks 30s.

[0085] [Fig.10A], [Fig.10B], [Fig.11A], [Fig.11B], [Fig.12A] and [Fig.12B] are views illustrating steps of yet another example of a method of manufacturing the electronic device 10 of FIGS. 1A, 1B and 1C.

[0086] More particularly, Figures 10A, 11A and 12A are sectional views and Figures 10B, 11B and 12B are top views illustrating steps of another example of a method for manufacturing the electronic device 10 of Figures 1A, 1B and 1C, [Fig.10A] being a view along the section plane AA of [Fig.10B], [Fig.11A] being a view along the section plane AA of [Fig.11B] and [Fig.12A] being a view along the section plane AA of [Fig.12B].

[0087] During the steps of Figures 10A, 10B, 11A, 11B, 12A and 12B, it is planned to form the alignment marks 30s on a support film 40 then transferring the support film 40 onto the upper face 12s of the substrate 12.

[0088] Figures 10A and 10B illustrate a structure identical to the structure illustrated in Figures 2A and 2B.

[0089] Figures 11A and 11B illustrate a structure comprising a support film 40, on and / or in which the alignment marks 30s are formed.

[0090] For example, the alignment marks 30s are formed in the support film 40. The alignment marks 30s are for example formed by etching. For example, after the etching step, the alignment marks 30s are revealed during a step of depositing, in the etched patterns, a material having the colorimetric properties mentioned in relation to FIGS. 1A to 1C.

[0091] Alternatively, the alignment marks 30s are formed on and in contact with the upper face of the support film 40. The alignment marks 30s are for example formed by screen printing.

[0092] The support film 40 is for example made of a polymer material, for example epoxy.

[0093] The structure illustrated in [Fig. 11 A] and 11B further comprises other alignment marks, similar to the alignment marks 38 illustrated in FIGS. 5A and 5B. The alignment marks 38 make it possible, for example, during a subsequent step, to position and align the support film 40 on the structure illustrated in FIGS. 10A and 10B by making the alignment marks 38 of the support film 40 coincide in top view with the alignment marks 34 of the structure illustrated in FIGS. 10A and 10B.

[0094] The structure illustrated in [Fig. 11 A] and 11B further comprises openings 42 passing through the support film 40 from one side to the other, from its upper face to its lower face. The openings 42 are for example distributed in the support film in a homogeneous manner. For example, the openings 42 are larger than the size of the electronic chips 20 which will be transferred subsequently to the upper face 12s of the substrate 12.

[0095] Figures 12A and 12B illustrate a structure obtained at the end of a step of transferring the structure illustrated in Figures 11A and 11B onto the structure illustrated in Figures 10A and 10B. More precisely, during this step, the lower face of the structure illustrated in [Fig. 10A] is brought into contact with the upper face of the structure illustrated in [Fig. 11A]. Even more precisely, during this step, the two structures are transferred onto each other by making the alignment marks 34 and 38 coincide, in top view.

[0096] At the end of this step, the alignment marks 30s are thus separated from the upper face 12s of the substrate 12 by all or part of the thickness of the support film 40.

[0097] At the end of the step of transferring the support film 40 onto the structure illustrated in FIGS. 10A and 10B, and similarly to what was described at the end of the steps of FIGS. 2A, 2B, 3A and 3B, the electronic chips 20 are for example mechanically fixed on the upper face 12s of the substrate 12 using the alignment marks 30s. The chips 20 are subsequently electrically connected to the substrate 12, so as to form the device 10 illustrated in FIGS. 1A to 1C. During the step of fixing the chips 20, the chips are for example fixed to the upper face 12s of the substrate 12, through the support film 40 by the openings 42. The openings 42 are for example aligned opposite the locations of the chips 20 on the upper face 12s of the substrate 12. The openings 42 are then sufficiently large so that the film 40 does not cover the areas 18s. For example, each opening 42 is larger, in top view, than the combination of a chip 20 and the pads 18s to which the chip is connected.

[0098] By way of example, after the mechanical fixing of the chips 20 on the upper face 12s of the substrate 12, the support film 40 is removed. The support film is for example removed between the step of mechanically fixing the chips 20 on the substrate 12 and the step of electrically connecting the chips 20 to the substrate 12. Alternatively, the support film 40 is removed after the step of electrically connecting the chips 20 to the substrate 12.

[0099] After cutting the units 32 of the device 10 so as to form individual components, these electronic components have applications in numerous industrial fields and, in particular, in the automotive field, in the field of communication or in the field of connected personal objects. For example, such components can be used in microelectromechanical systems, in sensors or in microcontrollers.

[0100] An advantage of the present embodiment is that it allows the alignment marks 30s, usually formed in one of the upper levels of the electrical conductors, to be moved onto the upper face of the protective layer 16.

[0101] Another advantage of the present embodiment is that it makes it possible to reduce the metallic bulk in the upper levels of the electrical conductors.

[0102] Yet another advantage of the present embodiment is that it allows the surface area of ​​the interconnect substrate 12 to be reduced.

[0103] Yet another advantage of the present embodiment is that it allows the tracks of the upper levels of the electrical conductors to be extended laterally.

[0104] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0105] In particular, although only the production of the alignment marks 30s has been described here, the alignment marks 30i can be produced on the surface of the lower face of the protective layer 16i by the same methods.

[0106] Furthermore, although an exemplary embodiment has been described in which the chip 20 is electrically connected to the interconnection substrate 12 by conductive wires connecting the electrical connection pads 24 formed on the side of the upper face of the chip to electrical connection pads 18 formed on the side of the upper face 12s of the substrate 12, the embodiments described are not limited to this particular case. As a variant, the chip 20 can be connected to the substrate by conductive balls connecting lower connection pads of the chip to electrical connection pads located on the side of the upper face 12s of the substrate 12 under the chip 20.

[0107] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Method for manufacturing an electronic device (10) comprising an interconnection substrate (12) comprising, on the side of an upper connection face (12s), an electrically insulating protective layer (16s), the electrically insulating protective layer (16s) comprising openings leaving accessible metallic electrical connection pads (18s) intended to be soldered or brazed to a connection element (26), the method comprising a step of forming alignment marks (30s) on the surface of the electrically insulating protective layer (16s) of the interconnection substrate (12), on the side of the upper face of the electrically insulating protective layer (16s).

2. The method of claim 1, wherein the alignment marks (30s) are gold or white.

3. A method according to claim 1 or 2, wherein the alignment marks (30s) have a dimension between 150 pm and 500 pm.

4. A method according to any one of claims 1 to 3, wherein the alignment marks (30s) are formed by screen printing on and in contact with the electrically insulating protective layer (16s).

5. A method according to any one of claims 1 to 3, wherein the alignment marks (30s) are adhesive and wherein the formation of the alignment marks (30s) comprises a step of transferring a support film (36), comprising on a lower face side the alignment marks (30s), onto the electrically insulating protective layer (16s) and a step of removing the support film (36) leaving on the surface of the electrically insulating protective layer (16s) the adhered alignment marks (30s).

6. A method according to any one of claims 1 to 3, wherein the alignment marks (30s) are deposited on the surface of the electrically insulating protective layer (16s) by picking up the alignment marks and then placing them on and in contact with the electrically insulating protective layer (16s).

7. A method according to any one of claims 1 to 3, wherein the formation of the alignment marks (30s) comprises a step of transferring a support film (40), in and / or on which the alignment marks (30s) are formed, onto the electrically insulating protective layer (16), the support film (40) comprising openings (42) allowing leaving the surface of the interconnection substrate (12) free of access for mounting the connection element (26).

8. Method according to any one of claims 1 to 7, comprising a step of mechanically fixing an electronic chip (20) on the upper connection face of the interconnection substrate (12).

9. Method according to claim 8, comprising a step of electrically connecting the electronic chip (20) to the interconnection substrate (12) via the electrical connection metal pads (18s) and the connection element (26).

10. The method of claim 8 or 9, wherein in the step of mechanically fixing the electronic chip (20), the electronic chip (20) is aligned on the upper connection face of the interconnect substrate (12) using the alignment marks (30s).

11. Method according to any one of claims 8 to 10, comprising a step of cutting the electronic device (10) so as to obtain a plurality of electronic components, each electronic component comprising an electronic chip (20).

12. Electronic device comprising: - an interconnection substrate (12) comprising, on the side of an upper connection face (12s), an electrically insulating protective layer (16s), the electrically insulating protective layer comprising openings allowing access to metallic electrical connection pads (18s) intended to be soldered or brazed to a connection element (26); and - alignment marks (30s) formed on the surface of the electrically insulating protective layer (16s), on the side of the upper face of the electrically insulating protective layer (16s).

13. Electronic device according to claim 12, comprising an electronic chip (20) fixed on the upper connection face of the interconnection substrate (12) and electrically connected to the interconnection substrate (12) via the electrical connection metal pads (18s) and the connection element (26).

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