Cover tape for packaging electronic component

By using antistatic agents such as tin phosphide, graphite nanotubes or polysulfide ketones in the cover glue to replace traditional antizirconium agents, the problem of difficult balance of adhesion and peelability and generation of static electricity when reducing the use of antizirconium agents is solved, and good electrostatic suppression and electronic component protection effects are achieved.

JP2025061310APending Publication Date: 2025-04-10SUMITOMO BAKELITE CO LTD
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Patent Information

Application Number
JP2025005354
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2025-01-15
Publication Date
2025-04-10

AI Technical Summary

Technical Problem

When existing cover glue reduces anti-rust agents and zirconium resistance, it is difficult to maintain good adhesion and peelability between the cover glue and the carrier glue, and at the same time, static electricity is generated during the peeling process, damaging electronic components.

Method used

Tin phosphide, graphite nanotubes or polysulfide ketones or their derivatives are used as antistatic agents in the cover glue to replace the traditional antizirconium agents. By optimizing the layer structure and composition of the cover glue, it ensures that it maintains good adhesion and electrostatic suppression effect during the peeling process.

Benefits of technology

In the case of reducing the use of anti-zirconium agent, a good balance between the cover glue and the carrier glue is achieved, which inhibits the generation of static electricity during the peeling process and protects the electronic components.

✦ Generated by Eureka AI based on patent content.

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Abstract

To provide a cover tape for packaging an electronic component which has an excellent balance of adhesiveness and peelability to a carrier tape when antimony is reduced, and can suppress the generation of static electricity due to peeling.SOLUTION: A cover tape for packaging an electronic component according to the present invention includes a base material layer, an intermediate layer, and a sealant layer in this order, the sealant layer includes an adhesive resin and an antistatic agent, and the antistatic agent includes one or more selected from the group consisting of (A) phosphorus-doped tin, (B) carbon nanotubes, (C) polythiophene or a polythiophene derivative, the 170° peel strength for a polystyrene film having an average surface roughness of 0.25 μm is 0.3 N or more and 0.9 N or less, and the antimony content for the entire cover tape is 0 ppm or more and 150 ppm or less.SELECTED DRAWING: Figure 1
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Description

[Technical field]

[0001] The present invention relates to a cover tape for packaging electronic components. [Background technology]

[0002] Conventionally, electronic components such as transistors, diodes, capacitors, and piezoelectric resistors are stored in a package consisting of a carrier tape in which pockets capable of storing the electronic components are continuously formed and a cover tape to be sealed to the carrier tape at the manufacturing site of electronic devices, and then the package is heat sealed. The package is then wound on a paper or plastic reel and transported to a work area where the electronic components are surface mounted on an electronic circuit board or the like. Then, the cover tape of the package is peeled off in the above-mentioned work area, and the electronic components are taken out of the pockets formed on the carrier tape and surface mounted on an electronic circuit board or the like. With the miniaturization of electronic devices in recent years, further miniaturization and high-level mounting of the electronic components are required. Therefore, electronic components in recent years tend to be more susceptible to static electricity than ever before.

[0003] In view of these circumstances, in recent years, there has been a demand for cover tapes used for transporting electronic components to have improved properties in various ways, as will be described later. First, the characteristics required for the cover tape are a good balance between sufficient adhesive strength to the carrier tape and peelability that allows it to be peeled off from the carrier tape in the mounting process. If the peel strength, which is the strength required to peel the cover tape from the carrier tape in the process of peeling the cover tape from the carrier tape, is too high, the carrier tape vibrates when the cover tape is peeled off, causing the electronic components to jump out of the storage pocket. On the other hand, if the adhesive strength between the carrier tape and the cover tape is low, the cover tape may peel off during the transportation of the package, causing the packed electronic components to fall out. Secondly, the characteristic required for the cover tape is antistatic property required to a degree that can suppress the breakdown (electrostatic destruction) of electronic components contained in the package due to static electricity generated by friction between the cover tape and electronic components during transportation, static electricity generated when peeling the cover tape from the carrier tape, static electricity generated from attached dust and contents, etc. In particular, various studies have been conducted on technologies to improve the antistatic property of the cover tape from the viewpoint of suppressing the effects of static electricity generated by friction between the cover tape and electronic components during transportation and static electricity generated when peeling the cover tape from the carrier tape.

[0004] For example, Patent Document 1 describes a cover tape for packaging electronic parts that uses acicular particles of antimony-doped tin oxide in an antistatic heat seal layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-064739 A Summary of the Invention [Problem to be solved by the invention]

[0006] As described above in the Background Art section, various studies have been conducted on improving the above-mentioned properties of conventional cover tapes. However, in recent years, it has been desired to reduce the use of antimony, which has been used as a good antistatic agent, from the viewpoint of environmental protection. In view of the above circumstances, the present inventors have worked to develop a cover tape for packaging electronic components that, when the antimony content is reduced, has a good balance of adhesion and releasability when peeling the carrier tape from the cover tape, and can suppress the generation of static electricity during peeling.

[0007] The present invention provides a cover tape for packaging electronic components which, when containing reduced antimony, has an excellent balance between adhesion to a carrier tape and peelability, and which has excellent antistatic properties associated with peeling of the carrier tape. [Means for solving the problem]

[0008] As a result of further investigation, the inventors have found that when the sealant layer of a cover tape for packaging electronic components contains one or more antistatic agents selected from the group consisting of (A) phosphorus-doped tin, (B) carbon nanotubes, or (C) polythiophene or polythiophene derivatives, and the amount of antimony is reduced, a cover tape for packaging electronic components can be realized which has a good balance between adhesion to the carrier tape and releasability and which can suppress the generation of static electricity associated with peeling, thereby completing the present invention.

[0009] [1] A base layer; The middle class, A sealant layer; A cover tape for packaging electronic components, comprising, in this order: the sealant layer comprises an adhesive resin and an antistatic agent; The antistatic agent is (A) phosphorus-doped tin (B) Carbon nanotubes (C) Polythiophene or polythiophene derivative Contains one or more selected from the group consisting of The peel strength against polystyrene film measured by the method described below is 0.3N or more and 0.9N or less. A cover tape for packaging electronic components, the antimony content of which, measured throughout the entire cover tape, is between 0 ppm and 150 ppm. <Peel strength measurement> The cover tape for packaging electronic devices is cut to a width of 5.5 mm, and the sealant layer side of the cover tape is aligned with the uneven surface side of a polystyrene film that is 8 mm wide and has an average surface roughness (Ra) of 0.25 μm. The uneven surface is heat-sealed using a two-blade iron with one blade 0.5 mm wide and 28 mm long under conditions of a sealing temperature of 160°C, a load of 5 kgf, a sealing time of 60 milliseconds, and a carrier tape feed pitch of 4 mm. The peel strength of the cover tape for packaging electronic devices against the polystyrene film is measured under conditions of a peel speed of 300 mm / min, a measurement temperature of 25°C, and a peel angle of 170°. [2] The cover tape for packaging electronic components according to the above [1], The surface resistance of the surface of the substrate layer measured at 25° C. and 50% RH is 1.0×10 13 A cover tape for packaging electronic components with a resistance of less than Ω. [3] The cover tape for packaging electronic components according to the above [1] or [2], The surface resistance of the sealant layer measured at 25° C. and 50% RH is 1.0×10 3 Ω or more 1.0×10 12 A cover tape for packaging electronic components with a resistance of less than Ω. [4] The cover tape for packaging electronic components according to any one of the above [1] to [3], A cover tape for packaging electronic components, in which the 170° peel strength of the cover tape for packaging electronic components against the polystyrene film is defined as P1, and the 170° peel strength of the cover tape for packaging electronic components against the polystyrene film measured by the <Peel strength measurement> after placing the cover tape for packaging electronic components at 40°C and 90% RH for 14 days is defined as P2, and the value of (P2 / P1) x 100 is 50% or more and 150% or less. [5] The cover tape for packaging electronic components according to any one of the items [1] to [4], A cover tape for packaging electronic components, having a triboelectric charge of 0.0 nC or more and 1.0 nC or less on the surface of a resin pellet measured at 25°C and 50% RH by the following steps (a) to (e). (a) The cover tape for packaging electronic devices is cut to a size of 25 mm wide and 200 mm long, folded in half lengthwise with the surface of the sealant layer on the inside, and both sides are taped to create a bag that is 25 mm wide and 100 mm long. (b) Prepare a resin pellet consisting of 85% by mass of silica and 15% by mass of epoxy resin and measuring 3 mm x 1.5 mm x 1 mm. (c) After the bag and the resin pellets are de-electrified, five of the resin pellets are placed in the bag, and the opening is taped and sealed. (d) The bag containing the resin pellets sealed in (c) is fixed to a vortex mixer and vibrated at 600 rpm for 5 minutes. (e) After removing the five resin pellets from the bag, all of them are transferred to a Faraday cup, and the amount of charge of the resin pellets is measured using a nanocoulomb meter at 25°C and 50% RH. The absolute value of the measured value is regarded as the amount of triboelectric charge. [6] The cover tape for packaging electronic components according to any one of the items [1] to [5], A cover tape for packaging electronic components that has a total light transmittance of 70% or more and 95% or less, measured with a light source D65, in accordance with JIS K7361-1 (1997). [7] The cover tape for packaging electronic components according to any one of the items [1] to [6], A cover tape for packaging electronic components with an external haze of 5% to 50% measured with a light source of D65, conforming to JIS K7136 (2000). [8] The cover tape for packaging electronic components according to any one of the items [1] to [7], A cover tape for packaging electronic components, wherein the (C) polythiophene or polythiophene derivative is poly-3,4-ethylenedioxythiophene or a derivative thereof. [9] The cover tape for packaging electronic components according to any one of the items [1] to [8], The cover tape for packaging electronic components, wherein the sealant layer comprises one or two members selected from the group consisting of polyacrylic acid derivatives and styrene-based polymers. Effect of the Invention

[0010] According to the present invention, a cover tape for packaging electronic components can be provided that, when the antimony content is reduced, has an excellent balance between adhesion to a carrier tape and peelability, and can suppress the generation of static electricity associated with peeling. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic diagram showing an example of a cover tape for packaging electronic components according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a diagram showing an example of a state in which a cover tape for packaging electronic components is bonded (heat sealed) to a carrier tape. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In all drawings, similar components are given similar reference numerals and their description will be omitted as appropriate. In addition, the drawings are schematic diagrams and do not correspond to the actual dimensional ratio.

[0013] <Cover tape for packaging electronic components> FIG. 1 is a schematic diagram showing an example of a cover tape for packaging electronic components according to the present embodiment. The cover tape for packaging electronic components of this embodiment is a cover tape for packaging electronic components that includes a base layer 1, an intermediate layer 2, and a sealant layer 3 in this order. In the cover tape 10 for packaging electronic devices, the sealant layer 3 is usually bonded to the carrier tape. In other words, the upper surface side in FIG. Moreover, each layer may be composed of a plurality of layers.

[0014] <Other layers> An adhesive layer (not shown) may be provided between each layer of the cover tape for packaging electronic components 10. This adhesive layer can improve the adhesion between each layer. Materials for forming the adhesive layer include urethane-based adhesive resins for dry lamination or adhesive resins for anchor coats, and generally include a combination of a polyester composition such as polyester polyol or polyether polyol with an isocyanate compound. Furthermore, layers other than the adhesive layer may be provided, such as a layer for improving the strength of the entire film, a water vapor barrier layer, etc.

[0015] <Base material layer> The base material layer 1 can be a film made from various materials, so long as it has the mechanical strength to withstand the external forces applied during processing of the cover tape 10 for packaging electronic components, heat sealing to the carrier tape, and use, and the heat resistance to withstand the heat during heat sealing.

[0016] Specific examples of materials constituting the base layer 1 include polyester resins, polyamide resins, polyolefin resins, polyacrylate resins, polymethacrylate resins, polyimide resins, polycarbonate resins, ABS resins, etc. Among these, polyester resins and polyolefin resins are preferred as materials constituting the base layer 1, and polyethylene terephthalate and polyethylene, which can improve mechanical strength, are particularly preferred. In addition, when selecting a polyamide resin as the material constituting the base layer 1, it is preferred to use nylon, which can improve mechanical strength and flexibility.

[0017] The form of the film used to form the base layer 1 may be a stretched film or a film stretched uniaxially or biaxially, but from the viewpoint of improving the mechanical strength of the cover tape for packaging electronic components, a film stretched uniaxially or biaxially is preferable.

[0018] The base layer 1 may be formed of a single layer film containing the above-mentioned materials, or may be formed using a multilayer film containing the above-mentioned materials in each layer. From the viewpoint of reducing the amount of static electricity generated by peeling off the carrier tape, the base layer 1 may contain an antistatic agent, or an antistatic layer may be provided as one layer of the base layer on the surface of the base layer 1 opposite to the surface on which the intermediate layer 2 is provided. When electronic components are contained in a package consisting of the carrier tape and the cover tape 10 for packaging electronic components and transported, if multiple packages are stacked and transported, the surface of the base layer 1 or the antistatic layer containing such an antistatic agent may come into contact with the bottom surface of the carrier tape of the package stacked on top.

[0019] The thickness of the base layer 1 is, for example, 6 μm or more, preferably 7 μm or more, and more preferably 8 μm or more. The thickness of the base layer 1 is, for example, 35 μm or less, preferably 33 μm or less, and more preferably 30 μm or less. If the thickness of the base layer 1 is equal to or less than the above upper limit, the rigidity of the cover tape for packaging electronic components is not too high, and even if a torsional stress is applied to the carrier tape after sealing, the cover tape for packaging electronic components 10 follows the deformation of the carrier tape, and the possibility of peeling off can be reduced. If the thickness of the base layer 1 is equal to or more than the above lower limit, the mechanical strength of the cover tape for packaging electronic components 10 becomes suitable, and even when the cover tape for packaging electronic components 10 is peeled off from the carrier tape at high speed, the possibility of the cover tape for packaging electronic components 10 breaking can be reduced. The substrate layer 1 may have a two-layer structure of a first substrate layer and a second substrate layer, or a three-layer structure having an additional layer. In this case, the material may be, for example, the same as that used for the substrate layer 1. The thickness is preferably the total thickness of the first substrate layer, the second substrate layer, etc., which is the "thickness of substrate layer 1."

[0020] <Middle Class> The intermediate layer 2 is a layer provided for the purpose of imparting cushioning properties to the cover tape 10 for packaging electronic components according to this embodiment, thereby improving the adhesion between the cover tape 10 for packaging electronic components and the carrier tape during sealing.

[0021] The intermediate layer 2 may be made of any material that can provide cushioning properties to the cover tape 10 for packaging electronic components, and examples of such materials include one or more selected from polyacrylic acid derivatives, polyacrylic acid ester derivatives, polyvinyl acetate derivatives, styrene-based resins, olefin-based resins, and cyclic olefin resins, and copolymers thereof. Among these, olefin-based resins are preferred, and ethylene-based resins are more preferred.

[0022] The thickness of the intermediate layer 2 is typically 10 μm or more and 50 μm or less, and preferably 15 μm or more and 45 μm or less, from the viewpoint of improving the adhesion between the cover tape 10 for packaging electronic devices and the carrier tape during sealing.

[0023] <Sealant layer> The sealant layer 3 contains an adhesive resin and an antistatic agent, and is provided on the side of the intermediate layer 2 opposite to the side that contacts the base layer 1, and is the layer that comes into contact with the carrier tape when the cover tape 10 for packaging electronic components is sealed (e.g., heat sealed) to the carrier tape. The sealant layer 3 has heat sealability and can be adhered to a carrier tape, and exhibits easy peelability so that it can be easily peeled off when in use. The antistatic agent is dissolved or dispersed in the resin of the sealant layer 3. That is, good compatibility is obtained between the adhesive resin and the antistatic agent, and the antistatic agent is uniformly dispersed throughout the sealant layer 3 in the adhesive resin serving as the matrix resin. The sealant layer 3 may be formed by laminating an adhesive resin layer and an antistatic layer in this order on the side opposite to the surface in contact with the intermediate layer 2.

[0024] Specific examples of the adhesive resin material of the sealant layer 3 include one or more selected from polyacrylic acid derivatives, polyacrylic acid ester derivatives, styrene-based polymers, olefin-based resins, urethane-based resins, and ester-based resins, and copolymers thereof. Among these, polyacrylic acid derivatives and styrene-based polymers are preferred from the viewpoint of favorable dissolution or dispersion of the antistatic agent.

[0025] The sealant layer 3 preferably contains, as the antistatic agent, one or more selected from the group consisting of (A) phosphorus-doped tin, (B) carbon nanotubes, and (C) polythiophene or polythiophene derivatives, which reduces the surface resistance of the sealant layer 3 to suppress the generation of static electricity associated with peeling, maintains adhesion, and provides good compatibility with the adhesive resin used in the sealant layer 3. Furthermore, by using (A) phosphorus-doped tin or (C) polythiophene or a polythiophene derivative as the antistatic agent, the effect of suppressing static electricity during peeling can be more reliably obtained.

[0026] Examples of the polythiophene or polythiophene derivative (C) include polythiophene, poly(3,4)-ethylenedioxythiophene, and poly(3-thiophene-β-ethanesulfonic acid). Among these, poly3,4-ethylenedioxythiophene or its derivative is preferred from the viewpoint of maintaining better antistatic properties and sealing properties.

[0027] The sealant layer 3 may contain other additives such as a dispersant for improving the dispersibility of the antistatic agent, silica sol, a leveling agent, a conductive assistant, and the like.

[0028] From the viewpoint of suitably performing the sealing operation and the peeling operation, the thickness of the sealant layer 3 is typically preferably 0.02 μm or more and 20 μm or less, and more preferably 0.03 μm or more and 15 μm or less.

[0029] The thickness of the cover tape for packaging electronic components according to this embodiment is preferably 40 μm or more and 65 μm or less, and more preferably 45 μm or more and 60 μm or less, from the viewpoint of ensuring film strength.

[0030] The characteristics of the cover tape for packaging electronic components according to this embodiment will be described below.

[0031] In the cover tape for packaging electronic components according to this embodiment, the upper limit of the antimony content measured on the entire cover tape for packaging electronic components is 150 ppm or less, preferably 140 ppm or less, and more preferably 130 ppm or less. The lower limit of the antimony content measured on the entire cover tape for packaging electronic components according to this embodiment is not particularly limited, but is 0 ppm or more. By setting the antimony content measured on the entire cover tape for packaging electronic components within the above range, it is possible to meet the demand for antimony reduction.

[0032] In the cover tape for packaging electronic components according to this embodiment, when the cover tape for packaging electronic components is 5.5 mm wide, the sealant layer side of the cover tape for packaging electronic components is aligned with the uneven surface side of a polystyrene film having an 8 mm wide uneven surface and an average surface roughness (Ra) of 0.25 μm, and heat-sealed using a two-blade iron with one blade having a width of 0.5 mm and a length of 28 mm under conditions of a sealing temperature of 160°C, a load of 5 kgf, a sealing time of 60 milliseconds, and a carrier tape feed pitch of 4 mm, the lower limit of the peel strength of the cover tape for packaging electronic components against the polystyrene film under conditions of a peel speed of 300 mm / min, a measurement temperature of 25°C, and a peel angle of 170° is 0.3 N or more, preferably 0.35 N or more, and more preferably 0.4 N or more. The upper limit of the 170° peel strength of the cover tape for packaging electronic components against the polystyrene film is not more than 0.9 N, preferably not more than 0.8 N, and more preferably not more than 0.7 N. By setting the 170° peel strength of the cover tape for packaging electronic components against the polystyrene film within the above range, a good balance between adhesion to the carrier tape and peelability can be achieved.

[0033] In the electronic component packaging cover tape according to the present embodiment, the 170° peel strength of the electronic component packaging cover tape against the polystyrene film is P1, and the 170° peel strength of the electronic component packaging cover tape against the polystyrene film measured in the same manner as P1 after placing the electronic component packaging cover tape at 40°C and 90% RH for 14 days is P2. The value of (P2 / P1)×100 is preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more, and is preferably 150% or less, more preferably 140% or less, and even more preferably 130% or less. By keeping the value of (P2 / P1)×100 within the above range, a stable peel strength can be maintained even after environmental changes during transportation or storage.

[0034] The surface resistance value of the surface of the above-mentioned base layer of the cover tape for packaging electronic components according to this embodiment, measured at 25° C. and 50% RH, is preferably 1.0×10 3 Ω or more, and more preferably 1.0×10 4 Ω or more, and more preferably 1.0×10 5 Ω or more, preferably 1.0×10 13 Ω or less, and more preferably 1.0×10 12 Ω or less, and more preferably 1.0×10 11 By setting the surface resistance value of the base material layer of the cover tape for packaging electronic components within the above range, static electricity generated due to various factors can be efficiently discharged to the outside. The surface of the base material layer refers to the exposed surface side of the base material layer in the cover tape for packaging electronic components (that is, the surface of the base material layer that is not in contact with the intermediate layer).

[0035] The surface resistance value of the surface of the sealant layer of the cover tape for packaging electronic components according to this embodiment, measured at 25° C. and 50% RH, is preferably 1.0×10 3 Ω or more, and more preferably 1.0×10 4 Ω or more, and more preferably 1.0×10 5 Ω or more, preferably 1.0×10 12 Ω or less, and more preferably 1.0×10 11 Ω or less, and more preferably 1.0×10 10 By controlling the surface resistance of the sealant layer of the cover tape for packaging electronic components, measured at 25° C. and 50% RH, to fall within the above range, the cover tape for packaging electronic components can have even better antistatic properties during peeling of the carrier tape. The surface of the sealant layer refers to the exposed surface side of the sealant layer in the cover tape for packaging electronic components (that is, the surface of the sealant layer that is not in contact with the intermediate layer).

[0036] In the cover tape for packaging electronic components according to the present embodiment, a resin pellet was placed in a bag made using the cover tape under conditions of 25°C and 50% RH, and the bag was vibrated, and the triboelectric charge on the surface of the resin pellet was measured by a predetermined method. The lower limit of the absolute value of the triboelectric charge on the surface of the resin pellet is preferably 0.0 nC or more. Also preferably, the upper limit of the absolute value of the triboelectric charge on the surface of the resin pellet is 1.0 nC or less, more preferably 0.8 nC or less, and even more preferably 0.6 nC or less. By doing so, the antistatic property associated with the peeling of the carrier tape can be further improved. Specifically, when the value of the triboelectric charge satisfies the above numerical range, even when the working environment at the manufacturing site of electronic devices is in a dry state with a humidity of about 30% RH, a cover tape with excellent charging properties against static electricity generated by friction between the cover tape and electronic components during transportation, static electricity generated when the cover tape is peeled off from the carrier tape, static electricity generated from attached dust or contents, etc. can be realized. The resin pellets used for measuring the triboelectric charge consist of 85% silica by mass and 15% epoxy resin by mass, and have dimensions of 3 mm x 1.5 mm x 1 mm. As the silica, a mixture of silica with an average particle size of 1 to 10 μm and silica with an average particle size of 0.5 to 1 μm can be used. As the epoxy resin, a phenol novolac resin can be used. As long as the silica and epoxy resin are mixed as described above, the results of the triboelectric charge will not be significantly affected even if the type of epoxy resin or the average particle size of the silica is slightly different.

[0037] The total light transmittance of the electronic component packaging cover tape according to this embodiment, measured with a light source D65 in accordance with JIS K7361-1 (1997), is preferably 70% or more, more preferably 75% or more, even more preferably 80% or more, preferably 95% or less, more preferably 94% or less, and even more preferably 93% or less. In this way, the package 100 consisting of the cover tape 10 for packaging electronic components and the carrier tape can be given a degree of transparency that allows inspection of whether or not electronic components are properly accommodated in the pocket of the carrier tape. That is, by setting the total light transmittance of the cover tape for packaging electronic components to be equal to or more than the lower limit, it becomes possible to visually confirm the electronic components accommodated inside the package 100 consisting of the cover tape 10 for packaging electronic components and the carrier tape from the outside of the package 100.

[0038] The external haze of the cover tape for packaging electronic components according to this embodiment, measured with a light source D65 in accordance with JIS K7136 (2000), is preferably 5% or more, more preferably 6% or more, and most preferably 7% or more, and is preferably 50% or less, more preferably 45% or less, and most preferably 40% or less. By making the external haze of the cover tape for packaging electronic components equal to or less than the upper limit, it is possible to impart transparency to a degree that allows inspection of whether electronic components are properly accommodated in the pockets of the carrier tape in a package consisting of the cover tape for packaging electronic components 10 and the carrier tape.

[0039] In this embodiment, it is possible to control the 170° peel strength against the polystyrene film and the antimony content in the entire cover tape for packaging electronic components by appropriately selecting conditions such as the type and amount of each component contained in the base layer 1, intermediate layer 2, and sealant layer 3 constituting the cover tape for packaging electronic components, the method for preparing the coating solution for forming the sealant layer, and the method for producing the cover tape for packaging electronic components. As a result, even in a cover tape for packaging electronic components with reduced antimony, the balance between adhesion to the carrier tape and peelability is excellent, and the generation of static electricity accompanying peeling can be suppressed. In addition, in this embodiment, by appropriately selecting the above conditions, it is possible to control the value of (P2 / P1) x 100, where P1 is the 170° peel strength against the polystyrene film and P2 is the 170° peel strength against the polystyrene film measured after storing the cover tape for packaging electronic devices at 40°C and 90% RH for 14 days, the surface resistance of the base material layer 1, the surface resistance of the sealant layer 3, the amount of triboelectric charge, the total light transmittance, and the external haze, and in the cover tape for packaging electronic devices with reduced antimony, the peel strength can be made stable even after environmental changes, the effect of suppressing static electricity during peeling can be more reliably achieved, and transparency to the extent that the electronic devices can be visually recognized from the outside can be imparted.

[0040] <Method of manufacturing cover tape for packaging electronic components> An example of a method for producing the cover tape for packaging electronic components according to this embodiment will be described. First, the intermediate layer 2 is formed on the surface of the base layer 1. The intermediate layer 2 can be formed by, for example, an extrusion lamination method or a dry lamination method. Next, a sealant layer 3 is formed by applying a predetermined material onto the intermediate layer 2 by a coating method and drying it, or laminating it by an extrusion lamination method.

[0041] When forming the above-mentioned adhesive layer, the material for the adhesive layer may be applied to the surface of the layer to be formed by a conventionally known application method.

[0042] The cover tape for packaging electronic components according to the present embodiment can be attached to a carrier tape to be used as a package. That is, it is preferable to use a package that includes a carrier tape having a plurality of storage compartments for storing electronic components, the electronic components stored in the storage compartments, and the cover tape for packaging electronic components arranged to cover the storage compartments. Such a package can suppress the generation of static electricity, and can more reliably protect the electronic components stored in the storage section from static electricity.

[0043] <Electronic component packaging> An electronic component package can be obtained from the cover tape for packaging electronic components of this embodiment described above and a carrier tape having electronic components housed in recesses. This will be described with reference to FIG.

[0044] In FIG. 2, cover tape 10 for packaging electronic components is used as a lid material for band-shaped carrier tape 20 having recessed pockets 21 continuously formed to match the shapes of electronic components. Specifically, the cover tape 10 for packaging electronic components is adhered (usually by heat sealing) to the surface of the carrier tape 20 so as to cover the entire opening of the pocket 21 of the carrier tape 20. Hereinafter, the structure obtained by adhering the cover tape 10 for packaging electronic components and the carrier tape 20 together will be referred to as the electronic component package 100.

[0045] The electronic component packaging body 100 can be produced, for example, by the following procedure. First, electronic components are placed in the pockets 21 of the carrier tape 20 . Next, the cover tape 10 for packaging electronic components is adhered to the surface of the carrier tape 20 by a heat sealing method so as to cover the entire opening of the pocket 21 of the carrier tape 20. At this time, the sealant layer 3 of the cover tape 10 for packaging electronic components is in contact with the carrier tape 20 (that is, the heat sealing is performed so that the "back surface" of the cover tape 10 for packaging electronic components in FIG. 2 becomes the sealant layer 3). The specific method and conditions for heat sealing are not particularly limited as long as the cover tape 10 for packaging electronic components is sufficiently strongly adhered to the carrier tape 20. Typically, a known heat sealing machine is used, and the heat sealing can be performed at a temperature of 100 to 240° C., a load of 0.1 to 10 kgf, and a time of 0.0001 to 1 second.

[0046] In this manner, a structure (electronic component packaging body 100) in which electronic components are hermetically housed is obtained. This structure (electronic component packaging body 100) is, for example, wound on a reel and then transported to a work area where the electronic components are mounted on an electronic circuit board, etc. The reel can be made of metal, paper, plastic, etc.

[0047] After the electronic component package 100 has been transported to the work area, the cover tape 10 for packaging electronic components is peeled off from the carrier tape 20, and the housed electronic components are taken out.

[0048] The electronic components contained in electronic component packaging 100 are not particularly limited. Examples include general components used in the manufacture of electric and electronic devices, such as semiconductor chips, transistors, diodes, capacitors, piezoelectric elements, optical elements, LED-related members, connectors, and electrodes.

[0049] Although the embodiments of the present invention have been described in detail above, these are merely examples of the present invention. In addition, various configurations other than those described above can be adopted. In addition, the present invention is not limited to the above-described embodiments. EXAMPLES

[0050] The embodiments of the present invention will be described in detail based on examples and comparative examples, but the present invention is not limited to these.

[0051] The constituent materials of the sealant layer shown in Table 1 are as follows. (adhesive resin) Resin 1: Poly(meth)acrylic acid derivative (Dainippon Ink "A450A") Resin 2: Styrene-based polymer (Nipol 2507H, manufactured by Nippon Zeon Co., Ltd.) Resin 3: Polyacrylic acid derivative ("Elbaloy AC1820" manufactured by Mitsui Dow Polychemicals) Resin 4: Styrene-based polymer ("Estyrene MS-600" manufactured by Nippon Steel Chemical Co., Ltd.) (Antistatic agent) Antistatic agent 1: Phosphorus-doped tin oxide (Mitsubishi Materials Corporation "SP-2") Antistatic agent 2: Carbon nanotubes (Sigmaaldrich "isoNanotubes-M (registered trademark) 750530") Antistatic agent 3: Polythiophene derivative (Sigmaaldrich "Aedotron (registered trademark) C3-NM") Antistatic agent 4: Polythiophene derivative (PEDOT:PSS) (Heraeus "Clevios P1000") Antistatic agent 5: Antimony-doped tin oxide (Mitsubishi Materials Corporation "T-1") Antistatic agent 6: Polypropylene / polyethylene glycol (Sanyo Chemical Industries, Ltd. "Pelestat 212")

[0052] <Example 1> [Preparation of Base Layer and Intermediate Layer] An anchor coating agent was applied to a 12 μm thick antistatic polyethylene terephthalate (PET) film ("E7455" manufactured by Toyobo Co., Ltd.) to a wet thickness of 4 μm by gravure coating, and after drying at 100°C, low-density polyethylene ("Sumikathen L705" manufactured by Sumitomo Chemical Co., Ltd., 37 μ thick) was extrusion laminated onto it, and then cooled with a cooling roll (surface temperature 20°C) to produce a laminated film consisting of a base layer and an intermediate layer.

[0053] A sealant layer having a thickness of 0.5 μm and composed of the components shown in Table 1 was formed on the intermediate layer side of the obtained laminated film by gravure coating. The total thickness of the cover tape is shown in Table 1.

[0054] <Examples 2 to 4, Comparative Examples 1 to 4> According to the formulation shown in Table 1, a cover tape for packaging electronic devices was produced in the same manner as in Example 1.

[0055] <170° peel strength against polystyrene film> Each electronic component packaging cover tape obtained above was cut to a width of 5.5 mm, and the sealant layer side of the electronic component packaging cover tape was aligned with the uneven surface side of a polystyrene film (Sumitomo Bakelite Co., Ltd., "CEL-E980A") with a width of 8 mm and an average surface roughness (Ra) of 0.25 μm on the uneven surface. Using a two-blade iron with a width of 0.5 mm and a length of 28 mm, the samples were heat-sealed using a heat sealer (Tokyo Wells Co., Ltd., "TWA-6621") under the conditions of a sealing temperature of 160°C, a load of 5 kgf, a sealing time of 60 milliseconds, a carrier tape feed pitch of 4 mm, and 2 rows and 7 hits, to prepare a sample. The peel strength (N) immediately after heat sealing was measured. The peel strength immediately after heat sealing was designated as P1 (N). The peel strength was measured using a peel tester (EPI "PTS-5000") under the conditions of a peel speed of 300 mm / min, a peel angle of 170°, and a measurement temperature of 25°C. The surface roughness (Ra) of the polystyrene film was measured on the portion of the polystyrene film to be laminated with the cover tape for packaging electronic components, in accordance with JIS B 0601 (2001), using a surface roughness measuring device (Mitutoyo's "SJ-210"), with the unit being μm. The cover tape for packaging electronic components obtained above was left in a 40°C, 90% RH environment for 14 days, and then the 170° peel strength (N) of the cover tape for packaging electronic components against a polystyrene film was measured in the same manner as above. The peel strength of the cover tape for packaging electronic components immediately after heat sealing after being left in a 40°C, 90% RH environment for 14 days was designated as P2 (N). From the obtained values ​​of P1 and P2, the value of (P2 / P1)×100 was calculated. The values ​​of P1, P2 and (P2 / P1)×100 are shown in Table 1.

[0056] <Antimony content> The cover tape for packaging electronic components obtained above was completely dissolved in a solution of nitric acid / hydrochloric acid / hydrofluoric acid using microwaves, and the antimony content (ppm) of the entire cover tape for packaging electronic components was measured by inductively coupled plasma-atomic emission spectrometry (IPC). The results are shown in Table 1.

[0057] <Surface resistance value of base layer> The surface resistance (Ω) of the substrate layer surface of the cover tape for packaging electronic components obtained above was measured in a 25° C., 50% RH environment using a surface resistance measuring instrument manufactured by SIMCO (manufactured by SIMCO, “ST-3”). The results are shown in Table 1. In addition, in Table 1, for example, "5.E+10" in Example 1 is "5×10 10 " represents.

[0058] <Surface resistance value of sealant layer> The surface resistance (Ω) of the sealant layer of the cover tape for packaging electronic components obtained above was measured in a 25°C, 50% RH environment using a surface resistance measuring device manufactured by SIMCO ("ST-3" manufactured by SIMCO). The results are shown in Table 1. In addition, for example, "2.E+09" in Example 1 in Table 1 is "2×10 9 " represents.

[0059] <Amount of triboelectric charge> In the cover tape for packaging electronic components obtained above, the amount of triboelectric charge on the surface of the resin pellets was measured under conditions of 25° C. and 50% RH by the following steps (a) to (e). (a) The cover tape for packaging electronic devices was cut to a size of 25 mm wide and 200 mm long, folded in half lengthwise with the surface of the sealant layer facing inward, and both sides were taped to create a bag 25 mm wide and 100 mm long. (b) A resin pellet consisting of 85% by mass of silica and 15% by mass of epoxy resin and measuring 3 mm x 1.5 mm x 1 mm was prepared. (c) After the bag and the resin pellets were de-staticized, five of the resin pellets were placed in the bag, and the opening was taped and sealed. (d) The bag containing the resin pellets sealed in (c) above was fixed to a vortex mixer (SCIENTIFIC INDUSTRIES, Inc., "G-560E") and vibrated at 600 rpm for 5 minutes. (e) Five of the resin pellets were removed from the bag and transferred to a Faraday cup (Model 231, manufactured by Electro-Tech Systems). The charge of the five resin pellets was measured using a nanocoulombmeter (Model 230, manufactured by Electro-Tech Systems) at 25°C and 50% RH. The absolute value of the measured value was taken as the amount of triboelectric charge. The results are shown in Table 1.

[0060] The measured triboelectric charge was then evaluated based on the following criteria. The results are shown in Table 1. Antistatic evaluation criteria: ◎: Triboelectric charge is 0.0nC or more and 0.2nC or less ○: Triboelectric charge is greater than 0.2 nC and less than 1.0 nC ×: Triboelectric charge is greater than 1.0 nC

[0061] <Total light transmittance> The total light transmittance (%) of the cover tape for packaging electronic components obtained above was measured in accordance with JIS K7361-1 (1997) using a Haze Meter NDH 2000 manufactured by Nippon Denshoku Kogyo Co., Ltd. under a light source of D65. The results are shown in Table 1.

[0062] <External Haze> The external haze (%) of the cover tape for packaging electronic components obtained above was measured in accordance with JIS K7136 (2000) using a Haze Meter NDH 2000 manufactured by Nippon Denshoku Kogyo Co., Ltd. under a light source of D65. The results are shown in Table 1.

[0063] [Table 1]

[0064] In Examples 1 to 4, cover tapes for packaging electronic components were obtained in which the 170° peel strength against a polystyrene film, the surface resistance value of the sealant layer surface, the surface resistance value of the base layer surface, the amount of triboelectric charge, the total light transmittance and the haze of the entire cover tape for packaging electronic components were within appropriate ranges while reducing the antimony content. Examples 1 to 4 showed peel strengths and the like comparable to those of Comparative Example 1 in which the antimony content was not reduced. In Comparative Example 2, the antimony content was reduced, but the 170° peel strength against a polystyrene film was not within the appropriate range. In Comparative Example 4, since the sealant layer did not contain an antistatic agent, a sufficient resistance value of the sealant surface was not obtained. In Comparative Example 3, the configurations of the base layer, intermediate layer, and sealant layer did not satisfy the requirements, and therefore the 170° peel strength against the polystyrene film was not within the appropriate range. [Explanation of symbols]

[0065] 1 Base material layer 2. Middle Tier 3 Sealant Layer 10 Cover Tape 20 Carrier Tape 21 Pocket 100 Electronic component packaging body

Claims

[Claim 1] A base layer; The middle class, A sealant layer; A cover tape for packaging electronic components, comprising: the sealant layer comprises an adhesive resin and an antistatic agent; The antistatic agent is (A) phosphorus-doped tin (B) Carbon nanotubes (C) Polythiophene or polythiophene derivative Contains one or more selected from the group consisting of The peel strength against a polystyrene film measured by the method described below in "Peel Strength Measurement" is 0.3 N or more and 0.9 N or less, The cover tape for packaging electronic components has an antimony content of 0 ppm or more and 150 ppm or less, measured for the entire cover tape for packaging electronic components. <Peel Strength Measurement> The cover tape for packaging electronic components is cut to a width of 5.5 mm, and the sealant layer side of the cover tape is aligned with the uneven surface side of a polystyrene film that is 8 mm wide and has an average surface roughness (Ra) of 0.25 μm. The uneven surface is heat-sealed using a two-blade iron with one blade measuring 0.5 mm wide and 28 mm long under conditions of a sealing temperature of 160°C, a load of 5 kgf, a sealing time of 60 milliseconds, and a carrier tape feed pitch of 4 mm. The peel strength of the cover tape for packaging electronic components against the polystyrene film is measured under conditions of a peel speed of 300 mm / min, a measurement temperature of 25°C, and a peel angle of 170°.

Citation Information

Patent Citations

  • Transparent double-sided conductive cover tape and resin composition for antistatic layer

    JP2019064739A