Emulation circuit, emulation apparatus, program development tool, program, method of monitoring state of special function register, and method of manufacturing semiconductor device

Abstract

To provide an emulation circuit which facilitates monitoring a special function register (SFR) in an application program by comparing an expected value with a flag value of the special function register.SOLUTION: An emulation circuit 21 includes a state comparison circuit 41, a counting circuit 43, and a flag comparison circuit 45. The state comparison circuit 41 stores a reference value of internal state which may be generated when a microcomputer 24 executes a program code. The flag comparison circuit 45 stores an expected value which is associated with a special function register circuit 23d. The state comparison circuit 41 detects a match between the reference value and a state value of internal state received from the microcomputer 24 during the execution of the program code. The flag comparison circuit 45 detects a match between the expected value in the flag comparison circuit 45 and the state value of the special function register. The counting circuit 43 measures the time elapsed between the match in the state comparison circuit 41 and the match in the flag comparison circuit 45.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to an emulation circuit, an emulation device, a program development tool, a program, a method for monitoring the state of a special function register, and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a program development environment for a microcomputer with multiple CPUs on the same chip. Patent Document 1 discloses the allocation of a memory area, which has an SFR (Special Function Register) area at a specific address, and in this SFR area, control registers for peripheral function circuits such as input / output ports and timer functions are allocated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-98692 Summary of the Invention [Problem to be solved by the invention]

[0004] An in-circuit emulator or an on-chip debug emulator (hereinafter referred to as "ICE") is used to debug a program stored in a microcomputer. The program accesses status flags (hereinafter referred to as "flags") in control registers such as special function registers (hereinafter referred to as "SFRs") to obtain information related to the status of peripheral circuits stored in the microcomputer or external circuits connected to the microcomputer. Debugging related to the contents of the special function registers is performed using, for example, a trace function and / or a step execution function, which are built into the ICE.

[0005] Specifically, when using an ICE to debug a program that checks SFR flag values, the trace contents, such as the program counter and / or SFR contents, are dumped after the program is executed. The dumped values ​​of the trace contents are compared with expected values ​​using the ICE's trace function until the SFR flag values ​​match the expected values. This comparison is repeated until the program is completed or debugging is complete.

[0006] If the trace function cannot be used on the ICE (for example, when an on-chip debug emulator is used), debugging is performed by repeating the execution of steps from the start of the check until the flag value of the SFR matches the expected value.

[0007] However, when debugging a user application program that compares the flag value of an SFR with an expected value, the following problems exist with the trace function and step execution function.

[0008] Regarding the trace function, the contents of the SFR flags are not reflected in the trace results until the program (instruction) reads them, which makes it difficult to understand the exact timing when the flags change.

[0009] Regarding the step execution function, in order to grasp the exact timing of flag changes, it is necessary to execute the program one instruction at a time and check the contents of the SFR at each step of execution. Executing each step and checking the contents of the SFR is cumbersome.

[0010] In addition, application programs are sometimes configured to periodically compare SFR flag values ​​with expected values. These application programs often include interrupt processing routines that are triggered when a preset condition is met. However, in order to check for delays and missed comparisons due to interrupts, new functions are required in addition to the above-mentioned trace and step execution functions.

[0011] What is needed is a debugging feature that makes it easy to understand the timing of flag changes.

[0012] The present disclosure aims to provide an emulation circuit, an emulation device, a program development tool, a program, a method for monitoring the state of a special function register, and a method for manufacturing a semiconductor device, which facilitate monitoring of a special function register in an application program. [Means for solving the problem]

[0013] An emulation circuit according to a first aspect of the present disclosure is an emulation circuit configured to be communicatively connected to a semiconductor device via a connection device and to be communicatively connected to a debugging device, the emulation circuit being connected to the connection device via a clock line, the clock line being configured to be capable of propagating a clock signal that causes the semiconductor device and the emulation circuit to operate in synchronization, the emulation circuit including a state comparison circuit, a counting circuit, and a flag comparison circuit, the state comparison circuit being configured to store a reference value of an internal state that may occur in the microcomputer of the semiconductor device when the microcomputer executes a program code, and the flag comparison circuit being configured to store a reference value of an internal state that may occur in the microcomputer when the microcomputer executes a program code, the state comparison circuit is configured to detect a match / mismatch between the state value of the internal state received from the microcomputer via the connection device and the reference value during execution of the program code; the flag comparison circuit is configured to detect a match / mismatch between at least a portion of the bit string signal received from the special function register circuit via the connection device and the expected value of the flag comparison circuit; and the counter circuit is configured to measure the elapsed time between the detection of the match in the state comparison circuit and the detection of the match in the flag comparison circuit and to store a count value related to the measurement.

[0014] An emulation device according to a second aspect of the present disclosure comprises a connection device configured to be connectable to a semiconductor device including a microcomputer, an input / output device configured to be connectable to a debugging device, an emulation circuit as described in the first aspect and connected to the connection device and the input / output device, and a mounting member on which the emulation circuit, the connection device, and the input / output device are mounted.

[0015] A third aspect of the present disclosure provides a program configured to be installed in a computer system including a display device, a processor, and a memory, the computer system being connected to an emulation circuit, the emulation circuit being connected to a semiconductor device including a microcomputer, the program being stored in the memory, and the program being configured, when executed by the processor, to cause the computer system to perform the following operations: requesting input of a reference value for an internal state that may occur in the microcomputer during execution of a program code to be executed by the microcomputer, and receiving the input, the reference value being stored in one or more expected value register circuits of a state comparison circuit of the emulation circuit; soliciting input of an expected value associated with a special function register circuit of the microcomputer, the expected value being stored in one or more expected value register circuits of a flag comparison circuit of the emulation circuit; soliciting input of the expected value and receiving the input; soliciting input of a start instruction instructing the program code to start operation, the start instruction synchronizing the emulation circuit and the microcomputer to operate the program code, and during operation of the program code, at least a portion of the internal state of the microcomputer is stored as a state value in a corresponding circuit of the emulation circuit; soliciting input of the start instruction and receiving the input;and displaying a register indication on the display device, wherein in the emulation circuit, a counting circuit of the emulation circuit starts counting in response to detection of a match between the state value and the reference value, and stops counting in response to detection of a match between at least a portion of the bit string signal received from the special function register circuit and an expected value of the expected value register circuit, the counting circuit updates a count value register circuit of the counting circuit based on at least the count value of the count circuit to generate an updated value and stores the updated value in the count value register circuit, and the register indication displays a register indication including at least a portion of the content of the count value register circuit;

[0016] A fourth aspect of the present disclosure provides a method for monitoring a state of a special function register of a microcomputer during execution of program code to be executed by the microcomputer, the method comprising: connecting a semiconductor device including the microcomputer to a connection device of an emulation device including an emulation circuit; inputting a reference value of an internal state that may occur in the microcomputer during execution of the program code, the reference value being stored in one or more first expected value register circuits of a state comparison circuit of the emulation circuit; inputting an expected value associated with the special function register, the expected value being stored in one or more second expected value register circuits of a flag comparison circuit of the emulation circuit; and inputting a start instruction to run the program code in the emulation device, the start instruction running the program code and monitoring the internal state of the semiconductor device during the operation of the program code. and inputting a start instruction, wherein at least some of the state values ​​of the special function registers are stored in corresponding circuits of the emulation circuit; and displaying a register display on a display device of the emulation device, wherein the emulation circuit causes a counter circuit of the emulation circuit to start counting in response to detection of a match between a certain state value of the state values ​​and the reference value, and the emulation circuit causes the counter circuit to stop the counting in response to detection of a match between at least a portion of a bit string signal received from the special function register during operation of the program code and the expected value, the emulation circuit holds a count value of a count value register circuit of the counter circuit, and the emulation circuit updates contents of a maximum value register circuit and a minimum value register circuit of the counter circuit based on the count value of the count value register circuit, and the register display displays the register display including an indication of the updated values ​​of the maximum value register circuit and the minimum value register circuit.

[0017] A method for manufacturing a semiconductor device according to a fifth aspect of the present disclosure comprises performing the method described in the fourth aspect to update the program code to create updated program code, and writing the updated program code to a flash memory of the semiconductor device to manufacture a written semiconductor device. [Effects of the Invention]

[0018] According to the above aspects, it is possible to provide an emulation circuit, an emulation device, a program development tool, a program, a method for monitoring the state of a special function register, and a method for manufacturing a semiconductor device, which facilitate monitoring of a special function register in an application program. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a diagram schematically showing a program development tool, an emulation device, and an emulation circuit according to this embodiment. [Figure 2] FIG. 2 is a diagram schematically showing a program development tool according to this embodiment. [Figure 3] FIG. 3 is a block diagram that schematically illustrates an exemplary emulation circuit according to this embodiment. [Figure 4] FIG. 4 is a block diagram that schematically illustrates an exemplary program development tool according to this embodiment. [Figure 5] FIG. 5 is a block diagram that schematically illustrates an exemplary program development tool according to this embodiment. [Figure 6] FIG. 6 is a block diagram that schematically illustrates an exemplary program development tool according to this embodiment. [Figure 7] FIG. 7 is a diagram schematically illustrating an exemplary computer system in a program development tool according to this embodiment. [Figure 8] FIG. 8 is a block diagram showing modules for a program of a program development tool according to this embodiment. [Figure 9]FIG. 9 is a diagram illustrating the main steps of various methods according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, where possible, identical parts will be designated by the same reference numerals and redundant description will be omitted.

[0021] FIG. 1 is a diagram schematically showing a program development tool, an emulation device, and an emulation circuit according to this embodiment.

[0022] The program development tool 11 includes an emulation device 13 and a debug device 15. An exemplary program development tool 11 is called an in-circuit emulator (ICE). The emulation device 13 includes a connection device 17, an input / output device 19, an emulation circuit 21, and a mounting member 27 such as a circuit board (board). The mounting member 27 mounts the emulation circuit 21, the connection device 17, and the input / output device 19.

[0023] The debug device 15 includes a computer system 20 that is connected to the emulation device 13 and includes a display device 31 , a processor 33 , and a memory 35 .

[0024] The connection device 17 is configured to be connectable to the semiconductor device 23. The input / output device 19 is configured to be connectable to the debugging device 15. The emulation circuit 21 is configured to be connected to the connection device 17 and the input / output device 19. The semiconductor device 23 includes a microcomputer 24. The mounting member 27 includes a clock line 39b, a local bus 39c, and a system bus 39d. The clock line 39b connects the emulation circuit 21 and the connection device 17 so that the semiconductor device 23 and the emulation circuit 21 operate synchronously. The local bus 39c enables communication (e.g., signals such as SFR addresses, SFR data, and strobe signals) between the semiconductor device 23 and the emulation circuit 21 via the connection device 17. The system bus 39d (communication bus) enables communication between the debugging device 15 and the emulation circuit 21 via the input / output device 19. The mounting member 27 can be, for example, a circuit board. The SFR line 39f connects the special function register circuit 23d of the microcomputer 24 to the emulation circuit 21.

[0025] The emulation circuit 21 is configured to be connected to the connection device 17 and the input / output device 19. The emulation circuit 21 can be manufactured by a semiconductor process for fabricating, for example, a CMOS semiconductor device.

[0026] The semiconductor device 23 includes a microcomputer 24, which includes a central processing unit 23a, a clock control circuit 23b, a bus bridge circuit 23c, a special function register circuit 23d, a program memory circuit 23e, and a peripheral circuit 23f.

[0027] The special function register of exemplary special function register circuit 23d stores a flag indicating the state of a port that controls an external device, for example. The value of the flag indicates the state of the external device controlled by semiconductor device 23, for example.

[0028] The emulation circuit 21 is connected to the connection device 17 via a clock line 39b, and the clock line 39b is configured to be capable of transmitting a clock signal CLK that causes the semiconductor device 23 and the emulation circuit 21 to operate in synchronization.

[0029] 1, emulation circuitry 21 generally includes a trace memory and trace circuitry 47 and a step and break circuitry 49. Trace memory and trace circuitry 47 is bidirectionally communicatively connected to special function register circuitry 23d and program memory circuitry 23e. Step and break circuitry 49 is connected to program memory circuitry 23e.

[0030] The step and break circuit 49 generates a program start signal in response to an instruction signal received from the debugging device 15 via the system bus 39d.

[0031] The trace memory and trace circuit 47 is connected to the special function register circuit 23d via a bus (e.g., an SFR bus). The trace memory and trace circuit 47 can transmit and / or receive via the bus (e.g., an SFR bus). This communication allows for the transmission and / or reception of signals such as SFR addresses, SFR data, and strobe signals.

[0032] The emulation circuit 21 further includes a state comparison circuit 41 , a counting circuit 43 , and a flag comparison circuit 45 .

[0033] The state comparison circuit 41 stores reference values ​​associated with internal states that may occur in the microcomputer 24 during execution of program code (e.g., application program code) by the microcomputer 24 of the semiconductor device 23. The state comparison circuit 41 stores and updates the stored values ​​of internal states that occur in the microcomputer 24 via the connection device 17 in synchronization with the clock signal CLK during execution of the application program code. Exemplary internal states include at least one of the program execution address, the address and / or register value of a special function register, and a flag of a special function register.

[0034] The state comparison circuit 41 is configured to detect a match / mismatch between a state value of the internal state of the microcomputer 24 and a reference value during execution of the program code.

[0035] The state comparison circuit 41 also receives a program start signal from the step and break circuit 49 .

[0036] The flag comparison circuit 45 stores an expected value associated with the special function register circuit 23d of the microcomputer 24. The flag comparison circuit 45 stores a state value of the internal state of the microcomputer 24 during execution of the program code, for example, a bit string signal from the special function register circuit 23d, and updates the stored value according to the operation of the microcomputer 24. The bit string signal includes, for example, at least one of a value of an SFR register and / or a flag value.

[0037] The flag comparison circuit 45 is configured to detect a match / mismatch between at least a portion of the bit string signal (SFR, flag) received from the special function register circuit 23d via the connection device 17 in synchronization with the clock signal CLK and the expected value of the flag comparison circuit 45.

[0038] The counter circuit 43 is configured to measure the elapsed time between the detection of a match in the state comparison circuit 41 and the detection of a match in the flag comparison circuit 45. The counter circuit 43 is also configured to store a count value related to this measurement. The stored count value can be updated each time the program code is repeatedly executed. The measurement of the elapsed time can be performed using, for example, a clock signal CLK.

[0039] In debugging the program code, emulation circuit 21 detects the occurrence of a reference value in the internal states that can occur in microcomputer 24. Then, emulation circuit 21 detects the occurrence of an event in which at least a portion of the bit string signal from special function register circuit 23d matches the expected value of flag comparison circuit 45. Using the occurrence of the internal state related to the reference value as a reference, emulation circuit 21 detects the occurrence of an event in which a certain state value among the internal states of the special function registers in semiconductor device 23 matches the expected value. Thus, the occurrence of the expected value of special function register circuit 23d is detected using the occurrence of the certain internal state set as the reference value as a reference.

[0040] Furthermore, in debugging program code, the execution of the program code can be repeated while the contents of the registers are maintained.

[0041] 2 is a diagram schematically illustrating a program development tool according to this embodiment. The emulation circuit 21 will be described with reference to FIGS. 1 and 2. The operation of the emulation circuit 21 is initiated in response to the state comparison circuit 41 receiving a program start signal SSRT from the step and break circuit 49.

[0042] The state comparison circuit 41 is configured to detect a match / mismatch between a state value of an internal state received from the microcomputer 24 via the connection device 17 in synchronization with the clock signal CLK during execution of the program code and a reference value of the state comparison circuit 41. The state comparison circuit 41 is also configured to generate a detection trigger signal SDTRG in response to the state value matching the reference value.

[0043] Specifically, the state comparison circuit 41 can include one or more first expected value register circuits 51. The first expected value register circuit 51 is configured to store reference values ​​of internal states that may occur in the microcomputer 24 when the microcomputer 24 of the semiconductor device 23 executes program code. These reference values ​​are provided in advance to the first expected value register circuit 51 via the system bus 39d.

[0044] The state comparison circuit 41 includes one or more state value update register circuits 53. The state value update register circuits 53 receive a certain state value of the internal state of the microcomputer 24 during operation of the semiconductor device 23 from the microcomputer 24 via the local bus 39c. The state value can be stored in the state value update register circuits 53. The state value of the state comparison circuit 41 is updated via the connection device 17 in synchronization with the clock signal CLK during execution of the program code.

[0045] The state comparison circuit 41 may also include a state comparator 55. The state comparator 55 compares the reference value of the first expected value register circuit 51 with the state value of the state value update register circuit 53 in synchronization with the clock signal CLK, and generates a detection trigger signal SDTRG when the comparison result indicates that the reference value and the state value match.

[0046] The state comparison circuit 41 can provide a detection trigger signal SDTRG to the counting circuit 43 .

[0047] Flag comparison circuit 45 detects a match / mismatch between at least a portion of the bit string signal received from special function register circuit 23d and an expected value of flag comparison circuit 45. Flag comparison circuit 45 is configured to generate an expected value match trigger signal SXTRG in response to at least a portion of the received bit string signal (SBIT) matching the expected value of flag comparison circuit 45.

[0048] Specifically, flag comparison circuit 45 includes one or more second expected value register circuits 61, which are configured to store expected values ​​associated with special function register circuit 23d of microcomputer 24. These expected values ​​are provided to second expected value register circuits 61 in advance via system bus 39d.

[0049] The flag comparison circuit 45 may include one or more flag update register circuits 63. The flag comparison circuit 45 receives, via the local bus 39c, the current value of the bit string in the special function register circuit 23d of the operating microcomputer 24 of the semiconductor device 23. This value may be stored in the flag update register circuit 63, for example.

[0050] The flag comparison circuit 45 may include a flag comparator 65. The flag comparator 65 detects a match / mismatch between at least a portion of the bit string signal received from the special function register circuit 23d via the connection device 17 in synchronization with the clock signal CLK and the expected value of the second expected value register circuit 61 of the flag comparison circuit 45. The flag comparator 65 compares the expected value of the second expected value register circuit 61 with the state value of the flag update register circuit 63, and generates an expected value match trigger signal SXTRG when the comparison result indicates a match between the expected value and the state value.

[0051] The flag comparison circuit 45 can provide the expected value match trigger signal SXTRG to the counter circuit 43 after receiving the measurement start trigger signal SCTRG.

[0052] The counter circuit 43 measures the time until at least a portion of the bit string signal from the special function register of the special function register circuit 23d reaches an expected value after the internal state of the microcomputer 24 during operation of the semiconductor device 23 reaches a reference value.

[0053] The counter circuit 43 may include a count register circuit 71. The count register circuit 71 is configured to measure the elapsed time between the detection of a match in the state comparison circuit 41 and the detection of a match in the flag comparison circuit 45, and stores a count related to this measurement. The stored count can be updated each time the program code is repeatedly executed.

[0054] Specifically, the count value register circuit 71 may include a maximum value register circuit 75 and a minimum value register circuit 77. The maximum value register circuit 75 stores the maximum value of the count values ​​of the measurements for each iteration of the program code, and the minimum value register circuit 77 stores the minimum value of the count values ​​of the measurements for each iteration of the program code.

[0055] The counting circuit 43 updates the maximum value register circuit 75 and the minimum value register circuit 77 based on the count value, the first stored value in the maximum value register circuit 75, and the second stored value in the minimum value register circuit 77. As a result of this updating, the maximum value register circuit 75 can store the maximum value of the count values ​​thus far, and the minimum value register circuit 77 can store the minimum value of the count values ​​thus far.

[0056] The count value register circuit 71 includes a first comparator 78b connected to the maximum value register circuit 75, and the first comparator 78b performs a first comparison to detect whether the count value matches or does not match the first stored value. The count value register circuit 71 may include a first update circuit 79b connected to the maximum value register circuit 75. The count value register circuit 71 includes a first update circuit 79b that updates the maximum value register circuit 75 based on the result of the first comparison, maintaining the stored value in the maximum value register circuit 75 greater than or equal to the count value. The maximum value register circuit 75 stores the updated update value as a first stored value.

[0057] The minimum value register circuit 77 includes a second comparator 78c configured to perform a second comparison to detect whether the count value and the second stored value match. The count value register circuit 71 may include a second update circuit 79c connected to the minimum value register circuit 77. The second update circuit 79c updates the minimum value register circuit 77 based on the result of the second comparison, so that the stored value in the minimum value register circuit 77 remains smaller than or equal to the count value. The minimum value register circuit 77 is configured to store the updated minimum update value as a second stored value.

[0058] The counting circuit 43 can be configured to provide at least one of the count value of the count value register circuit 71, the first stored value, and the second stored value to the debugging device 15. The debugging device 15 can display the first stored value and the second stored value on a display device in response to updating of the emulation circuit 21.

[0059] Providing at least one of the count value of the count value register circuit 71, the first stored value, and the second stored value to the debugging device 15 can be performed in response to a request received from the debugging device 15. The debugging device 15 can store some or all of the received first stored value and second stored value as history. The debugging device 15 can display all or part of the series of history.

[0060] The counter circuit 43 may further include a count circuit 72. In response to receiving the detection trigger signal SDTRG, the counter circuit 43 starts counting by the count circuit 72. In addition, in response to receiving the expected value match trigger signal SXTRG, the counter circuit 43 stops counting by the count circuit 72.

[0061] The count register circuit 71 may include a count register 73, which is configured to store the count of the measurement and to update the count of the count circuit 72. In response to receiving the expected value match trigger signal SXTRG, the count circuit 43 can cause the count register 73 to stop updating the count. The count register circuit 71 of the count circuit 43 stores the count when the count circuit 72 is stopped.

[0062] The start of the elapsed time is identified by the counter circuit 43 initiating counting of the clock signal CLK in the count circuit 72 in response to receiving the detection trigger signal SDTRG.

[0063] In addition, in response to receiving the detection trigger signal SDTRG, the counter circuit 43 can generate a measurement start trigger signal SCTRG that indicates that the counter circuit 43 has started counting. The measurement start trigger signal SCTRG can be provided to the flag comparison circuit 45.

[0064] The end of the elapsed time is identified by the counter circuit 43 causing the count circuit 72 to stop counting the clock signal CLK in response to receiving the expected value match trigger signal SXTRG.

[0065] 3 is a block diagram illustrating an exemplary emulation circuit according to the present embodiment. The emulation circuit 21 includes a state comparison circuit 41, a counter circuit 43, a flag comparison circuit 45, and a control circuit 40. The exemplary state comparison circuit 41 may include multiple state comparison circuits, such as a state comparison circuit 41b, a state comparison circuit 41c, and a state comparison circuit 41d. The control circuit 40 is connected to the system bus 39d and generates a signal to activate one of the state comparison circuits 41b, 41c, and 41d in response to a signal from the debug device 15.

[0066] The exemplary flag comparison circuit 45 includes an output control circuit 67. The output control circuit 67 can receive the measurement start trigger signal SCTRG and, after receiving the measurement start trigger signal SCTRG, enables output of the expected value match trigger signal SXTRG.

[0067] The exemplary counting circuit 43 includes a count control circuit 70 that starts counting in a counting circuit 72 in response to receiving a detection trigger signal SDTRG. The count control circuit 70 also stops counting in a counting circuit 72 in response to receiving an expected value match trigger signal SXTRG. The count control circuit 70 can generate a measurement start trigger signal SCTRG. The count control circuit 70 causes a count value register 73 to update the count value of the counting circuit 72. The count control circuit 70 can cause the count value register 73 to stop updating the count value in response to receiving the expected value match trigger signal SXTRG.

[0068] Figure 4 is a block diagram schematically showing an exemplary program development tool according to the present embodiment. Figure 5 is a block diagram schematically showing an exemplary program development tool according to the present embodiment. Figure 6 is a block diagram schematically showing an exemplary program development tool according to the present embodiment.

[0069] The emulation device 13 will be described with reference to Figures 1 to 3 and Figure 4. Specifically, Figure 4 will be referred to in order to describe the state comparison circuit 41b shown in Figure 3.

[0070] The status values ​​of the internal state of the microcomputer 24 may include the current address of the currently executing program code being executed in the semiconductor device 23 .

[0071] In the state comparison circuit 41 (41b), the first expected value register circuit 51 includes an address register 51b. The address register 51b stores, as a reference value, a start address that is a reference for the execution of the program code.

[0072] Prior to the execution of the program code, the start address is provided to the first expected value register circuit 51 from the debugging device 15 via the system bus 39d of the program development tool 11. Specifically, the start address represents the value of a physical address.

[0073] The state comparison circuit 41 receives a program start signal SSRT from the step and break circuit 49 .

[0074] When execution of the program code starts, the state comparison circuit 41 is configured to receive the instruction address (current address) of the program code being executed in the semiconductor device 23 via the connection device 17 from the semiconductor device 23 as a state value of the internal state.

[0075] Specifically, in the state comparison circuit 41, the state value update register circuit 53 includes an address update register 53b, and the address update register 53b stores the instruction address (current address) of the program code currently being executed.

[0076] The state comparator 55 of the state comparison circuit 41 includes an address comparator 55b, which detects whether the values ​​of the start address and the instruction address match. The state comparison circuit 41 generates a detection trigger signal SDTRG in response to the current address matching the start address. An exemplary address comparator 55b may include, for example, a logic circuit that detects a bit-by-bit match / mismatch between the start address and the instruction address.

[0077] In the counter circuit 43, the count circuit 72 and the maximum value register circuit 75 and minimum value register circuit 77 of the count value register circuit 71 can be reset via the system bus 39d of the program development tool prior to execution of the program code.

[0078] The reset process can provide the maximum value register circuit 75 with a reset value for the maximum value register circuit 75 and can provide the minimum value register circuit 77 with a reset value for the minimum value register circuit 77 .

[0079] In flag comparison circuit 45, second expected value register circuit 61 may include an expected value register 61b that stores an expected value associated with a certain special function register of special function register circuit 23d of microcomputer 24. This expected value is provided to expected value register 61b from debug device 15 via system bus 39d prior to execution of the program code.

[0080] The flag comparison circuit 45 is configured to receive a bit string signal SBIT (including SFR values ​​and / or flags) from the special function register circuit 23d of the semiconductor device 23 via the connection device 17 during execution of the program code. The bit string signal SBIT includes at least a portion of the flags of the special function register. The bit string signal can be updated periodically, for example, for each step of the program code.

[0081] Flag comparison circuit 45 can detect whether at least some or all of the flags in the special function register match or mismatch with the expected value. When flag comparison circuit 45 monitors only some of the flags in the special function register, it masks the bit string of the special function register to match the comparison bit width with the width of the effective bits of the expected value.

[0082] Specifically, the flag update register circuit 63 may include a flag update register 63b and a masking register 63c. The masking register 63c is used to select one or more bits to be compared from the bit string signal SBIT. The masking register 63c receives a masking value from the debug device 15 via the system bus 39d prior to execution of the program code.

[0083] The flag update register circuit 63 applies a masking value in the masking register 63c to generate a masked bit string signal. The value of the masked bit string signal can be held as an update value in the flag update register 63b. The flag update register 63b stores the flag of the masked bit string signal. In the exemplary flag update register circuit 63, the bit string signal SBIT from the special function register, the flag update register 63b, and the masking register 63c can all have the same bit width.

[0084] The flag comparator 65 compares the expected value in the expected value register 61b with the masked bit string signal in the flag update register 63b, and generates an expected value match trigger signal SXTRG when the comparison result indicates a match between the expected value and the update value. The flag comparator 65 includes, for example, a logic circuit that detects a match / mismatch for each bit between the expected value in the second expectation register circuit 61 and the update value of the masked bit string signal.

[0085] As described above, the detection trigger signal SDTRG is provided to the counter circuit 43 in response to a match between the physical address and the start address in the execution of the program code. The counter circuit 43 starts counting by the count circuit 72. The expected value match trigger signal SXTRG is provided to the counter circuit 43 in response to a match between at least a portion of the flags of the special function register and the expected value. The counter circuit 43 stops counting by the count circuit 72. The count value of the count circuit 72 represents a period defined by the time interval between two matches.

[0086] Emulation circuit 21 is also provided with address register 51b, address update register 53b, expected value register 61b, and flag update register 63b. Emulation circuit 21 allows debug device 15 to display the number of clock-based cycles (maximum and minimum values) until a match between the flag value of a special function register and its expected value occurs after an address previously specified in the program code is executed. Emulation circuit 21 enables debugging to be performed more quickly and efficiently than when using the trace function and step execution function used in trace memory and trace circuit 47 and step and break circuit 49.

[0087] (Example Action 1) Prior to the operation of the application program, the debug device 15 performs the initialization and initial value setting already described in the emulation circuit 21 via the system bus 39d. After the initialization and initial value setting, the operation of the application program begins. In synchronization with the clock signal CLK from the semiconductor device 23, the state comparator 55 compares the value of the address register 51b with the value of the address update register 53b, and if these values ​​match, outputs a detection trigger signal SDTRG. The detection trigger signal SDTRG can be, for example, a one-shot trigger pulse.

[0088] In response to receiving the detection trigger signal SDTRG, the counter circuit 43 starts counting in the count circuit 72 in synchronization with the clock signal CLK. After starting counting in the count circuit 72, the counter circuit 43 outputs a measurement start trigger signal SCTRG in response to receiving the detection trigger signal SDTRG. The measurement start trigger signal SCTRG is provided to the flag comparison circuit 45. The measurement start trigger signal SCTRG can be, for example, a one-shot trigger pulse.

[0089] The flag comparator circuit 45 calculates the logical product of the bit string signal from the semiconductor device 23 and the masking value of the masking register 63c in synchronization with the clock signal CLK. The value of this logical product is stored in the flag update register 63b and is compared with the expected value of the expected value register 61b in synchronization with the clock signal CLK. After receiving the measurement start trigger signal SCTRG, when this comparison result changes from mismatch to match, the flag comparator 65 outputs an expected value match trigger signal SXTRG. The expected value match trigger signal SXTRG can be, for example, a one-shot trigger pulse. The expected value register 61b, the bit string signal SBIT, the flag update register 63b, and the masking register 63c can have the same bit width.

[0090] In response to receiving the expected value match trigger signal SXTRG, the counter circuit 43 synchronizes with the clock signal CLK and stops the counting of the count circuit 72. The counter circuit 43 stores the count value of the count circuit 72 at the time of stopping the counting in the count value register 73.

[0091] After the count value register 73 stores the count value of the count circuit 72 , the count value of the count value register 73 is used to update the values ​​of the maximum value register circuit 75 and the minimum value register circuit 77 .

[0092] In the first comparison, the count value is compared with the reset values ​​of the maximum value register circuit 75 and the minimum value register circuit 77. As a result of the comparison, the maximum value register circuit 75 stores the larger of the reset value of the maximum value register circuit 75 and the current count value as an updated value. Also, the minimum value register circuit 77 stores the smaller of the reset value of the minimum value register circuit 77 and the current count value that is greater than zero as an updated value.

[0093] In the subsequent comparison, the maximum value register circuit 75 stores the larger of the existing value of the maximum value register circuit 75 and the current count value as an updated value, and the minimum value register circuit 77 stores the smaller of the existing value of the minimum value register circuit 77 and the current count value as an updated value.

[0094] The debugging device 15 reads the emulation circuit 21 via the system bus 39d and displays the stored values ​​of the maximum value register circuit 75 and the minimum value register circuit 77 on the screen of the display device 31.

[0095] The state comparison circuit 41c in the emulation circuit 21 shown in FIG. 3 will be described with reference to FIGS. 1 to 3 and 5. FIG.

[0096] The status value of the internal status of microcomputer 24 includes the SFR address of the special function register in special function register circuit 23d of microcomputer 24 and at least a part of the SFR data flag associated with this special function register.

[0097] The first expected value register circuit 51 of the state comparison circuit 41 (41c) includes a special function register address circuit 51c and a special function register data circuit 51d. The special function register address circuit 51c stores a reference address associated with a special function register in the special function register circuit 23d as a reference value. The special function register data circuit 51d stores expected value data at the reference address associated with the special function register as a reference value.

[0098] The state comparison circuit 41 receives a program start signal SSRT from the step and break circuit 49 .

[0099] Prior to the execution of the program code, the base address and expected value data are provided from the debug device 15 to the special function register address circuit 51c and the special function register data circuit 51d via the system bus 39d, respectively.

[0100] The state value update register circuit 53 can include an SFR address update register 53c and an SFR data update register 53d.

[0101] The state comparison circuit 41 receives, via the connection device 17, from the semiconductor device 23, an SFR address associated with the base address of a special function register associated with the program code being executed in the semiconductor device 23, and an SFR data flag (e.g., a bit string signal) associated with this SFR address. The SFR address and SFR data flag are stored in an SFR address update register 53c and an SFR data update register 53d, respectively, of the state value update register circuit 53. The SFR data flag includes at least a portion of the flag of the special function register. The SFR data flag can be updated periodically, for example, for each step of the program code, and the state comparison circuit 41 holds the updated value.

[0102] Status comparison circuit 41 can detect whether at least some or all of the SFR data flags of the special function register match or mismatch with a reference value. When flag comparison circuit 45 monitors a portion of the flags of the special function register, it masks the bit string of the special function register to match the width of the comparison bits of the expected value.

[0103] The state value update register circuit 53 may further include a masking register 53f. The masking value of the masking register 53f is provided to the masking register 53f from the debug device 15 via the system bus 39d prior to the execution of the program code.

[0104] The state value update register circuit 53 applies the masking value of the masking register 53f to the update value of the SFR data received from the semiconductor device 23 to generate masked SFR data (e.g., a masked bit string signal) and stores it in the SFR data update register 53d. The SFR data, the special function register data circuit 51d, the SFR data update register 53d, and the masking register 53f can all have the same bit width.

[0105] The status comparator 55 includes an SFR address comparator 55c and an SFR data comparator 55d. The SFR address comparator 55c detects whether the reference address value and the updated value of the SFR address match, and the SFR data comparator 55d detects whether the expected data value and the updated value of the SFR data flag match. The status comparison circuit 41 generates a detection trigger signal SDTRG in response to both matches. The status comparator 55 includes, for example, logic circuits that detect bit-by-bit match / mismatch between the reference address value and the SFR address, and bit-by-bit match / mismatch between the expected data value and the SFR data flag.

[0106] In the state comparison circuit 41 (41c in FIG. 3), the state comparator 55 includes an output circuit 55g, which receives two match signals and outputs a detection trigger signal SDTRG in response to receiving the two match signals.

[0107] As already explained, in the counter circuit 43, the count circuit 72, maximum value register circuit 75, and minimum value register circuit 77 can be reset via the system bus 39d of the program development tool prior to execution of the program code. The reset process can provide a reset value for the maximum value register circuit 75 to the maximum value register circuit 75, and can provide a reset value for the minimum value register circuit 77 to the minimum value register circuit 77.

[0108] In flag comparison circuit 45, second expected value register circuit 61 may include an expected value register 61c that stores an expected value associated with a certain special function register of special function register circuit 23d of microcomputer 24. This expected value is provided to expected value register 61c from debug device 15 via system bus 39d prior to execution of the program code.

[0109] The flag comparison circuit 45 is configured to receive a bit string signal from a special function register of the semiconductor device 23 via the connection device 17 during execution of the program code. The bit string signal includes at least a portion of the flags of the special function register. The bit string signal can be updated periodically, for example, for each step of the program code.

[0110] As already explained, flag comparison circuit 45 can detect whether at least some or all of the flags in the special function register match or mismatch with expected values. When flag comparison circuit 45 monitors a portion of the flags in the special function register, it masks the bit string of the special function register to match the comparison bits of the expected value.

[0111] The flag update register circuit 63 may include a flag update register 63b and a masking register 63c. The masking register 63c is used to select one or more bits to be compared from the bit string signal SBIT. The flag update register circuit 63 applies a masking value of the masking register 63c to the updated value of the bit string signal SBIT received from the special function register to generate a masked bit string signal and store it in the flag update register 63b.

[0112] The flag comparator 65 compares the expected value in the expected value register 61c with the updated value of the masked bit string signal in the flag update register 63b, and generates an expected value match trigger signal SXTRG when the comparison result indicates a match between the expected value and the updated value. The flag comparator 65 includes, for example, a logic circuit that detects a match / mismatch for each bit between the expected value in the expected value register 61c and the updated value of the masked bit string signal.

[0113] As described above, the detection trigger signal SDTRG is provided to the counter circuit 43 in response to the SFR address and SFR data flags matching the reference address and expected data, respectively, during execution of the program code. The counter circuit 43 starts counting by the count circuit 72. The expected value match trigger signal SXTRG is provided to the counter circuit 43 in response to at least a portion of the flags of the special function register matching the expected value. The counter circuit 43 stops counting by the count circuit 72. The count value of the count circuit 72 represents a period defined by the time interval between two matches.

[0114] The emulation circuit 21 is also provided with a special function register address circuit 51c, a special function register data circuit 51d, an SFR data update register 53d, an expected value register 61c, and a flag update register 63b. The emulation circuit 21 allows the debug device 15 to display the number of clock-based cycles (e.g., maximum and minimum values) required until the flag value of the special function register matches its expected value after an SFR address and its data specified in advance by the program code match a reference value. The emulation circuit 21 enables debugging to be performed more efficiently and in a shorter time than when using the trace function and step execution function of the trace memory and trace circuit 47 and the step and break circuit 49.

[0115] (Example Action 2) Prior to the operation of the application program, the debug device 15 performs the initialization and initial value setting already explained in the emulation circuit 21 via the system bus 39d. After the initialization and initial value setting, the operation of the application program starts. The SFR addresses and SFR data flags accessed by the application program are used as reference values. The registers related to the SFR addresses and SFR data flags in the emulation circuit 21 are updated based on the SFR addresses and SFR data flags in the semiconductor device 23 in synchronization with the clock signal CLK.

[0116] During the operation of the application program, when the SFR address and SFR data flag match their respective pre-specified reference values, the state comparison circuit 41 outputs a detection trigger signal SDTRG, which may be, for example, a one-shot trigger pulse.

[0117] In response to receiving the detection trigger signal SDTRG, the counter circuit 43 starts counting in the count circuit 72 in synchronization with the clock signal CLK. After starting counting in the count circuit 72, the counter circuit 43 outputs a measurement start trigger signal SCTRG in response to receiving the detection trigger signal SDTRG. The measurement start trigger signal SCTRG is provided to the flag comparison circuit 45. The measurement start trigger signal SCTRG can be, for example, a one-shot trigger pulse.

[0118] Flag comparator circuit 45 receives a bit string signal that is a collection of flags from the special function registers, and the bit string signal is updated in synchronization with clock signal CLK.

[0119] The flag comparison circuit 45 calculates the logical product of the bit string signal from the semiconductor device 23 and the masking value of the masking register 63c in synchronization with the clock signal CLK. The expected value register 61c, the bit string signal, the masking register 63c, and the second flag update register 63d all have the same bit width. The value of this logical product is stored in the flag update register 63b and compared with the expected value of the expected value register 61c in synchronization with the clock signal CLK. After receiving the measurement start trigger signal SCTRG, when this comparison result changes from mismatch to match, the flag comparison circuit 45 outputs the expected value match trigger signal SXTRG. The expected value match trigger signal SXTRG can be, for example, a one-shot trigger pulse.

[0120] In response to receiving the expected value match trigger signal SXTRG, the counter circuit 43 stops the counting of the count circuit 72. The counter circuit 43 stores in the count value register 73 the count value of the count circuit 72 at the time of stopping the counting.

[0121] After the count circuit 72 is stopped, the maximum value register circuit 75 and the minimum value register circuit 77 are updated as already explained.

[0122] The debugging device 15 reads the emulation circuit 21 via the system bus 39d and displays the stored values ​​of the maximum value register circuit 75 and the minimum value register circuit 77 on the screen of the display device 31.

[0123] The state comparison circuit 41d in the emulation circuit 21 shown in FIG. 3 will be described with reference to FIGS. 1 to 3 and 6. FIG.

[0124] The status value of the internal status of microcomputer 24 includes at least a part of the SFR flags of the SFR register in special function register circuit 23d of microcomputer 24.

[0125] The first expected value register circuit 51 of the state comparison circuit 41 (41d) includes an expected value flag register 51f, which is configured to store flag expected values ​​related to the special function registers as reference values.

[0126] The state comparison circuit 41 receives the program start signal SSRT from the step and break circuit 49 .

[0127] State comparison circuit 41 includes expected value flag register 51f, which stores first expected value data of first flags associated with at least some of the special function registers in special function register circuit 23d.

[0128] Prior to the execution of the program code, the first expected value data is provided from the debugging device 15 to the expected value flag register 51f via the system bus 39d.

[0129] The state comparison circuit 41 receives from the semiconductor device 23 via the connection device 17 the SFR data flag (for example, an SFR bit string signal, an SFR bit string) of the special function register related to the program code being executed in the semiconductor device 23.

[0130] The state value update register circuit 53 may include a first flag update register 53g, which stores the SFR data flag.

[0131] The SFR data flags include flags of at least some of the special function registers in special function register circuit 23d. The SFR data flags can be updated periodically, for example, at each step of the program code, and state comparison circuit 41 holds the updated values.

[0132] Status comparator 55 includes SFR data flag comparator 55f. SFR data flag comparator 55f can check whether some or all of the SFR data flags match or do not match the first expected value data. When flag comparison circuit 45 monitors a portion of the flags of the special function register, it masks the bit string of the special function register to match the width of the comparison bits of the expected value.

[0133] Specifically, the state value update register circuit 53 may include a masking register 53h. The first flag update register 53g stores at least a portion of the bit string signal from the special function register. The masking register 53h is used to select one or more bits from the bit string signal to be compared. The state comparator 55 applies a masking value in the masking register 53h to the updated value of the bit string signal received from the special function register to generate a masked bit string signal and stores it in the first flag update register 53g.

[0134] The state value update register circuit 53 applies the masking value of the masking register 53h to generate a masked bit string signal, whose value can be held as an update value in the first flag update register 53g.

[0135] Masking register 53f receives a masking value from debug device 15 via system bus 39d prior to execution of program code.

[0136] The SFR data flag comparator 55f detects whether the updated value of the first flag update register 53g matches the first expected value data of the expected value flag register 51f. The state comparison circuit 41 is configured to generate a detection trigger signal SDTRG in response to this match. The SFR data flag comparator 55f includes, for example, a logic circuit that detects match / mismatch for each bit between the value of the first expected value data and the value of the SFR data flag.

[0137] As already described, in the counter circuit 43, the count circuit 72 and the maximum value register circuit 75 and minimum value register circuit 77 of the count value register circuit 71 can be reset prior to execution of the program code. This resetting can be performed via the system bus 39d of the program development tool.

[0138] In flag comparison circuit 45, second expectation register circuit 61 may include expectation register 61d, which stores second expected value data for the second flag associated with at least a portion of special function register circuit 23d. The second expected value data is provided to expectation register 61d from debugging device 15 via system bus 39d prior to execution of the program code.

[0139] The flag comparison circuit 45 is configured to receive second flag data (bit string signal) from the special function register of the semiconductor device 23 via the connection device 17 during execution of the program code. The second flag data includes at least a portion of the flags of the special function register. The second flag data can be updated periodically, for example, for each step of the program code.

[0140] The second expected value register circuit 61 can check whether at least some or all of the flags of the special function register match or mismatch with the expected value. When the flag comparison circuit 45 monitors some of the flags of the special function register, it masks the bit string of the special function register to match the width of the comparison bits of the expected value.

[0141] Specifically, the flag update register circuit 63 includes a second flag update register 63d and a masking register 63f. The second flag update register 63d stores at least a portion of the bit string signal SBIT from the special function register. The masking register 63f is used to select one or more bits from the bit string signal to be compared. The flag comparator 65 applies a masking value in the masking register 63f to the updated value of the bit string signal SBIT received from the special function register to generate a masked bit string signal and store it in the second flag update register 63d.

[0142] The flag update register circuit 63 applies the masking value of the masking register 63f to generate a masked bit string signal, the value of which can be held as an update value in the second flag update register 63d.

[0143] Prior to execution of the program code, masking register 63f receives a masking value from debug device 15 via system bus 39d prior to execution of the program code.

[0144] The special function register circuit 23d stores a first flag and a second flag as mutually different flags. A change in the first flag is associated with a change in the second flag in the operation of the program code.

[0145] As described above, the detection trigger signal SDTRG is provided to the counter circuit 43 in response to at least a portion of the first flag matching the expected value data (reference value) during execution of the program code. The counter circuit 43 starts counting by the counting circuit 72. The expected value match trigger signal SXTRG is provided to the counter circuit 43 in response to at least a portion of the second flag matching the expected value, causing the counter circuit 43 to stop counting by the counting circuit 72. The count value of the counting circuit 72 represents a period defined by the time interval between two matches.

[0146] The emulation circuit 21 is also provided with an expected value flag register 51f, a first flag update register 53g, an expected value register 61d, and a second flag update register 63d. The emulation circuit 21 can display on the debug device 15 the number of clock-based cycles (maximum and minimum) required until the state value of the second flag matches its expected value after the state value of the first flag matches the expected value due to execution of the program code. The emulation circuit 21 enables debugging to be performed more efficiently and in a shorter time than when using the trace function and step execution function (which adjust the interval between comparisons of the flag and the expected value and the timing of the start of comparison during debugging) used in the trace memory and trace circuit 47 and the step and break circuit 49.

[0147] (Example Action 3) Prior to the operation of the application program, the debug device 15 performs the initialization and initial value setting already described in the emulation circuit 21 via the system bus 39d. After the initialization and initial value setting, the operation of the application program begins. The first flag in the special function register circuit 23d accessed by the application program is used as a reference value. The register related to the first flag in the emulation circuit 21 is updated based on the first flag register in the special function register circuit 23d in the semiconductor device 23 in synchronization with the clock signal CLK.

[0148] During the operation of the application program, when the first flags match their respective pre-specified reference values ​​(first expected values), the state comparison circuit 41 outputs a detection trigger signal SDTRG. The detection trigger signal SDTRG can be, for example, a one-shot trigger pulse.

[0149] In response to receiving the detection trigger signal SDTRG, the counter circuit 43 starts counting in the count circuit 72 in synchronization with the clock signal CLK. After starting counting in the count circuit 72, the counter circuit 43 outputs a measurement start trigger signal SCTRG in response to receiving the detection trigger signal SDTRG. The measurement start trigger signal SCTRG is provided to the flag comparison circuit 45. The measurement start trigger signal SCTRG can be, for example, a one-shot trigger pulse.

[0150] The flag comparison circuit 45 receives a bit string signal related to the second flag from the special function register circuit 23d. The bit string signal SBIT is updated in synchronization with the clock signal CLK.

[0151] The flag comparison circuit 45 calculates the logical product of the bit string signal from the semiconductor device 23 and the masking value of the masking register 63f in synchronization with the clock signal CLK. The second expected value register 61d, the bit string signal SBIT, the second flag update register 63d, and the masking register 63f all have the same bit width. The value of this logical product is compared with the expected value of the second expected value register circuit 61 in synchronization with the clock signal CLK. After receiving the measurement start trigger signal SCTRG, when this comparison result changes from mismatch to match, the flag comparison circuit 45 outputs an expected value match trigger signal SXTRG. The expected value match trigger signal SXTRG can be, for example, a one-shot trigger pulse.

[0152] In response to receiving the expected value match trigger signal SXTRG, the counter circuit 43 synchronizes with the clock signal CLK and stops the counting of the count circuit 72. The counter circuit 43 stores the count value of the count circuit 72 at the time of stopping the counting in the count value register 73.

[0153] After the count circuit 72 is stopped, the maximum value register circuit 75 and the minimum value register circuit 77 are updated as already explained.

[0154] The debugging device 15 reads the stored values ​​of the maximum value register circuit 75 and the minimum value register circuit 77 via the system bus 39d and displays them on the screen of the display device 31.

[0155] As can be seen from the above description, the program development tool 11 includes a computer system 20 connected to an emulation device 13 .

[0156] 7 is a diagram illustrating an example of a computer system in a program development tool according to the present embodiment. The debugging device 15 may include an example computer system 20.

[0157] The computer system 20 uses hardware resources for the debug device 15. The exemplary computer system 20 may include a processor 141 (central processing unit: CPU), a memory 142 (storage device), an input / output port 143, and a network port 144, and may also include an input device 145, a display 146, and peripheral circuits 148, as needed. The memory 142 is communicatively coupled to the processor 141. The input / output port 143 is communicatively coupled to the processor 141. The network port 144 is communicatively coupled to the processor 141 and is connected to an (external) network. The input device 145 is communicatively coupled to the processor 141. The display 146 is communicatively coupled to the processor 141 and the memory 142. The processor 141, the memory 142, the input / output port 143, the network port 144, the input device 145, and the display 146 are connected via a bus 147. The memory 142 stores a program (140b) and register display data (140c).

[0158] In the debug device 15, the program 140b, when executed by the processor 141, causes the processor 141 to perform processes according to modules that will be described subsequently. As will be understood from the above description, the emulation circuit 21 includes various registers. In the debug device 15, the contents of registers in the emulation circuit 21, such as the registers of the state comparison circuit 41, the counting circuit 43, and the flag comparison circuit 45, can be displayed on a display device.

[0159] 8 is a block diagram showing modules for a program of the program development tool according to this embodiment. The modules (see 140b in FIG. 7) can be stored in the memory (142) in the form of a program that defines instructions. Specifically, the memory (142) is configured to store a series of instructions.

[0160] A program for the debugging device 15 (see 140b in FIG. 7) is installed in the computer system 20 of the program development tool 11. This program monitors the internal state of the microcomputer 24 and the state of the special function register circuit 23d when the microcomputer 24 of the semiconductor device 23 is executing program code to be executed by the microcomputer 24.

[0161] The instructions, when executed, can be configured to cause the processor (141) to perform the operation of a module (140b, see FIG. 7). The present embodiment discloses aspects of various modules. In the following description, exemplary modules are described. Aspects of the present embodiment are not limited to the exemplary modules, but can additionally include modules associated with the operation of the emulation circuit 21 already described. A group of exemplary modules is subsequently described.

[0162] Module MD1: To request and receive input of expected values ​​as reference values ​​for the internal states that will occur in the microcomputer 24 during its operation. This reference value is stored in the first expected value register circuit 51 of the state comparison circuit 41.

[0163] Module MD2: soliciting and receiving expected values ​​associated with special function register circuit 23d of microcomputer 24; The expected values ​​are stored in one or more second expected value register circuits 61 (expected value registers 61b, 61c, 61d) of the flag comparison circuit 45 of the emulation circuit 21.

[0164] Module MD3: To request input of an initialization instruction for instructing initialization of the emulation circuit 21 and to receive this input. This initialization includes initializing the emulation circuit 21, such as the count circuit 72 and count value register circuit 71 of the counter circuit 43. Specifically, the count circuit 72 and the maximum value register circuit 75 and minimum value register circuit 77 of the count value register circuit 71 are initialized to store their respective initial values. The count circuit 72, maximum value register circuit 75, and minimum value register circuit 77 can be initialized by, for example, resetting.

[0165] Module MD4: Requesting and receiving input of a start instruction that instructs the program code to start operating.

[0166] The input of the start instruction causes the microcomputer 24 of the semiconductor device 23 to start executing the program code to be executed. In response to the start instruction, the emulation circuit 21 and the microcomputer 24 execute the program code in synchronization. During the execution of the program code, at least some of the internal state values ​​of the microcomputer 24 are reflected in the stored values ​​of circuits such as corresponding registers of the emulation circuit 21. Such circuits include, for example, the address update register 53b, the SFR address update register 53c, the SFR data update register 53d, and the first flag update register 53g.

[0167] The state comparison circuit 41 is configured to detect a match / mismatch between a state value of an internal state received from the microcomputer 24 via the connection device 17 during execution of the program code and a reference value. The flag comparison circuit 45 is configured to detect a match / mismatch between at least a portion of the bit string signal SBIT stored in the flag update register circuit 63 and an expected value of the second expected value register circuit 61 (61b to 61d) of the flag comparison circuit 45. At least a portion of the bit string signal SBIT is provided from the special function register circuit 23d of the microcomputer 24 via the connection device 17. The counter circuit 43 is configured to measure the elapsed time between the detection of a match in the state comparison circuit 41 and the detection of a match in the flag comparison circuit 45. A count value related to this measurement is stored in the count value register circuit 71.

[0168] Module MD5: In response to at least one of the maximum value register circuit 75 and the minimum value register circuit 77 being updated, the first stored value of the maximum value register circuit 75 and the second stored value of the minimum value register circuit 77 are displayed on the register display. This register display can be updated periodically (e.g., synchronously with the operation of the microcomputer) or irregularly (e.g., independently of the operation of the microcomputer 24). Specifically, the contents of the count value register circuit 71 can be displayed to the debug device 15 during or after the execution of the program code.

[0169] Module MD6: To hold register values ​​in the emulation circuit 21 and execute program code.

[0170] The group of modules may further include additional modules as described below.

[0171] Additional Module 1: In response to the state comparison circuit 41 of the emulation circuit 21 detecting a match between the state value and the reference value, the register display that displays the contents of the count value register circuit 71 on the display device of the debugging device 15 is updated.

[0172] The counting circuit 43 starts counting the counting circuit 72, and the debugging device 15 can update the count value register circuit 71 based on the progress of the counting. The debugging device 15 can display a register display on the display device, and the register display can include a first indicator (e.g., a geometric mark) that indicates that the state value matches the reference value.

[0173] Additional Module 2: In response to the detection of a match between the expected value in the second expected value register circuit 61 and the updated value in the flag update register circuit 63, the register indication is updated. In response to this match, the counter circuit 43 stops the counting circuit 72 and retains the updated value in the count value register circuit 71. The updated value in the flag update register circuit 63 may include at least a portion of the bit string signal received from the special function register circuit 23d. This register indication may include a second indicator (e.g., a geometric mark different from the first indicator) indicating that the bit string signal matches the expected value.

[0174] FIG. 9 is a diagram illustrating the main steps of a method for debugging program code, a method for monitoring the state of a special function register of a microcomputer, and a method for manufacturing a semiconductor device according to the present invention.

[0175] Referring to Figure 9, a method 100 is shown. This embodiment discloses various method aspects. In the following description, exemplary steps are described. The method aspects according to this embodiment are not limited to the exemplary steps.

[0176] The method 100 includes step ST1, in which a semiconductor device 23 including a microcomputer 24 is connected to an emulation circuit 21 via a connection device 17.

[0177] When power is applied to the emulation device 13, the semiconductor device 23 and the emulation circuit 21 become capable of bidirectional communication. After initialization, the semiconductor device 23 and the emulation circuit 21 become operable in synchronization with the clock signal of the semiconductor device 23 in response to a start signal. Furthermore, when power is applied to the debugging device 15, the emulation device 13 and the debugging device 15 become capable of bidirectional communication, and the program development tool 11 becomes operable.

[0178] The method 100 includes step ST2. In step ST2, input of a reference value is requested and this input is received. The reference value is a value (expected value) of an internal state that may occur in the microcomputer 24 during operation of the microcomputer 24. The emulation device 13 sets the reference value in the state comparison circuit 41. In this setting, the reference value is input from the debugging device 15 connected to the emulation device 13. An exemplary reference value is input in an input field (e.g., "REFIN" in FIG. 1) of the display device of the debugging device 15. The reference value is stored in one or more first expected value register circuits 51 of the state comparison circuit 41.

[0179] The method 100 includes step ST3. In step ST3, an input of an expected value is requested and received. The expected value is a value associated with a special function register of the special function register circuit 23d. The emulation device 13 sets the expected value in the flag comparison circuit 45. In this setting, the expected value is input from the debugging device 15 connected to the emulation device 13. An exemplary expected value is input in an input field (e.g., "EXPIN" in FIG. 1) of a display device of the debugging device 15. The expected value is stored in one or more second expected value register circuits 61 of the flag comparison circuit 45.

[0180] The method 100 includes step ST4. In step ST4, an initialization command is input to initialize the emulation circuit 21. An exemplary input of the initialization command is to press an initialization button (e.g., "INTIN" in FIG. 1) on the display device of the debugging device 15. The emulation device 13 initializes the count circuit 72 of the counter circuit 43 and the count value register circuit 71, specifically, the maximum value register circuit 75 and the minimum value register circuit 77. In response to the initialization command, the count circuit 72, the maximum value register circuit 75, and the minimum value register circuit 77 store their respective initial values. The initial values ​​can be provided by the debugging device 15.

[0181] The method 100 includes step ST5. In step ST5, a start command is input to instruct the emulation device 13 to start operating. An exemplary start command input is to press a start command button (e.g., "STRIN" in FIG. 1) on the display device of the debugging device 15. The start command is input from the debugging device, causing the microcomputer 24 to start executing the program code to be executed. The emulation circuit 21 and the microcomputer 24 operate synchronously.

[0182] During operation of the program code, at least some of the state values ​​of the internal state of the semiconductor device 23 are reflected as state values ​​in circuits such as corresponding registers in the emulation circuit 21. In the emulation circuit 21, the state comparison circuit 41 detects whether a state value generated in the microcomputer 24 during operation of the microcomputer 24 matches a reference value. The flag comparison circuit 45 detects whether at least a portion of the bit string signal SBIT received from the special function register of the special function register circuit 23d of the semiconductor device 23 matches an expected value in the first expected value register circuit 51. The counter circuit 43 measures the elapsed time from the detection of a match in the state comparison circuit 41 to the detection of a match in the flag comparison circuit 45. The measurement of the elapsed time can be performed using the count circuit 72 of the counter circuit 43. The count value register circuit 71 of the counter circuit 43 stores the count value of the count circuit 72.

[0183] The method 100 includes step ST6, in which after a start command is input, at least a part of the contents of the count value register circuit 71 of the counting circuit 43 is updated as a register display on the display device 31 periodically or irregularly.

[0184] The register display may include, for example, a first indicator (e.g., INDC1 in FIG. 1 ) on the display device 31 of the debugging device 15. The exemplary first indicator indicates that a match between a certain state value and a reference value has been detected in the emulation circuit 21. The counter circuit 43 starts counting and updates the count value register circuit 71 according to the progress of the counting. For example, the register value of the count value register circuit 71 may be displayed on the display device 31 of the debugging device 15.

[0185] The register display may include, for example, a second indicator (e.g., INDC2 in FIG. 1 ) on the display device 31 of the debugging device 15. The exemplary second indicator indicates that a match between the bit string signal received from the special function register during the operation of the program code and the expected value of the second expected value register circuit 61 has been detected. In response to this match, the counter circuit 43 stops timing and holds the updated value of the count value register circuit 71. In addition, the register value of the flag update register circuit 63 may be displayed on the display device 31 of the debugging device 15.

[0186] The method 100 includes step ST7. In step ST7, the stored values ​​of the maximum value register circuit 75 and the minimum value register circuit 77 are displayed on the display device 31 of the debugging device 15. The updated values ​​of the maximum value register circuit 75 and the minimum value register circuit 77 can also be displayed on the display device 31 of the debugging device 15.

[0187] The contents of the maximum value register circuit 75 and the minimum value register circuit 77 are updated based on the updated value of the second expected value register circuit 61. The emulation circuit 21 updates the maximum value register circuit 75 and the minimum value register circuit 77 in response to detection of a match between at least a portion of the bit string signal received from the special function register and the expected value of the second expected value register circuit 61.

[0188] The method 100 includes step ST8. In step ST8, the register display displayed on the display device 31 of the debugging device 15 can be updated. Specifically, the contents of the maximum value register circuit 75 and the minimum value register circuit 77 are maintained, and a start command is input again. The current program code (or the updated program code) is run in the emulation device 13. The updated contents of the maximum value register circuit 75 and the minimum value register circuit 77 are displayed on the display device 31.

[0189] The method 100 includes a step ST9 in which an indication of the elapsed time of the counter circuit 43 can be provided to the debug device 15 during or after the execution of the program code.

[0190] The method 100 includes a step ST10, in which, after inputting an initialization command, the register representations of the contents of the maximum value register circuit 75 and the minimum value register circuit 77 can be updated periodically or irregularly.

[0191] The method 100 includes a step ST11 in which the existing program code is modified based on at least a register representation based on the existing program code, where the modified program code is generated by modifying the program code based on at least the contents of the register representation.

[0192] The method 100 includes step ST12, in which a start command is input after connecting the semiconductor device 23 to the emulation device 13, and the updated program code of the semiconductor device 23 is run using the emulation device 13.

[0193] The method 100 includes step ST13, in which the updated program code is written into an electrically rewritable semiconductor memory such as a flash memory of the semiconductor device 23, thereby manufacturing the semiconductor device 23 with the updated program code.

[0194] The updated program code is installed in the microcomputer 24. The semiconductor device 23 including this microcomputer 24 is connected to the connection device 17. After connecting the semiconductor device 23 to the emulation device 13, an initialization command is input again, and then a start command to run the updated program code in the emulation device 13 is input.

[0195] The steps of the exemplary method 100 may be organized as program modules, and the program modules may be organized as various steps.

[0196] According to the above disclosure, it is possible to provide embodiments that facilitate monitoring of special function registers in an application program by comparing flag values ​​of the special function registers with expected values. The embodiments include, but are not limited to, an emulation circuit, an emulation device, a program development tool, a program, a method for monitoring the status of a special function register, and a method for manufacturing a semiconductor device.

[0197] As described above, the present embodiment can have various aspects.

[0198] An emulation circuit according to a first aspect of this embodiment is an emulation circuit configured to be communicatively connected to a semiconductor device via a connection device and to be communicatively connected to a debug device, the emulation circuit being connected to the connection device via a clock line, the clock line being configured to be able to propagate a clock signal that causes the semiconductor device and the emulation circuit to operate in synchronization, the emulation circuit including a state comparison circuit, a counting circuit, and a flag comparison circuit, the state comparison circuit being configured to store a reference value of an internal state that may occur in the microcomputer of the semiconductor device when the microcomputer executes a program code, and the flag comparison circuit being configured to store a reference value of an internal state that may occur in the microcomputer of the semiconductor device when the microcomputer executes a program code, The state comparison circuit is configured to store an expected value associated with a special function register of a special function register circuit of a microcomputer, the state comparison circuit is configured to detect a match / mismatch between a state value of the internal state received from the microcomputer via the connection device and the reference value during execution of the program code, the flag comparison circuit is configured to detect a match / mismatch between at least a portion of a bit string signal received from the special function register circuit via the connection device and the expected value of the flag comparison circuit, and the counting circuit is configured to measure the elapsed time between the detection of the match in the state comparison circuit and the detection of the match in the flag comparison circuit and to store a count value related to the measurement.

[0199] In the emulation circuit of a second aspect according to the first aspect of this embodiment, the state comparison circuit includes one or more first expected value register circuits, and the first expected value register circuits are configured to store the reference value, the state comparison circuit includes one or more state value update register circuits, and the state value update register circuits are configured to store the state value of the internal state, the flag comparison circuit includes one or more second expected value register circuits, and the second expected value register circuits are configured to store the expected value, the flag comparison circuit includes one or more flag update register circuits, and the flag update register circuits are configured to store at least a portion of the bit string signal, and the counter circuit includes a count value register the count register circuit is configured to measure the elapsed time between the detection of the match in the state comparison circuit and the detection of the match in the flag comparison circuit, and to store a count related to a result of the measurement, the count register circuit includes a count register configured to store the count, a maximum value register circuit, and a minimum value register circuit, and the count circuit is capable of updating the maximum value register circuit and the minimum value register circuit based on the count, a first value stored in the maximum value register circuit, and a second value stored in the minimum value register circuit, so that the maximum value register circuit stores the maximum value of the count and the minimum value register circuit stores the minimum value of the count.

[0200] In the emulation circuit of a third aspect according to the second aspect of this embodiment, the maximum value register circuit can be configured to perform a first comparison of the count value with the first stored value and update the maximum value register circuit based on the result of the first comparison to maintain the stored value of the maximum value register circuit greater than or equal to the count value, and the minimum value register circuit can be configured to perform a second comparison of the count value with the second stored value and update the minimum value register circuit based on the result of the second comparison to maintain the stored value of the minimum value register circuit less than or equal to the count value.

[0201] In the emulation circuit of the second aspect of this embodiment or the fourth aspect according to the second aspect, the counting circuit may be configured to provide at least one of the count value, the first storage value, and the second storage value of the counting value register circuit to the debugging device.

[0202] In the emulation circuit of the fifth aspect according to the fourth aspect of this embodiment, providing at least one of the count value, the first storage value and the second storage value of the count value register circuit to the debugging device can be performed in response to a request from the debugging device.

[0203] In the emulation circuit of a sixth aspect according to any one of the second to fifth aspects of this embodiment, the counter circuit further includes a count circuit, the state comparison circuit is configured to generate a detection trigger signal in response to the state value matching the reference value, the start of the elapsed time is identified by the counter circuit starting counting the clock signals in response to receiving the detection trigger signal, the flag comparison circuit is configured to generate an expected value match trigger signal in response to at least a portion of the received bit string signal matching the expected value in the second expected value register circuit of the flag comparison circuit, the end of the elapsed time is identified by the counter circuit stopping counting the clock signals in response to receiving the expected value match trigger signal, and the count value register circuit of the counter circuit is configured to store the count value when the count circuit is stopped.

[0204] In the emulation circuit of a seventh aspect according to the sixth aspect of this embodiment, the first expected value register circuit includes an address register configured to store a start address as the reference value, the status value update register circuit includes an address update register that receives a current address during execution of the program code from the semiconductor device via the connection device and stores the current address as the status value, the status comparison circuit is configured to generate the detection trigger signal in response to the current address in the address update register matching the start address, and the flag update register circuit of the flag comparison circuit can be configured to receive the bit string signal as the status value from the special function register circuit via the connection device during execution of the program code.

[0205] In an emulation circuit of an eighth aspect according to the sixth or seventh aspect of this embodiment, the first expected value register circuit of the state comparison circuit includes a special function register address circuit and a special function register data circuit, and the special function register address circuit and the special function register data circuit are configured to store a reference address for the special function register and expected value data for the reference address, respectively, as the reference value; the state value update register circuit of the state comparison circuit includes an SFR address update register and an SFR data update register, and the SFR address update register and the SFR data update register are configured to receive an SFR address of the special function register circuit and SFR data of the SFR address, respectively, as the state value; the state comparison circuit is configured to generate the detection trigger signal in response to at least a portion of the SFR data and the SFR address matching the reference address and the expected value data, respectively; and the flag update register circuit of the flag comparison circuit can be configured to receive the bit string signal as the state value from the special function register circuit via the connection device during execution of the program code.

[0206] In an emulation circuit of a ninth aspect according to any one of the sixth to eighth aspects of this embodiment, the first expected value register circuit of the state comparison circuit includes one or more expected value flag registers, and the expected value flag register is configured to store first expected value data of first flags related to at least a part of the special function register circuit as the reference value, and the state value update register circuit of the state comparison circuit includes a first flag update register, and the first flag update register is configured to receive one or more SFR bit strings related to the first flags from the special function register circuit via the connection device, and the state comparison circuit updates at least one of the SFR bit strings. the flag comparison circuit is configured to generate the detection trigger signal in response to at least a portion of the special function register matching the first expected value data, the second expected value register circuit of the flag comparison circuit is configured to store second expected value data of a second flag associated with at least a portion of the special function register as the expected value, the flag comparison circuit includes a second flag update register, the second flag update register receives the bit string signal from the semiconductor device via the connection device, the bit string signal includes the second flag of the special function register circuit, and the special function register circuit stores the first flag and the second flag as mutually different flags.

[0207] The emulation device according to the tenth aspect of this embodiment comprises a connection device configured to be connectable to a semiconductor device including a microcomputer, an input / output device configured to be connectable to a debugging device, an emulation circuit described in any one of the first to ninth aspects and connected to the connection device and the input / output device, and a mounting member on which the emulation circuit, the connection device, and the input / output device are mounted.

[0208] A program according to an eleventh aspect of this embodiment is a program configured to be installed in a computer system including a display device, a processor, and a memory, The computer system is connected to an emulation circuit, and the emulation circuit is connected to a semiconductor device including a microcomputer. The program is stored in the memory, and the program, when executed by the processor, is configured to cause the computer system to perform the following operations: requesting input of a reference value of an internal state that may occur in the microcomputer during execution of program code to be executed by the microcomputer, and receiving the input, the reference value being stored in one or more expected value register circuits of a state comparison circuit of the emulation circuit; requesting input of an expected value associated with a special function register circuit of the microcomputer, and receiving the input, the expected value being stored in one or more expected value register circuits of a flag comparison circuit of the emulation circuit; requesting input of an expected value and receiving the input; and requesting input of a start instruction that instructs the start of operation of the program code, and receiving the input. wherein the start instruction synchronizes the emulation circuit and the microcomputer to operate the program code, and at least a part of the internal state of the microcomputer is stored as a state value in a corresponding circuit of the emulation circuit during operation of the program code; requesting input of a start instruction and receiving the input; displaying a register display on the display device, wherein in the emulation circuit, a counting circuit of the emulation circuit starts counting in response to detection of a match between the state value and the reference value, and stops counting in response to detection of a match between at least a part of the bit string signal received from the special function register circuit and an expected value of the expected value register circuit, the counting circuit updates a count value register circuit of the counter circuit based on at least the count value of the count circuit to generate an updated value and holds the updated value in the count value register circuit, and the register display displays a register display including at least a part of the content of the count value register circuit.

[0209] A twelfth aspect of this embodiment is a method for monitoring a state of a special function register of a microcomputer when program code to be executed by the microcomputer is being executed, the method comprising: connecting a semiconductor device including the microcomputer to a connection device of an emulation device including an emulation circuit; inputting a reference value of an internal state that may occur in the microcomputer when the program code is being executed, the reference value being stored in one or more first expected value register circuits of a state comparison circuit of the emulation circuit; inputting an expected value associated with the special function register, the expected value being stored in one or more second expected value register circuits of a flag comparison circuit of the emulation circuit; and inputting a start instruction to run the program code in the emulation device, the start instruction running the program code and monitoring an internal state of the semiconductor device during the operation of the program code. inputting a start instruction, wherein state values ​​of at least some of the states are stored in corresponding circuits of the emulation circuit; and displaying a register display on a display device of the emulation device, wherein the emulation circuit causes a counter circuit of the emulation circuit to start counting in response to detection of a match between a certain state value of the state values ​​and the reference value, and the emulation circuit causes the counter circuit to stop the counting in response to detection of a match between at least a portion of a bit string signal received from the special function register during operation of the program code and the expected value, the emulation circuit causes a count value of a count value register circuit of the counter circuit to be held, and the emulation circuit updates contents of a maximum value register circuit of the counter circuit and a minimum value register circuit of the counter circuit based on the count value of the count value register circuit, and the register display displays the register display including an indication of the updated values ​​of the maximum value register circuit and the minimum value register circuit.

[0210] A method for manufacturing a semiconductor device according to a thirteenth aspect of this embodiment comprises carrying out the method described in the twelfth aspect to update the program code to create updated program code, and writing the updated program code into a flash memory of the semiconductor device to manufacture a semiconductor device with the updated program code.

[0211] The present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the present disclosure, all of which are included in the technical concept of the present disclosure. [Explanation of symbols]

[0212] 11. Program development tools, 13. Emulation device, 15. Debugging device, 17. Connection device, 19. Input / output devices, 20. Computer systems, 21... Emulation circuit, 23. Semiconductor device, 23a...Central processing unit, 23b Clock control circuit, 23c... Bus bridge circuit, 23d... Special function register circuit, 23e...Program memory circuit, 23f...peripheral circuit, 24. Microcomputer, 27. Mounting member, 31...display device, 33 processors, 35... memory, 39b Clock line, 39c···Local bus, 39d···System bus, 39f···SFR line, 40... control circuit, 41, 41b, 41c, 41d: State comparison circuit; 43. Counting circuit, 45...Flag comparison circuit, 51... First expected value register circuit; 51b Address register, 51c... Special function register address circuit, 51d... Special function register data circuit, 51f Expected value flag register, 53...State value update register circuit, 53b Address Update Register, 53c SFR Address Update Register, 53d SFR data update register, 53f, 53h... Masking registers, 53g First flag update register, 55...State comparator, 55b Address comparator, 55c SFR address comparator, 55d···SFR data comparator, 55f···SFR data flag comparator 55f, 55g... Output circuit, 61... Second expected value register circuit; 61b, 61c, 61d... Expected value registers, 63...Flag update register circuit, 63b Flag Update Register, 63d Second flag update register, 63c, 63f... Masking registers, 65···Flag comparator, 67···Output control circuit, 70...Count control circuit, 71... Count value register circuit; 72···Counting circuit, 73. Count value register, 75... Maximum value register circuit, 77... Minimum value register circuit, 78b...1st comparator, 78c...Second comparator, 79b...1st update circuit 79c...2nd update circuit CLK: Clock signal, SCTRG Measurement start trigger signal, SDTRG: Detection trigger signal, SSRT: Program start signal, SXTRG: Expected value match trigger signal.

Claims

1. An emulation circuit configured to be communicatively connected to a semiconductor device via a connection device and to be communicatively connected to a debugging device, the emulation circuit is connected to the connection device via a clock line, and the clock line is configured to be capable of propagating a clock signal that causes the semiconductor device and the emulation circuit to operate in synchronization with each other; the emulation circuit includes a state comparison circuit, a counting circuit, and a flag comparison circuit; the state comparison circuit is configured to store a reference value of an internal state that may occur in the microcomputer when the microcomputer of the semiconductor device executes a program code; the flag comparison circuit is configured to store an expected value associated with a special function register of a special function register circuit of the microcomputer; the state comparison circuit is configured to detect a match / mismatch between the state value of the internal state received from the microcomputer via the connection device during execution of the program code and the reference value; the flag comparison circuit is configured to detect a match / mismatch between at least a portion of the bit string signal received from the special function register circuit via the connection device and the expected value of the flag comparison circuit; the counter circuit is configured to measure the elapsed time between the detection of the match in the state comparison circuit and the detection of the match in the flag comparison circuit, and to store a count value related to the measurement. Emulation circuit.

2. the state comparison circuit includes one or more first expected value register circuits, the first expected value register circuits being configured to store the reference value; the state comparison circuit includes one or more state value update register circuits, the state value update register circuits configured to store the state values ​​of the internal states; the flag comparison circuit includes one or more second expected value register circuits, the second expected value register circuits configured to store the expected values; the flag comparison circuit includes one or more flag update register circuits, the flag update register circuits configured to store at least a portion of the bit string signal; the counter circuit includes a count value register circuit, the count value register circuit being configured to measure an elapsed time between the detection of the match in the state comparison circuit and the detection of the match in the flag comparison circuit, and to store a count value relating to a result of the measurement; the count register circuit includes a count register configured to store the count, a maximum value register circuit, and a minimum value register circuit; the counting circuit updates the maximum value register circuit and the minimum value register circuit based on the count value, the first value stored in the maximum value register circuit, and the second value stored in the minimum value register circuit so that the maximum value register circuit stores the maximum value of the count value and the minimum value register circuit stores the minimum value of the count value.

2. The emulation circuit of claim 1.

3. the maximum value register circuit is configured to perform a first comparison of the count value with the first stored value, and to update the maximum value register circuit based on a result of the first comparison, thereby maintaining the stored value of the maximum value register circuit greater than or equal to the count value; The minimum value register circuit is configured to perform a second comparison between the count value and the second stored value and to update the minimum value register circuit based on the result of the second comparison, thereby maintaining the stored value of the minimum value register circuit smaller than or equal to the count value.

3. The emulation circuit of claim 2.

4. the counting circuit is configured to provide at least one of the count value, the first stored value, and the second stored value of the counting value register circuit to the debugging device; 3. The emulation circuit of claim 2.

5. providing at least one of the count value, the first stored value, and the second stored value of the count value register circuit to the debugging device in response to a request from the debugging device; 5. The emulation circuit of claim 4.

6. the counting circuit further includes a counting circuit; the state comparison circuit is configured to generate a detection trigger signal in response to the state value matching the reference value; the beginning of the elapsed time is identified by causing the counting circuit to start counting the clock signal in response to receiving the detection trigger signal; the flag comparison circuit is configured to generate an expected value match trigger signal in response to at least a portion of the received bit string signal matching the expected value of the second expected value register circuit of the flag comparison circuit; the end of the elapsed time is identified by the counting circuit stopping counting of the clock signal in response to receiving the expected value match trigger signal; the count value register circuit of the counting circuit is configured to store the count value when the counting circuit is stopped; 3. The emulation circuit of claim 2.

7. the first expected value register circuit includes an address register configured to store a starting address as the reference value; the state value update register circuit includes an address update register that receives a current address during execution of the program code from the semiconductor device via the connection device and stores the current address as the state value; the state comparison circuit is configured to generate the detection trigger signal in response to the current address of the address update register matching the start address; the flag update register circuit of the flag comparison circuit is configured to receive the bit string signal as the status value from the special function register circuit via the connection device during execution of the program code; 7. An emulation circuit according to claim 6.

8. the first expected value register circuit of the state comparison circuit includes a special function register address circuit and a special function register data circuit, the special function register address circuit and the special function register data circuit being configured to store a reference address associated with the special function register and expected value data associated with the reference address, respectively, as the reference value; the state value update register circuit of the state comparison circuit includes an SFR address update register and an SFR data update register, the SFR address update register and the SFR data update register being configured to receive, as the state value, an SFR address of the special function register circuit and SFR data of the SFR address, respectively; the state comparison circuit is configured to generate the detection trigger signal in response to at least a portion of the SFR data and the SFR address matching the reference address and the expected value data, respectively; the flag update register circuit of the flag comparison circuit is configured to receive the bit string signal as the status value from the special function register circuit via the connection device during execution of the program code; 7. An emulation circuit according to claim 6.

9. the first expected value register circuit of the state comparison circuit includes one or more expected value flag registers, and the expected value flag registers are configured to store first expected value data of first flags associated with at least a portion of the special function register circuits as the reference value; the state value update register circuit of the state comparison circuit includes a first flag update register, the first flag update register being configured to receive one or more SFR bit strings related to the first flag from the special function register circuit via the connection device; the state comparison circuit is configured to generate the detection trigger signal in response to at least a portion of the SFR bit string matching the first expected value data; the second expected value register circuit of the flag comparison circuit is configured to store second expected value data of second flags related to at least a part of the special function registers as the expected values; the flag comparison circuit includes a second flag update register, the second flag update register receiving the bit string signal from the semiconductor device via the connection device; the bit string signal includes the second flag of the special function register circuit; the special function register circuit stores the first flag and the second flag as mutually different flags; 7. An emulation circuit according to claim 6.

10. a connection device configured to be connectable to a semiconductor device including a microcomputer; an input / output device configured to be connectable to the debugging device; an emulation circuit according to any one of claims 1 to 9 and connected to the connection device and the input / output device; a mounting member on which the emulation circuit, the connection device, and the input / output device are mounted; An emulation device comprising:

11. A program configured to be installed on a computer system including a display device, a processor, and a memory, comprising: the computer system is connected to an emulation circuit; the emulation circuit is connected to a semiconductor device including a microcomputer; The program is stored in the memory, The program, when executed by the processor, is configured to cause the computer system to perform the following operations: requesting and receiving input of reference values ​​for internal states that may occur in the microcomputer during execution of a program code to be executed by the microcomputer, the reference values ​​being stored in one or more expected value register circuits of a state comparison circuit of the emulation circuit; soliciting and receiving expected values ​​associated with special function register circuits of the microcomputer, the expected values ​​being stored in one or more expected value register circuits of a flag comparison circuit of the emulation circuit; requesting and receiving an input of a start instruction for instructing the start of operation of the program code, the start instruction causing the emulation circuit and the microcomputer to synchronize and operate the program code, and during the operation of the program code, at least a part of the internal state of the microcomputer is stored as a state value in a corresponding circuit of the emulation circuit; displaying a register display on the display device, wherein in the emulation circuit, a counting circuit of the emulation circuit starts counting in response to detection of a match between the state value and the reference value, and stops counting in response to detection of a match between at least a portion of the bit string signal received from the special function register circuit and the expected value of the expected value register circuit, the counting circuit updates a count value register circuit of the counting circuit based on at least the count value of the count circuit to generate an updated value and holds the updated value in the count value register circuit, and the register display displays a register display including at least a portion of the content of the count value register circuit; program.

12. 1. A method for monitoring the state of a special function register of a microcomputer during the execution of program code to be executed by said microcomputer, comprising: connecting a semiconductor device including the microcomputer to a connection device of an emulation device including an emulation circuit; inputting reference values ​​of internal states that may occur in the microcomputer during execution of the program code, the reference values ​​being stored in one or more first expected value register circuits of a state comparison circuit of the emulation circuit; inputting expected values ​​associated with the special function registers, the expected values ​​being stored in one or more second expected value register circuits of a flag comparison circuit of the emulation circuit; inputting a start instruction to run the program code in the emulation device, the start instruction running the program code, and during the operation of the program code, at least some state values ​​of an internal state of the semiconductor device are stored in a corresponding circuit of the emulation circuit; displaying a register display on a display device of the emulation device, wherein the emulation circuit causes a counter circuit of the emulation circuit to start counting in response to detection of a match between a certain state value among the state values ​​and the reference value, and the emulation circuit causes the counter circuit to stop counting in response to detection of a match between at least a part of a bit string signal received from the special function register during operation of the program code and the expected value, the emulation circuit causes a count value of a count value register circuit of the counter circuit to be held, and the emulation circuit updates contents of a maximum value register circuit and a minimum value register circuit of the counter circuit based on the count value of the count value register circuit, and the register display includes an indication of the updated values ​​of the maximum value register circuit and the minimum value register circuit; A method for providing the above.

13. performing the method of claim 12 to perform the program code update to produce updated program code; writing the updated program code into a flash memory of the semiconductor device to manufacture a semiconductor device in which the program code has been written; Equipped with A method for manufacturing a semiconductor device.

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