Semiconductor device

Abstract

To provide a transistor including an oxide semiconductor film with higher field effect mobility and higher reliability.SOLUTION: A semiconductor device includes an oxide semiconductor film. The semiconductor device includes a first insulating film, an oxide semiconductor film on the first insulating film, a second insulating film and a third insulating film on the oxide semiconductor film, and a gate electrode on the second insulating film. In particular, the second insulating film includes a silicon oxynitride film. Because of excess oxygen by an oxygen plasma process, oxygen can be supplied to the oxide semiconductor film efficiently.SELECTED DRAWING: Figure 44

Description

[Technical Field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film, a manufacturing method thereof, and a semiconductor device including the oxide semiconductor film. The present invention relates to a display device and an electronic device having the same.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, The present invention relates to a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are all semiconductor devices. The semiconductor device may include a conductive device. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. There are.

[0005] For example, the active layer of a transistor is 18 / cm 3 is less than Amorphous oxides containing indium (In), gallium (Ga), and zinc (Zn) were used. A transistor is disclosed (see Patent Document 1).

[0006] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. Although they operate faster and are easier to manufacture than transistors using polycrystalline silicon, It is known that the electrical characteristics are easily fluctuated and unreliable. The threshold voltage of a transistor changes before and after a thermal stress test (BT test). In this specification, the threshold voltage is the voltage required to turn a transistor on. The gate voltage is the voltage required for the gate to This refers to the potential difference between the potential of the electrode and the potential of the gate. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0008] In a transistor using an oxide semiconductor film for a channel region, The oxygen vacancies that can occur in the oxide semiconductor film affect the transistor characteristics. When an oxygen vacancy is formed, hydrogen bonds to the oxygen vacancy, and the hydrogen becomes a carrier supply source. When a carrier source is generated in the semiconductor film, the electrical characteristics of a transistor having an oxide semiconductor film are improved. This results in a change in the electrical properties, typically a shift in the threshold voltage.

[0009] For example, if there are too many oxygen vacancies in the oxide semiconductor film, the threshold voltage of the transistor may decrease. The oxide semiconductor film is shifted to the negative-polarity side, resulting in a normally-on characteristic. In particular, in the channel region, there is little oxygen vacancy or the device does not have normally-on characteristics. It is preferable that the amount of oxygen deficiency is such that there is no oxygen deficiency.

[0010] In addition, if there is a carrier trap center in the gate insulating film, the threshold voltage of the transistor It is desirable to have a small number of carrier trap centers, but the gate insulation This may increase if a treatment such as plasma treatment is performed after the formation of the insulating film.

[0011] In view of the above problems, one embodiment of the present invention is to provide a transistor including an oxide semiconductor film. One of the objectives is to suppress fluctuations in thermal characteristics and improve reliability. An object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment of the present invention is to provide a novel display device.

[0012] The above description of the problem does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. Problems other than those mentioned above may be solved by the specification. These are obvious from the description of the specification, etc., and other issues can be extracted from the description of the specification, etc. It is possible to do this. [Means for solving the problem]

[0013] One embodiment of the present invention is a semiconductor device including a transistor including an oxide semiconductor film, The transistor is formed on a substrate by an oxide semiconductor film, a gate insulating layer thereon, and a gate insulating layer thereon. The gate insulating layer has a silicon oxynitride film. When analyzed by thermal desorption spectroscopy, the edge layer had a mass-to-charge ratio of M / z=3, which corresponds to that of oxygen molecules. The results showed that the maximum peak of the emission of 2 appeared when the substrate temperature was above 150°C and below 350°C. It is characterized by being able to

[0014] In this embodiment, the temperature range during measurement in thermal desorption spectroscopy is from 80°C to 500°C. It is preferable that the temperature is up to °C.

[0015] In each of the above embodiments, the oxide semiconductor film contains In and M (M is Al, Ga, Y, or In each of the above embodiments, the oxide semiconductor film preferably includes Sn and Zn. It is preferable that the crystal portion has a c-axis orientation.

[0016] Another embodiment of the present invention is a semiconductor device including any one of the above embodiments and a display element. Another aspect of the present invention is a display device including the display device and a touch sensor. Another aspect of the present invention is a display module having any of the above aspects. a semiconductor device, the display device, or the display module according to any one of the preceding claims, and an operation key or is an electronic device having a battery.

[0017] Another embodiment of the present invention is a semiconductor device including a transistor having an oxide semiconductor film. The method includes forming an oxide semiconductor film over a substrate, and forming at least an oxynitride silicon film thereon. A gate insulating layer including a silicon film is formed, and the gate insulating layer is subjected to oxygen plasma treatment. After forming the gate electrode on the gate insulating layer, heat treatment is performed at 150°C or higher and 450°C or lower. The oxygen in the gate insulating layer is diffused into the oxide semiconductor film, and the conductivity of the oxide semiconductor film is reduced. do.

[0018] In each of the above aspects, the oxygen plasma treatment is preferably carried out at a substrate temperature of 350° C. or less. In each of the above aspects, the silicon oxynitride film is formed by plasma CVD at 350° C. It is preferable to form the film at the following substrate temperature.

[0019] Another embodiment of the present invention is a semiconductor device including a transistor having an oxide semiconductor film. The method includes forming an oxide semiconductor film over a substrate, and forming at least an oxynitride silicon film thereon. A gate insulating layer containing a silicon film is formed, and an oxide semiconductor is spat on the gate insulating layer in an atmosphere containing oxygen. This allows oxygen to be added to the gate insulating layer while forming a film on the gate insulating layer. After forming a gate electrode on the oxide semiconductor layer, heat treatment is performed at 150° C. or higher and 450° C. or lower. Oxygen in the gate insulating layer is diffused into the film, thereby reducing the electrical conductivity of the oxide semiconductor film. [Effects of the Invention]

[0020] According to one embodiment of the present invention, a transistor including an oxide semiconductor film can be prevented from fluctuating in electrical characteristics. Further, according to one embodiment of the present invention, A novel semiconductor device can be provided. An apparatus can be provided.

[0021] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device. [Figure 3] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 8] FIG. 1 is a diagram illustrating the range of atomic ratios of oxide semiconductors according to the present invention. [Figure 9] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 10] 10A and 10B show evaluation results of a silicon oxynitride film according to one embodiment of the present invention. [Figure 11] 10A and 10B show evaluation results of a silicon oxynitride film according to one embodiment of the present invention. [Figure 12] 10A and 10B show evaluation results of a silicon oxynitride film according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 14] FIG. 10 is a diagram showing the effect of oxygen diffusion according to one embodiment of the present invention. [Figure 15] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 16] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 17] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 18] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 19]FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 20] FIG. 1 is a cross-sectional view illustrating one embodiment of a display device. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for forming an EL layer. [Figure 22] FIG. 1 is a conceptual diagram illustrating a droplet ejection device. [Figure 23] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 24] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 25] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 26] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 27] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 28] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 29] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 30] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 31] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 32] FIG. 2 is a diagram illustrating a display module. [Figure 33] 1A to 1C illustrate electronic devices. [Figure 34] 1A to 1C illustrate electronic devices. [Figure 35] FIG. 1 is a perspective view illustrating a display device. [Figure 36] 10A and 10B are graphs illustrating Id-Vg characteristics and threshold voltage shifts of transistors. [Figure 37] A diagram illustrating the results of TDS analysis. [Figure 38] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 39] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 40] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 41] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 42] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 43] A diagram explaining the electrical resistance of an IGZO film. [Figure 44] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 45] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 46] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 47] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 48] FIG. 2 is a block diagram showing an example of the configuration of a CPU. [Figure 49] FIG. 1 is a circuit diagram illustrating an example of a memory element. [Figure 50] 1 shows drain current-gate voltage characteristics of a transistor according to one embodiment of the present invention. [Figure 51] 10A and 10B show results of a GBT test on a transistor according to one embodiment of the present invention. [Figure 52] 1 shows current stress characteristics of a transistor according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the present invention in various ways without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0024] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations and are not limited to the shapes or values ​​shown in the drawings.

[0025] In addition, the ordinal numbers "first," "second," and "third" used in this specification are intended to be used to indicate a mixture of elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0026] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in explaining the relationship with reference to the drawings. The values ​​change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0027] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) It has a channel region, and a current flows between the source and the drain through the channel forming region. In this specification and the like, the channel region is a region through which a current can flow. This refers to the area where the flow occurs.

[0028] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably. .

[0029] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0030] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0031] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." It may be possible to change the term to

[0032] Unless otherwise specified, in this specification and the like, the off-state current refers to the current that flows when a transistor is in an off-state. The drain current when the device is in the on state (also known as the non-conducting state or cut-off state). , Unless otherwise specified, for n-channel transistors, the voltage between the gate and source, Vg When s is lower than the threshold voltage Vth, in a p-channel transistor, the gate and source This refers to the state in which the voltage Vgs between the gates is higher than the threshold voltage Vth. For example, The off-state current of a transistor is the voltage between the gate and source, Vgs, and the threshold voltage, Vth. It may refer to the drain current when the voltage is lower than

[0033] The off-state current of a transistor may depend on Vgs. The current is I or less if there is a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor is the current that flows in the off state at a given Vgs. Off-state or sufficiently reduced off-current at Vgs within a given range It may refer to the off-state current in the off state at Vgs, etc.

[0034] As an example, when the threshold voltage Vth is 0.5V and Vgs is 0.5V, The current is 1×10 -9 A, and the drain current at Vgs of 0.1 V is 1×10 -13 A, and the drain current at Vgs = -0.5 V is 1 × 10 -19 A and Vgs The drain current at -0.8V is 1×10 -22 A n-channel transistor The drain current of the transistor is as follows when Vgs is -0.5V: Or, when Vgs is in the range of -0.5V to -0.8V, 1×10 -19 A or below Therefore, the off-state current of the transistor is 1×10 -19 It may be said that it is below A. The drain current of the transistor is 1×10 -22 Because there exists a Vgs below A , the off-state current of the transistor is 1×10 -22 It may be said that it is below A.

[0035] In this specification and the like, the off-state current of a transistor having a channel width W is expressed as It is sometimes expressed as the current value that flows per a given channel width (for example, 1 μm). In the latter case, the unit of the off-state current is the current / length dimension. It may be expressed in units with a constant value (e.g., A / μm).

[0036] The off-state current of a transistor may depend on temperature. Unless otherwise specified, the off voltage is measured at room temperature, 60°C, 85°C, 95°C, or 125°C. Or, the reliability of the semiconductor device containing the transistor may be in doubt. or the temperature at which a semiconductor device including the transistor is used (for example, For example, it may refer to the off-state current at any temperature between 5°C and 35°C. The off-state current of the transistor is I or less, which means that the The temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the temperature at which the transistor The temperature at which the semiconductor device containing the stator is used (for example, any one of 5°C to 35°C) This indicates that there exists a value of Vgs at which the off-state current of the transistor is equal to or less than I at This may occur.

[0037] The off-state current of a transistor may depend on the voltage Vds between the drain and the source. In this specification, unless otherwise specified, the off-state current is measured when Vds is 0.1 V, 0.8 V, 1 V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or It may represent the off-state current at 20 V. Or, the semiconductor including the transistor Vds that guarantees the reliability of devices, etc., or semiconductor devices that include the transistor The off-state current of a transistor is sometimes expressed as the off-state current at Vds used in The current is less than or equal to I when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2 .5V, 3V, 3.3V, 10V, 12V, 16V, 20V, including transistors Vds that guarantees the reliability of the semiconductor device in which the transistor is included, or Vds used in devices, etc., Vg at which the off-state current of a transistor is I or less It may refer to the existence of a value of s.

[0038] In the above description of the off-state current, the drain may be read as the source. may also refer to the current that flows through the source when the transistor is in the off state.

[0039] In this specification and the like, the term "leak current" may be used to mean the same thing as "off-state current." In this specification and the like, the off-state current refers to, for example, the current when a transistor is in an off state. It can refer to the current that flows between the source and drain.

[0040] In this specification and the like, the threshold voltage of a transistor refers to the voltage at which a channel Specifically, it refers to the gate voltage (Vg) when the threshold voltage of a transistor is The voltage is plotted by plotting the gate voltage (Vg) on ​​the horizontal axis and the square root of the drain current (Id) on the vertical axis. In the curve (Vg-√Id characteristics), the straight line obtained by extrapolating the tangent line with the maximum slope is Gate voltage (Vg) at the point where the square root of the drain current (Id) intersects with 0 (Id is 0A) Alternatively, the threshold voltage of a transistor can be expressed as the channel length L and the channel The width of the panel is W, and the value of Id[A]×L[μm] / W[μm] is 1×10 -9 [A] Sometimes refers to gate voltage (Vg).

[0041] In addition, even when the term "semiconductor" is used in this specification, it does not mean, for example, that the material has sufficient conductivity. If the conductivity is too low, it may have the properties of an "insulator." The boundary between "compounds" and "compounds" is vague and may not be strictly distinguishable. The "semiconductor" described above may be replaced with "insulator" in some cases. The term "insulator" in the specification etc. may be replaced with "semiconductor." In some cases, the term "insulator" used in this specification and the like can be replaced with "semi-insulator."

[0042] In addition, even when the term "semiconductor" is used in this specification, it does not mean, for example, that the material has sufficient conductivity. If the chemical composition is very high, it may have the properties of a "conductor." The boundary between "electrode" and "electrode" is vague and it may not be possible to strictly distinguish them. The "semiconductor" described above may be replaced with "conductor" in some cases. The term "conductor" in the specification etc. may be replaced with "semiconductor" in some cases.

[0043] In this specification, impurities in a semiconductor refer to substances other than the main components that constitute the semiconductor film. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The formation of DOS (Density of States) in semiconductors and the The semiconductor may have poor mobility or poor crystallinity. In the case of a nitride semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements. These include elements of Group 2, Group 14, Group 15, and transition metals other than the main component. , hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, oxygen vacancies can be created by the inclusion of impurities such as hydrogen. In addition, when the semiconductor contains silicon, the properties of the semiconductor are changed. The impurities include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements, etc.

[0044] (Embodiment 1) In this embodiment, a semiconductor device having a gate insulating film including an excess oxygen region according to one embodiment of the present invention will be described. Also, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. do.

[0045] <1-1. Configuration example 1 of semiconductor device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. FIG. 1(B) corresponds to a cross-sectional view of the cut surface taken along the dashed line X1-X2 shown in FIG. 1(A). 1(C) corresponds to a cross-sectional view of the cut surface taken along the dashed line Y1-Y2 shown in FIG. 1(A). In FIG. 1A, for simplicity, the transistor 100 Some of the components (such as an insulating film that functions as a gate insulating film) are omitted in the illustration. , the dashed dotted line X1-X2 direction is the channel length direction, and the dashed dotted line Y1-Y2 direction is the channel width direction. In the top view of the transistor, As in FIG. 1A, some of the components may be omitted in the illustration.

[0046] The transistor 100 shown in FIGS. 1A, 1B, and 1C is a so-called top-gate structure transistor. It is a star.

[0047] The transistor 100 includes an insulating film 104 on a substrate 102 and an oxide semiconductor on the insulating film 104. a film 108, an insulating film 110 over the oxide semiconductor film 108, and a conductive film 112 over the insulating film 110 and an insulating film 116 over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. do.

[0048] The oxide semiconductor film 108 is made of In, M (M is Al, Ga, Y, or Sn), and Z. n.

[0049] Note that the oxide semiconductor film 108 overlaps with the conductive film 112 and is in contact with the insulating film 104. A first region 108i contacting the insulating film 110 and a second region 108n contacting the insulating film 116. The second region 108n has a higher carrier density than the first region 108i. That is, the oxide semiconductor film 108 of one embodiment of the present invention has a region with a different carrier density. It has two regions:

[0050] The carrier density of the first region 108i is 1×10 5 cm -3 More than 1×10 18 cm -3 Less than 1 x 10 is preferable. 7 cm -3 More than 1×10 17 cm -3 The following is more preferable: , 1×10 9 cm -3 5x10 or more 16 cm -3 Even better: 1 x 10 10 c m -3 More than 1×10 16 cm -3 Even better: 1 x 10 11 cm -3 1x or more 10 15 cm-3 The following is even more preferred:

[0051] In the embodiment shown in FIGS. 1A, 1B, and 1C and in the embodiment of the present invention, an oxide semiconductor film Although the example in which 108 is a single layer is mainly shown, it may also be a laminated structure of films with different carrier densities. For example, the oxide semiconductor film 108 is formed by The first oxide semiconductor film may be formed as a two-layer stack with the second oxide semiconductor film. The carrier density of the oxide semiconductor film is made higher than that of the second oxide semiconductor film, so that the oxide semiconductor film has a different carrier density. Therefore, an oxide semiconductor film having a region where the oxide semiconductor film is formed can be formed.

[0052] The first oxide semiconductor film has a slightly smaller amount of oxygen vacancies than the second oxide semiconductor film. The impurity concentration of the second oxide semiconductor film may be increased or slightly increased compared to that of the first oxide semiconductor film.

[0053] In order to increase the carrier density of the first oxide semiconductor film, oxygen deficiency is introduced into the first oxide semiconductor film. An element that forms oxygen defects can be added to bond the oxygen defects with hydrogen or the like. Representative elements that form the above are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, and sulfur. , chlorine, and rare gases. Representative examples of rare gas elements include helium and neon. argon, krypton, xenon, and the like. Of the elements mentioned above, nitrogen is particularly preferred as the forming element.

[0054] For example, when the first oxide semiconductor film is formed, argon gas and monoxide gas are used as deposition gases. When the first oxide semiconductor film is formed using nitrogen gas, the first oxide semiconductor film contains a nitrogen element. In this case, the first oxide semiconductor film may have a higher nitrogen content than the second oxide semiconductor film. It has a region with high element concentration.

[0055] That is, the first oxide semiconductor film has an increased carrier density and is slightly n-type. An oxide semiconductor film with increased carrier density is sometimes called a "slightly-n" film. be.

[0056] For example, when the voltage (Vg) applied to the gate of a transistor is greater than 0V and less than 30V, In this case, the carrier density of the first oxide semiconductor film is 1×10 16 cm -3 Beyond 1× 10 18 cm -3 Less than 1 x 10 is preferable. 16 cm -3 Beyond 1×10 17 cm -3 The following is more preferred:

[0057] In addition, when the carrier density of the first oxide semiconductor film is increased, the first oxide semiconductor film In this case, the crystallinity of the oxide semiconductor film 10 may be lower than that of the oxide semiconductor film 10. 8 has a stacked structure of an oxide semiconductor film with low crystallinity and an oxide semiconductor film with high crystallinity. In addition, there is a correlation between the crystallinity of an oxide semiconductor film and the film density of the oxide semiconductor film. The higher the crystallinity of an oxide semiconductor film, the higher the film density. The semiconductor layer has a stacked structure of an oxide semiconductor film with a low film density and an oxide semiconductor film with a high film density.

[0058] Note that the crystallinity of the oxide semiconductor film 108 can be evaluated by, for example, X-ray diffraction (XRD). Analysis is performed using a transmission electron microscope (TEM) or Analysis using a Transmission Electron Microscope The film density of the oxide semiconductor film 108 can be analyzed by, for example, This is measured using an X-ray reflectometer (XRR). It can be determined.

[0059] The second region 108n is in contact with the insulating film 116. The insulating film 116 is made of nitrogen or hydrogen. Therefore, nitrogen or hydrogen in the insulating film 116 is added to the second region 108n. The second region 108n is further enriched by adding nitrogen or hydrogen from the insulating film 116. The carrier density becomes even higher.

[0060] The transistor 100 also includes an insulating film 118 on the insulating film 116 and a layer between the insulating films 116 and 118. A conductive film electrically connected to the second region 108n through an opening 141a provided in the 120a and the second region 1 through the opening 141b provided in the insulating films 116 and 118. 08n, and a conductive film 120b electrically connected to the first and second electrodes 120a and 120b.

[0061] In this specification and the like, the insulating film 104 is referred to as a first insulating film, and the insulating film 110 is referred to as a second insulating film. The insulating film 116 is referred to as the third insulating film, and the insulating film 118 is referred to as the fourth insulating film. The conductive film 112 may function as a gate electrode. The conductive film 120b functions as a source electrode, and the conductive film 120c functions as a drain electrode. do.

[0062] The insulating film 110 also functions as a gate insulating film. The insulating film 110 has an excess oxygen region made of a silicon nitride film. As a result, excess oxygen is supplied to the first region 108i of the oxide semiconductor film 108. In particular, in the present invention, the insulating film 110 is preferably heated to 300° C. or less after being formed. Preferably, oxygen is added by oxygen plasma treatment at a substrate temperature of 250° C. or less. Therefore, excess oxygen in the insulating film 110 can be supplied to the oxide semiconductor film in a much larger amount than in the conventional method. The oxygen plasma treatment in one aspect of the present invention is characterized by being able to perform the treatment using a plasma containing oxygen. This refers to plasma processing. For example, the gas used during plasma processing is oxygen added to the film. The gas may contain gases other than oxygen as long as the effect of the plasma treatment is not impaired. The gas may be 90% oxygen and 10% argon in flow ratio.

[0063] The insulating film 110 according to one embodiment of the present invention is a single layer of a silicon oxynitride film or a silicon oxynitride film. It has a laminated structure with a film, and TDS (Thermal Desorption Spectroscopy) Thermal desorption spectroscopy (TDS) analysis revealed that the mass-to-charge ratio M / The substrate temperature of the maximum peak within the temperature range of the emission measurement for z=32 is 150°C or more and 300°C or more. Ideally, the temperature is between 150°C and 250°C. The emission characteristics of oxygen molecules at this time are synonymous with the emission characteristics at a mass-to-charge ratio of 32. The measurement temperature range for analysis is typically between 80°C and 500°C, and above 500°C The analysis results are excluded from the release characteristics of oxygen molecules. By filling the defects with excess oxygen in the insulating film 110, a highly reliable semiconductor device is provided. In this specification, the substrate temperature is measured by the TDS analysis. It means temperature.

[0064] As a method of adding oxygen to a silicon oxynitride film in the prior art, N2O gas or NO2 gas is used. However, the present inventors have reported that the silicon oxynitride film is treated with N2O gas. When plasma treatment is performed using NO2 gas or NO2 gas, the number of electron trap centers increases. It was confirmed that one of the reasons for this is that the silicon oxynitride film contained in the insulating film 110 Nitrogen oxides (NO x ) increases. -When a thermal stress test (BT test) is performed, the gate electrode is subjected to positive bias stress. To avoid a positive shift in the threshold voltage when added, nitrogen oxide (NO x It is advisable not to use plasma treatment using N2O gas or NO2 gas, which increases the That is, the method of performing oxygen plasma treatment after forming the insulating film 110, which is a feature of one embodiment of the present invention, is as follows: It is valid.

[0065] In addition, the oxide semiconductor film 108 has a region in which the atomic ratio of In is higher than the atomic ratio of M. It is preferable that the oxide semiconductor film 108 has a region where the atomic ratio of In is higher than the atomic ratio of M. By doing so, the field-effect mobility of the transistor 100 can be increased. The field effect mobility of transistor 100 is 10 cm 2 / Vs, more preferably The field effect mobility of transistor 100 is 30 cm 2 / Vs can be exceeded.

[0066] For example, the above-mentioned high field effect mobility transistor is connected to a gate driver that generates a gate signal. driver (especially, the demultiplexer connected to the output terminal of the shift register of the gate driver) By using it in a semiconductor device or display device with a narrow frame width (also called a narrow frame), can be provided.

[0067] When oxygen vacancies are formed in the oxide semiconductor film 108, hydrogen is bonded to the oxygen vacancies, and carriers are generated. When a carrier supply source is generated in the oxide semiconductor film 108, the oxide semiconductor The variation in the electrical characteristics of the transistor 100 having the dielectric film 108, typically the shift in the threshold voltage, Therefore, in the oxide semiconductor film 108, particularly in the first region 108i, The less oxygen deficiency there is, the more preferable.

[0068] The oxygen vacancies formed in the first region 108i are compensated for by the excess oxygen contained in the insulating film 110. Therefore, the first region 108i of the oxide semiconductor film 108 is filled with impurity-concentrated The oxide semiconductor film has a low impurity concentration and a low density of defect states. A material with a low oxygen density, i.e., a low oxygen vacancy, is called a high-purity intrinsic material or substantially a high-purity intrinsic material. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a carrier generation source. Therefore, the carrier density can be reduced. The transistor in which the hole region is formed has electrical characteristics in which the threshold voltage is negative (normal It is rare for this to occur (also known as "on").

[0069] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. In addition, the trap level density may be low due to the high purity intrinsic or substantially high purity. The intrinsic oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6 μm Even if the channel length L of the device is 10 μm, the voltage between the source electrode and the drain electrode (drain In the range of 0.1V to 10V, the off-state current is Below the measurement limit of the isa, i.e., 1 × 10 -13 It can achieve a characteristic of A or below.

[0070] The transistor 100A shown in FIGS. 2A, 2B, and 2C includes a conductive film 106 on a substrate 102. By providing the conductive film, the structure of the transistor 100 shown in FIGS. 2(A), (B), and (C) are formed by adding a conductive film 106. The conductive film 12 and the conductive film 106 can be used as a gate electrode.

[0071] In the structure of FIG. 2(A), (B), and (C), the conductive film 112 and the conductive film 106 are connected to the gate electrode at the same potential. The transistor 201 was used as the electrode, and the processing conditions after the insulating film 110 was changed. The Id-Vg characteristics of the transistor 202 and the transistor 203 are shown in FIG. The measurement conditions were: the substrate temperature was room temperature, and Id = 0.1 V and Id = 10 V. The Vg was changed in the range of -15 V to +20 V. The Id-Vg characteristics of the transistor under condition 207 are shown. The size conditions are L=2 μm and W=50 μm, and condition 207 is the channel size condition. The Id-Vg characteristics were measured by comparing the conductive film 112 and the conductive film 106. The measurements were taken using the gate electrode as a gate electrode. The characteristics for Id = 0.1 V and 10 V were also overlaid. Furthermore, the measurement results of multiple transistors on a specific substrate are overlaid and shown. There are.

[0072] The insulating film 110 of the transistor 201, the transistor 202, and the transistor 203 is The transistor 201 is made of silicon oxynitride and the film formation conditions are the same. After the formation of the insulating film 110, neither N2O plasma treatment nor oxygen plasma treatment was performed. The transistor 202 was fabricated by forming an insulating film 110 and then using an N2O plasma. A conductive film 112 was formed by performing a thermal treatment. After that, oxygen plasma treatment was performed to form the conductive film 112. 1, the insulating film 110 of the transistor 202 and the transistor 203 is heated to 250° C. Heat treatment was carried out with the upper limit set.

[0073] The Id-Vg characteristics of the transistor 201 show that the threshold voltage is significantly shifted negatively. On the other hand, the Id-Vg characteristics of the transistor 202 and the transistor 203 are as follows: The threshold voltage is around 0 V. That is, the N2O plasma treatment after the insulating film 110 is formed, Alternatively, oxygen plasma treatment is effective as a means for increasing excess oxygen in the insulating film 110. Yes.

[0074] On the other hand, FIG. 36(B) shows the results of the BT test on the transistors 202 and 203. The vertical axis represents the shift in threshold voltage (ΔVth) in the Id-Vg characteristics. The unit is [V]. The channel size of the transistor for which this BT test was performed is L = 3μ The BT test conditions were gate bias of +30V or -30V, Under 10,000lx illumination by white LED light or in darkness, BT test time 60min That is, positive gate bias stress (PBTS) and negative gate bias stress (NBS) NBTS, light-induced positive gate bias stress PBITS, light-induced negative gate bias stress The BT test was conducted under four conditions: The substrate temperature was set to 60°C during the measurement of the Id-Vg characteristics.

[0075] The BT test results of transistor 202 were due to positive gate bias stress (PBTS). The threshold voltage shift is approximately +8V, while the threshold voltage of transistor 203 is The shift was about +2 V. This was due to the silicon oxynitride film contained in the insulating film 110. Nitrogen oxides (NO x ) is the insulator of transistor 203 This shows that the amount of the oxide in the insulating film 110 of the transistor 202 is greater than that in the insulating film 110 of the transistor 202. .

[0076] As described above, in the semiconductor device according to one embodiment of the present invention, the oxynitride contained in the gate insulating film Nitrogen oxide (NO) in silicon dioxide films x ) while preventing the increase of excess oxygen in the oxide semiconductor film. A gate insulating film that can be supplied to the oxide semiconductor layer is formed above the oxide semiconductor layer. By supplying a sufficient amount of oxygen, oxygen defects in the oxide semiconductor layer can be reduced, and the transistor can be Therefore, it is possible to provide a semiconductor device with excellent reliability. It is possible.

[0077] <1-2. Components of semiconductor device> Next, the components included in the semiconductor device of this embodiment will be described in detail.

[0078] [substrate] There is no particular restriction on the material of the substrate 102, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, glass substrates, ceramic substrates, quartz substrates, and surface treatment substrates are A fiber substrate or the like may be used as the substrate 102. Also, silicon or silicon carbide may be used as the material. A single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, etc. It is also possible to apply a substrate, an SOI substrate, etc., on which a semiconductor element is provided. The substrate 102 may be a glass substrate. In this case, the 6th generation (1500mm x 1850mm) and 7th generation (1870mm x 2200 mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800 By using large area substrates such as 10th generation (2950mm x 3400mm), It is possible to fabricate a display device of this type.

[0079] In addition, a flexible substrate is used as the substrate 102, and the transistor 100 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is used to separate the semiconductor device from the substrate 102 after a part or all of the semiconductor device is completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to less rigid or flexible substrates.

[0080] [First insulating film] The insulating film 104 can be formed by a method such as sputtering, CVD, evaporation, or pulsed laser deposition (P The insulating film 104 can be formed by appropriately using a laser diode (LD) method, a printing method, a coating method, or the like. For example, a single layer or a stacked layer of an oxide insulating film or a nitride insulating film can be formed. Note that in order to improve the interface characteristics with the oxide semiconductor film 108, At least a region in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 104, By the heat treatment, oxygen contained in the insulating film 104 is transferred to the oxide semiconductor film 108. It is possible to do this.

[0081] The thickness of the insulating film 104 is 50 nm or more, or 100 nm or more and 3000 nm or less, or The thickness of the insulating film 104 can be set to 200 nm or more and 1000 nm or less. The amount of oxygen released from the insulating film 104 can be increased, and the insulating film 104 and the oxide semiconductor The interface state at the interface with the oxide semiconductor film 108 and the oxygen vacancies contained in the oxide semiconductor film 108 It is possible to reduce

[0082] The insulating film 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn oxide The insulating film 1 may be formed as a single layer or a multilayer. As the layer 04, a laminated structure of a silicon nitride film and a silicon oxynitride film is used. The insulating film 104 has a laminated structure, with a silicon nitride film on the lower layer and a silicon oxynitride film on the upper layer. By using the silicon film, oxygen can be efficiently introduced into the oxide semiconductor film 108. do.

[0083] [Conductive film] A conductive film 112 functions as a gate electrode, a conductive film 120a functions as a source electrode, and a conductive film 120b functions as a source electrode. The conductive film 120b that functions as a rain electrode may be made of chromium (Cr), copper (Cu), aluminum (Al), or the like. Aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tungsten Ta (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (N i), iron (Fe), cobalt (Co), or the above-mentioned metal elements The alloys can be formed using alloys containing the above-mentioned metal elements or alloys combining the above-mentioned metal elements. This can be done.

[0084] The conductive films 112, 120a, and 120b are made of an oxide containing indium and tin (In -Sn oxide), oxide containing indium and tungsten (In-W oxide), In oxides containing indium, tungsten and zinc (In-W-Zn oxides), indium and oxides containing indium and titanium (In-Ti oxides), oxides containing indium, titanium, and tin oxides containing indium and zinc (In-Ti-Sn oxides), ), oxides containing indium, tin and silicon (In-Sn-Si oxide), indium Oxide conductors such as oxides containing aluminum, gallium, and zinc (In-Ga-Zn oxide) Alternatively, an oxide semiconductor may be used.

[0085] Here, the oxide conductor will be described. In this specification and the like, the oxide conductor is referred to as OC( The oxide conductor may be, for example, When oxygen vacancies are formed in an oxide semiconductor and hydrogen is added to the oxygen vacancies, donors are formed in the vicinity of the conduction band. As a result, the oxide semiconductor becomes electrically conductive. An oxide semiconductor that has been etched can be called an oxide conductor. Because of its large energy gap, it is transparent to visible light. is an oxide semiconductor that has a donor level near the conduction band. The influence of absorption due to donor levels is small, and the transparency to visible light is comparable to that of oxide semiconductors. It has.

[0086] In particular, when the conductive film 112 is made of the above-mentioned oxide conductor, excess oxygen is added to the insulating film 110. This is preferable because it can

[0087] The conductive films 112, 120a, and 120b are made of a Cu-X alloy film (X is Mn, Ni, C r, Fe, Co, Mo, Ta, or Ti) may be used. This allows for processing using a wet etching process, which reduces manufacturing costs. It becomes Noh.

[0088] Furthermore, the conductive films 112, 120a, and 120b contain titanium, among the above-mentioned metal elements. Contains one or more selected from tungsten, tantalum, and molybdenum. In particular, the conductive films 112, 120a, and 120b are preferably made of tantalum nitride films. The tantalum nitride film is electrically conductive and has high resistance to copper and hydrogen. Furthermore, the tantalum nitride film has high barrier properties. Therefore, the conductive film in contact with the oxide semiconductor film 108 or the conductive film in the vicinity of the oxide semiconductor film 108 It can be most suitably used as the conductive film.

[0089] The conductive films 112, 120a, and 120b can also be formed by electroless plating. Materials that can be formed by the electroless plating method include, for example, Cu, Ni, Al, and A. Use one or more selected from the group consisting of u, Sn, Co, Ag, and Pd. In particular, when Cu or Ag is used, the electrical resistance of the conductive film can be reduced. This is preferable because it can be

[0090] [Second insulating film] The insulating film 110 functioning as the gate insulating film of the transistor 100 of one embodiment of the present invention is a single Silicon oxynitride layer or laminate structure formed by plasma-enhanced chemical vapor deposition The insulating film 110 is subjected to oxygen plasma treatment.

[0091] When the insulating film 110 according to one embodiment of the present invention is analyzed by TDS, it is found that it is incompatible with oxygen molecules within the measurement temperature range. The substrate temperature at the maximum peak of the emission of the mass-to-charge ratio M / z=32, which corresponds to the substrate temperature, was 150 to 300°C. 37 to 44, the insulating film 1 according to one embodiment of the present invention will be described. 10, that is, the characteristics of the silicon oxynitride film that has been subjected to oxygen plasma treatment will be described.

[0092] Excess oxygen atoms in the silicon oxynitride film are desorbed by thermal excitation, and the desorption temperature is The bond state of the atoms in the silicon oxynitride film varies depending on the Therefore, the excess oxygen atoms are contained in the silicon oxynitride film at low temperatures. After the oxidation, when the oxide semiconductor film is heated to a high temperature in a step of supplying oxygen atoms to the oxide semiconductor film, The amount of oxygen atoms supplied can be increased.

[0093] When forming a silicon oxynitride film by plasma enhanced chemical vapor deposition (PECVD), Silicon oxynitride films formed under high temperature conditions are dense and have excellent electrical insulation and withstand voltage characteristics. Considering only these advantages, it is not surprising that a silicon oxynitride film is used in a semiconductor device. In this case, it is desirable to have a high substrate temperature during the deposition of the silicon oxynitride film. When a silicon oxynitride film is used as the gate insulating film of a transistor using a silicon dioxide film as the channel, In order to achieve this, excessive oxygen atoms in the silicon oxynitride film are more effectively supplied to the oxide semiconductor film. This is important in order to enhance reliability.

[0094] In order to increase the amount of excess oxygen atoms, in this embodiment, after forming a silicon oxynitride film, Then, the silicon oxynitride film is subjected to oxygen plasma treatment. The substrate temperature during this process is set to 350° C. or less, preferably 250° C. or less. When it is desired to increase the amount of excess oxygen atoms in the film, the substrate temperature is lowered during film formation.

[0095] By changing the conditions of the oxygen plasma treatment for the silicon oxynitride film, An example in which oxygen can be supplied to the oxide semiconductor film in a large amount is shown below. When the sample shown below was analyzed by TDS, the mass-to-charge ratio M / z=32, which corresponds to the oxygen molecule, The sample was a 100 nm thick silicon oxynitride film on a non-alkali glass substrate. The silicon oxynitride film was then subjected to oxygen plasma treatment. The data used to quantify the amount of oxygen molecules released when the substrate was heated was The temperature range is from 80 to 450°C. The gas used in oxygen plasma treatment is oxygen only. The silicon oxynitride film is formed by plasma CVD using SiH4 gas and N2O gas. The substrate temperature during film formation was 350°C. The substrate temperature during oxygen plasma treatment was 350°C. do.

[0096] From Figure 37, it can be seen that the lower the oxygen plasma treatment pressure is in the range of 40 Pa to 250 Pa, the The higher the discharge power, the more oxygen atoms from the silicon oxynitride film are converted into oxygen molecules. It is clear that more is emitted.

[0097] Figure 38 shows the mass-to-charge ratio (M / z) corresponding to water molecules when the following samples were subjected to TDS analysis. The results are for the amount of emission at 18. Figure 38(A) shows sample 221, and Figure 38(B) shows sample 222. The results for sample 223 are shown in Figure 38(C). All samples were deposited on non-alkali glass substrates. A GZO film was deposited to a thickness of 100 nm, followed by a silicon oxynitride film to a thickness of 100 nm. The silicon oxynitride film is formed using SiH4 gas and N2O gas by plasma CVD. The substrate temperature during film formation was 350°C. The oxygen plasma treatment was performed on sample 221 at a discharge power of 500 W, and on sample 222 at a discharge power of 3000 W. The vertical axis represents the signal intensity, which indicates the amount of released protein.

[0098] When forming an IGZO film on a sample for TDS analysis, oxide was used as the target. The atomic ratio of the target was indium:gallium:zinc=4:2:4. The substrate temperature during film formation was 130°C, the film formation gas flow ratio was Ar:O2=9:1, and the film formation The pressure is 0.6 Pa.

[0099] In Figure 38, comparing the amount of water molecules released by each sample at around 120°C, sample 221 had the most. The next highest concentration was in sample 222, and the lowest was in sample 223. This is because the amount of oxygen in the silicon oxynitride film One of the reasons for this is thought to be that the plasma treatment reduced the amount of water adsorbed on the surface.

[0100] 39(A) and 39(B) show the results of the films of Sample 221, Sample 222, and Sample 223. Hydrogen concentration was measured using secondary ion mass spectrometry (SIMS). The results are from measurements using SIMS. The profile measurement was carried out toward the surface of the silicon nitride film. The direction in which the profile was measured is shown in each figure of FIG. 6, a profile 217 in the IGZO film and a profile 218 in the substrate are shown. .

[0101] FIG. 39(A) shows the water vapor in the silicon oxynitride film as a function of the discharge power of the oxygen plasma treatment. Figure 39(B) shows the SIMS analysis results quantifying the hydrogen concentration in the IGZO film. The SIMS analysis results for quantitatively determining the concentration are shown below. Sample 221 is without oxygen plasma treatment, and sample Sample 222 was produced under a discharge power of 500W, and sample 223 was produced under a discharge power of 3000W.

[0102] The horizontal axis in Figure 39 is the depth direction perpendicular to the film surface. 0 nm on the horizontal axis is a convenient position for SIMS measurement. In FIG. 39(A), the region 225 corresponds to the vicinity of the surface of the silicon oxynitride film. Sample 222 and Sample 223 are samples that were subjected to oxygen plasma treatment under the hydrogen concentration in region 225. 3 is lower than that of sample 221 without oxygen plasma treatment. The difference in the amount of water molecules released from the surface was due to the oxygen plasma treatment of the silicon oxynitride film. This is thought to be due to the reduction in adsorbed water.

[0103] In addition, in FIG. 39(B), under the condition of oxygen plasma treatment, the hydrogen concentration in the IGZO film At this time, the hydrogen concentration in the IGZO film decreases as the discharge power increases. The oxygen plasma treatment of the silicon oxynitride film reduces the amount of oxygen only on the surface of the silicon oxynitride film. It is also effective in reducing the hydrogen concentration in the IGZO film, i.e., the oxide semiconductor film.

[0104] 39(C) and 39(D) show the hydrogen concentrations in the films of samples 226, 227, and 228. The results are shown in the SIMS measurement results. Sample 226 was prepared under the same conditions as Sample 221. In the manufacturing process of sample 226, the gas pressure conditions in the chamber during oxygen plasma treatment were Sample 228 was prepared under the same gas pressure conditions in the chamber. The sample was prepared with a pressure of 40 Pa. Figure 39(C) shows the hydrogen concentration in the silicon oxynitride film. Figure 39(D) shows the quantitative analysis of the hydrogen concentration in the IGZO film. In the gas pressure condition inside the bar, in the range of 40 Pa to 200 Pa, the lower the pressure, the greater the oxidation. It is believed that the hydrogen concentration in the compound semiconductor film can be reduced.

[0105] Figure 40 shows the mass-to-charge ratio M / z corresponding to oxygen molecules when the following sample was analyzed by TDS. The results are for the amount of emission at 320 nm. All samples have an IGZO film on a non-alkali glass substrate. A 100 nm thick silicon oxynitride film was then formed. The silicon film was formed by plasma CVD using SiH4 gas and N2O gas. The temperature was 350°C. The discharge power was 3000W, and the gas pressure in the chamber was 200P. In a, oxygen plasma treatment was performed.

[0106] For each sample used in the TDS analysis, the oxygen plasma treatment time was 30sec, Figure 40(B) is 60sec, Figure 40(C) is 100sec, Figure 40(D) ​​is 40(E) is for 300 seconds, and FIG. 40(E) is for 600 seconds. These are at a substrate temperature of 220°C and oxygen Plasma treatment was performed for 30 seconds in Figure 40(F), 60 seconds in Figure 40(G), Figure 40(H) shows the time for 100 seconds, and Figure 40(I) shows the time for 300 seconds. Oxygen plasma treatment was carried out at 50°C.

[0107] From FIG. 40, it can be seen that the longer the oxygen plasma treatment time for the silicon oxynitride film, the greater the oxygen release. In addition, if the substrate temperature during oxygen plasma treatment is low, the amount of oxygen It can be seen that the amount of released is large.

[0108] FIG. 41 shows the amount of oxygen released shown in FIG. 40, with the horizontal axis representing the treatment time and the vertical axis representing the amount of oxygen released. The broken line 231 shows the results of oxygen plasma treatment at a substrate temperature of 220° C. (FIG. 40(A)). 40(E)). The solid line 232 shows the value obtained from the oxygen plating at a substrate temperature of 350°C. The values ​​obtained from the results of the Zuma process (Figs. 40(F) to 40(I)) are shown. The amount of oxygen released under the condition of plasma treatment substrate temperature 350℃ increases as the oxygen plasma treatment time increases. 2×10 14 molecules / cm 2 The oxygen release at the same substrate temperature of 220°C is saturated at The amount of oxygen was at least 1.2 × 10 15 molecules / cm 2 in In other words, in order to increase the amount of oxygen released, the substrate temperature during oxygen plasma treatment It can be seen that 220°C is more desirable than 350°C.

[0109] In Figure 42, a silicon oxynitride film was formed to a thickness of 100 nm on a non-alkali glass substrate. Then, the silicon oxynitride film was subjected to oxygen plasma treatment. The results were obtained by TDS analysis. The figure shows the amount of emission at the mass-to-charge ratio M / z=32, which corresponds to the oxygen molecule. The silicon oxynitride film The film was formed using plasma CVD using SiH4 gas and N2O gas. The results are for when the temperature during silicon oxynitride film formation was 350°C. The release rate in the range of 80°C to 450°C is 5.17×10 14 molecules / cm 2 It was. FIG. 42(B) shows the results when the temperature during silicon oxynitride film formation was set to 220°C. At a constant temperature, the release amount in the range of 80°C to 450°C is 1.47×10 15 molecule / c m 2 It was.

[0110] One possible reason for the difference between Figure 42(A) and Figure 42(B) is as follows: Nitric oxide. When the temperature during silicon dioxide film formation is low, i.e., 220°C, the film density is low and These voids provide room for excess oxygen to be added, absorbing more excess oxygen. Or it may be possible to supply.

[0111] In this way, in order to supply excess oxygen from the silicon oxynitride film to the oxide semiconductor film, The silicon oxynitride film is treated with oxygen plasma at a low substrate temperature of 350°C or less, for example, 220°C. By performing a laser treatment, increasing the discharge power, and reducing the pressure inside the chamber during discharge, The oxygen plasma treatment time is increased, and the temperature for forming the silicon oxynitride film is decreased. It is effective to form the silicon oxynitride film so as to serve as a source of excess oxygen. If this is the case, it is also effective to increase the thickness of the silicon oxynitride film.

[0112] On the other hand, when a silicon oxynitride film is formed on an oxide semiconductor film by plasma CVD, Depending on the conditions, the electrical resistance of the oxide semiconductor film may decrease. An IGZO film was formed on the substrate to a thickness of 50 nm, and a silicon oxynitride film was formed on top of that. The electrical resistance of the IGZO film of each sample is shown. Each sample is a square substrate with a side length of 1 cm. The silicon oxynitride film was removed at 2 mm corners, and the 2 mm The electrical resistance between adjacent electrodes was measured using these electrodes as terminals. The unit is Ω.

[0113] The silicon oxynitride film is formed using the plasma CVD method with SiH4 gas and N2O gas. The thickness of the silicon oxynitride film was increased from 0 nm, i.e., no film formation treatment, to 60 nm. The conditions were varied up to the point shown in FIG. 43(A). The temperature for film formation was 350°C, and the results for each sample in Figure 43(B) were obtained at the time of film formation of the silicon oxynitride film. The film was formed at a substrate temperature of 220° C. The dashed line 235 in FIG. 43 indicates the state before the silicon oxynitride film was formed. is the electrical resistance value of the IGZO film.

[0114] When forming a silicon oxynitride film by plasma CVD, the hydrogen plasma in the chamber Hydrogen diffuses into the IGZO film in the atmosphere, and oxygen vacancies combine with hydrogen and other elements to form an oxidized nitride film. It is possible that the electrical resistance of the silicon oxide nitride film is reduced. The tendency is that the condition of the substrate temperature of 350°C shown in FIG. 43(A) is better than the condition of the substrate temperature of 350°C shown in FIG. 43(B). This is more pronounced than the condition of 220°C substrate temperature. This is thought to be due to the promotion of hydrogen diffusion into the ZO film and the bonding of oxygen vacancies with hydrogen, etc. From this perspective, when a silicon oxynitride film is formed by plasma CVD, It is desirable that the substrate temperature be low.

[0115] In order to confirm the effect of oxygen plasma treatment, the present inventors have A display device was fabricated that had a silicon oxynitride film that had been subjected to the annealing treatment in its structure. The display device was disassembled, and the pixel electrodes were removed from the display device to obtain transistors, which were then analyzed by TDS. The results of the emission amount at the mass-to-charge ratio M / z=32 corresponding to the oxygen molecule are shown in Figure 44. The organic resin was removed from all the samples. After the silicon oxynitride film was formed, Sample 241 was not subjected to oxygen plasma treatment, and sample 242 was subjected to oxygen plasma treatment for 120 minutes. Sample 243 was subjected to oxygen plasma treatment for 600 seconds. Although the structure of the device is different from that of one embodiment of the present invention, a silicon oxynitride film is formed on an IGZO film. and at a process temperature after the silicon oxynitride film formation or the oxygen plasma treatment. The limit is 250°C.

[0116] On the other hand, one embodiment of the present invention includes an oxide semiconductor film and a silicon oxynitride film as a gate insulating film. A commercially available display device other than the above was disassembled, and sample 244 was prepared with the pixel electrodes removed. When sample 244 was analyzed by TDS, the mass-to-charge ratio M / z=32, which corresponds to the oxygen molecule, was detected. The amount of discharge is shown in FIG.

[0117] Sample 241, which is a silicon oxynitride film without oxygen plasma treatment, has a T of 150°C or less. The maximum peak appears within the measurement temperature range of the DS analysis, while the same oxygen plasma treatment The samples 242 and 243, which were under the same conditions, showed the maximum temperature between 150 and 350°C. On the other hand, under sample conditions of a commercially available display device other than that of one embodiment of the present invention, a peak of 35 The maximum peak appeared between 0°C and 450°C within the measurement temperature range. The sample of the device shown is a sample fabricated under the condition that the silicon oxynitride film is subjected to oxygen plasma treatment. The difference can be determined by the sample temperature at which the maximum peak appears.

[0118] The silicon oxynitride film that has been subjected to oxygen plasma treatment contains a sufficient amount of excess oxygen. In a subsequent step, heat treatment is performed to supply oxygen to the oxide semiconductor film, and a semiconductor device or a display device can be manufactured. Even after completion, the silicon oxynitride film that has been subjected to oxygen plasma treatment, which is a feature of the present invention, can be used as a T DS analysis revealed that the amount of release at a mass-to-charge ratio of M / z=32, which corresponds to the oxygen molecule, was 150°C. The maximum peak appears between 100°C and 350°C within the measurement temperature range. When the oxide semiconductor film in the transistor included in the device is subjected to heat treatment in this temperature range, It can be seen that the conductivity decreases.

[0119] In the manufacturing process of a transistor, after performing oxygen plasma treatment on a silicon oxynitride film, Heat treatment at 150°C or higher, preferably 200°C or higher, and more preferably 250°C or higher. However, when the heat treatment temperature is 450° C., oxygen can be supplied to the oxide semiconductor film. If the temperature exceeds this value, oxygen in the oxide semiconductor film may combine with hydrogen to form water depending on the heat treatment gas atmosphere. In addition, when a film containing a metal material is formed, In this case, oxygen in the oxide semiconductor film is absorbed in the same manner, so the upper limit of the heat treatment temperature must be determined appropriately. Determine.

[0120] The insulating film 110 is not a single layer of the silicon oxynitride film, but is formed by plasma chemical vapor deposition, By sputtering or the like, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, Silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, dioxide film ZrO2 film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film a two-layer laminate structure using an insulating layer containing one or more of a cerium oxide film and a neodymium oxide film; Alternatively, it may have a laminated structure of three or more layers.

[0121] In addition, the oxide semiconductor film 108, which functions as a channel region of the transistor 100, The insulating film 110 is preferably an oxide insulating film, and has an oxygen content in excess of the stoichiometric composition. In other words, it is more preferable that the insulating film 11 has a region containing The insulating film 110 is an insulating film capable of releasing oxygen. To provide the insulating film 110, for example, the insulating film 110 is formed in an oxygen atmosphere, or the insulating film 110 is formed in an oxygen atmosphere. The film 110 may be heat-treated in an oxygen atmosphere.

[0122] When hafnium oxide is used as one film in the laminated structure of the insulating film 110, Hafnium oxide has the following advantages: It has a low dielectric constant compared to silicon oxide and silicon oxynitride. Therefore, compared to when silicon oxide is used, the thickness of the insulating film 110 can be made larger. Therefore, the leakage current due to the tunnel current can be reduced. A transistor with a small off-state current can be realized. Hafnium has a higher relative dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is required. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0123] Furthermore, it is preferable that the insulating film 110 has few defects. The signal observed by ESR (Electron Spin Resonance) is small. For example, the signal described above is E, which is observed at a g value of 2.001. The signal due to the E' center is the signal due to the dangling of silicon. The insulating film 110 has a spin density of 3 x10 17 spins / cm 3 Less than or equal to 5 x 10 16 spins / cm 3 Below A silicon oxide film or a silicon oxynitride film may be used.

[0124] In addition to the above signals, the insulating film 110 also contains signals originating from nitrogen dioxide (NO2). The signal is split into three signals due to the nuclear spin of N. The g values ​​of each are between 2.037 and 2.039 (first signal). g-value is between 2.001 and 2.003 (second signal) and g-value is 1.964 and 1.966 (the third signal).

[0125] For example, the insulating film 110 may be formed by using a material having a spin density of 0.1 to 1.0 times that of nitrogen dioxide (NO2). , 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Less than 100% insulation Preferably, a membrane is used.

[0126] In addition, nitrogen oxides (NO x ) forms a level in the insulating film 110. The level is located within the energy gap of the oxide semiconductor film 108. Therefore, nitrogen oxides (NO x ) diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108. When this happens, the level may trap electrons on the insulating film 110 side. The trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108. Therefore, the insulating film 110 As for the thickness of the film, if a film containing a small amount of nitrogen oxide is used, the threshold voltage of the transistor can be reduced. This can reduce the amount of

[0127] Nitrogen oxides (NO x As an insulating film with a small amount of ) released, for example, a silicon oxynitride film is used. The silicon oxynitride film can be used. In TDS analysis, it is found that nitrogen oxide (N O x ) is a membrane that releases more ammonia than water, and typically releases ammonia is 1×10 18 molecules / cm 3 5x10 or more 19 molecules / cm 3 The above is as follows. The amount of ammonia released is measured when the heating temperature in the TDS analysis is between 50°C and 650°C. or the total amount in the range of 50°C to 550°C.

[0128] Nitrogen oxides (NO x ) reacts with ammonia and oxygen during heat treatment, By using an insulating film with a high nitrogen release rate, x ) is reduced.

[0129] When the insulating film 110 was analyzed by SIMS, the nitrogen concentration in the film was 6×10 20 atom s / cm 3 It is preferable that the following is true:

[0130] [Oxide semiconductor film] The oxide semiconductor film 108 can be formed using the above-described materials.

[0131] When the oxide semiconductor film 108 is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose must satisfy the relation In>M. The atomic ratio of the metal elements in such a sputtering target is preferably In: M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1 etc.

[0132] In addition, when the oxide semiconductor film 108 is an In-M-Zn oxide, the sputtering target As the target, it is preferable to use a target containing polycrystalline In-M-Zn oxide. By using a target containing crystalline In-M-Zn oxide, it is possible to obtain a crystalline oxide semiconductor. The atomic ratio of the oxide semiconductor film 108 to be formed is as follows: The atomic ratio of the metal elements contained in the sputtering target is ±40%. For example, the composition of the sputtering target used for the oxide semiconductor film 108 may vary. When the atomic ratio of In:Ga:Zn is 4:2:4.1, the oxide semiconductor film 1 The composition of 08 may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0133] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 e V or more. In this way, by using an oxide semiconductor with a wide energy gap, The off-current of the transistor 100 can be reduced.

[0134] The thickness of the oxide semiconductor film 108 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm. The thickness is set to at most 100 nm, and more preferably at least 3 nm and at most 50 nm.

[0135] The oxide semiconductor film 108 may have a non-single-crystal structure. CAAC-OS (C Axis Aligned Crystalline Oxi) Semiconductor), including polycrystalline, microcrystalline, or amorphous structures. nothing.

[0136] [Third insulating film] The insulating film 116 contains nitrogen or hydrogen. For example, the insulating film 116 may be a nitride insulating film. Specific examples of the nitride insulating film include silicon nitride and silicon oxynitride. The hydrogen concentration in the insulating film 116 is 1 x10 22 atoms / cm 3 The insulating film 116 is preferably an oxide semiconductor. The second region 108n of the conductive film 108 is in contact with the insulating film 116. The concentration of impurities (nitrogen or hydrogen) in the region 108n increases, and the capacitance of the second region 108n increases. Rear density can be increased.

[0137] [Fourth insulating film] The insulating film 118 can be an oxide insulating film. The insulating film 118 can be a stacked film of an oxide insulating film and a nitride insulating film. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, oxide Hafnium oxide, gallium oxide, Ga-Zn oxide, or the like may be used.

[0138] The insulating film 118 is a film that functions as a barrier film for hydrogen, water, and the like from the outside. It is preferable.

[0139] The thickness of the insulating film 118 is 30 nm or more and 500 nm or less, or 100 nm or more and 400 nm or less. It can be as follows:

[0140] <1-3. Transistor configuration example 2> Next, regarding the transistors having different structures from those shown in FIGS. 1(A), 1(B), and 1(C), the transistors shown in FIG. Explain using B)(C).

[0141] 2A is a top view of a transistor 100A, and FIG. 2B is a dot-and-dash diagram of FIG. 2A. 2(C) is a cross-sectional view taken along the line X1-X2, and FIG. 2(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 2(A). Figure.

[0142] The transistor 100A shown in FIGS. 2A, 2B, and 2C includes a conductive film 106 on a substrate 102 and a , the insulating film 104 on the conductive film 106, the oxide semiconductor film 108 on the insulating film 104, and the oxide An insulating film 110 on the semiconductor film 108, a conductive film 112 on the insulating film 110, an insulating film 104, The insulating film 116 is formed over the oxide semiconductor film 108 and the conductive film 112 .

[0143] The transistor 100A includes the following components in addition to the components of the transistor 100 described above: a conductive film 106; and an opening 143.

[0144] The opening 143 is provided in the insulating films 104 and 110. The conductive film 106 is also provided with the opening 143. The conductive film 106 is electrically connected to the conductive film 112 through the opening 143. The same potential is applied to the conductive film 112. and the conductive film 112 may be applied with different potentials. The conductive film 106 may be used as a light-shielding film. For example, the conductive film 106 may be made of a light-shielding material. By forming the first region 108i, it is possible to suppress light from below from being irradiated onto the first region 108i. .

[0145] In addition, in the case of the transistor 100A, the conductive film 106 is a first gate electrode ( The conductive film 112 functions as a second gate electrode (also referred to as a tom gate electrode). The insulating film 104 functions as a first gate electrode. The insulating film 110 functions as a second gate insulating film. .

[0146] The conductive film 106 is made of the same material as the conductive films 112, 120a, and 120b described above. In particular, the conductive film 106 can be formed from a material containing copper, which reduces the electrical resistance. For example, the conductive film 106 may be a titanium nitride film or a nitride film. A laminated structure in which a copper film is provided over a tantalum film or a tungsten film is used, and conductive films 120a and 120b are formed. 20b is a laminated structure in which a copper film is provided on a titanium nitride film, a tantalum nitride film, or a tungsten film. In this case, the transistor 100A is preferably a pixel transistor of a display device. By using the conductive film 106 in either one or both of the driving transistor and the conductive film 107, The parasitic capacitance between the conductive film 106 and the conductive film 120a and the parasitic capacitance between the conductive film 106 and the conductive film 120b are Therefore, the conductive film 106, the conductive film 120a, and the conductive The film 120b is connected to the first gate electrode, the source electrode, and the drain electrode of the transistor 100A. It is not only used as a pole, but also as a power supply wiring for a display device, a signal supply wiring, or a connection. It can also be used for connecting wiring.

[0147] In this way, the transistor 100A shown in FIGS. 2(A), 2(B), and 2(C) has the same structure as the transistor 100A described above. Unlike the transistor 100, conductive films functioning as gate electrodes are formed above and below the oxide semiconductor film 108. As shown in the transistor 100A, the semiconductor device of one embodiment of the present invention has a structure including a film. The device may be provided with a plurality of gate electrodes.

[0148] As shown in FIGS. 2B and 2C, the oxide semiconductor film 108 is used as a first gate electrode. and a conductive film 112 that functions as a second gate electrode. They are positioned opposite each other and are sandwiched between two conductive films that function as gate electrodes.

[0149] The length of the conductive film 112 in the channel width direction is equal to the length of the oxide semiconductor film 108 in the channel width direction. The length of the oxide semiconductor film 108 in the channel width direction is longer than the length of the insulating film 110. The conductive film 112 and the conductive film 106 are sandwiched between the insulating film 112 and the conductive film 106. 04 and the opening 143 formed in the insulating film 110. One of the side surfaces of the conductive film 108 in the channel width direction is connected to the conductive film 112 with the insulating film 110 sandwiched therebetween. They are facing each other.

[0150] In other words, the conductive films 106 and 112 are formed in the openings provided in the insulating films 104 and 110. The region 143 is connected to the oxide semiconductor film 108 and is located outside the side edge of the oxide semiconductor film 108. It has a region.

[0151] With this structure, the oxide semiconductor film 108 included in the transistor 100A The conductive film 106 functions as a first gate electrode and the conductive film 108 functions as a second gate electrode. It can be electrically surrounded by the electric field of the conductive film 112. As shown in FIG. 1, a channel region is formed by the electric field of the first gate electrode and the second gate electrode. The device structure of the transistor that electrically surrounds the oxide semiconductor film 108 is called Surrou. This can be called a nded channel (S-channel) structure.

[0152] Since the transistor 100A has an S-channel structure, the conductive film 106 or the conductive The electric field for inducing a channel is effectively applied to the oxide semiconductor film 108 by the conductive film 112. This improves the current driving capability of the transistor 100A and increases the on-state current. In addition, since it is possible to increase the on-current, The transistor 100A can be miniaturized. The semiconductor film 108 is surrounded by the conductive film 106 and the conductive film 112. Therefore, the mechanical strength of the transistor 100A can be increased.

[0153] Note that the opening of the oxide semiconductor film 108 in the channel width direction of the transistor 100A An opening different from opening 143 may be formed on the side where opening 143 is not formed.

[0154] As shown in the transistor 100A, the transistor is formed with a semiconductor film sandwiched therebetween. When a pair of gate electrodes are connected to each other, one gate electrode is connected to signal A and the other gate is connected to signal B. A fixed potential Vb may be applied to the electrodes. Also, a signal A may be applied to one gate electrode and a signal B may be applied to the other gate electrode. A signal B may be applied to the gate electrode of the other gate electrode. However, the other gate electrode may be given a fixed potential Vb.

[0155] The signal A is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V1 or potential V2 (V1>V2). For example, the potential V1 may be set to a high power supply potential, and the potential V2 may be set to a low power supply potential. Signal A may be an analog signal.

[0156] The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of a transistor. The fixed potential Vb may be the potential V1 or the potential V2. This is preferable because it is not necessary to provide a separate potential generating circuit for generating Vb. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. As a result, the gate-source voltage V The drain current when gs is 0V is reduced, and the leakage current of the circuit having the transistor is reduced. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current is improved when the gate-source voltage Vgs is at a high power supply potential, For example, the fixed potential Vb can be set to a low voltage. It may be higher than the source potential.

[0157] The signal B is, for example, a signal for controlling the conductive state or the non-conductive state. It is a digital signal that takes on two types of potential: potential V3 or potential V4 (V3>V4). For example, the potential V3 may be set to a high power supply potential, and the potential V4 may be set to a low power supply potential. Signal B may be an analog signal.

[0158] If signal A and signal B are both digital signals, signal B has the same digital value as signal A. In this case, the on-state current of the transistor is improved, and the transistor is effectively In this case, the potential V1 and the potential V2 of the signal A can be increased. The potential V2 may be different from the potentials V3 and V4 in the signal B. For example, The gate insulating film corresponding to the gate to which signal B is input corresponds to the gate to which signal A is input. If the gate insulating film is thicker than the gate insulating film, the potential amplitude of signal B (V3-V4) is V1-V2) to prevent the transistor from turning on or off. The influence of signal A on the conduction state must be equal to the influence of signal B on the conduction state. It may be possible.

[0159] If signal A and signal B are both digital signals, signal B will have a different digital value than signal A. In this case, the transistors can be controlled by signals A and B separately. For example, when a transistor is an n-channel transistor, If the signal is a channel type, then only if signal A is at potential V1 and signal B is at potential V3 When the signal A is at potential V2 and the signal B is at potential V4, When only one transistor is in a non-conducting state, the functions of a NAND circuit, NOR circuit, etc. can be achieved with one transistor. In addition, the signal B is a signal for controlling the threshold voltage VthA. For example, the signal B may be a period during which the circuit having the transistor is operating and a period during which the signal B is The signal B may be a signal whose potential is different from that during the period when the circuit is not operating. In this case, signal B may be a signal with a different potential according to the operation mode. In some cases, the potential may not be switched very frequently.

[0160] If both signal A and signal B are analog signals, signal B is an analog signal with the same potential as signal A. signal, an analog signal obtained by multiplying the potential of signal A by a constant, or by adding a constant to the potential of signal A. In this case, the on-current of the transistor increases. This may improve the operating speed of a circuit that includes a transistor. In this case, the transistors are controlled by signals A and B. This can be done separately, and higher functionality may be achieved.

[0161] Signal A may be a digital signal and signal B may be an analog signal. Signal A may be an analog signal and signal B a digital signal.

[0162] When a fixed potential is applied to both gate electrodes of a transistor, the transistor is treated as a resistor element. For example, if a transistor is an n-channel In the case of a transistor, the fixed potential Va or the fixed potential Vb can be increased (decreased). In some cases, the effective resistance of the resistor can be lowered (raised). By making Vb high (low), the In some cases, an effective resistance lower (higher) than that expected may be obtained.

[0163] The other configurations of the transistor 100A are the same as those of the transistor 100 shown above. This has the same effect.

[0164] An insulating film may be further formed on the transistor 100A. 3(A) and 3(B) are cross-sectional views of the transistor 100B. The top view of the transistor 100B is similar to that of the transistor 100A shown in FIG. Therefore, the description here will be omitted.

[0165] The transistor 100B shown in FIGS. 3A and 3B includes conductive films 120a and 120b and an insulating film. The insulating film 122 is provided on the film 118. The other configurations are the same as those of the transistor 100A. and has the same effect.

[0166] The insulating film 122 has a function of planarizing unevenness due to transistors and the like. The material 122 may be an insulating material and may be made of an inorganic or organic material. Inorganic materials include silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, and silicon nitride films. Examples of the organic material include silicon film, aluminum oxide film, and aluminum nitride film. Examples of the material include photosensitive resin materials such as acrylic resin and polyimide resin.

[0167] <1-4. Transistor configuration example 3> Next, regarding a configuration different from that of the transistor 100A shown in FIGS. 2A, 2B, and 2C, a transistor shown in FIG. 4 This will be explained using:

[0168] 4A and 4B are cross-sectional views of the transistor 100C. The top view of the transistor C is the same as that of the transistor 100A shown in FIG. The explanation will be omitted.

[0169] The transistor 100C shown in FIGS. 4A and 4B has a stacked structure of a conductive film 112, a conductive film 11 The shape of the insulating film 110 and the shape of the insulating film 110 are different from those of the transistor 100A.

[0170] The conductive film 112 of the transistor 100C includes a conductive film 112_1 on the insulating film 110 and a conductive film For example, the conductive film 112_1 may be formed of an oxide film. By using a conductive film, excess oxygen can be added to the insulating film 110. The conductive oxide film is formed by sputtering in an atmosphere containing oxygen gas. The oxide conductive film can be formed of, for example, an oxide containing indium and tin. tungsten and indium oxide, tungsten, indium and zinc oxide oxides containing titanium and indium; oxides containing titanium, indium, and tin oxide, oxide containing indium and zinc, oxide containing silicon, indium and tin Examples of suitable oxides include oxides containing indium, gallium, and zinc.

[0171] 4B, in the opening 143, the conductive film 112_2 and the conductive film 112_3 are When forming the opening 143, a conductive film that becomes the conductive film 112_1 is formed. After this, an opening 143 is formed, thereby making it possible to obtain the shape shown in FIG. 4(B). When an oxide conductive film is used as the conductive film 112_1, the conductive film 112_2 and the conductive film 106 By using a structure in which the conductive film 112 and the conductive film 106 are connected, the connection resistance between the conductive film 112 and the conductive film 106 can be reduced. This can be done.

[0172] The conductive film 112 and the insulating film 110 of the transistor 100C have a tapered shape. More specifically, the lower end of the conductive film 112 is formed outside the upper end of the conductive film 112. The lower end of the insulating film 110 is formed outside the upper end of the insulating film 110. In addition, the lower end of the conductive film 112 is formed at approximately the same position as the upper end of the insulating film 110 .

[0173] The conductive film 112 and the insulating film 110 of the transistor 100C are tapered. Compared with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular, the insulating film 11 This is preferable because it can improve the coverage of 6.

[0174] The other configurations of the transistor 100C are the same as those of the transistor 100A shown above. and has the same effect.

[0175] <1-5. Manufacturing method of semiconductor device> Next, an example of a method for manufacturing the transistor 100A shown in FIGS. 2A, 2B, and 2C will be described. 5 to 7. Note that FIGS. 5 to 7 show a method for manufacturing the transistor 100A. 1A and 1B are cross-sectional views in the channel length (L) direction and the channel width (W) direction, illustrating the method.

[0176] First, the conductive film 106 is formed on the substrate 102. Next, the conductive film 106 is formed on the substrate 102. An insulating film 104 is formed on the insulating film 104, and an island-shaped oxide semiconductor film 108i_0 is formed over the insulating film 104. (See FIG. 5(A)).

[0177] The conductive film 106 can be formed by selecting the above-described material. In this case, the conductive film 106 is formed by depositing tungsten with a thickness of 50 nm using a sputtering apparatus. A laminated film of the film and a copper film having a thickness of 400 nm is formed.

[0178] The conductive film to be formed into the conductive film 106 can be processed by wet etching or dry etching. Either one or both of the wet etching methods may be used. After etching the copper film by etching method, the tungsten film is etched by dry etching method. The conductive film is processed by etching to form a conductive film 106 .

[0179] The insulating film 104 can be formed by a method such as sputtering, CVD, evaporation, or pulsed laser deposition (P The layer can be formed by appropriately using a laser diode (LD) method, a printing method, a coating method, or the like. As the insulating film 104, a silicon nitride film having a thickness of 400 nm was formed using a plasma CVD apparatus. and a silicon oxynitride film having a thickness of 50 nm.

[0180] After the insulating film 104 is formed, oxygen may be added to the insulating film 104. The oxygen to be added may be an oxygen radical, an oxygen atom, an oxygen atomic ion, an oxygen molecular ion, etc. The methods of addition include ion doping, ion implantation, and plasma treatment. In addition, after forming a film that suppresses oxygen desorption on the insulating film, the insulating film is Oxygen may be added to 104.

[0181] The film for suppressing the desorption of oxygen mentioned above includes indium, zinc, gallium, tin, and aluminum. , chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungste The insulating film can be formed using a conductive film or a semiconductor film having one or more of the following:

[0182] In addition, when oxygen is added by plasma treatment, the oxygen is excited by microwaves to form high-density oxygen. By generating plasma, the amount of oxygen added to the insulating film 104 can be increased.

[0183] The island-shaped oxide semiconductor film 108i_0 can be, for example, a single layer. The oxide semiconductor film can be formed by stacking a first oxide semiconductor film and a second oxide semiconductor film. When the first oxide semiconductor film is formed by laminating the first oxide semiconductor film, the first oxide semiconductor film is formed under the conditions of: It is preferable to set either the substrate temperature or the oxygen flow rate ratio, or both, lower than that of the film.

[0184] Specifically, the first oxide semiconductor film is formed under the conditions that the substrate temperature is equal to or higher than room temperature and less than 150° C. Preferably, the temperature is 100°C or higher and 140°C or lower, and the oxygen flow rate is more than 0% and less than 30%. The second oxide semiconductor film is formed under the conditions of a substrate temperature of 150° C. or higher and a The substrate temperature is set to 0°C or less, preferably 160°C to 200°C, and the oxygen flow rate is set to 30% or more. The upper limit shall be 100% or less.

[0185] By using the above-described formation conditions, oxide semiconductor films with different carrier densities can be stacked to form a semiconductor layer. Note that the first oxide semiconductor film and the second oxide semiconductor film can be formed in vacuum. Forming them continuously is more preferable because impurities are not introduced into the interfaces.

[0186] Note that the oxide semiconductor film 108i_0 is formed by heating, so that the oxide semiconductor film 108 On the other hand, the substrate 102 may be a large glass substrate (for example, When a sixth to tenth generation oxide semiconductor film is used, the substrate temperature during the formation of the oxide semiconductor film 108 is If the temperature is set to 200° C. or higher and 300° C. or lower, the substrate 102 may deform (distort or warp). Therefore, when a large glass substrate is used, the formation of the oxide semiconductor film 108 is difficult. By keeping the substrate temperature during film application between 100°C and 200°C, deformation of the glass substrate is suppressed. It is possible.

[0187] In addition, the sputtering gas must be highly purified. The oxygen gas or argon gas used has a dew point of -40°C or less, preferably -80°C or less, more preferably Preferably, a gas purified to a temperature of -100°C or less, more preferably -120°C or less, is used. By doing so, moisture and the like can be prevented from being taken into the oxide semiconductor film as much as possible.

[0188] In addition, when the oxide semiconductor film is formed by a sputtering method, The chamber is designed to remove as much water as possible, which is an impurity for the oxide semiconductor film. A high vacuum (5×10) was created using a suction-type vacuum pump such as an OP-pump. -7 Pa to 1× 10 -4 It is preferable to evacuate the gas to a pressure of about 100 Pa, especially when the sputtering device is in standby mode. In the chamber, gas molecules corresponding to HO (gas molecules corresponding to M / z=18) ) partial pressure to 1×10 -4 Pa or less, preferably 5 x 10 -5 It is preferable that the value is less than or equal to Pa. .

[0189] The first oxide semiconductor film was formed under the conditions of: The sputtering method was used to deposit In:Ga:Zn (atomic ratio: 4:2:4.1). The substrate temperature during the formation of the first oxide semiconductor film was set to 130° C. The gas used was oxygen gas with a flow rate of 20 sccm and argon gas with a flow rate of 180 sccm. (oxygen flow ratio 10%).

[0190] The second oxide semiconductor film was formed under the conditions of: The sputtering method was used to deposit In:Ga:Zn (atomic ratio: 4:2:4.1). The substrate temperature during the formation of the second oxide semiconductor film was set to 170° C. The gas used was oxygen gas with a flow rate of 60 sccm and argon gas with a flow rate of 140 sccm. (Oxygen flow ratio 30%).

[0191] In the above, the first oxide semiconductor film and the second oxide semiconductor film are grown at a substrate temperature and oxygen flow rate ratios are changed to stack oxide semiconductor films with different carrier densities. However, the present invention is not limited to this. For example, when forming the first oxide semiconductor film, In the second oxide semiconductor film, the carrier density is different from that of the first oxide semiconductor film by adding an impurity element. An oxide semiconductor film may be formed. The impurity element may be hydrogen, boron, carbon, or nitrogen. fluorine, phosphorus, sulfur, chlorine, rare gases, etc.

[0192] Note that the impurity element added to the first oxide semiconductor film can be selected from the above-described elements. Nitrogen is particularly preferable. For example, when the first oxide semiconductor film is formed, argon gas and and nitrogen gas are used as the deposition gas, or argon gas and nitrous oxide gas are used as the deposition gas. By using the nitrogen gas, nitrogen can be added to the first oxide semiconductor film.

[0193] In addition, when an impurity element is used in forming the first oxide semiconductor film, the impurity element is To avoid contamination of a film to which an impurity element is not to be added, for example, the second oxide semiconductor film, It is preferable to provide an independent chamber for forming the first oxide semiconductor film.

[0194] After the first oxide semiconductor film is formed, an impurity element is added to the first oxide semiconductor film. The impurity element may be added after the first oxide semiconductor film is formed, for example, by the following method. A doping process or a plasma process can be used.

[0195] After the first oxide semiconductor film and the second oxide semiconductor film are formed, heat treatment is performed. The first oxide semiconductor film and the second oxide semiconductor film may be dehydrogenated or dehydrated. The temperature of the heat treatment is typically 150°C or higher and lower than the substrate distortion point, or 250°C or higher and lower than 45°C. The temperature is 0°C or lower, or 300°C or higher and 450°C or lower.

[0196] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, or nitrogen. Alternatively, the heating may be carried out in an inert gas atmosphere containing oxygen. In addition, hydrogen, water, etc. may be added to the inert atmosphere and oxygen atmosphere. The treatment time may be from 3 minutes to 24 hours.

[0197] The heat treatment can be performed using an electric furnace, an RTA device, or the like. Therefore, the heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. This can reduce processing time.

[0198] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is formed and then subjected to heat treatment. By performing the above, the hydrogen concentration in the oxide semiconductor film obtained by SIMS was increased to 5×10 1 9 atoms / cm 3 or less, or 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1×10 18 atoms / cm 3 or less, or 5 x 10 17 atoms / cm 3 or less, or 1×10 16 atoms / cm 3 The following can be done: can.

[0199] Next, the insulating film 110_0 is formed over the insulating film 104 and the oxide semiconductor film (FIG. 5B). reference).

[0200] The insulating film 110_0 is a silicon oxide film or a silicon oxynitride film formed by plasma chemical It is formed using a plasma-enhanced chemical vapor deposition (PECVD) system or simply called a plasma CVD system. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, and the like. Examples of oxidizing gases include silane, trisilane, and fluorinated silane. Examples of oxidizing gases include oxygen, ozone, and monoxide. Examples include dinitrogen and nitrogen dioxide.

[0201] In addition, the flow rate of the oxidizing gas is set to 20 times the flow rate of the deposition gas for the insulating film 110_0. The pressure in the processing chamber is set to 100 Pa or greater but less than 100 times, or 40 times or greater but less than 80 times. By using a plasma CVD device with a pressure of less than 50 Pa or less, it is possible to obtain an oxide with a small amount of defects. A silicon nitride film can be formed.

[0202] Also, as the insulating film 110_0, a film is placed in a processing chamber of a plasma CVD apparatus that has been evacuated. The substrate is maintained at a temperature of 280°C or higher and 400°C or lower, and raw material gas is introduced into the processing chamber. The pressure in the air is 20 Pa or more and 250 Pa or less, and more preferably 100 Pa or more and 250 Pa or less. The insulating film 110 is formed by supplying high frequency power to an electrode provided in the processing chamber under the following conditions. As a result, a dense silicon oxide film or silicon oxynitride film can be formed. do.

[0203] The insulating film 110_0 may be formed by a plasma CVD method using microwaves. Microwaves refer to the frequency range from 300MHz to 300GHz. The electron temperature is low and the electron energy is small. The proportion of the carbon dioxide used is small, so it can be used to dissociate and ionize more molecules. Therefore, it is possible to excite a high density plasma (high density plasma). In addition, the deposition is less damaged by plasma, and an insulating film 110_0 having fewer defects is formed. This can be done.

[0204] The insulating film 110_0 can be formed by a CVD method using organic silane gas. The organic silane gas is ethyl silicate (TEOS: chemical formula Si(OC2H5)4). , tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetra Siloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethylcyclotetrasiloxane dimethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), Silicon-containing compounds such as dimethylaminosilane (SiH(N(CH3)2)3) By using the CVD method with organic silane gas, it is possible to obtain highly insulating films with high coating properties. A velum 110_0 can be formed.

[0205] In this embodiment, a plasma CVD apparatus is used to form the insulating film 110_0, which is 100 nm thick. A silicon oxynitride film is formed.

[0206] Next, a mask is formed by lithography at a desired position on the insulating film 110_0. By etching the insulating film 110_0 and a part of the insulating film 104, the conductive film 106 is reached. An opening 143 is formed (see FIG. 5(C)).

[0207] The opening 143 can be formed by either wet etching or dry etching. In this embodiment, a dry etching method is used. Then, an opening 143 is formed.

[0208] Next, a conductive film 112 is formed on the conductive film 106 and the insulating film 110_0 so as to cover the opening 143. In addition, when a metal oxide film is used as the conductive film 112_0, for example, When oxygen is added from the conductive film 112_0 to the insulating film 110_0 during the formation of the film 112_0, In some cases, this is the case (see FIG. 5(D)).

[0209] In FIG. 5(D), the oxygen added to the insulating film 110_0 is schematically represented by an arrow. In addition, the conductive film 112_0 is formed so as to cover the opening 143. 106 and the conductive film 112_0 are electrically connected.

[0210] When a metal oxide film is used as the conductive film 112_0, the conductive film 112_0 is formed by is preferably formed by sputtering in an atmosphere containing oxygen gas. By forming the conductive film 112_0 in an atmosphere containing oxygen gas, the insulating film 110_ Oxygen can be suitably added to the conductive film 112_0. The method is not limited to the sputtering method, but may be other methods such as ALD (Atomic Lay The er Deposition method may also be used.

[0211] In this embodiment, the conductive film 112_0 is formed by sputtering. 100nm In-Ga-Zn oxide IGZO film (In:Ga:Zn=4:2:4 0.1 (atomic ratio). Also, before the formation of the conductive film 112_0 or the conductive film 112_ After the insulating film 110_0 is formed, oxygen addition treatment may be performed in the insulating film 110_0. The method may be the same as the method for adding oxygen after the insulating film 104 is formed. .

[0212] Next, a mask 140 is formed at a desired position on the conductive film 112_0 by a lithography process. (See Figure 6(A)).

[0213] Next, etching is performed from above the mask 140 to remove the conductive film 112_0 and the insulating film 110_ After the conductive film 112_0 and the insulating film 110_0 are processed, the mask 140 By processing the conductive film 112_0 and the insulating film 110_0, an island-shaped conductive film 112 and an island-shaped insulating film 110 are formed (see FIG. 6(B)).

[0214] In this embodiment, the conductive film 112_0 and the insulating film 112_1 are formed by dry etching. Process 10_0.

[0215] When the conductive film 112 and the insulating film 110 are processed, the conductive film 112 is not overlapped with the insulating film 110. The thickness of the oxide semiconductor film may be thin. During this processing, the thickness of the insulating film 104 in a region where the oxide semiconductor film does not overlap may be thin. In addition, when processing the conductive film 112_0 and the insulating film 110_0, an etchant or The etching gas (e.g., chlorine) is added to the oxide semiconductor film, or a conductive When a constituent element of the film 112_0 or the insulating film 110_0 is added to the oxide semiconductor film There is.

[0216] Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film, and the conductive film 112. Note that by forming the insulating film 116, the oxide semiconductor film in contact with the insulating film 116 becomes the second The oxide semiconductor film in contact with the insulating film 110 is the first region 108i. As a result, an oxide semiconductor having a first region 108i and a second region 108n is obtained. A membrane 108 is formed (see FIG. 6(C)).

[0217] The insulating film 116 can be formed by selecting the above-described material. In this case, a 100 nm thick nitride oxide film was deposited as the insulating film 116 using a plasma CVD apparatus. In addition, when forming the silicon nitride oxide film, a plasma treatment is performed. The two steps of the plasma treatment and the film formation treatment are carried out at a temperature of 220°C. Argon gas was introduced into the chamber at a flow rate of 100 sccm before the film was formed. The pressure is set to 40 Pa, and the RF power supply (27.12 MHz) is supplied with 1000 W of power. The film formation process was carried out using silane gas at a flow rate of 50 sccm and nitrogen gas at a flow rate of 5000 sccm. Ammonia gas at a flow rate of 100 sccm was introduced into the chamber. The pressure is set to 100 Pa, and 1000 W of power is supplied to the RF power source (27.12 MHz). .

[0218] Since the insulating film 116 includes a silicon nitride oxide film, the second region 1 in contact with the insulating film 116 Nitrogen or hydrogen in the silicon nitride oxide film can be supplied to the insulating film. By setting the temperature at which the insulating film 116 is formed to the above temperature, excess oxygen contained in the insulating film 110 is evaporated to the outside. It is possible to suppress the release of the gas into the body.

[0219] Next, the insulating film 118 is formed over the insulating film 116 (see FIG. 7A).

[0220] The insulating film 118 can be formed by selecting the above-mentioned material. In this case, a plasma CVD apparatus was used to deposit an oxide nitride silicon film having a thickness of 300 nm as the insulating film 118. Form a polymer membrane.

[0221] Next, a mask is formed by lithography at a desired position on the insulating film 118, and then the insulating film 1 18 and a part of the insulating film 116 are etched to form an opening that reaches the second region 108n. The portions 141a and 141b are formed (see FIG. 7(B)).

[0222] The insulating film 118 and the insulating film 116 can be etched by wet etching or Either one or both of the dry etching method and the dry etching method may be used. The insulating film 118 and the insulating film 116 are processed by dry etching.

[0223] Next, the second region 108n and the insulating film 118 are formed so as to cover the openings 141a and 141b. A conductive film is formed on the conductive film 120a and the conductive film 120b. b is formed (see FIG. 7(C)).

[0224] The conductive films 120a and 120b can be formed by selecting the above-mentioned materials. In this embodiment, the conductive films 120a and 120b are formed by a sputtering device. A laminated film of a tungsten film having a thickness of 50 nm and a copper film having a thickness of 400 nm is formed.

[0225] The conductive films 120a and 120b are processed by wet etching. In this embodiment, either one or both of the etching method and the dry etching method may be used. After etching the copper film by wet etching, the tongue is removed by dry etching. The stainless steel film is etched to form conductive films 120a and 120b. .

[0226] Through the above steps, the transistor 100A shown in FIGS. 2(A), 2(B), and 2(C) is manufactured. can be done.

[0227] The films constituting the transistor 100A (insulating film, metal oxide film, oxide semiconductor film, conductive film, In addition to the above-mentioned forming methods, the film may be formed by sputtering, chemical vapor deposition (CVD), It can be formed using vacuum evaporation, pulsed laser deposition (PLD), or ALD. Alternatively, it can be formed by a coating method or a printing method. Typical examples of the method include a coating method and a plasma enhanced chemical vapor deposition (PECVD) method, but a thermal CVD method may also be used. An example of the thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0228] In the thermal CVD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gas and oxidant are simultaneously mixed in the chamber. The film is formed by sending the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0229] Thermal CVD methods such as MOCVD can be used to form the above-mentioned conductive films, insulating films, oxide semiconductor films, and metal oxide films. For example, when forming an In-Ga-Zn-O film, are trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3) 3), and dimethylzinc (Zn(CH3)2). First, triethylgallium (Ga(C2H5)3) is used instead of trimethylgallium. Dimethyl zinc can also be replaced by diethyl zinc (Zn(C2H5)2). Cut.

[0230] In addition, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and hafnium Liquids containing hafnium precursors (hafnium alkoxides, tetrakisdimethylamide hafnium Hf[N(CH3)2]4) and tetrakis(ethylmethylamide) The raw material gas is vaporized hafnium (e.g., hafnium amide) and ozone (O 3) Two types of gases are used.

[0231] In addition, when forming an aluminum oxide film using a film formation device that uses ALD, the solvent and Liquid containing aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: vaporized raw material gas (such as HCl) and oxidizing agent (H2O). Examples include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum. Minium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) be.

[0232] In addition, when forming a silicon oxide film using a film forming device that uses ALD, The silane is adsorbed onto the surface to be coated, and oxidizing gas (O2, nitrous oxide) radicals are supplied. and reacts with the adsorbate.

[0233] In addition, when forming a tungsten film using a film formation device that uses ALD, WF6 gas is used. and B2H6 gas are introduced sequentially to form an initial tungsten film, and then WF6 gas and H2 The tungsten film is formed using SiH4 gas instead of B2H6 gas. It may be used.

[0234] In addition, oxide semiconductor films, such as In-Ga-Zn-O films, can be formed using a film formation system that utilizes ALD. When forming a film, an In-O layer is formed using In(CH3)3 gas and O3 gas. Then, a GaO layer was formed using Ga(CH3)3 gas and O3 gas, and then a Zn( The ZnO layer is formed using CH3)2 gas and O3 gas. In addition, the examples are not limited to the above. In addition, In-Ga-O layers, In-Zn-O layers, and G A mixed compound layer such as a-Zn-O layer may be formed. HO gas obtained by bubbling water with an inert gas may be used, but O gas containing no H It is preferable to use three gases.

[0235] In this embodiment, an example in which the transistor includes an oxide semiconductor film is shown. However, one embodiment of the present invention is not limited thereto. For example, the semiconductor layer may not have a channel region of a transistor. In the vicinity of the region, source region, or drain region, Si (silicon), Ge (gel silicon germanium), SiGe (silicon germanium), GaAs (gallium arsenide), etc. The insulating layer 11 may be made of a material that is

[0236] Note that the structures and methods described in this embodiment mode may be combined as appropriate with structures and methods described in other embodiment modes. It can be used in combination.

[0237] (Embodiment 2) In this embodiment, a transistor that can be used in one embodiment of the present invention described in Embodiment 1 will be described. 10 shows a modified example of a transistor.

[0238] In the transistor 100C shown in FIGS. 4A and 4B, the insulating film 110 The transistor is formed shorter in the channel length direction, and the doping process or plasma By adding impurity elements or by heat treatment, as shown in Figure 45, A region 108n_2 may be provided between the first region 108i and the second region 108n. At this time, the conductivity of the region 108n_2 is higher than that of the first region 108i, and the conductivity of the second region 108n_2 is higher than that of the first region 108i. By forming such a region 108n_2, a semiconductor device or When the display device is in operation, the electric field strength at the drain end of the transistor becomes locally large. This can prevent this.

[0239] Note that the structures and methods described in this embodiment mode may be combined as appropriate with structures and methods described in other embodiment modes. It can be used in combination.

[0240] (Embodiment 3) In this embodiment, an oxide semiconductor that can be used in one embodiment of the present invention will be described. explain.

[0241] <2-1. Composition of oxide semiconductor> The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0242] Here, the oxide semiconductor is InMZnO having indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, tin, etc. Other elements that can be used for element M include boron, silicon, titanium, iron, Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Hafnium, tantalum, tungsten, magnesium, etc. However, as the element M In some cases, a combination of the above elements may be used.

[0243] <Structure> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c-axis alignable oxide semiconductor) gned crystalline oxide semiconductor), polycrystalline nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) amorphous oxide semiconductors) and amorphous oxide semiconductors etc.

[0244] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0245] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. The distortion may also have lattice arrangements such as pentagons and heptagons. In CAAC-OS, clear grain boundaries (grain boundaries) are observed even near the strain. It is not possible to confirm the grain boundary (also called grain boundary distortion) due to the distortion of the lattice arrangement. This is because the CAAC-OS has a high SiO2 content in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms changes due to the substitution of metal elements. This is thought to be because distortion can be tolerated by, for example, increasing the thickness.

[0246] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when indium in the In layer is replaced with element M, (In,M ) layer.

[0247] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0248] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS.

[0249] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and nc The compound may have two or more of -OS and CAAC-OS.

[0250] <Atomic ratio> Next, with reference to FIGS. 8(A), 8(B), and 8(C), the oxide semiconductor according to the present invention will be described. The preferred range of the atomic ratio of indium, element M, and zinc contained in the alloy will be described below. Note that the atomic ratio of oxygen is not shown in Figures 8(A), 8(B), and 8(C). In addition, the atomic ratios of indium, element M, and zinc in the oxide semiconductor are Let these terms be [In], [M], and [Zn].

[0251] In Figures 8(A), 8(B), and 8(C), the dashed lines indicate the [In]:[M]:[Z n] = (1 + α):(1 - α):1, where the atomic ratio (-1 ≦ α ≦ 1) is [In] :[M]:[Zn]=(1+α):(1-α):2 atomic ratio line, [In]: The line where the atomic ratio of [M]:[Zn]=(1+α):(1-α):3, [In]:[ The line where the atomic ratio of [M]:[Zn]=(1+α):(1-α):4, and [In] : Represents the line where the atomic ratio of [M]:[Zn]=(1+α):(1-α):5.

[0252] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is :[M]:[Zn]=1:1:β atomic ratio line, [In]:[M]:[Zn] = 1:2:β atomic ratio line, [In]:[M]:[Zn]=1:3:β atoms The line where the atomic ratio is [In]:[M]:[Zn]=1:4:β Represents in.

[0253] In addition, the [In]:[M]:[Zn] shown in Figures 8(A), 8(B), and 8(C) Oxide semiconductors with an atomic ratio of 0:2:1 or close to that ratio have a spinel-type crystal structure. Easy to take.

[0254] In addition, multiple phases may coexist in an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel The two phases of the hexagonal crystal structure and the layered crystal structure tend to coexist. When [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and the layered structure When multiple phases coexist in an oxide semiconductor, different Grain boundaries may be formed between the crystalline structures.

[0255] A region A shown in FIG. 8A is a region containing indium, the element M, and zinc in the oxide semiconductor. An example of a preferred range of the atomic ratio is shown.

[0256] By increasing the indium content of an oxide semiconductor, the carrier mobility of the oxide semiconductor can be improved. Therefore, oxide semiconductors with a high indium content can be used. The oxide semiconductor has higher carrier mobility than an oxide semiconductor having a low indium content.

[0257] On the other hand, when the content of indium and zinc in the oxide semiconductor is low, the carrier mobility Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity In the case of a near value (for example, region C shown in FIG. 8C), the insulating property is high.

[0258] Therefore, the oxide semiconductor of one embodiment of the present invention has high carrier mobility and few crystal grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 8(A), which tends to form a layered structure without any problem. It's nice.

[0259] In particular, in region B shown in FIG. 8(B), CAAC-OS is more likely to occur than in region A. An excellent oxide semiconductor with high carrier mobility can be obtained.

[0260] CAAC-OS is an oxide semiconductor with high crystallinity. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of oxide semiconductors can be degraded by the inclusion of impurities and the generation of defects. Therefore, CAAC-OS is an oxide with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable.

[0261] Region B is the region where [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Nearby values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, [In]:[M]:[Zn]=5:1:7 and its neighboring values.

[0262] Note that the properties of an oxide semiconductor are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the oxide semiconductor may differ depending on the formation conditions. When forming a film of semiconductor material using a sputtering device, the atomic ratio of the target may deviate. Also, depending on the substrate temperature during film formation, the film thickness is higher than the target [Zn]. Therefore, the region shown in the figure is a region where the oxide semiconductor is particularly The boundary between Region A and Region C is a region showing the atomic ratio that tends to have certain characteristics. isn't it.

[0263] [Transistors with oxide semiconductors] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0264] By using the oxide semiconductor in a transistor, carrier scattering at the grain boundary can be reduced. This allows for a reduction in the amount of charge, making it possible to realize a transistor with high field effect mobility. Furthermore, a highly reliable transistor can be realized.

[0265] In addition, an oxide semiconductor with low carrier density is used for a channel region of a transistor. In the case where the carrier density of the oxide semiconductor film is reduced, it is preferable that the oxide semiconductor film In this specification and the like, the impurity concentration in the semiconductor layer is reduced to reduce the defect level density. A low concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0266] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0267] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0268] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0269] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0270] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0271] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 Do the following:

[0272] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. Therefore, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is The degree is 5×10 in SIMS. 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below, further Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0273] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that the SIM is reduced as much as possible. The hydrogen concentration obtained by S is 1×10 20 atoms / cm 3 Less than 1x1 0 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than, More preferably, 1 × 10 18 atoms / cm 3 Less than.

[0274] By using an oxide semiconductor with sufficiently reduced impurities for a channel region of a transistor, Stable electrical properties can be imparted.

[0275] <Band diagram> Next, the case where the oxide semiconductor has a two-layer structure or a three-layer structure will be described. A stacked structure of a semiconductor S1, an oxide semiconductor S2, and an oxide semiconductor S3, and a stacked structure The band diagram of the adjacent insulator, the stacked structure of the oxide semiconductor S2 and the oxide semiconductor S3, and The band diagram of the insulator adjacent to the stacked structure and the product of the oxide semiconductor S1 and the oxide semiconductor S2 are shown in Fig. The layer structure and the band diagram of the insulator in contact with the stacked structure are explained using Figure 9. .

[0276] FIG. 9(A) shows an insulator I1, an oxide semiconductor S1, an oxide semiconductor S2, an oxide semiconductor S3, 9(B) is an example of a band diagram in the thickness direction of a stacked structure having an insulator I2. ) is a multilayer structure having an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. FIG. 9(C) shows an example of a band diagram in the film thickness direction of a layer structure. Band diagram in the thickness direction of a stacked structure consisting of a conductor S1, an oxide semiconductor S2, and an insulator I2 For ease of understanding, the band diagram is divided into insulator I1 and oxide semiconductor S1. , the energy levels of the conduction band minimum of the oxide semiconductor S2, the oxide semiconductor S3, and the insulator I2 Indicates the degree (Ec).

[0277] The oxide semiconductors S1 and S3 have lower conduction band energy levels than the oxide semiconductor S2. The energy level is close to the vacuum level, typically the energy level at the bottom of the conduction band of the oxide semiconductor S2. The difference between the energy level at the bottom of the conduction band of the oxide semiconductor S1 and the oxide semiconductor S3 is 0. 15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less That is, the electron affinities of the oxide semiconductors S1 and S3 and the oxide semiconductors S4 and S5 are preferably The difference between the electron affinity of the S2 molecule is 0.15 eV or more, or 0.5 eV or more and 2 eV or more. It is preferably below 1 eV, or 1 eV or less.

[0278] As shown in FIGS. 9(A), 9(B), and 9(C), the oxide semiconductor S1, the oxide semiconductor S2, and the oxide semiconductor S3 are In the conductor S2 and the oxide semiconductor S3, the energy level at the bottom of the conduction band changes gradually. In other words, it can be said that the material changes continuously or is joined continuously. In order to have a gate diagram, the interface between the oxide semiconductor S1 and the oxide semiconductor S2 or the oxide The defect level density of the mixed layer formed at the interface between the semiconductor S2 and the oxide semiconductor S3 is reduced. It is recommended to do so.

[0279] Specifically, the oxide semiconductor S1 and the oxide semiconductor S2, the oxide semiconductor S2 and the oxide semiconductor S 3) has a common element other than oxygen (as the main component), resulting in a mixture with a low defect level density. For example, the oxide semiconductor S2 can be an In-Ga-Zn oxide semiconductor. In this case, the oxide semiconductor S1 and the oxide semiconductor S3 are In-Ga-Zn oxide semiconductors, It is preferable to use a Ga-Zn oxide semiconductor, gallium oxide, or the like.

[0280] At this time, the main carrier path is the oxide semiconductor S2. Defects at the interface with semiconductor S2 and at the interface between oxide semiconductor S2 and oxide semiconductor S3 Since the level density can be reduced, the effect of interface scattering on carrier conduction is small. A high on-current can be obtained.

[0281] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide semiconductor S3, the trap level can be moved away from the oxide semiconductor S2. This structure allows the threshold voltage of the transistor to be shifted in the positive direction. This can prevent the following from happening.

[0282] The oxide semiconductors S1 and S3 have higher electrical conductivity than the oxide semiconductor S2. At this time, the oxide semiconductor S2 and the oxide semiconductor S2 are used. The interface between the oxide semiconductor S1 and the oxide semiconductor S2 and the oxide semiconductor S3 is mainly the channel. For example, the oxide semiconductor S1 and the oxide semiconductor S3 have the following structure as shown in FIG. In this case, an oxide semiconductor having an atomic ratio shown in region C where the insulating property is high may be used. Region C shown in FIG. 8(C) is [In]:[M]:[Zn]=0:1:0 and its vicinity. value, [In]:[M]:[Zn]=1:3:2 and its neighboring values, and [In]:[M ]:[Zn]=1:3:4 and its neighboring atomic ratios.

[0283] In particular, when an oxide semiconductor having an atomic ratio shown in region A is used for the oxide semiconductor S2, The compound semiconductor S1 and the oxide semiconductor S3 have an [M] / [In] ratio of 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor having a sufficient conductivity. Oxide semiconductors with [M] / ([Zn]+[In]) of 1 or more that can provide high insulation It is preferable to use a conductor.

[0284] <2-2. Structure using oxide semiconductor in transistor> Next, a structure in which an oxide semiconductor is used for a transistor will be described.

[0285] Note that the use of an oxide semiconductor in a transistor can prevent carrier scattering at grain boundaries. This allows for the realization of transistors with high field-effect mobility. Furthermore, a highly reliable transistor can be realized.

[0286] In addition, an oxide semiconductor with low carrier density is used for a channel region of a transistor. For example, the oxide semiconductor preferably has a carrier density of 8×10 11 / cm 3 Less than preferred Or 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 is less than 1×10 -9 / cm 3 That's all there is to it.

[0287] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. In addition, the carrier density can be reduced because the material is intrinsically or substantially pure. Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0288] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0289] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0290] Here, the influence of each impurity in an oxide semiconductor will be described.

[0291] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0292] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 Do the following:

[0293] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. Therefore, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is The degree is 5×10 in SIMS. 19atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below, further Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0294] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, hydrogen in the oxide semiconductor It is preferable that the SIM is reduced as much as possible. The hydrogen concentration obtained by S is 1×10 20 atoms / cm 3 Less than 1x1 0 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than, More preferably, 1 × 10 18 atoms / cm 3 Less than.

[0295] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0296] In addition, the oxide semiconductor film has an energy gap of 2 eV or more, or 2.5 eV or more, or It is preferable that the electron energy is 3 eV or more.

[0297] The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm. 0 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0298] In addition, when the oxide semiconductor film is an In-M-Zn oxide, an In-M-Zn oxide film is formed. The atomic ratio of the metal elements in the sputtering target used for this purpose is In:M:Zn= 1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2: 1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, In:M:Z Preferably, n=5:1:7, etc.

[0299] The atomic ratio of metal elements in the oxide semiconductor film to be formed is determined by the above sputtering method. The atomic ratio of metal elements contained in the target can vary by approximately plus or minus 40%. For example, a sputtering target with an atomic ratio of In:Ga:Zn=4:2 When the oxide semiconductor film is formed using In:Ga:Zn=4.1, the atomic ratio of the oxide semiconductor film to be formed is In:Ga:Zn=4. In addition, as a sputtering target, the atomic ratio may be around I When n:Ga:Zn=5:1:7 is used, the atomic ratio of the oxide semiconductor film to be formed is I In some cases, the n:Ga:Zn ratio is approximately 5:1:6.

[0300] <2-3. Structure of oxide semiconductors> Hereinafter, a CAC(Cl) compound that can be used in a transistor disclosed in one embodiment of the present invention will be described. This paper explains the structure of the oud-Aligned Composite OS.

[0301] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0302] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0303] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (GaX4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0304] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0305] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0306] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0307] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the crystals are randomly dispersed in a mosaic pattern. Structure is a secondary factor.

[0308] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0309] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0310] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0311] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas to be used is preferably selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the oxygen gas, the better. For example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%. It is preferable that the content is 0% or more and 10% or less.

[0312] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction, the measurement region It can be seen that no orientation in the ab plane direction or the c axis direction is observed.

[0313] In addition, the CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the Therefore, the electron diffraction pattern indicates that CAC-OS The crystal structure is nc (nano-c) which has no orientation in the plane direction and cross-sectional direction. It can be seen that it has a crystal structure.

[0314] For example, in the case of CAC-OS, an In-Ga-Zn oxide, energy dispersive X-ray Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using a copy of the GaO X3 The region where is the principal component and , InX2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed. It can be confirmed that it has the structure shown in the figure.

[0315] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0316] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or InO X The cloud-like distribution of the region where 1 is the main component in the oxide semiconductor results in a high field effect. Mobility (μ) can be achieved.

[0317] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0318] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) can be achieved. can.

[0319] Furthermore, semiconductor devices using CAC-OS are highly reliable. It is ideal for a variety of semiconductor devices, including displays.

[0320] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0321] (Fourth embodiment) When an oxide conductor is used for the conductive film 112 in the transistor 100 of one embodiment of the present invention, Excess oxygen can be added to the insulating film 110, and the excess oxygen can be further added to the oxide semiconductor film 108. This is preferable because it can diffuse into the first region 108i of the silicon oxynitride. It is possible that defects in the insulating film 110 including the silicon film can also be reduced. Defects in the insulating film 110 when an oxide conductor is used for the conductive film 112 will be described.

[0322] The defects in the silicon oxynitride film cause leakage when an electric field is applied above and below the silicon oxynitride film. The conditions for forming a metal film on a silicon oxynitride film and the amount of oxygen The conditions for forming an oxide conductor on a silicon nitride film and the conditions for forming a MOS (Metal We formed silicon oxide nitride (SiOxN) samples and The leakage current of each silicon oxynitride film can be evaluated to obtain information on defects in the film. can.

[0323] To evaluate defects in the insulating film 110 when an oxide conductor is used for the conductive film 112 The following two samples are prepared: The first MOS sample 317 is a P-type MOS sample. A silicon oxynitride film is formed to a thickness of 10 nm on a silicon substrate to which impurities have been added. A metal film is formed thereon.

[0324] The second MOS sample 318 is formed on a silicon substrate doped with impurities that impart P-type conductivity. A silicon oxynitride film is formed to a thickness of 10 nm, and an oxide conductive film is formed on top of that. A metal film is formed on the surface.

[0325] The metal film is made of titanium nitride with a thickness of 30 nm and tungsten with a thickness of 135 nm on top. The conductive oxide film is made of In-Ga- Using a Zn oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]), The film is formed by sputtering in a 0.00% oxygen gas atmosphere.

[0326] In the high electric field region, the current flowing through the silicon oxynitride film is The im(FN) current is dominant. The FN current is expressed as J in Eq. FNIt is expressed as:

[0327]

number

[0328] From Equation 1, ln(J / E 2 ) versus 1 / E gives a straight line, but If there is a depression level, part of the FN plot will deviate from the straight line. The outlying region is called the ledge region, where electrons of the FN current are trapped in the deep defect level. This is due to the process that the trapped electrons form a fixed charge, which causes the parallelism of the IV curve. This parallel shift induces a shift, forming a ledge region. Load density can be estimated.

[0329] FIG. 10A shows a MOS structure including a metal region 310 and an oxide region 311. 1 and the energy band diagram of the silicon region 312 are shown.

[0330] The film corresponding to the oxide region 311 is a first MOS sample 317 and a second MOS sample 318. In each case, the metal region 310 is a silicon oxynitride film. The film corresponding to the first MOS sample 317 is a metal film, and the film corresponding to the second MOS sample In the case of the pull 318, it is an oxide conductive film and a metal film on top of it.

[0331] When a voltage is applied to the top and bottom of the silicon oxynitride film, the metal region 31 0 electrons are injected 315 into traps 314 in the oxide region 311 .

[0332] Therefore, we consider Equation 2, which assumes that a positive charge is trapped in the trap level, and Equation 3, which assumes that a positive charge is trapped in the trap level. Equation 3 assumes that negative charges are trapped at the charge injection site, and the IV curve before and after charge injection is From the trap shift (ΔVg), the trapped charge density (Qt(t)) and the trapped charge center of gravity We can estimate the position 316(x(_)). ox is the oxide region 31 This means a thickness of 1.

[0333]

number

number

[0334] Here, the position of the center of gravity of the trapped charge 316 is the silicon region in the oxide region 311. It is expressed as the distance from the interface with 312. Also, from the charge injection time dependence of the trapped charge density, The surface density of all trapped charges in the oxide region 311 can be calculated.

[0335] The surface density of all trapped charges in the oxide region obtained in this way is shown in Fig. 10(B), and the trap The position of the center of gravity of the charge is shown in FIG. 10(C). Therefore, the second MOS sample 318 has a low surface density of all trapped charges in the silicon oxynitride film. It can be seen that the trapped charge center of gravity 316 moves to the opposite side of the electrode. do.

[0336] In the FN plot obtained at this time (see FIG. 11(A)), the second MOS sample The measurement results of 318 show that the ledge region 321 seen in the first MOS sample 317 has disappeared. The vertical axis of Fig. 11(A) is ln(J / E 2 ) [A / MV 2 ], which is simply 10 and 11, the second MOS sample 3 In the method of 18, an oxide conductive film is formed on a silicon oxynitride film, so that the oxide conductive film The density of trapped charges (electrons trapped in deep defect levels) in the silicon nitride film is reduced. It can be seen that...

[0337] FIG. 11B shows a structure of a first MOS sample 317 and a second MOS sample 318. The structure is shown in the figure. Each of them is made of silicon 319, silicon oxynitride film 326, and metal film 3 The second MOS sample 318 has an oxide conductive film 313. The second MOS sample 318 has a metal film 3 In the first MOS sample 317 in which 25 was formed on the silicon oxynitride film 326, The center of gravity 328 of the trapped charge 327 in the silicon dioxide film 326 is located almost in the center. It is believed that defects exist evenly in the silicon oxynitride film 326 (see FIG. 11(B)). On the other hand, when the oxide conductive film 313 is used, the center of gravity of the trapped charge 327 is The position 329 is located near the interface between the silicon 319 and the silicon oxynitride film 326. The wrap charge density is also small. From the above results, it is clear that the formation of the oxide conductive film 313 The defect density in the silicon oxide film 326 is reduced in the region close to the oxide conductive film 313. It is thought that...

[0338] In this manner, in the transistor 100 of one embodiment of the present invention, the conductive film 112 is formed of an oxide conductive material. It can be seen that the use of the material has the effect of reducing the defect density of the insulating film 110.

[0339] (Embodiment 5) In this embodiment, the substrate temperature is set to 350° C., and a silicon oxynitride film is formed to form the insulating film 11. The characteristics of the transistor 100 when forming a gate insulating film 100 are shown below.

[0340] The insulating film 110 serving as the gate insulating film of the transistor 100 of one embodiment of the present invention Desirable features are fewer defects, less damage to the oxide semiconductor film 108, and oxidation. supplying excess oxygen to the compound semiconductor film 108.

[0341] In Embodiment 1, the insulating film functioning as the gate insulating film of the transistor 100 of one embodiment of the present invention is The insulating film 110 is a silicon oxynitride film formed by plasma chemical vapor deposition. When the temperature during silicon oxynitride film formation is low, the voids are filled with excess oxygen. The oxide semiconductor film can absorb or supply a large amount of excess oxygen. showed.

[0342] When the temperature during the formation of the silicon oxynitride film is high, the film density is high, i.e., the number of defects is small. Therefore, the first region 108i of the oxide semiconductor film 108 can be formed. A silicon oxynitride film was formed on the substrate at a substrate temperature of 350°C, and then the substrate temperature was increased to 220°C. The silicon oxynitride film is formed at a temperature of 100° C., that is, the insulating film 110 has a laminated structure. This is effective for achieving high reliability.

[0343] Considering the productivity when laminating this insulating film 110, it is desirable that the film formation temperature be constant. Desirable.

[0344] FIG. 12A shows the results of comparing the wet etching rates of silicon oxynitride films. In both Sample 351 and Sample 352, a silicon oxynitride film was formed on glass. The temperatures were 220°C for sample 351 and 350°C for sample 352.

[0345] In both Sample 351 and Sample 352, the silicon oxynitride film was formed by plasma CVD. The gases used were SiH4 = 20 sccm and N2O = 3000 sccm. The pressure was 0.00 Pa and the film formation power was 100 W. The solution used for wet etching was HF( 0.5%) and the temperature was room temperature.

[0346] As shown in FIG. 12(A), the etching rate of sample 352 is smaller. Therefore, when the silicon oxynitride film is formed at a substrate temperature of 350°C, the It can be said that a denser film can be obtained than when forming the film at 0°C.

[0347] FIG. 12(B) shows the results of FT-IR measurements of silicon oxynitride films. Sample 35 In both Sample 3 and Sample 354, a silicon oxynitride film was formed on a silicon wafer. The temperature was 220°C for sample 353 and 350°C for sample 354. Number 1050cm -1 The dotted line 357 drawn parallel to the vertical axis in is the wave number.

[0348] In both Sample 353 and Sample 354, the silicon oxynitride film was formed by plasma CVD. The gases used were SiH4 = 20 sccm and N2O = 3000 sccm. The pressure was 100 Pa and the film formation power was 100 W.

[0349] As shown in FIG. 12(B), Sample 354 has a small amount of Si-O bonds. This also shows that the silicon oxynitride film is formed at a low temperature. When forming a film at 350°C, a denser film is obtained than when forming a film at 220°C. It can be said that.

[0350] FIG. 12(C) shows the nitrogen oxide (NO x ) concentration by ESR method The results are compared. The vertical axis is the spin density. An oxide semiconductor film was formed to a thickness of 10 nm on the silicon dioxide film, and a silicon oxynitride film was formed to a thickness of 20 nm on the silicon dioxide film. A conductive oxide film is formed on the silicon dioxide film to a thickness of 100 nm. Remove before R measurement.

[0351] The substrate temperature during the deposition of the silicon oxynitride film was 220°C for sample 355 and 3 The temperature was 50° C. In both Sample 355 and Sample 356, the oxide semiconductor film was In—Ga—Zn Using an oxide target (In:Ga:Zn=4:2:4.1 [atomic ratio]), 90% The sputtering was performed in an atmosphere of 10% argon gas and 10% oxygen gas at a substrate temperature of 130°C. The silicon oxynitride film is formed by the plasma CVD method, and the gases used are The flow rates are SiH4 = 20sccm and N2O = 3000sccm. The deposition pressure is 200Pa. The deposition power is 100 W. The oxide conductive film is formed using an In-Ga-Zn oxide target. The film was formed by sputtering using In:Ga:Zn=4:2:4.1 [atomic ratio]. To film.

[0352] FIG. 12(C) shows the results of the nitrogen oxide film after the silicon oxynitride film is formed and after the oxide conductive film is removed. Things (NO x ) derived from the spin density [spins / cm 3 ]. In this way, the oxidized nitride When silicon film is formed at a substrate temperature of 350°C, it is formed at 220°C. Nitrogen oxides (NO x ) film with a low concentration can be obtained.

[0353] These results show that the dense, low-defect, and x ) concentration is low, and the substrate temperature during film formation It is considered preferable to use a silicon oxynitride film with a temperature of 350° C. as the insulating film 110. However, as shown in FIG. 43(A), when the substrate temperature during film formation was 350°C, When a silicon nitride film is used for the insulating film 110, the resistance of the oxide semiconductor film 108 is reduced. cormorant.

[0354] The following methods can be used to prevent the resistance of the oxide semiconductor film 108 from decreasing. is an oxygen plasma treatment 361 in a plasma CVD apparatus after the insulating film 110 is formed (FIG. 13 The other is heat treatment after the insulating film 116 is formed (see FIG. 13(B)). These treatments can increase the supply of excess oxygen 362 to the oxide semiconductor film 108. It is particularly preferable to use these treatments in combination.

[0355] The oxygen plasma treatment 361 in the plasma CVD apparatus after the insulating film 110 is performed as in Example 1. The method shown in FIG. 1 can be used for the heat treatment after the insulating film 116 is formed. It can be performed under the conditions of 350°C in an atmosphere for 1 hour.

[0356] Further, heat treatment after the formation of the insulating film 116 is effective for adding oxygen to the oxide semiconductor film. The results of the experiment conducted to demonstrate this are shown in Figures 14(A) and (B). The sample was prepared by forming an oxide semiconductor film with a thickness of 100 nm on a glass substrate and then A silicon oxide film is formed to a thickness of 100 nm, and a conductive oxide film is formed on the silicon oxide film to a thickness of 100 nm. A silicon nitride film was formed thereon to a thickness of 100 nm.

[0357] The oxide semiconductor film was formed using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4 .1 [atomic ratio]) in an atmosphere of 90% argon gas and 10% oxygen gas The film is formed by sputtering at a substrate temperature of 130°C.

[0358] The silicon oxynitride film was formed by plasma CVD at a substrate temperature of 220°C under different film formation conditions. The film is formed by stacking two layers. First, the first film formation condition is as follows: SiH4=5 The deposition pressure is 20 Pa and the deposition power is The power was 100 W. A 30 nm film was formed under the first film formation condition. x The second film formation condition is as follows: SiH4 = 160 sccm, N2O=4000sccm. The deposition pressure was 200Pa and the deposition power was 1500W. A 70 nm film is formed under the second film formation conditions.

[0359] The oxide conductive film was formed using an In-Ga-Zn oxide target (In:Ga:Zn=4:2:4. 1 [atomic ratio]), two layers are formed under different film formation conditions. The film conditions were 100% 18 Sputtering method in an O gas atmosphere at a substrate temperature of 170°C The first film formation condition is 10 nm. The second film formation condition is 90% Ar. Ngas and 10% 18 Sputtering was performed in an atmosphere of O gas at a substrate temperature of 170°C. A film is formed to a thickness of 90 nm under the second film formation conditions.

[0360] The silicon nitride film was formed using a substrate temperature of 220°C and a silane gas flow rate of 50 sccm. Nitrogen gas with a flow rate of 5000 sccm and ammonia gas with a flow rate of 100 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the parallel plate electrodes installed in the plasma CVD device This is done by supplying 1000W of RF power between them.

[0361] Thereafter, sample 365 was not subjected to heat treatment, and sample 366 was heated at 250°C in a nitrogen atmosphere. The sample 367 is subjected to a heat treatment at a temperature of 350° C. in a nitrogen atmosphere.

[0362] 14(A) and (B) are the results of SIMS analysis of Sample 365, Sample 366, and Sample 367. R 18 The results of the O concentration distribution evaluation. 18 O is sample 365, sample 366, sample 367, It is only used when forming the oxide conductive film, so it is difficult to 18 When O concentration is high, 18 O is thought to have diffused from the oxide conductive film. Profile evaluation was carried out while drilling towards the site.

[0363] In Figures 14(A) and (B), the horizontal axis indicates the depth from the surface of the sample, and the vertical axis indicates the thickness of the oxide conductive film. 368, a silicon oxynitride film 369, and an oxide semiconductor film 370. 18 Detect O In FIG. 14(A), the SIMS signal in the silicon oxynitride film 369 is 18 14B, the O concentration in the oxide semiconductor film 370 is also quantified. 1 8 The O concentration is quantified.

[0364] As can be seen from the results of FIGS. 14(A) and (B), after the silicon nitride film was formed, the heat treatment By this, more oxygen in the silicon oxynitride film can be diffused into the oxide semiconductor film. Cut.

[0365] In addition, in order to investigate which step of heat treatment is effective for adding oxygen to the oxide semiconductor film, The results of the experiment conducted with this objective are shown in Figure 14(C).

[0366] The sample evaluated in this experiment is a quartz substrate on which an oxide semiconductor film is formed to a thickness of 40 nm. A silicon oxynitride film is formed on the substrate with a thickness of 150 nm, and an oxide conductive film is formed on the silicon oxynitride film with a thickness of 10 nm. 0 nm thick, and a silicon nitride film is formed on top of it to a thickness of 100 nm. In FIG. 14C, the horizontal axis represents the manufacturing process, and the vertical axis represents the resistance of the oxide semiconductor film. The manufacturing method is shown below.

[0367] First, an oxide semiconductor film is formed on a substrate (step A). The conditions were the same as those of Samples 365 to 367. After Step A, the resistance value of the oxide semiconductor film was Measure.

[0368] Next, a silicon oxynitride film is formed on the oxide semiconductor film (Step B). The film was formed by plasma CVD at a substrate temperature of 350°C. SiH4 = 20sccm, N2O = 3000sccm. The deposition pressure is 200Pa. The film formation power is 100 W. After this step B, the resistance of the oxide semiconductor film is measured.

[0369] Next, a heat treatment is performed in a nitrogen atmosphere at a temperature of 350°C (step C). After this step C, the oxide The resistance of the semiconductor film is measured.

[0370] Next, oxygen plasma treatment is performed at a substrate temperature of 350° C. (Step D). The conditions are as follows: oxygen is introduced into the chamber at a flow rate of 3000 sccm, and the pressure is set to 40 Pa. A 3000W RF power was supplied between the parallel plate electrodes installed in the plasma CVD device. After step D, the resistance of the oxide semiconductor film is measured.

[0371] Next, an oxide conductive film is formed (step E). The conditions for forming the oxide conductive film are the same as those for sample 365. The conditions are the same as those for Sample 367. After this step E, the resistance of the oxide semiconductor film is measured.

[0372] Next, a silicon nitride film is formed (step F). The conditions for forming the silicon nitride film are the same as those for sample 36. The conditions are the same as those of Samples 5 to 367. After this step F, the resistance of the oxide semiconductor film is measured. .

[0373] Next, a heat treatment is performed in a nitrogen atmosphere at a temperature of 250° C. (Step G1). The resistance of the nitride semiconductor film was measured. Another sample was heated to 350°C instead of 250°C. After this step G2, the resistance of the oxide semiconductor film was measured. Measure.

[0374] In FIG. 14C, the resistance values ​​of the oxide semiconductor films after steps A to G1 and G2 are As shown, although the resistance value of the oxide semiconductor film decreases in the silicon oxynitride film formation process, It can be seen that the efficiency is significantly improved by baking the silicon nitride film at 350°C after deposition. After the step A and the step G2, the resistance value of the oxide semiconductor film is measured by the resistance measuring device. is 4.0 x 10 7It was larger than Ω.

[0375] From this, it is believed that heat treatment at 350°C after silicon nitride film formation promotes peroxygenation. This promotion of hyperoxygenation is shown in Figure 14 (A) and (B), By IMS 18 The concentration of O has also been explained.

[0376] Oxygen plasma treatment after the formation of the silicon oxynitride film and 350°C treatment after the formation of the silicon nitride film When the heat treatment at 350°C was used in combination with the heat treatment at 350°C, the silicon oxynitride film was The transistor 100 manufactured using the above method was fabricated using silicon oxynitride at a substrate temperature of 350° C. Then, the substrate temperature is raised to 220° C. and a silicon oxynitride film is formed to form an insulating film 11 The reliability of the transistor 100 was equivalent to that of the transistor 100 fabricated using the method described above. The reliability is evaluated by a bias-thermal stress test, and is shown in Example 1 below. vinegar.

[0377] That is, by performing a treatment for supplying a sufficient amount of excess oxygen to the oxide semiconductor film 108, a dense The silicon oxynitride film, which has a small defect density, is used as the insulating film 110 at a substrate temperature of 350° C. This can improve productivity.

[0378] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0379] (Embodiment 6) In this embodiment, an example of a display device including the semiconductor device exemplified in the previous embodiment will be described. This will be explained below with reference to FIGS. 15 to 20.

[0380] 15 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 provided on a substrate 701 and a source driver 703 provided on the first substrate 701 are connected to the pixel portion 702. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, a sealant 712 arranged to surround the gate driver circuit section 704 and the gate driver circuit section 706; and a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 are sealed. Although not shown in FIG. 15, a display element is provided between the first substrate 701 and the second substrate 705. can be done.

[0381] In addition, the display device 700 has an area surrounded by a sealing material 712 on the first substrate 701. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are arranged in a region different from the pixel section 702. The circuit section 706 and the FPC terminal section 708 (FPC: Flexible Printed Circuit) electrically connected to each other. In addition, the FPC terminal portion 708 is provided with The FPC 716 is connected to the pixel section 702 and the source driver circuit Various signals are supplied to the pixel section 704 and the gate driver circuit section 706. 02, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section 7 08 are connected to signal lines 710. Various signals are supplied by the FPC 716. 7. The pixel section 702, the source driver circuit section 704, the gate driver circuit section 706, and the like are connected to each other via a signal line 710. The power supply is provided to a driver circuit portion 706 and an FPC terminal portion 708.

[0382] The display device 700 may be provided with a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example is shown in which the element portion 702 is formed on the same first substrate 701, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, a single crystal A driving circuit substrate formed of a semiconductor film or a polycrystalline semiconductor film is formed on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. It can be used.

[0383] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706. The driver circuit section 706 includes a plurality of transistors.

[0384] The display device 700 can also include various elements. For example, electroluminescence (EL) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (which emit light according to the current transistor), electron emission element, liquid crystal element, electronic ink element, electrophoresis element, electro Wetting elements, plasma display panels (PDPs), MEMS (microelectromechanical systems) Electro-mechanical systems) displays (e.g., grating light valves) (GLV), Digital Micromirror Device (DMD), Digital MicroShutter (DMS) element, interferometric modulation (IMOD) element, etc. etc.), piezoelectric ceramic displays, etc.

[0385] An example of a display device using an EL element is an EL display. An example of a display device using an emission element is a field emission display (FED) ) or SED type flat panel display (SED: Surface-conduction Electron-emitter Displays (ELDs) are also available. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). LCD, reflective LCD, direct-view LCD, projection LCD An example of a display device using an electronic ink element or an electrophoretic element is an electrophoretic display. Semi-transmissive LCD displays and reflective LCD displays are also available. In this case, a part or all of the pixel electrode is designed to function as a reflective electrode. For example, a part or all of the pixel electrodes may be made of aluminum, silver, etc. Furthermore, in this case, a memory circuit such as an SRAM should be placed under the reflective electrode. This can further reduce power consumption.

[0386] The display method of the display device 700 may be a progressive method, an interlace method, etc. In addition, RG can be used as a color element controlled by pixels when displaying colors. For example, the R pixel and the G pixel are not limited to the three colors R, G, and B (R represents red, G represents green, and B represents blue). It may be composed of four pixels: a blue pixel, a blue pixel, and a white pixel. As shown above, two colors of RGB compose one color element, and two different colors are created depending on the color element. Alternatively, you can select one or more colors such as yellow, cyan, magenta, etc. for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, but also to monochrome display devices. The present invention can also be applied to display devices such as those shown in the accompanying drawings.

[0387] In addition, white light is emitted from the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) In order to display full color on the display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) Yellow (Y) and other colors can be used in combination as appropriate. The color reproducibility can be improved compared to when no color layer is used. By arranging a region having a colored layer and a region not having a colored layer, the region not having a colored layer can be The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30%. When using elements to display full color, R, G, B, Y, and W are each represented by a light emitting element. By using a self-luminous element, it is possible to make the light emitted from an element that is not a colored layer. However, power consumption may be further reduced.

[0388] In addition, as a colorization method, a part of the light emitted from the above-mentioned white light is passed through a color filter. In addition to the color filter method, which converts red, green, and blue A method that uses each of the three colors (three-color method), or a method that uses part of the blue light to emit red or green light A color conversion method (color conversion method, quantum dot method) may also be applied.

[0389] In this embodiment, a structure in which a liquid crystal element and an EL element are used as a display element will be described. The following description will be given with reference to Figures 16 to 18. Note that Figures 16 and 17 are based on the dashed line shown in Figure 15. This is a cross-sectional view of the QR, and the display element is a liquid crystal element. 8 is a cross-sectional view taken along the dashed line QR in FIG. 15, and is a diagram showing a display device using an EL element. This is the configuration.

[0390] First, the common parts shown in FIGS. 16 to 18 will be explained, and then the different parts will be explained. The following is an explanation.

[0391] <3-1. Explanation of common parts of display devices> The display device 700 shown in FIGS. 16 to 18 includes a wiring portion 711, a pixel portion 702, and It includes a source driver circuit section 704 , an FPC terminal section 708 , and a sealing material 712 . The lead wiring portion 711 has a signal line 710. The pixel portion 702 has a transistor. The source driver circuit portion 704 includes a transistor 750 and a capacitor 790. The inverter has a transistor 752.

[0392] The transistor 750 and the transistor 752 are the same as the transistor 1 shown in FIGS. 00B. Note that the configuration of the transistor 750 and the transistor 752 is In this regard, other transistors shown in the above embodiment may be used.

[0393] The transistor used in this embodiment is a highly purified oxide semiconductor in which the formation of oxygen vacancies is suppressed. The transistor has a conductive film. The off-state current of the transistor can be reduced. This allows for a longer retention time for electrical signals such as This allows the frequency of refresh operations to be reduced, resulting in reduced power consumption. This has the effect of suppressing the above.

[0394] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed driving is used in a liquid crystal display. By using this in a device, the switching transistor in the pixel section and the driver used in the driver circuit section can be In other words, a driver transistor can be formed on the same substrate as a separate driver circuit. Since it is not necessary to use a semiconductor device formed from a silicon wafer or the like, The number of parts can be reduced. Also, in the pixel section, transistors that can be driven at high speed are used. By using the star, high quality images can be provided.

[0395] The capacitor 790 is a conductive film which functions as a first gate electrode of the transistor 750. The lower electrode is formed through a process of processing the same conductive film as that of the transistor 750. A conductive film that functions as a source electrode and a drain electrode, or a second gate electrode and an upper electrode formed through a process of processing the same conductive film. In addition, a first gate insulating film of the transistor 750 is provided between the lower electrode and the upper electrode. an insulating film formed through a process of forming the same insulating film as the insulating film that functions as the transistor; The insulating film that functions as the protective insulating film on the transistor 750 is formed through a process. That is, the capacitor 790 has a dielectric film formed between a pair of electrodes. It has a laminated structure in which an insulating film that functions as a film is sandwiched.

[0396] 16 to 18, a transistor 750, a transistor 752, and a capacitor A planarization insulating film 770 is provided on the element 790 .

[0397] 16 to 18, the transistor 750 and the source The transistor 752 of the driver circuit section 704 has the same structure as the transistor 752. However, the present invention is not limited to this. For example, the pixel portion 702 and the source driver The driver circuit section 704 may use transistors different from those in the pixel section 70. 2 uses a top-gate transistor, and the source driver circuit section 704 uses a bottom-gate transistor. or a bottom-gate transistor is used in the pixel portion 702. and a configuration in which a top-gate transistor is used in the source driver circuit portion 704. The source driver circuit section 704 may be referred to as a gate driver circuit section. You can change it.

[0398] The signal line 710 serves as the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed through the same process as the conductive film that functions as the signal line 710. When materials containing this material are used, there is little signal delay caused by wiring resistance, making it possible to display on a large screen. This becomes:

[0399] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed through the same process as the conductive film that functions as the inner electrode. The terminals of the FPC 716 are electrically connected via an anisotropic conductive film 780 .

[0400] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. .

[0401] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The body 778 is a columnar spacer obtained by selectively etching the insulating film. The distance (cell gap) between the first substrate 701 and the second substrate 705 is controlled by a It should be noted that the structures 778 may be spherical spacers.

[0402] On the second substrate 705 side, a light-shielding film 738 that functions as a black matrix and a A colored film 736 that functions as a color filter, a light-shielding film 738, and an insulating film that contacts the colored film 736. A veneer 734 is provided.

[0403] <3-2. Configuration example of a display device using a liquid crystal element> The display device 700 shown in FIG. 16 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 7 The conductive film 774 is disposed on the second substrate 705 side. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 changes depending on the voltage applied to the conductive film 774. Therefore, the transmission or non-transmission of light is controlled, and an image can be displayed.

[0404] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is electrically connected to a functional conductive film. This functions as a pixel electrode, that is, one electrode of the display element.

[0405] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. As a conductive film that transmits visible light, for example, For example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum, Alternatively, a material containing silver may be used.

[0406] When a conductive film that is reflective to visible light is used as the conductive film 772, the display device 700 In addition, a conductive film that transmits visible light is used as the conductive film 772. When used, the display device 700 becomes a transmissive liquid crystal display device.

[0407] In addition, by changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. 17. The display device 700 shown in FIG. This is an example of a configuration that uses a horizontal electric field method (e.g., FFS mode) as the driving method. In the structure shown in FIG. 1, an insulating film 773 is provided over a conductive film 772, and a conductive film 7 In this case, the conductive film 774 is provided as a common electrode. and an electric field generated between the conductive films 772 and 774 through the insulating film 773. The alignment state of the liquid crystal layer 776 can be controlled by this.

[0408] Although not shown in FIGS. 16 and 17, either the conductive film 772 or the conductive film 774 An alignment film is provided on one or both of the liquid crystal layers 776 on the side in contact with the liquid crystal layer 776. Although not shown in FIGS. 16 and 17, a polarizing member, a phase difference member, an anti-reflection member, etc. Optical members (optical substrates) such as stoppers may be provided as appropriate. Circularly polarized light from a differential substrate may also be used. may also be used.

[0409] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and high molecular weight liquid crystals are used. Polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, liquid crystal materials can be in a cholesteric phase, a smectic phase, a cubic phase, a chiral phase, etc. It shows the nematic phase, isotropic phase, etc.

[0410] When the in-plane switching system is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the crystalline phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed Since the liquid crystal display has a short wavelength and is optically isotropic, no alignment treatment is required. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This can prevent the liquid crystal display device from being damaged or broken during the manufacturing process. Furthermore, liquid crystal materials that exhibit a blue phase have little viewing angle dependency.

[0411] When a liquid crystal element is used as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fring e Field Switching) mode, ASM (Axially Symmetry ric aligned Micro-cell) mode, OCB (Optical C compensated birefringence mode, FLC (Ferroel etric Liquid Crystal) mode, AFLC (AntiFerro You can use modes such as electric Liquid Crystal.

[0412] Furthermore, normally black type liquid crystal display devices, for example, those employing vertical alignment (VA) mode The liquid crystal display device may be a transmission type. For example, the MVA (Multidomain Vertical Alignment) model mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0413] <3-3. Display devices using light-emitting elements> The display device 700 shown in FIG. 18 includes a light-emitting element 782. The light-emitting element 782 is formed by a conductive film 7 18 includes a light-emitting element 72, an EL layer 786, and a conductive film 788. The EL layer 786 of the element 782 emits light, thereby displaying an image. The EL layer 786 includes an organic compound or an inorganic compound such as quantum dots.

[0414] Materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. In addition, materials that can be used for quantum dots include colloidal quantum dot materials. materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, etc. Also, elements in groups 12 and 16, 13 and 15, or 14 and 16 Materials containing the group may also be used. Lead (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb ), gallium (Ga), arsenic (As), aluminum (Al), etc. A matte material may also be used.

[0415] The organic compounds and inorganic compounds described above can be prepared by, for example, deposition methods (including vacuum deposition methods). ), droplet ejection method (also called inkjet method), coating method, gravure printing method, etc. The EL layer 786 can be formed using a low molecular weight material, a medium molecular weight material (oligosaccharides), or the like. The polymer may comprise a polymeric material, such as a dimer or dendrimer.

[0416] Here, a method for forming the EL layer 786 by droplet discharge will be described with reference to FIG. 21A to 21D are cross-sectional views illustrating a method for manufacturing the EL layer 786. do.

[0417] First, a conductive film 772 is formed over a planarization insulating film 770. An insulating film 730 is formed on the insulating film 730 (see FIG. 21A).

[0418] Next, droplets are discharged from a droplet discharge device 783 onto the exposed portions of the conductive film 772, which are openings in the insulating film 730. The droplets 784 are ejected to form a layer 785 containing the composition. The conductive film 772 is attached to the conductive film 772 (see FIG. 21B).

[0419] The step of discharging the droplets 784 may be performed under reduced pressure.

[0420] Next, the solvent is removed from the layer 785 containing the composition, and the layer is solidified to form an EL layer 786. (See FIG. 21(C)).

[0421] The solvent may be removed by a drying step or a heating step.

[0422] Next, a conductive film 788 is formed on the EL layer 786 to form a light-emitting element 782 (FIG. 21(D) )reference).

[0423] In this way, when the EL layer 786 is formed by the droplet discharge method, the composition can be selectively discharged. This reduces material waste. Since no additional steps are required, the process can be simplified and costs can be reduced.

[0424] The droplet discharge method described above is a method using a nozzle having a discharge port for discharging the composition, or one or more This is a general term for anything that has a means for ejecting droplets, such as a head with multiple nozzles.

[0425] Next, a droplet discharge device used in the droplet discharge method will be described with reference to FIG. FIG. 14 is a conceptual diagram illustrating a droplet ejection device 1400.

[0426] The droplet discharge device 1400 has a droplet discharge means 1403. has a head 1405 and a head 1412.

[0427] The head 1405 and the head 1412 are connected to a control means 1407, which controls the computer. By controlling the controller 1410, it is possible to draw in a pre-programmed pattern. Cut.

[0428] The timing of drawing may be, for example, the timing of the marker 14 formed on the substrate 1402. Alternatively, the reference point may be determined based on the outer edge of the substrate 1402. Here, the marker 1411 is detected by the imaging means 1404, and the image processing means 14 The signal converted to a digital signal by 09 is recognized by computer 1410 and a control signal is generated. and sends it to the control means 1407.

[0429] The imaging means 1404 may be a charge coupled device (CCD) or a complementary metal oxide semiconductor (C An image sensor using a MOS (metal oxide semiconductor) can be used. The information of the pattern to be formed is stored in the storage medium 1408. Based on this, a control signal is sent to the control means 1407, and the individual heads 14 of the droplet ejection means 1403 are The material to be discharged is supplied from the material supply source 14. 13, a material supply source 1414 is connected to head 1405 and head 1412 through piping, respectively. Supplied.

[0430] The inside of the head 1405 is a space filled with a liquid material as shown by the dotted line 1406, and a discharge space. Although not shown, the head 1412 and the head 14 The head 1405 and head 1412 have the same internal structure as the head 1405. The nozzles of the head 1405 and head 1412 are different sizes. By providing the heads in different sizes, different materials can be printed at the same time with different widths. It is possible to discharge and draw multiple types of luminescent materials, etc., and when drawing over a wide area, In order to improve throughput, the same material is ejected from multiple nozzles at the same time to create a pattern. When a large substrate is used, the head 1405 and the head 1412 move over the substrate as shown in FIG. You can freely scan in the X, Y, and Z directions shown in the figure and freely set the drawing area. This allows the same pattern to be drawn multiple times on a single substrate.

[0431] The step of discharging the composition may be carried out under reduced pressure. After the composition is discharged, one or both of the steps of drying and baking are carried out. The steps of drying and baking are Both processes involve heat treatment, but the purpose, temperature and time are different. The firing process is carried out under normal pressure or reduced pressure by laser light irradiation, instantaneous thermal annealing, or heating furnace. The timing and number of times of the heat treatment are not particularly limited. In order to perform the drying and baking processes well, the temperature at that time must be adjusted depending on the material and composition of the substrate. It depends on the nature of the thing.

[0432] As described above, the EL layer 786 can be manufactured using a droplet discharge apparatus.

[0433] The display device 700 shown in FIG. 18 will now be described.

[0434] In the display device 700 shown in FIG. 18, an insulating film 73 is formed over a planarization insulating film 770 and a conductive film 772. The insulating film 730 covers part of the conductive film 772. Therefore, the conductive film 788 has a light-transmitting property, and the EL layer 78 In this embodiment, the top emission structure is For example, a bottom electrode that emits light to the conductive film 772 side is used. An emission structure or a dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 is also available. It can also be applied to cushion structures.

[0435] A colored film 736 is provided at a position overlapping the light-emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided in the position, the lead wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, a colored film The configuration may be such that 736 is not provided.

[0436] <3-4. Example of a configuration in which an input / output device is provided in a display device> Furthermore, the display device 700 shown in FIGS. 17 and 18 may be provided with an input / output device. An example of the device is a touch panel.

[0437] 19 and 18 show a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 17. FIG. 20 shows a configuration in which a touch panel 791 is provided on a display device 700.

[0438] FIG. 19 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. 20 is a cross-sectional view of a configuration in which a touch panel 791 is provided on the display device 700 shown in FIG. do.

[0439] First, the touch panel 791 shown in FIGS. 19 and 20 will be described below.

[0440] The touch panel 791 shown in FIGS. 19 and 20 is provided between the substrate 705 and the colored film 736. The touch panel 791 is a so-called in-cell type touch panel. It may be formed on the substrate 705 side before forming the insulating film 704.

[0441] The touch panel 791 includes a light-shielding film 738, an insulating film 792, an electrode 793, and an electrode 794. 94, an insulating film 795, an electrode 796, and an insulating film 797. When a detection object such as an iron comes close to the electrode 793, the mutual capacitance between the electrode 794 changes. can be detected.

[0442] 19 and 20, an electrode 793 and an electrode The electrode 796 is connected to the insulating film 795 through an opening. 19 and 20, the electrode 794 is electrically connected to the two electrodes 793 that sandwich the electrode 794. 20 shows an example of a configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702. However, the present invention is not limited to this, and may be formed in the source driver circuit section 704, for example.

[0443] The electrodes 793 and 794 are provided in a region overlapping with the light-shielding film 738. As shown, the electrode 793 is preferably provided so as not to overlap with the light emitting element 775 . As shown in FIG. 20, the electrode 793 is provided so as not to overlap with the liquid crystal element 782. In other words, the electrode 793 overlaps with the light-emitting element 782 and the liquid crystal element 775. In other words, the electrode 793 has a mesh shape. By doing so, the electrode 793 can be configured not to block light emitted from the light-emitting element 782. Alternatively, the electrode 793 may have a structure that does not block light that passes through the liquid crystal element 775. Therefore, the reduction in brightness due to the placement of the touch panel 791 is extremely small. Therefore, a display device with high visibility and reduced power consumption can be realized. 794 can be configured in a similar manner.

[0444] In addition, since the electrodes 793 and 794 do not overlap with the light-emitting element 782, The electrode 794 can be made of a metal material with low transmittance for visible light. Since the electrodes 793 and 794 do not overlap with the liquid crystal element 775, A metal material with low transmittance of visible light can be used.

[0445] Therefore, compared with electrodes made of oxide materials with high visible light transmittance, This makes it possible to lower the resistance of electrode 794, improving the sensor sensitivity of the touch panel. This can be done.

[0446] For example, the electrodes 793, 794, and 796 may be made of conductive nanowires. The average diameter of the nowire is 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. The size of the nanowires may be set to 5 nm or more and more preferably 25 nm or less. The wires are made of metal nanowires such as Ag nanowires, Cu nanowires, or Al nanowires. For example, electrodes 793 and 794 may be used. When Ag nanowires are used for either one or all of 4, 796, Light transmittance of 89% or more, sheet resistance of 40Ω / square or more, 100Ω / square or more e or less.

[0447] 19 and 20 show examples of the configuration of an in-cell type touch panel. For example, a so-called on-cell type touch panel formed on the display device 700 may be used. and a so-called out-cell type touch panel that is attached to the display device 700. You may do so.

[0448] In this way, the display device according to one embodiment of the present invention can be used in combination with various types of touch panels. You can be there.

[0449] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0450] (Embodiment 7) In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. Explanations will be given.

[0451] <4. Circuit configuration of display device> The display device shown in FIG. 23A includes a region having pixels of a display element (hereinafter referred to as a pixel portion 502). ) and a circuit section (hereinafter referred to as a circuit section) that is disposed outside the pixel section 502 and has a circuit for driving the pixel. a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 506) ) and a terminal portion 507. Note that the protection circuit 506 may not be provided. Good too.

[0452] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. If a part or the whole of the pixel portion 502 is not formed on the same substrate, the driver circuit A part or all of the unit 504 may be a COG or TAB (Tape Automated Board). This can be implemented by

[0453] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). A driving circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements The gate driver 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel. 04a), for supplying signals (data signals) for driving the display elements of the pixels. The pixel driver 504 includes a driving circuit such as a circuit (hereinafter referred to as a source driver 504b).

[0454] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via the slave unit 507, and a signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc. The gate driver 504a outputs a pulse signal to a wiring to which a scanning signal is applied (hereinafter , and the scanning lines GL_1 to GL_X). A plurality of gate drivers 504a are provided, and the scanning lines GL_1 to GL_3 are driven by the plurality of gate drivers 504a. Alternatively, the gate driver 504a may control the GL_X separately. However, the gate driver 504 has a function of supplying a may also supply another signal.

[0455] The source driver 504b includes a shift register and the like. Through the slave unit 507, in addition to the signal for driving the shift register, the source of the data signal is also output. The source driver 504b outputs a signal (image signal) to the pixel circuit 504b based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 504b. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of the data signal. The data lines DL_1 to DL_Y are connected to the data lines DL_2 through DL_Y. Alternatively, the source driver 504b may have a function to supply an initialization signal. However, the present invention is not limited to this, and the source driver 504b may supply other signals. It is Noh.

[0456] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a plurality of analog switches to generate a signal. The image signal can be time-divided and output as a data signal. The source driver 504b may be configured as follows.

[0457] Each of the plurality of pixel circuits 501 is supplied with a scanning signal via one of a plurality of scanning lines GL. A pulse signal is input to the data line DL, and a data signal is given to the data line DL through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 04a controls the writing and holding of data of the data signal. For example, The pixel circuit 501 is connected to a gate driver 506 via a scanning line GL_m (m is a natural number equal to or less than X). A pulse signal is input from 04a, and the data line DL_n (n A data signal is input from the source driver 504b via the line 504c (where Y is a natural number equal to or less than Y).

[0458] The protection circuit 506 shown in FIG. 23A is, for example, a gate driver 504a and a pixel circuit 50 1. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The protection circuit 504b is connected to the data line DL, which is the wiring between the protection circuit 504b and the pixel circuit 501. The circuit 506 can be connected to a wiring between the gate driver 504a and the terminal section 507. Alternatively, the protection circuit 506 may be provided on the wiring between the source driver 504b and the terminal section 507. The terminal section 507 can be connected to the display device via an external circuit. This refers to the part where terminals for inputting control signals and image signals are provided.

[0459] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit 506 protects the wiring. It is a circuit that connects a line to another wiring.

[0460] As shown in FIG. 23A, a pixel section 502 and a driver circuit section 504 are provided with a protection circuit 506. By providing a This can improve the resistance of the display device to overcurrents caused by electrical discharges, etc. However, the configuration of the protection circuit 506 is not limited to this. For example, the protection circuit 506 may be provided in the gate driver 504a. A configuration in which a protection circuit 506 is connected, or a configuration in which a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal section 507. You can also do this.

[0461] In FIG. 23(A), the gate driver 504a and the source driver 504b However, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is separately formed. A substrate (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted. It may also be configured as follows.

[0462] Furthermore, the plurality of pixel circuits 501 shown in FIG. 23(A) may have the configuration shown in FIG. 23(B), for example. It is possible.

[0463] The pixel circuit 501 shown in FIG. 23B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiments. It can be used.

[0464] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential ( A common potential may be applied to the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row. One of the poles may be given a different potential.

[0465] For example, the display device including the liquid crystal element 570 can be driven in TN mode, STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned Mix cro-cell mode, OCB (Optically Compensated B refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. Crystal) mode, MVA mode, PVA (Patterned Ver Artificial Alignment) mode, IPS mode, FFS mode, or TBA( Transverse Bend Alignment mode may also be used. In addition to the above-mentioned driving method, the display device can also be driven by an ECB (Electric Carbide) drive. lly Controlled Birefringence mode, PDLC (Po lymer Dispersed Liquid Crystal) mode, PNLC( Polymer Network Liquid Crystal mode, guest host However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. can be used.

[0466] In the pixel circuit 501 in the mth row and the nth column, the source electrode or the drain electrode of the transistor 550 One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines GL _m. The transistor 550 can be turned on or off. This has the function of controlling the writing of data of the data signal.

[0467] One of the pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, referred to as a potential supply line VL). and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0468] For example, in a display device having the pixel circuit 501 shown in FIG. 23(B), The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG. 50 is turned on to write the data of the data signal.

[0469] The pixel circuit 501 in which the data has been written is maintained by turning off the transistor 550. By repeating this process for each row, an image can be displayed.

[0470] Furthermore, the plurality of pixel circuits 501 shown in FIG. 23(A) may have the configuration shown in FIG. 23(C), for example. It is possible.

[0471] The pixel circuit 501 shown in FIG. 23C includes transistors 552 and 554 and a capacitor element The transistor 552 and the transistor 554 are connected to the light-emitting element 562 and the light-emitting element 572. The transistor described in the above embodiment can be applied to either one or both of the transistors.

[0472] One of the source electrode and the drain electrode of the transistor 552 is connected to a transistor Further, the transistor 55 is electrically connected to a line (hereinafter referred to as a data line DL_n). The gate electrode 2 is electrically connected to the wiring to which the gate signal is given (hereinafter referred to as the scanning line GL_m). are connected to the network.

[0473] The transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of

[0474] One of the pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, referred to as a potential supply line VL_ a) and the other is electrically connected to the source electrode and drain electrode of the transistor 552. It is electrically connected to the other of the electrodes.

[0475] The capacitor 562 functions as a storage capacitor for holding written data.

[0476] One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is connected to the source of transistor 552. The gate electrode is electrically connected to the other of the source electrode and the drain electrode.

[0477] One of the anode and the cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b. The other end is electrically connected to the other of the source electrode and drain electrode of the transistor 554. can be.

[0478] The light emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this, and An inorganic EL element made of an inorganic material may also be used.

[0479] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0480] In a display device having the pixel circuit 501 of FIG. 23(C), for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written into the ON state.

[0481] The pixel circuit 501 in which the data is written is maintained by turning off the transistor 552. Furthermore, the transistor 554 is turned on and off in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 By repeating this process for each row, an image can be displayed.

[0482] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0483] (Embodiment 8) In this embodiment, one of the circuit configurations to which the transistors described in the above embodiments can be applied is An example will be described with reference to FIGS.

[0484] In this embodiment, the transistor including the oxide semiconductor described in the above embodiment is In the following description, the OS transistor will be referred to as an OS transistor.

[0485] <5. Inverter circuit configuration example> FIG. 24(A) shows a circuit that can be applied to a shift register, a buffer, etc. included in a driver circuit. 8 shows a circuit diagram of an inverter 800. The inverter 800 changes the logic of a signal applied to an input terminal IN. The inverter 800 outputs the inverted signal to the output terminal OUT. The signal S BGis a signal that can switch the electrical properties of an OS transistor. is.

[0486] FIG. 24B shows an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be fabricated using only transistors, it is called CMOS (Complementary Metal Oxide Semiconductor) Metal Oxide Semiconductor inverter (CMOS inverter) It can be produced at a lower cost than when producing a conventional ferrite core.

[0487] The inverter 800 having the OS transistor is a C inverter made of Si transistors. The inverter 800 can be placed on a CMOS circuit. Therefore, it is possible to suppress an increase in the circuit area due to the addition of the inverter 800.

[0488] The OS transistors 810 and 820 have a first gate that functions as a front gate and a back gate. The second gate acts as a gate and the first gate acts as either a source or a drain. The semiconductor device has a terminal and a second terminal that functions as the other of the source or drain.

[0489] The first gate of the OS transistor 810 is connected to the second terminal of the OS transistor 810. The second gate of the OS transistor 810 is connected to the signal S BG It is connected to the wiring that supplies A first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. The second terminal of the transistor 810 is connected to the output terminal OUT.

[0490] A first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. Connected to the wiring.

[0491] FIG. 24C is a timing chart for explaining the operation of the inverter 800. In FIG. In the timing chart of Figure 24(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are signal waveform, signal S BG and the change in the threshold voltage of the OS transistor 810. This shows the following.

[0492] signal S BG to the second gate of the OS transistor 810. The threshold voltage of 10 can be controlled.

[0493] signal S BG is the voltage V for shifting the threshold voltage negatively. BG_A , threshold voltage Voltage V for positive shift of pressure BG_B The second gate has a voltage V BG_A of By providing this, the OS transistor 810 has a threshold voltage V TH_A shift it negatively to Also, the second gate can be connected to a voltage V BG_B By providing 810 is the threshold voltage V TH_B can be shifted positively to

[0494] To visualize the above explanation, FIG. 25(A) shows one of the electrical characteristics of a transistor. The Id-Vg curve is shown.

[0495] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A Noyo By increasing the value as shown in FIG. 25(A), the curve is shifted to the dashed line 840. The electrical characteristics of the OS transistor 810 can be determined by applying a voltage to the second gate. Pressure V BG_B By making it smaller, the curve represented by the solid line 841 in Figure 25(A) As shown in FIG. 25A, the OS transistor 810 can shift the signal No. S BG voltage V BG_A Or voltage V BG_B By switching like this, The low voltage can be shifted either positively or negatively.

[0496] The threshold voltage is V TH_B By shifting the voltage to the positive side, the OS transistor 810 can be made to be in a state where it is difficult for current to flow. This state is shown in FIG. 25(B). Shown in a simplified form.

[0497] As shown in FIG. 25B, the current I B Extremely small Therefore, when the signal applied to the input terminal IN is high level, the OS transistor When the inverter 820 is in the ON state (ON), it can rapidly decrease the voltage at the output terminal OUT. can.

[0498] As shown in FIG. 25B, a state in which a current is difficult to flow through the OS transistor 810 Therefore, the signal at the output terminal in the timing chart shown in FIG. 24(C) can be The signal waveform 831 can be changed sharply. This reduces the through current that flows between the wiring that supplies the signal, allowing for low power consumption. It is possible to perform the work.

[0499] Also, the threshold voltage is V TH_A By shifting it negatively, the OS The transistor 810 can be brought into a state in which current can easily flow. As shown in Figure 25(C), the current I A Less Both current I B Therefore, the signal applied to the input terminal IN can be When the OS transistor 820 is in the OFF state at the negative level, the voltage of the output terminal OUT As shown in FIG. 25C, the OS transistor 8 24(C) is achieved. This allows the signal waveform 832 at the output terminal in the timing chart to be changed sharply.

[0500] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of the star 820 is switched, that is, before time T1 or T2. For example, as shown in FIG. 24(C), when the signal applied to the input terminal IN is at a high level, Before the time T1 when the transistor switches to the threshold voltage V TH_A From the threshold voltage V TH_ B It is preferable to change the threshold voltage of the OS transistor 810. As shown in (C), at time T2 the signal applied to the input terminal IN switches to low level. before the threshold voltage V TH_B to threshold voltage V TH_AOS Transistor 8 It is preferable to switch the threshold voltage of 10.

[0501] In the timing chart of FIG. 24(C), the signal S BG However, other configurations may be used. For example, The voltage for controlling the voltage is applied to the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. As shown in A).

[0502] 26A, in addition to the circuit configuration shown in FIG. 24B, an OS transistor 850 is The first terminal of OS transistor 850 is connected to the second gate of OS transistor 810. The second terminal of the OS transistor 850 is connected to the voltage V BG_B (or voltage V BG_A The first gate of the OS transistor 850 is connected to a wiring that supplies a signal S F The second gate of the OS transistor 850 is connected to a line that supplies a voltage V BG_ B (or voltage V BG_A ) is connected to the wiring that provides

[0503] The operation of FIG. 26(A) will be described using the timing chart of FIG. 26(B).

[0504] The voltage for controlling the threshold voltage of the OS transistor 810 is applied to the input terminal IN. Before time T3 when the signal switches to a high level, the second gate of OS transistor 810 The signal S F is set to a high level to turn on the OS transistor 850. Let node NBG Voltage V to control the threshold voltage BG_B Give.

[0505] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current. , once node N BG The voltage V BG_B Therefore, O The second gate of the S transistor 850 is connected to the voltage V BG_B The number of actions to give electricity is reduced. Pressure V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0506] In the circuit configurations of FIGS. 24B and 26A, the second gate of the OS transistor 810 Although the configuration in which the voltage applied to the port is controlled externally has been shown, a different configuration can be used. For example, a voltage for controlling the threshold voltage may be set as a signal to be applied to the input terminal IN. Alternatively, the second gate of the OS transistor 810 may be provided with a second gate electrode of the OS transistor 810. An example of a circuit configuration that can realize the above is shown in FIG.

[0507] In Fig. 27(A), the input terminal IN and the OS transformer are connected in the circuit configuration shown in Fig. 24(B). A CMOS inverter 860 is provided between the second gate of the transistor 810 and the CMOS inverter 860. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The terminal is connected to the second gate of OS transistor 810.

[0508] The operation of FIG. 27(A) will be explained using the timing chart of FIG. 27(B). In the timing chart of 27(B), the signal waveform of the input terminal IN and the signal of the output terminal OUT are 8B, the output waveform IN_B of the CMOS inverter 860, and the output waveform IN_B of the OS transistor 810. The change in threshold voltage is shown.

[0509] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is 25(a) can be used as a signal to control the threshold voltage of the resistor 810. As described in FIGS. 25A to 25C, the threshold voltage of the OS transistor 810 is controlled. For example, at time T4 in FIG. 27(B), the signal applied to the input terminal IN is At a high level, the OS transistor 820 is turned on. Therefore, the OS transistor 810 is in a state where it is difficult for current to flow. This allows the voltage at the output terminal OUT to drop sharply.

[0510] Also, at time T5 in FIG. 27(B), the signal applied to the input terminal IN is low level. At this time, the OS transistor 820 is turned off. Therefore, the OS transistor 810 can be made to be in a state where current can easily flow. , the voltage at the output terminal OUT can be increased sharply.

[0511] As described above, in the configuration of this embodiment, in the inverter having the OS transistor, The back gate voltage is switched according to the logic of the signal at the input terminal IN. By configuring the input terminal I The threshold voltage of the OS transistor is controlled by the signal given to N. The UT voltage can be changed sharply. Also, the through current between the wiring that supplies the power supply voltage can be reduced. Therefore, it is possible to reduce power consumption.

[0512] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0513] (Embodiment 9) In this embodiment, the transistor including the oxide semiconductor (O An example of a semiconductor device using a plurality of S transistors in a plurality of circuits is shown in FIGS. 28 to 31. This will be explained using:

[0514] <6. Circuit configuration example of semiconductor device> 28A is a block diagram of a semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has 906.

[0515] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG is simply It is possible to use multiple voltages instead of a single voltage. ORG is input from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage V based on the externally applied voltage V0. The voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without receiving multiple power supply voltages from the unit.

[0516] The circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the 902 is V ORG and voltage V SS (VORG >V SS ) and applied based on For example, the power supply voltage of the circuit 904 is a voltage V POG and voltage V SS (V P OG >V ORG ) is a voltage applied based on the above. For example, the power supply voltage of the circuit 906 is , voltage V ORG and voltage V SS and voltage V NEG (V ORG >V SS >V NEG ) and stamped based on The voltage V SS is equivalent to the ground potential (GND), The number of types of voltages generated by the power supply circuit 901 can be reduced.

[0517] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates a voltage. The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG Therefore, The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage applied from the outside. It is possible.

[0518] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates a voltage. The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG Therefore, The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage provided from the outside. It is possible.

[0519] Figure 28(B) shows the voltage V POG FIG. 28C shows an example of the circuit 904 operating in 10 is an example of a waveform of a signal for operation.

[0520] 28B shows a transistor 911. The signal that can be output is, for example, a voltage V POG and voltage V SS The signal is generated based on the When resistor 911 is in the conducting state, the voltage V POG , and when operating in a non-conducting state, the voltage V SS Voltage V POG As shown in FIG. 28(C), the voltage V ORG Greater than Therefore, the transistor 911 can more reliably connect the source (S) and the drain (D). As a result, the circuit 904 can be a circuit with reduced malfunction. do.

[0521] Figure 28(D) shows the voltage V NEG FIG. 28(E) shows an example of a circuit 906 that operates in the 10 is an example of a waveform of a signal for operation.

[0522] FIG. 28D shows a transistor 912 having a back gate. The signal applied to the gate of the capacitor 912 is, for example, a voltage V ORG and voltage V SS Generated based on This signal is applied to the transistor 912 at a voltage V ORG , non-conducting When operating in this state, the voltage V SS Also, the back gate of the transistor 912 is generated based on The signal applied to the port is voltage V NEG It is generated based on the voltage V NEG is shown in Figure 28(E). As shown, the voltage V SS (GND). The threshold voltage can be controlled to be positively shifted. 912 can be made non-conductive more reliably, and the As a result, the circuit 906 has reduced malfunctions and low power consumption. The circuit can be powered.

[0523] In addition, the voltage V NEG may be directly applied to the back gate of the transistor 912. Alternatively, the voltage V ORG and voltage V NEG Based on this, a voltage is applied to the gate of the transistor 912. and supplying the signal to the back gate of the transistor 912. stomach.

[0524] Also, FIGS. 29(A) and (B) show modified examples of FIGS. 28(D) and (E).

[0525] In the circuit diagram shown in FIG. 29A, a control circuit is provided between the voltage generating circuit 905 and the circuit 906. The transistor 922 whose conduction state can be controlled by the transistor 921 is shown. , an n-channel OS transistor. BG teeth , which is a signal for controlling the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors like transistor 922.

[0526] In the timing chart of FIG. 29(B), the control signal S BG The change in the potential of the transistor The potential state of the back gates of the transistors 912A and 912B is determined by the node N BG Shown by the change in potential Control signal S BG When the voltage at the node N BG is the voltage V NEG Then, the control signal S BG When is low, node N BG is electrically floating. , the off-current is small. Therefore, the node N BG Even if the The applied voltage V NEG can be maintained.

[0527] FIG. 30A shows an example of a circuit configuration applicable to the voltage generating circuit 903 described above. The voltage generating circuit 903 shown in FIG. 30A includes diodes D1 to D5 and a capacitor C The charge pump is a five-stage circuit having C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 directly or via an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS The voltage applied based on voltage, by applying a clock signal CLK, the voltage V ORG to a positive voltage five times greater than The boosted voltage V POG It should be noted that the forward currents of the diodes D1 to D5 are The voltage is set to 0 V. By changing the number of stages in the charge pump, the desired voltage V PO G can be obtained.

[0528] FIG. 30B shows an example of a circuit configuration applicable to the voltage generating circuit 905 described above. The voltage generating circuit 905 shown in FIG. 30B includes diodes D1 to D5 and a capacitor C The charge pump is a four-stage circuit having C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 directly or via an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS The voltage applied based on voltage, the clock signal CLK is applied to the ground, i.e., the voltage V S S to voltage V ORG The voltage V is stepped down to a negative voltage four times that of NEG It is possible to obtain The forward voltage of the diodes D1 to D5 is set to 0 V. By changing NEG can be obtained.

[0529] The circuit configuration of the voltage generating circuit 903 described above is not limited to the configuration of the circuit diagram shown in FIG. For example, modifications of the voltage generating circuit 903 are shown in FIGS. The voltage generating circuit 903 may be modified as shown in FIGS. 31(A) to 31(C). In the circuits 903A to 903C, the voltage applied to each wiring can be changed, or the This can be achieved by changing the layout.

[0530] The voltage generating circuit 903A shown in FIG. 31A includes transistors M1 to M10, a capacitor The clock signal CLK is supplied to the transistors C11 to C14 and the inverter INV1. The voltages are applied to the gates of the transistors M1 to M10 either directly or via an inverter INV1. By applying a clock signal CLK, the voltage V ORG boosted to four times the positive voltage Voltage V POG By changing the number of stages, the desired voltage V POG of The voltage generating circuit 903A shown in FIG. By using an OS transistor as M10, the off-state current can be reduced, and the capacitors C11 to C Therefore, the leakage of the charge held in 14 can be suppressed. ORG to voltage V P OG It is possible to boost the voltage to

[0531] The voltage generating circuit 903B shown in FIG. 31B includes transistors M11 to M14, The clock signal CLK is generated by: The voltage is applied to the gates of the transistors M11 to M14 directly or via an inverter INV2. By applying a clock signal CLK, the voltage V ORG rises to twice the positive voltage The applied voltage V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. Therefore, leakage of the electric charge held in the capacitors C15 and C16 can be suppressed. Pressure V ORG to voltage V POG It is possible to boost the voltage to

[0532] 31C includes an inductor Ind1, a transistor M15, diode D6, and capacitor C17. Transistor M15 is the control The conduction state is controlled by the control signal EN. ORG Rising The applied voltage V POG The voltage generating circuit 903C shown in FIG. Since the voltage is boosted using the inductor Ind1, the voltage is boosted with high conversion efficiency. It is possible.

[0533] As described above, in the configuration of this embodiment, the voltage required for the circuit of the semiconductor device is internally supplied. Therefore, the semiconductor device can reduce the number of power supply voltages that need to be applied externally. can.

[0534] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible.

[0535] (Embodiment 10) In this embodiment, a display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described. This will be explained with reference to FIGS. 32 to 35.

[0536] <7-1. Display module> The display module 7000 shown in FIG. 32 is made up of an upper cover 7001 and a lower cover 7002. In between, touch panel 7004 connected to FPC7003 and touch panel 7005 connected to FPC7005 Display panel 7006, backlight 7007, frame 7009, printed circuit board 7010 , and a battery 7011.

[0537] The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.

[0538] The upper cover 7001 and the lower cover 7002 are connected to the touch panel 7004 and the display panel 7005. The shape and dimensions can be changed appropriately to match the size of 006.

[0539] The touch panel 7004 is a resistive or capacitive touch panel. 7006. In addition, the opposing substrate (sealing substrate) of the display panel 7006 ) can also be equipped with a touch panel function. It is also possible to provide an optical sensor in each pixel of the 06 to create an optical touch panel.

[0540] The backlight 7007 has a light source 7008. In FIG. Although the configuration in which the light source 7008 is disposed on the 7007 has been exemplified, the present invention is not limited to this. For example, a light source 7008 is arranged at the end of a backlight 7007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a panel or the like, the backlight 7007 may not be provided.

[0541] The frame 7009 has a function of protecting the display panel 7006 and also a function of preventing the operation of the printed circuit board 7010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 7009 may also function as a heat sink.

[0542] The printed circuit board 7010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply to the power supply circuit can be an external commercial power supply or Alternatively, the power source may be a separately provided battery 7011. This can be omitted if a commercial power source is used.

[0543] In addition, the display module 7000 includes additional components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided as follows.

[0544] <7-2.Electronic equipment 1> Next, examples of electronic devices are shown in FIGS. 33(A) to 33(E).

[0545] FIG. 33(A) shows the appearance of the camera 8000 with the viewfinder 8100 attached. Figure.

[0546] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button The camera 8000 has a detachable lens 8006 attached thereto. It is being used.

[0547] Here, the camera 8000 is used, and the lens 8006 is removed from the housing 8001 and replaced. However, the lens 8006 and the housing may be integrated.

[0548] The camera 8000 can capture an image by pressing the shutter button 8004. The display unit 8002 also functions as a touch panel. It is also possible to take an image by

[0549] The housing 8001 of the camera 8000 has a mount with electrodes, and a finder 8100 In addition, a strobe device, etc. can be connected.

[0550] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0551] The housing 8101 has a mount that engages with the mount of the camera 8000, The mount can be attached to the camera 8000. and displays on a display unit 8102 an image or the like received from a camera 8000 via the electrode. It is possible.

[0552] The button 8103 functions as a power button. The display of 102 can be switched on and off.

[0553] The display unit 8002 of the camera 8000 and the display unit 8102 of the finder 8100 are The display device according to one embodiment of the present invention can be applied.

[0554] In FIG. 33(A), the camera 8000 and the finder 8100 are treated as separate electronic devices. These are configured to be detachable, but the housing 8001 of the camera 8000 is equipped with a display device. The camera may have a built-in viewfinder.

[0555] FIG. 33B is a diagram showing the appearance of the head mounted display 8200.

[0556] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820 3, a display unit 8204, a cable 8205, etc. The mounting unit 8201 also has a battery It has a built-in Teri 8206.

[0557] A cable 8205 supplies power from a battery 8206 to the main body 8203. 3 is equipped with a wireless receiver and the like, and displays video information such as received image data on a display unit 8204. In addition, the camera installed in the main body 8203 can record the movements of the user's eyeballs and eyelids. The user's viewpoint is input by capturing the user's viewpoint and calculating the coordinates of the user's viewpoint based on that information. It can be used as a force means.

[0558] Furthermore, the wearing section 8201 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8203 detects the current flowing through the electrodes in accordance with the movement of the user's eyeballs, The device may have a function to recognize the user's gaze. By doing so, the attachment unit 8201 may have a function of monitoring the pulse of the user. The sensor may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc. The display unit 8204 may have a function to display the user's biological information. The image displayed on the display unit 8204 can be changed according to the movement of the object. good.

[0559] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0560] 33(C), (D), and (E) are diagrams showing the appearance of the head-mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, and a band. The lens 8302 has a blade-shaped fixture 8304 and a pair of lenses 8305 .

[0561] The user can view the display on the display unit 8302 through the lens 8305. It is preferable to arrange the display portion 8302 in a curved manner. By doing so, the user can feel a high sense of realism. Although the configuration in which one display unit 8302 is provided has been illustrated, the present invention is not limited to this. For example, In this case, one display is provided for each eye of the user. If the configuration is such that the display section is arranged, it will be possible to perform 3D display using parallax. .

[0562] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. A display device including a semiconductor device of one embodiment has extremely high definition, and therefore, as shown in FIG. Even if the image is enlarged using the lens 8305, the pixels are not visible to the user, and the image is more Highly realistic images can be displayed.

[0563] <7-3.Electronic equipment 2> Next, an example of an electronic device different from the electronic devices shown in FIGS. 33(A) to 33(E) will be described with reference to FIG. Shown in Figures 34(A) to 34(G).

[0564] The electronic devices shown in FIGS. 34A to 34G include a housing 9000, a display portion 9001, a speaker 9002, and a touch panel 9003. 9003, operation keys 9005 (including power switch or operation switch), connection terminal 9006, Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light , liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow (including functions to measure volume, humidity, gradient, vibration, odor or infrared), microphone 9008, etc.

[0565] The electronic devices shown in FIGS. 34A to 34G have various functions. Functions for displaying information (still images, videos, text images, etc.) on the display, touch panel function, Functions that display calendars, dates, or times, etc., and various software (programs) Therefore, it has the functions of controlling processing, wireless communication, and various computer networks using wireless communication functions. Functions for connecting to networks and transmitting or receiving various data using wireless communication functions Function: Reads out programs or data recorded on a recording medium and displays them on the display. The electronic devices shown in FIGS. 34(A) to 34(G) can have the following functions. The functions that can be provided are not limited to these, and various other functions can be provided. Although not shown in FIGS. 34(A) to 34(G), the electronic device may have a plurality of display units. The electronic device may be provided with a camera or the like to take still images. A function to record video and save the captured images to a recording medium (external or built-in to the camera) The image capturing device may have a function of capturing an image on a display unit, a function of displaying a captured image on a display unit, etc.

[0566] The electronic devices shown in FIGS. 34A to 34G will be described in detail below.

[0567] FIG. 34(A) is a perspective view showing a television device 9100. 00 is a display unit 9001 with a large screen, for example, 50 inches or more, or 100 inches or more. A display unit 9001 can be incorporated.

[0568] 34(B) is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 is For example, it has one or more functions selected from a telephone, a notebook, an information viewing device, etc. In practice, it can be used as a smartphone. A speaker 9003, a connection terminal 9006, a sensor 9007, etc. may be provided. The terminal 9101 can display text and image information on multiple screens. The operation buttons 9050 (also referred to as operation icons or simply icons) are displayed on the display unit 9001. In addition, information 9051 shown in a dashed rectangle can be displayed on one side of the display unit 9001. It should be noted that an example of the information 9051 is an email or S Displays to notify you of incoming calls, such as NS (social networking services), and Subjects of e-mails and SNS, sender names of e-mails and SNS, date and time, time, battery The remaining battery capacity, antenna reception strength, etc. Or, the location where information 9051 is displayed Instead of the information 9051, operation buttons 9050 or the like may be displayed.

[0569] 34(C) is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 is The display unit 9001 has a function of displaying information on three or more surfaces. 9053 and 9054 are displayed on different sides. The user of the information terminal 9102 has the mobile information terminal 9102 stored in the breast pocket of his / her clothes. You can check the display (information 9053 in this case) by A position where the caller's telephone number or name can be observed from above the mobile information terminal 9102 The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check and decide whether to accept the call or not.

[0570] FIG. 34(D) is a perspective view showing a wristwatch-type mobile information terminal 9200. 200 is for mobile phone calls, e-mail, document viewing and creation, music playback, internet communication, It can run various applications such as computer games. The display surface of the unit 9001 is curved, and the display can be performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 has a connection terminal 9006. It is also possible to exchange data directly with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Alternatively, power may be supplied wirelessly without going through a power supply.

[0571] 34(E), (F), and (G) are perspective views showing a foldable mobile information terminal 9201. 34(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG. F) The mobile information terminal 9201 changes from one of the unfolded state and the folded state to the other. 34(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is unfolded. In this state, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 1 is attached to three housings 9000 connected by hinges 9055. The hinge 9055 allows the two housings 9000 to bend. , and the mobile information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm or more and 150 mm or less. It is possible.

[0572] Next, the electronic devices shown in FIGS. 33(A) to 33(E) and FIGS. 34(A) to 34(G) An example of an electronic device different from the electronic device shown in FIG. 35(A)(B) is shown in FIG. 35(A)( FIG. 35B is a perspective view of a display device having a plurality of display panels. 35(A) is a perspective view of a rolled-up display panel; FIG. 35(B) is a perspective view of a rolled-up display panel; FIG.

[0573] The display device 9500 shown in FIGS. 35(A) and 35(B) includes a plurality of display panels 9501 and a shaft portion 95 11 and a bearing portion 9512. The plurality of display panels 9501 have a display area 9 502 and a light-transmitting region 9503.

[0574] The display panels 9501 are flexible. 9501 are provided so that they partially overlap each other. For example, two adjacent tables The light-transmitting regions 9503 of the display panels 9501 can be overlapped. By using the display panel 9501, a large screen display device can be provided. The display panel 9501 can be rolled up depending on the situation, making it a versatile display. The device may be a device.

[0575] 35(A) and 35(B), the display area 9502 is adjacent to the display panel 9501. However, the present invention is not limited to this. For example, the adjacent display panels 95 By overlapping the display areas 9502 of the first and second images without any gaps, a continuous display area 9502 is created. That's fine.

[0576] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is not limited to an electronic device that does not have a display portion. It can also be applied to

[0577] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0578] (Embodiment 11) <Semiconductor circuits> The transistors disclosed in the present specification and the like are used in OR circuits, AND circuits, NAND circuits, and N Logic circuits such as OR circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits, encoder circuits, decoder circuits, amplifier circuits, analog switch circuits, It can be used in various semiconductor circuits such as integrating circuits, differentiating circuits, and memory elements.

[0579] An example of a semiconductor circuit using the transistor disclosed in this specification is shown in the circuit diagram of FIG. In the circuit diagram, in order to clearly show that the transistor is made of an oxide semiconductor, In addition, the circuit symbol for a transistor using an oxide semiconductor is marked with "OS."

[0580] The semiconductor circuit shown in FIG. 46(A) includes a p-channel transistor 281 and an n-channel transistor An inverter circuit in which transistors 282 are connected in series and the gates of the transistors are connected together. 1 shows an example of a path configuration.

[0581] The semiconductor circuit shown in FIG. 46(B) includes a p-channel transistor 281 and an n-channel transistor 2 shows an example of the configuration of an analog switch circuit in which transistors 282 are connected in parallel.

[0582] The semiconductor circuit shown in FIG. 46C includes a transistor 281a, a transistor 281b, a transistor 2 shows an example of a configuration of a NAND circuit using a transistor 282a and a transistor 282b. The NAND circuit is a combination of the potentials input to the input terminals IN_A and IN_B. The output potential changes depending on the combination.

[0583] <Storage device> In the semiconductor circuit shown in FIG. 47A, one of the source and drain of the transistor 289 is connected to a , a memory device connected to the gate of the transistor 1281 and one electrode of the capacitor 257 47B shows an example of the configuration of the transistor 289. 10 shows a configuration example of a memory device in which one of the drains is connected to one of the electrodes of the capacitor 257. is doing.

[0584] The semiconductor circuit shown in FIG. 47(A) and FIG. 47(B) is The charge input from the other drain can be held at node 256. By using a transistor using an oxide semiconductor for the transistor 289, It can hold a charge of 256.

[0585] In FIG. 47A, a p-channel transistor is shown as the transistor 1281. However, an n-channel transistor may be used. Therefore, the transistor 281 or the transistor 282 may be used. An OS transistor may be used as 1281.

[0586] Here, the semiconductor device (memory device) shown in FIG. 47(A) and FIG. 47(B) will be described in detail. Let me explain in detail.

[0587] The semiconductor device shown in FIG. 47A includes a transistor 1281 using a first semiconductor and a second The semiconductor device includes a transistor 289 and a capacitor 257 .

[0588] The transistor 289 is an OS transistor as described in the above embodiment. The small off-state current of the capacitor 289 allows long-term storage in a specific node of the semiconductor device. It is possible to retain the contents, i.e., no refresh operation is required or This allows for extremely low frequency of refresh operations, making it possible to use low power consumption storage devices. It becomes a place.

[0589] In FIG. 47A, the wiring 251 is one of the source and drain of the transistor 1281. The wiring 252 is electrically connected to the source or drain of the transistor 1281. The wiring 253 is electrically connected to the source or drain of the transistor 289. The wiring 254 is electrically connected to the gate of the transistor 289. The gate of transistor 1281, the source of transistor 289, The other of the drains and one of the electrodes of the capacitor 257 are electrically connected to the node 256. The wiring 255 is electrically connected to the other electrode of the capacitor 257. .

[0590] The memory device shown in FIG. 47A has a characteristic of being able to hold charge applied to the node 256. By having this, it is possible to write, hold, and read information as shown below.

[0591] [Write operation, hold operation] Writing and holding of data will be described. First, the potential of the wiring 254 is set to the value of 289 is turned on. As a result, the potential of the wiring 253 is changed to the node 256. That is, a predetermined charge is applied to the node 256 (write). The charges that give two different potential levels (hereinafter referred to as "Low-level charge" and "High-level charge") Then, the potential of the wiring 254 is set to By setting the potential at which the transistor 289 is turned off, charge is held at the node 256 .

[0592] Note that the high level charge provides a higher potential to the node 256 than the low level charge. When a p-channel transistor is used as the transistor 1281, Both the high level charge and the low level charge are at the threshold of transistor 1281. The charge is set to a value higher than the value voltage. When using a transistor, both the high-level charge and the low-level charge are This potential is lower than the threshold voltage of the transistor 1281. That is, the High level Both the charge and the low-level charge provide a potential that turns the transistor 1281 off. It is the electric charge.

[0593] Since the off-state current of the transistor 289 is extremely small, the charge of the node 256 is maintained for a long period of time. It is held as such.

[0594] [Read operation] Next, the reading of information will be described. With a potential (constant potential) applied, the wiring 255 is supplied with a read potential V R Given node 256 The information stored in the

[0595] The potential given by the high-level charge is V H , the voltage given by the low level charge V place L Then, the readout potential V R is {(Vth-V H )+(Vth+V L )} / 2 When data is not being read, the potential of the wiring 255 is If a p-channel transistor is used in 1281, V H A higher potential is used, and the transistor When using an n-channel transistor for the 1281, V L If we use a lower potential, stomach.

[0596] For example, when a p-channel transistor is used as the transistor 1281, The Vth of the 1281 is -2V, and V H to 1V, V L If we set it to -1V, then V R -2V The potential written to node 256 is V H When V is connected to wire 255, R is given When this occurs, the gate of transistor 1281 is connected to V R +V H , i.e., -1V is applied. Since -1V is higher than Vth, the transistor 1281 is not turned on. The potential of the wiring 252 does not change. L When Wiring 255 to V R is applied to the gate of transistor 1281. R +V L , that is, Since -3V is lower than Vth, transistor 1281 is turned on. As a result, the potential of the wiring 252 changes.

[0597] In addition, when an n-channel transistor is used as the transistor 1281, The Vth of the 1281 is 2V, and V H to 1V, V L If we set it to -1V, then V R Let's set it to 2V. The potential written to node 256 is V H When V is connected to wire 255, R is given and V is applied to the gate of transistor 1281. R +V H, i.e., 3V is applied. 3V is V th, the transistor 1281 is turned on. The potential written to node 256 changes to V L When V is connected to wire 255, R is applied to the gate of transistor 1281. R +V L , i.e., 1 V is applied Since 1V is lower than Vth, the transistor 1281 does not turn on. The potential of the wiring 252 does not change.

[0598] By determining the potential of the wiring 252, the data stored in the node 256 can be read. can be done.

[0599] The semiconductor device shown in FIG. 47B differs from the semiconductor device shown in FIG. 47A in that it does not include the transistor 1281. In this case, the operation is the same as that of the semiconductor device shown in FIG. It is possible to write and retain more information.

[0600] The reading of data in the semiconductor device shown in FIG. 47B will be described. When a potential that turns on the transistor 289 is applied to the wiring 253 and the capacitor 257 are electrically connected, and charge is redistributed between the wiring 253 and the capacitor 257 . As a result, the potential of the wiring 253 changes. The amount of change in the potential of the wiring 253 is Depending on the potential (or charge stored at node 256), it takes on different values.

[0601] For example, the potential of the node 256 is V, the capacitance of the capacitor 257 is C, and the capacitance of the wiring 253 is If the component is CB and the potential of the wiring 253 before the charge redistribution is VB0, The potential of the wiring 253 after this is (CB×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is such that the potential of the node 256 is V1 and V0 (V1>V0). If the potential V1 is held in one state, the potential of the wiring 253 (=(CB × VB0+C×V1) / (CB+C)) is the voltage of the wiring 253 when the potential V0 is maintained. It can be seen that it is higher than the first place (=(CB×VB0+C×V0) / (CB+C)).

[0602] Then, by comparing the potential of the wiring 253 with a predetermined potential, information can be read out. .

[0603] The memory device described above includes a transistor using an oxide semiconductor and having extremely low off-state current. By applying this, it is possible to retain memory contents for a long period of time. No refresh operations are required or refresh operations can be performed very infrequently Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is not fixed (it is preferable to keep the potential fixed), It is possible to retain the memory contents.

[0604] In addition, since the memory device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, electron injection into the floating gate Since electrons are not extracted from the floating gate, there is no degradation of the insulator. That is, the storage device according to one aspect of the present invention has the same characteristics as a conventional nonvolatile memory. There is no limit to the number of times it can be rewritten, which is the issue, and it is a storage device with dramatically improved reliability. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0605] <cpu> Next, an example of a CPU using the above-mentioned transistor will be described. FIG. 10 is a block diagram showing an example of the configuration of a CPU that partially uses transistors.

[0606] The CPU shown in FIG. 48 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and ROM interface 1189 are Of course, the CPU shown in FIG. 48 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, the configuration including the CPU or arithmetic circuit shown in Figure 48 is considered as one core, and a configuration including multiple such cores is considered as one core. It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be a bit or the like.

[0607] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0608] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0609] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0610] In the CPU shown in FIG. 48, a memory cell is provided in the register 1196. The above-mentioned transistors and memory devices can be used as the memory cells of 1196. do.

[0611] In the CPU shown in FIG. 48, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the storage elements in register 1196 are supplied with a power supply voltage. If data retention in the capacitor is selected, data rewriting to the capacitor is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0612] FIG. 49 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1730 includes a circuit 1701 in which stored data is volatilized when the power is cut off, and a circuit 1702 in which stored data is volatilized when the power is cut off. A circuit 1702 in which data is not volatile, a switch 1703, a switch 1704, and a logic element The circuit includes a transistor 1706, a capacitor 1707, and a circuit 1720 having a selection function. 1702 includes a capacitor element 1708, a transistor 1709, a transistor 1710, The memory element 1730 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0613] Here, the above-described memory device can be used for the circuit 1702. When the supply of power supply voltage to the The ground potential (0V) or the potential at which the transistor 1709 is turned off is continuously input. For example, if the gate of the transistor 1709 is grounded via a load such as a resistor, do.

[0614] The switch 1703 uses a transistor 1713 of one conductivity type (for example, n-channel type). The switch 1704 is configured to have the opposite conductivity type to the transistor 1713 (for example, a p-type Here, the switch 170 is configured using a transistor 1714 of a type (channel type). The first terminal of switch 1 corresponds to one of the source and drain of transistor 1713. The second terminal of 703 corresponds to the other of the source and drain of the transistor 1713, The transistor 1703 is turned on by a control signal RD input to the gate of the transistor 1713. Conduction or non-conduction between the terminal and the second terminal (i.e., the on or off state of the transistor 1713) The first terminal of the switch 1704 is connected to the first terminal of the transistor 1714. The second terminal of the switch 1704 corresponds to one of the source and drain of the transistor 171. 4, and the switch 1704 is connected to the gate of the transistor 1714. The control signal RD input to the output controls the conduction or non-conduction between the first terminal and the second terminal. (i.e., the on or off state of transistor 1714) is selected.

[0615] One of the source and drain of the transistor 1709 is connected to a pair of electrodes of the capacitor 1708. The connection point is electrically connected to one of the gates of the transistor 1710 and the gate of the transistor 1711. The node M2 ​​is connected to the source or drain of the transistor 1710. The other is electrically connected to a wiring (for example, a GND line) that can supply 1703 (one of the source and drain of the transistor 1713) The second terminal of the switch 1703 (the source and drain of the transistor 1713) is connected to the The other terminal of the switch 1704 (the source and drain terminal of the transistor 1714) The second terminal of the switch 1704 (the source of the transistor 1714) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1703 (the other of the source and drain of the transistor 1713) ) and the first terminal of the switch 1704 (one of the source and drain of the transistor 1714) ), an input terminal of the logic element 1706, and one of a pair of electrodes of the capacitor 1707. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1707 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1708 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 170. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0616] The capacitors 1707 and 1708 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0617] A control signal WE is input to the gate electrode of the transistor 1709. The switch 1704 is connected to the first terminal by a control signal RD different from the control signal WE. A conductive state or a non-conductive state between the first terminal of one switch and the second terminal of the other switch is selected. When the second terminals of one switch are in a conductive state, the first and second terminals of the other switch are not conductive. This is the state.

[0618] The other of the source and drain of the transistor 1709 is connected to a data register held in the circuit 1701. In FIG. 49, the signal output from the circuit 1701 is The example shown is input to the other of the source and drain of the switch 1703. The signal output from the second terminal (the other of the source and drain of the transistor 1713) is The logic value is inverted by the logic element 1706 to become an inverted signal, and is output via the circuit 1720. and input to the circuit 1701.

[0619] In FIG. 49, the second terminal of the switch 1703 (the source and drain of the transistor 1713) The signal output from the other of the two inputs is routed through logic element 1706 and circuit 1720. The example shown is an input to the circuit 1701, but is not limited to this. The signal output from the other of the source and drain of the transistor 1713 is inverted. For example, the following may be input to the circuit 1701 without being inverted: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1703 (the other of the source and drain of the transistor 1713) A signal output from the node can be input to the node.

[0620] The transistor 1709 in FIG. 49 is the same as the transistor 100 exemplified in the above embodiment. A control signal WE is input to the gate electrode, and a back gate electrode The control signal WE2 can be input to the The constant potential may be, for example, a ground potential or a source potential of the transistor 1709. The control signal WE2 is set to a potential smaller than the threshold voltage of the transistor 1709. This is a potential signal for controlling the voltage, and when the gate voltage of the transistor 1709 is 0V, The drain current of the transistor 1709 can be further reduced. It is also possible to use a transistor without two gates.

[0621] In addition, in FIG. 49, among the transistors used in the memory element 1730, The transistors other than the transistor 1709 are formed on a layer or substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1730 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the storage element 1730 may be a transistor other than the transistor 1709. The transistors are classified into a transistor in which a channel is formed in an oxide semiconductor layer and a transistor in which a channel is formed in an oxide semiconductor layer. A transistor having a channel formed in a layer or substrate 1190 made of a semiconductor other than a silicon substrate is combined. They may also be used in combination.

[0622] For example, a flip-flop circuit can be used for the circuit 1701 in FIG. The logic element 1706 may be, for example, an inverter or a clocked inverter. It is possible.

[0623] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1730, The data stored in the circuit 1701 is transferred to the capacitor 1702 provided in the circuit 1702. 8 can be held at node M2.

[0624] As described above, the off-state current of an OS transistor is extremely small. The off-state current of a transistor whose channel is formed in crystalline silicon is Therefore, the transistor is designated as transistor 1709. By using this, the capacitor 1708 can be used even when power supply voltage is not supplied to the memory element 1730. Thus, the signal stored in the storage element 1730 is maintained for a long period of time. It is possible to retain the stored contents (data) even during a power outage.

[0625] In addition, by providing the switches 1703 and 1704, the power supply voltage can be re-supplied. This can shorten the time it takes for the circuit 1701 to retain the original data after the power is turned off.

[0626] In the circuit 1702, the signal held at the node M2 ​​is input to the gate of the transistor 1710. Therefore, after the supply of the power supply voltage to the storage element 1730 is resumed, The state of transistor 1710 (on or off) depends on the signal held on node M2. The state (OFF state) is determined and can be read out from the circuit 1702. Therefore, the state stored in the node M2 Even if the potential corresponding to the input signal fluctuates slightly, the original signal can still be read accurately. is.

[0627] Such a memory element 1730 is a memory such as a register or cache memory of the CPU. By using this in equipment, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped is restored in a short time. Therefore, the entire CPU, or one or more logic components that make up the CPU, In circuits, short-term power outages are possible, and power outages can be increased in frequency. This allows for reduced power consumption.

[0628] In this embodiment, the memory element 1730 is used as a CPU. The 730 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R Also applicable to F-Id (Radio Frequency Identification) It is possible.

[0629] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible. [Example]

[0630] In this example, a transistor corresponding to the transistor 100A shown in FIG. In this example, the following samples 381 and 382 were used. Samples 381 and 382 were prepared and evaluated. The samples 381 and 382 have transistors with a channel length L This is a sample in which a transistor with a gate width of 3 μm and a channel width of W=50 μm was formed. and sample 382 differ in the method of forming the insulating film 110.

[0631] The samples 381 and 382 prepared in this example will be described below. In the description, the reference numerals attached to the transistor 100A shown in FIG. 2 will be used.

[0632] First, a conductive film 106 was formed on a substrate 102. A glass substrate was used as the substrate 102. The conductive film 106 was made of a titanium film having a thickness of 10 nm and a copper film having a thickness of 100 nm. was formed using a sputtering device.

[0633] Next, an insulating film 104 was formed on the substrate 102 and the conductive film 106. A silicon nitride film having a thickness of 400 nm and a silicon oxynitride film having a thickness of 50 nm were deposited by plasma etching. The film was formed using a CVD apparatus.

[0634] The conditions for forming the insulating film 104 were a substrate temperature of 350° C. and a silica flow rate of 200 sccm. Ammonia gas with a flow rate of 100 sccm was mixed with nitrogen gas with a flow rate of 2000 sccm. The pressure was set to 100 Pa and the parallel gas was introduced into the chamber. A 2000W RF power was supplied between the flat electrodes to form a 50nm thick silicon nitride film. Then, the flow rate of ammonia gas was changed to 2000 sccm, and a 300 nm thick nitride film was formed. A silicon film was formed, and then the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 5 Then, the substrate temperature was set to 350°C and the flow rate was set to 20 scc. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber. The pressure was set to 40 Pa, and a 100 W power was applied between the parallel plate electrodes installed in the plasma CVD device. RF power was supplied to deposit a silicon oxynitride film having a thickness of 50 nm.

[0635] Next, the oxide semiconductor film 108 was formed over the insulating film 104. was formed using a sputtering device.

[0636] The oxide semiconductor film 108 was an IGZO film having a thickness of 40 nm, grown at a substrate temperature of 130°C. Argon gas and oxygen gas were introduced into the chamber at a flow rate ratio of 9:1, and the pressure was The pressure was 0.6 Pa, and an oxide semiconductor target (In:G The film was formed by applying 2500 W of AC power to a mixture of aluminum and zinc (Al:Zn=4:2:4.1 [atomic ratio]).

[0637] Next, the insulating film 110 was formed over the insulating film 104 and the oxide semiconductor film .

[0638] The insulating film 110 of the sample 381 includes a first silicon oxynitride film having a thickness of 30 nm, The second silicon oxynitride film is 100 nm thick, and the third silicon oxynitride film is 20 nm thick. The first silicon oxynitride film was formed using a plasma CVD device. The film conditions were a substrate temperature of 350°C, silane gas at a flow rate of 20 sccm, and a silane gas flow rate of 30 Nitrous oxide gas at 0.00 sccm was introduced into the chamber, and the pressure was set to 200 Pa. A 100W RF power was supplied between the parallel plate electrodes installed in the plasma CVD device to form the film. The deposition conditions for the second silicon oxynitride film were as follows: substrate temperature 220°C; Silane gas with a flow rate of 160 sccm and nitrous oxide gas with a flow rate of 4000 sccm were mixed. The pressure was set to 200 Pa, and the parallel flat plate installed in the plasma CVD device was The film was formed by supplying 1500W of RF power between the electrodes of the plate. The deposition conditions for the silicon nitride film were the same as those for the first silicon oxynitride film.

[0639] On the other hand, the insulating film 110 of the sample 382 was a silicon oxynitride film having a thickness of 150 nm. The silicon oxynitride film was formed as a single layer using a plasma CVD apparatus. The substrate temperature was set to 350°C, and the flow rate of silane gas was 20 sccm and the flow rate of 18000 sccm. m of dinitrogen monoxide gas was introduced into the chamber, the pressure was set to 200 Pa, and plasma CV The film was formed by supplying 100 W of RF power between the parallel plate electrodes placed in the D device.

[0640] As described above, the sample 381 and the sample 382 differ in the method of manufacturing the insulating film 110. The other steps are the same.

[0641] Next, the sample 381 and the sample 382 were heated at a substrate temperature of 350° C. for 1 hour in a nitrogen atmosphere. Processed.

[0642] Next, Sample 381 and Sample 382 were subjected to oxygen plasma treatment at a substrate temperature of 350°C. The oxygen plasma treatment was carried out under the following conditions: oxygen was introduced into the chamber at a flow rate of 3000 sccm; The pressure was set to 40 Pa, and a 3000 W power was applied between the parallel plate electrodes installed in the plasma CVD device. The RF power was supplied for 250 seconds.

[0643] Next, desired regions of the insulating film 110 and the insulating film 104 are removed to form openings reaching the conductive film 106. Section 143 was formed.

[0644] Next, a conductive film 112 was formed on the insulating film 110 so as to cover the opening 143. 12 is a 10 nm thick In-Ga-Zn oxide first layer and a 90 nm thick In-Ga-Zn oxide second layer. The second layer, In-Ga-Zn oxide, was formed using a sputtering device. The conditions for forming the In-Ga-Zn oxide film were a substrate temperature of 170°C and a flow rate of 200 sccm. cm of oxygen gas was introduced into the chamber, and the pressure was set to 0.6 Pa. The oxide semiconductor target (In:Ga:Zn=4:2:4.1 [atomic ratio]) was placed in the The second layer of In-Ga-Zn oxide was deposited by supplying 2500 W of AC power to the substrate. The conditions were a substrate temperature of 170°C, argon gas at a flow rate of 180 sccm, and argon gas at a flow rate of 2 0 sccm of oxygen gas was introduced into the chamber, the pressure was set to 0.6 Pa, and sputtering The oxide semiconductor target (In:Ga:Zn=4:2:4.1 [atom]) was placed in the laser irradiation equipment. The film was formed by supplying 2500 W of AC power to the electrode (electron number ratio).

[0645] Thereafter, the insulating film 110 and the conductive film 112 are processed into an island shape using a dry etching apparatus. As a result, part of the surface of the oxide semiconductor film 108 was exposed.

[0646] Next, the insulating film 116 is formed over the insulating film 104, the oxide semiconductor film 108, and the conductive film 112. did.

[0647] The insulating film 116 was formed through two steps: a plasma treatment and a film formation treatment. For the Zuma treatment, the substrate temperature was set to 220°C, and argon gas was introduced at a flow rate of 100 sccm. The pressure was set to 40 Pa, and the parallel plates installed in the plasma CVD device An RF power of 1000 W was supplied between the electrodes. Silane gas with a flow rate of 50 sccm, nitrogen gas with a flow rate of 5000 sccm, and m of ammonia gas was introduced into the chamber, the pressure was set to 100 Pa, and plasma CVD was performed. A silicon nitride film was formed by supplying 1000W of RF power between the parallel plate electrodes installed in the device. was deposited to a thickness of 100 nm.

[0648] Next, an insulating film 118 was formed on the insulating film 116 .

[0649] The conditions for forming the insulating film 118 were a substrate temperature of 220° C. and a silica flow rate of 160 sccm. Nitrogen gas and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0.0 Pa, and a 1500 W RF power was applied between the parallel plate electrodes installed in the plasma CVD device. Electric power was supplied to deposit a silicon oxynitride film to a thickness of 300 nm.

[0650] Next, desired regions of the insulating films 116 and 118 are removed to form openings reaching the oxide semiconductor film 108. The portions 141a and 141b were formed.

[0651] The openings 141a and 141b were formed by dry etching.

[0652] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 141a and 141b. The conductive film is processed into an island shape to form a conductive film 12 that functions as a source electrode and a drain electrode. 0a, 120b were formed.

[0653] The conductive films 120a and 120b are a 50 nm thick Ti film and a 400 nm thick Al film. and a 100 nm thick Ti film were formed using a sputtering device.

[0654] Next, an acrylic film was formed to a thickness of 1.5 μm as a flattening film.

[0655] Next, a heat treatment was performed in a nitrogen atmosphere at a substrate temperature of 250°C. Processed for 1 hour.

[0656] By the above steps, Samples 381 and 382 of this example were prepared. The maximum temperature in the preparation process of sample 382 was 350°C.

[0657] In the drain current-gate voltage characteristics of the transistor of sample 381, the channel length is 2 μ Figure 50(A) shows the case with a channel length of 3 μm, Figure 50(B) shows the case with a channel length of 6 μm The drain current vs. gate current of the transistor of sample 382 is shown in Figure 50(C). In the voltage characteristics, the channel length is 2 μm as shown in Figure 50(D), and the channel length is 3 μm as shown in Figure 50(E). The channel width is 1000 sq.m. The channel width is 6 μm. The voltage between the source electrode and the drain electrode (drain voltage) is 0. Measurements were taken under the conditions of 1 V and 10 V. Also, each graph shows the results of transistors on the same substrate. 20 characteristics are overwritten.

[0658] As shown in Figures 50(A) to 50(F), the dots of the prepared sampl...

Claims

1. A semiconductor device including a transistor having an oxide semiconductor film, The transistor is an oxide semiconductor film over a substrate; a gate insulating layer on the oxide semiconductor film; a gate electrode on the gate insulating layer, the gate insulating layer includes a silicon oxynitride film, In the results of measuring the gate insulating layer on the substrate by thermal desorption spectroscopy, the maximum peak of the emission amount of oxygen molecules with a mass-to-charge ratio of M / z=32 appears in a semiconductor device where the substrate temperature is 150°C or higher and 350°C or lower.

2. In claim 1, The substrate temperature range during measurement by thermal desorption spectroscopy is from 80°C to 500°C.

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