amplifier

Abstract

To provide an amplifier capable of outputting a signal component, which is not affected by distortion caused by a filter, without reducing removal accuracy of an error component included in an input signal.SOLUTION: An amplifier 100 comprises: a signal polarity inversion circuit 200; an amplifier circuit 301 which is connected to the signal polarity inversion circuit 200 and in which a current based on a voltage Vb is generated and outputted from output terminals OUTP1 and OUTN1; a signal polarity inversion circuit 201 which includes input terminals respectively connected to the output terminals OUTP1 and OUTN1 and outputs the current outputted from the amplifier circuit 301 with a polarity of a positive phase or a reverse phase; a capacitor CL which obtains a voltage based on the current outputted from the signal polarity inversion circuit 201; and a compensation circuit 350 to which a node 12 and a node 10 are connected and a node 13 and a node 11 are connected and which extracts an input error component current including an input error component of the amplifier circuit 301 from a voltage between both terminals of the capacitor CL and supplies the extracted input error component current to the node 10 and the node 11.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier for amplifying a minute signal. [Background technology]

[0002] Chopper amplifiers are known as amplifiers that amplify minute signals. A conventional chopper amplifier includes a chopper modulator, a first-stage differential amplifier, a chopper demodulator, a second-stage differential amplifier, and a filter disposed in a signal path from an input terminal to an output terminal (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-216705 Summary of the Invention [Problem to be solved by the invention]

[0004] However, conventional chopper amplifiers tend to have large resistance and capacitance in order to enhance the attenuation effect of the filter disposed in the signal path. This means that the filter occupies a large area, resulting in an increase in chip area. Furthermore, the signal components output from the output terminal are signal components that have passed through the filter disposed in the signal path, and therefore are subject to distortion by the filter. In other words, conventional chopper amplifiers suffer from poor amplification accuracy due to the influence of the filter, resulting in reduced signal quality.

[0005] The present invention has been made in consideration of the above-mentioned problems, and has as its object to provide an amplifier that can output signal components that are not affected by distortion due to a filter, without reducing the accuracy of removing error components contained in an input signal. [Means for solving the problem]

[0006] An amplifier according to an embodiment of the present invention includes a first signal polarity inversion circuit that outputs an input signal input from an input terminal with positive or negative polarity; a first voltage-to-current conversion circuit that is connected to the first signal polarity inversion circuit and generates an output current based on the output voltage of the first signal polarity inversion circuit and outputs the output current from a first output terminal and a second output terminal; a second signal polarity inversion circuit that has a first input terminal and a second input terminal that are connected to the first output terminal and the second output terminal of the first voltage-to-current conversion circuit, respectively, and outputs the current output from the first voltage-to-current conversion circuit with positive or negative polarity; and a second signal polarity inversion circuit that is connected to the second signal polarity inversion circuit and generates a voltage based on the current output from the second signal polarity inversion circuit. a load capacitor for obtaining a voltage from the first voltage-current converter circuit; and a compensation circuit connected to a first terminal of the load capacitor and a first node which is a connection point between the first output terminal of the first voltage-current converter circuit and the first input terminal of the second signal polarity inversion circuit, and connected to a second terminal of the load capacitor and a second node which is a connection point between the second output terminal of the first voltage-current converter circuit and the second input terminal of the second signal polarity inversion circuit, the compensation circuit extracting an input error component current corresponding to the input error component from a voltage across both terminals of the load capacitor which includes the input error component of the first voltage-current converter circuit, and negatively feeding back the extracted input error component current to the first node and the second node. [Effects of the Invention]

[0007] According to the present invention, it is possible to obtain signal components that are not affected by distortion caused by a filter without reducing the accuracy of removing error components contained in an input signal. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of the configuration of an amplifier according to an embodiment of the present invention; [Figure 2] 1 is a circuit diagram showing an example of the configuration of a signal polarity inverting circuit in the amplifier according to the present embodiment. [Figure 3] FIG. 2 is a circuit diagram showing an example of the configuration of a sample-and-hold integrator circuit in the amplifier according to the present embodiment. [Figure 4] 4 is a time chart showing the operation of the amplifier according to the present embodiment. [Figure 5] 4 is a time chart of a sample-and-hold integrator circuit in the amplifier according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an amplifier according to an embodiment of the present invention will be described with reference to the drawings.

[0010] FIG. 1 is a block diagram of an amplifier 100, which is an example of an amplifier according to an embodiment of the present invention.

[0011] The amplifier 100 includes a modulation signal polarity inversion circuit 200, a first-stage amplifier circuit 301, a demodulation signal polarity inversion circuit 201, a second-stage amplifier circuit 304, an OTA 302, a sample-and-hold integration circuit 400 having a signal component separation function, an OTA 303, input terminals IN1 and IN2, and output terminals OUT1 and OUT2. The OTA 302, the sample-and-hold integration circuit 400, and the OTA 303 form a compensation circuit 350 that compensates for an input error current contained in the output signal from the amplifier circuit 301.

[0012] The amplifier circuit 301 is configured with an operational transconductance amplifier (OTA) having input terminals INP1 and INN1 and output terminals OUTP1 and OUTN1 and a transconductance gm1. The amplifier circuit 301, which serves as a first voltage-current converter, has an input offset voltage. For example, the offset voltage Vos is shown at the input terminal INP1.

[0013] The OTA 302 serving as a second voltage-current converter is an operational transconductance amplifier with transconductance gm2 having input terminals INP2 and INN2 and output terminals OUTP2 and OUTN2. The OTA 303 serving as a third voltage-current converter is an operational transconductance amplifier with transconductance gm3 having input terminals INP3 and INN3 and output terminals OUTP3 and OUTN3. The amplifier circuit 304 is configured as a fully differential amplifier circuit. That is, the amplifier circuit 304 has a first input terminal (+) and a second input terminal (-), and a first output terminal (+) and a second output terminal (-).

[0014] The compensation circuit 350 is a negative feedback circuit that connects nodes 12 and 13, which are the connection points between the signal polarity inversion circuit 201 and the amplifier circuit 304, to nodes 10 and 11, which are the connection points between the amplifier circuit 301 and the signal polarity inversion circuit 200, and feeds back a current based on the voltage Vc between nodes 12 and 13.

[0015] In OTA 302, input terminal INP2 is connected to node 12, and input terminal INN2 is connected to node 13. In addition, output terminal OUTP2 is connected to input terminal INX of sample-hold integrator circuit 400, and the connection point with input terminal INX forms node 20. In addition, output terminal OUTN2 is connected to input terminal INY of sample-hold integrator circuit 400, and the connection point with input terminal INY forms node 21.

[0016] In OTA 303, input terminal INP3 is connected to output terminal OUTX of sample-hold integrator circuit 400 to form node 30. Input terminal INN3 is connected to output terminal OUTY of sample-hold integrator circuit 400 to form node 31. Output terminal OUTP3 is connected to node 10, and output terminal OUTN3 is connected to node 11.

[0017] In amplifier 100, input signal Vin input between input terminals IN1 and IN2 is modulated by signal polarity inversion circuit 200, and a modulated signal of voltage Va is output. The modulated signal is supplied to amplifier circuit 301, which has an offset voltage Vos, and voltage Vb, including the offset voltage Vos, is converted into a current and output. Here, in amplifier circuit 301, when the difference between the voltage at input terminal INP1 and the voltage at input terminal INN1, i.e., when voltage Vb is positive (Vb>0), the larger the difference, the larger the current sourced from output terminal OUTP1 and sunk from output terminal OUTN1. On the other hand, when voltage Vb is negative (Vb<0), the larger the difference, the larger the current sunk from output terminal OUTP1 and sourced from output terminal OUTN1.

[0018] An input error component is included in the current output from the amplifier circuit 301. The current output from the amplifier circuit 301 is demodulated by the signal polarity inversion circuit 201, and the voltage Vc across the capacitor CL as a load capacitance connected between the node 12 and the node 13 is supplied to the amplifier circuit 304 and the compensation circuit 350, respectively.

[0019] The voltage supplied to the amplifier circuit 304 is amplified by the amplifier circuit 304 and then output as an output voltage Vout between output terminals OUT1 and OUT2 connected to the amplifier circuit 304.

[0020] On the other hand, the voltage Vc supplied to the compensation circuit 350 is converted into a current by the OTA 302, the charge is accumulated and redistributed by the sample-and-hold integration circuit 400, the input error component current of the amplifier circuit 301 is extracted by the OTA 303, and the input error component current contained in the current output from the amplifier circuit 301 is canceled.

[0021] Here, the OTAs 302 and 303 have the same voltage-current conversion characteristics as the amplifier circuit 301. That is, when a voltage Vc, which is the difference between the voltage at the input terminal INP2 and the voltage at the input terminal INN2, and a voltage Vd, which is the difference between the voltage at the input terminal INP3 and the voltage at the input terminal INN3, are positive (Vc>0, Vd>0), the larger the difference, the larger the currents sourced from the output terminals OUTP2 and OUTP3 and sunk from the output terminals OUTN2 and OUTN3, respectively, of the OTAs 302 and 303.

[0022] On the other hand, when the voltages Vc and Vd are negative (Vb<0), the larger the difference, the larger the current sunk from the output terminals OUTP2 and OUTP3 and sourced from the output terminals OUTN2 and OUTN3, respectively.

[0023] Next, the configurations of the signal polarity inverting circuits 200 and 201 and the sample-hold integrating circuit 400 will be described in more detail.

[0024] 2 is a circuit diagram showing a configuration example of signal polarity inversion circuit 200. Note that signal polarity inversion circuit 201 is not substantially different from signal polarity inversion circuit 200, and therefore the description of signal polarity inversion circuit 201 will be omitted by describing signal polarity inversion circuit 200. In other words, the description of signal polarity inversion circuit 200 can be substituted for the description of signal polarity inversion circuit 201 by changing the reference numeral 200 to 201.

[0025] The signal polarity inversion circuit 200 includes input terminals INX and INY, four switches SW1, SW2, SW3, and SW4, and output terminals OUTX and OUTY. The input terminal INX is connected to the output terminal OUTX via switch SW1 and to the output terminal OUTY via switch SW2. The input terminal INY is connected to the output terminal OUTX via switch SW3 and to the output terminal OUTY via switch SW4. The signal polarity inversion circuit 200 switches the polarity of signals input to the input terminals INX and INY between positive and negative phases in synchronization with control signals φ1 and φ2, and outputs the signals to the output terminals OUTX and OUTY.

[0026] In the signal polarity inverting circuit 200, the input terminal INX is connected to the input terminal IN1 (FIG. 1), while the input terminal INY is connected to the input terminal IN2 (FIG. 1). The output terminal OUTX is connected to the input terminal INP1 (FIG. 1) of the amplifier circuit 301, while the output terminal OUTY is connected to the input terminal INN1 (FIG. 1) of the amplifier circuit 301. In the signal polarity inverting circuit 201, the input terminal INX is connected to the OUTP1 of the amplifier circuit 301 and the output terminal OUTP3 of the OTA 303, while the input terminal INY is connected to the OUTN1 of the amplifier circuit 301 and the output terminal OUTN3 of the OTA 303. The output terminal OUTX is connected to the first input terminal (+) of the amplifier circuit 304 and the input terminal INP2 (FIG. 1) of the OTA 302, while the output terminal OUTY is connected to the second input terminal (-) of the amplifier circuit 304 and the input terminal INN2 (FIG. 1) of the OTA 302.

[0027] FIG. 3 is a circuit diagram showing an example of the configuration of a sample-hold integration circuit 400 having a signal component separation function.

[0028] The sample and hold integration circuit 400 includes input terminals INX and INY, output terminals OUTX and OUTY, eight switches SW11, SW12, SW13, SW14, SW15, SW16, SW17, and SW18, and sampling capacitors C1, C2, C3, and C4.

[0029] In the sample-and-hold integration circuit 400, the input terminal INX is connected to the output terminal OUTP2 and also to first terminals of capacitors C1, C2, C3, and C4 via switches SW11, SW13, SW15, and SW17, respectively. The input terminal INY is connected to the output terminal OUTN2 and also to second terminals of capacitors C1, C2, C3, and C4 via switches SW12, SW14, SW16, and SW18, respectively.

[0030] Here, the connection point between switch SW13 and capacitor C2, the connection point between switch SW14 and capacitor C2, the connection point between switch SW11 and capacitor C1, the connection point between switch SW12 and capacitor C1, the connection point between switch SW15 and capacitor C3, the connection point between switch SW16 and capacitor C3, the connection point between switch SW17 and capacitor C4, and the connection point between switch SW18 and capacitor C4 are referred to as node 22, node 23, node 24, node 25, node 26, node 27, node 28, and node 29, respectively.

[0031] In the sample-and-hold integration circuit 400, the output terminal OUTX is connected to the first terminal of the capacitor C2 via a switch SW19, to the second terminal of the capacitor C1 via a switch SW21, to the first terminal of the capacitor C4 via a switch SW23, and to the second terminal of the capacitor C3 via a switch SW25. The output terminal OUTY is connected to the first terminal of the capacitor C1 via a switch SW20, to the second terminal of the capacitor C2 via a switch SW22, to the first terminal of the capacitor C3 via a switch SW24, and to the second terminal of the capacitor C4 via a switch SW26.

[0032] The amplifier 100 configured as described above converts the output signals of the amplifier circuit 301 and the OTAs 302 and 303 into currents, enabling signal addition and subtraction using capacitors, which has the advantage of facilitating signal addition and subtraction without complicating the configuration. The amplifier 100 is switched at timings illustrated in FIGS. 4 and 5 (described later), allowing the compensation circuit 350 to remove only the signal component current from a current containing a mixture of the signal component of the signal to be amplified and the input error component of the amplifier circuit 301, thereby extracting only the input error component current of the amplifier circuit 301. The amplifier 100 cancels the input error component of the amplifier circuit 301 by gradually negatively feeding back the input error component current of the amplifier circuit 301 extracted by the compensation circuit 350 to nodes 10 and 11, which are the output nodes of the amplifier circuit 301, through discrete analog operation.

[0033] Next, the operation of the amplifier 100 will be described.

[0034] FIG. 4 is a time chart showing an example of the operation of amplifier 100, and FIG. 5 is a time chart of sample-and-hold integrator circuit 400. The horizontal axes of both FIG. 4 and FIG. 5 represent time (period), and both time charts show the same time period. The vertical axes of FIG. 4 represent input signal Vin, offset voltage Vos, control signals φ1, φ2, φ3, φ4, φ1A, φ1B, φ2A, φ2B, and voltages at nodes 10, 11, 12, 13, 20, 21, 30, and 31, respectively. The vertical axes of FIG. 5 represent voltages at nodes 22, 23, 24, 25, 26, 27, 28, and 29 in sample-and-hold integrator circuit 400, respectively.

[0035] One operation cycle of the amplifier 100 is a period from 1T to 4T, and each period has the same length (ΔT). The input signal Vin has a frequency that is sufficiently low compared to the frequencies of the control signals φ1 and φ2, and is therefore almost a DC voltage in FIG.

[0036] The control signal φ1 is at a high level (hereinafter referred to as "H level") during periods 1T to 2T, and at a low level (hereinafter referred to as "L level") during periods 3T to 4T. The control signal φ2 is at an L level during periods 1T to 2T, and at an H level during periods 3T to 4T. That is, the level of the control signal φ2 changes at a timing that is opposite to that of the control signal φ1.

[0037] Therefore, in the signal polarity inversion circuits 200, 201, during the period 1T to 2T, the input terminal INX is connected to the output terminal OUTX and the input terminal INY is connected to the output terminal OUTY, and during the following period 3T to 4T, the input terminal INX is connected to the output terminal OUTY and the input terminal INY is connected to the output terminal OUTX.

[0038] Since the signal polarity inversion circuit 200 operates as described above, the voltage Va between the output terminals OUTX and OUTY of the signal polarity inversion circuit 200 is centered around the operating point voltage Vcm of the input signal Vin, and has a voltage value of +Vin during the period 1T to 2T and -Vin during the period 3T to 4T. In other words, the signal polarity inversion circuit 200 operates as a modulator, and the voltage Va is the voltage of the modulated signal that appears between the output terminals OUTX and OUTY.

[0039] The voltage Vb appearing between the input terminals INP1 and INN1 of the amplifier circuit 301 is a voltage obtained by adding a DC offset voltage Vos to the voltage Va. That is, the voltage value is +Vos+Vin during the period 1T to 2T, and +Vos-Vin during the period 3T to 4T.

[0040] If the current output from the amplifier circuit 301 during the period 1T to 2T and the current output from the amplifier circuit 301 during the period 3T to 4T are respectively designated as current I11 and current I12, the current I11 and current I12 can be expressed by the following equations (1) and (2) using transconductance gm1: I11=gm1×(+Vos+Vin) ---(1) I12=gm1×(+Vos-Vin) ---(2) The current I11 and the current I12 are input to the signal polarity inversion circuit 201.

[0041] As described above, signal polarity inversion circuit 201 operates in the same manner as signal polarity inversion circuit 200, and therefore chopper demodulates the signal component of input signal Vin at frequency fc and chopper modulates the input error component of amplifier circuit 301 at frequency fc. The current flowing into nodes 12 and 13, which are output nodes of signal polarity inversion circuit 201, is positive phase (=I11) during the period 1T to 2T and negative phase (=-I12) during the period 3T to 4T.

[0042] Here, if the capacitance value C of the capacitor CL connected between the node 12 and the node 13, the duration of the period 1T to 2T and the duration of the period 3T to 4T are 2ΔT, of the voltage Vc generated between the nodes 12 and 13, the voltages Vc1 and Vc2 generated between the nodes 12 and 13 during the period 1T to 2T are respectively expressed by the following equations (3) and (4). The voltages Vc1 and Vc2 are input to the amplifier circuit 304 and the OTA 302, respectively.

[0043]

number

[0044]

number

[0045] After separately charging capacitors C2, C4 and capacitors C1, C3, capacitors C1 and C2 are connected via SW19, 20, 21, and 22, and capacitors C3 and C4 are connected via SW23, 24, 25, and 26. This redistributes the charge stored in capacitors C1, C2, C3, and C4, thereby removing only the signal component current from the current that contains a mixture of signal components and input error components of the amplifier circuit 301, and extracting only the input error component current of the amplifier circuit 301.

[0046] Furthermore, in analog discrete operation in which the operation of the period 1T to 4T is one cycle, the magnitude of the input error component of the amplifier circuit 301 in the nth (n is a natural number) operation period is stored as the charging voltage of the capacitor, and sampling of the input error component of the amplifier circuit 301 in the (n+1)th analog discrete operation is started from the nth capacitor charging voltage, which is an integration function.

[0047] Based on the current output from the OTA 302, the sample-and-hold integration circuit 400 charges capacitor C2 with a charge of gm1×gm2×(+Vin-Vos)×2ΔT÷C×ΔT via switches SW13 and SW14 during period 4T, charges capacitor C1 with a charge of gm1×gm2×(+Vin+Vos)×2ΔT÷C×ΔT via switches SW11 and SW12 during period 1T, and then connects capacitors C1 and C2 via switches SW19, SW20, SW21, and SW22 during periods 2T to 3T to redistribute the charged charges. The charge Q12 remaining in capacitors C1 and C2 after the redistribution of the charged charges is expressed by equation (7), -gm1×gm2×Vos×2ΔT÷C×ΔT×2.

[0048]

number

[0049] Similarly to capacitors C1 and C2, for capacitors C3 and C4, based on the current output from OTA 302, for example, during period 2T, a charge of gm1×gm2×(+Vin+Vos)×2ΔT÷C×ΔT is charged to capacitor C3 via switches SW15 and SW16, and during period 3T, a charge of gm1×gm2×(+Vin-Vos)×2ΔT÷C×ΔT is charged to capacitor C4 via switches SW17 and SW18, and then during periods 4T to 1T, capacitors C3 and C4 are connected via switches SW23, SW24, SW25, and SW26 to redistribute the charged charge.

[0050] The charge Q34 remaining in capacitors C3 and C4 after the charge redistribution is expressed by equation (7), -gm1×gm2×Vos×2ΔT÷C×ΔT×2, where the signal component is removed and only the charge of the offset voltage Vos corresponding to the input error component of amplifier circuit 301 is stored. Furthermore, since the charge Q(n) stored after charge redistribution during the period 4T to 1T in the nth analog discrete operation period, with the period 1T to 4T being one cycle, is held in capacitors C3 and C4, the charging of capacitors C3 and C4 in the (n+1)th analog discrete operation is started with the held charge Q(n) as the initial value, and therefore sample hold integrator circuit 400 with signal component separation function has integral characteristics.

[0051] If the capacitance value of capacitors C1, C2, C3, and C4 is Cs, the voltage Vd between the output terminal OUTX and the output terminal OUTY of the sample and hold integration circuit 400 during the periods 2T to 3T and 4T to 1T is expressed by equation (8) of -gm1×gm2×Vos×2ΔT÷C×ΔT×2÷(Cs×2), and is input to the OTA 303.

[0052]

number

[0053]

number

[0054] As described above, according to the amplifier of this embodiment, the amplifier circuit is configured with an OTA, and an OTA and a sample-and-hold integrator circuit having a signal component separation function are provided in the negative feedback path, thereby extracting the input error component of the amplifier circuit from a current containing a mixture of signal components and input error components of the amplifier circuit, and negatively feeding back the extracted input error component in stages through discrete analog operation.By this negative feedback, the amplifier of this embodiment can cancel the input error component current of the first-stage amplifier circuit without providing a filter such as a low-pass filter (LPF) or high-pass filter (HPF) in the signal transmission path used in conventional chopper amplifiers, thereby obtaining a signal component from which the input error component has been removed.

[0055] According to the amplifier of this embodiment, the input error component current of the first-stage amplifier circuit can be canceled without disposing a filter in the signal transmission path used in conventional chopper amplifiers, so there is no drawback to not disposing a filter, i.e., there is no reduction in the accuracy of removing the error component contained in the input signal. Furthermore, since no filter is disposed, there are no drawbacks that would otherwise occur if a filter were disposed. In other words, according to the amplifier of this embodiment, signal distortion does not occur when the signal passes through the filter, and signal components from which the input error component has been removed can be obtained without the influence of distortion.

[0056] The present invention is not limited to the above-described embodiments. Various other embodiments may be implemented, and various omissions, additions, substitutions, or modifications may be made without departing from the spirit and scope of the invention. For example, the level transitions of the control signals φ1, φ2, φ3, φ4, φ1A, φ1B, φ2A, and φ2B in amplifier 100 are not limited to the timing illustrated in FIG. 4. Amplifier 100 may operate at any timing that allows current Id, expressed by equation (9) above, to be supplied as a compensation current in a direction that cancels the error current. Furthermore, the polarities of the input and output terminals of amplifier circuit 301, OTA 302, OTA 303, and amplifier circuit 304 may be designed as appropriate. These embodiments and modifications are within the scope and spirit of the invention, and are also within the scope of the claims and their equivalents. [Explanation of symbols]

[0057] 100 Amplifier 200 signal polarity inversion circuit (first signal polarity inversion circuit) 201 Signal polarity inversion circuit (second signal polarity inversion circuit) 301 Amplification circuit (first current conversion circuit) 302 OTA (second current conversion circuit) 303 OTA (third current conversion circuit) 400 Sample and hold integrator circuit CL Capacitor (load capacitance) IN1, IN2 input terminals OUT1, OUT2 output terminals

Claims

1. a first signal polarity inversion circuit that outputs an input signal input from an input terminal with a positive phase or a negative phase polarity; a first voltage-current conversion circuit connected to the first signal polarity inversion circuit, generating an output current based on an output voltage of the first signal polarity inversion circuit, and outputting the output current from a first output terminal and a second output terminal; a second signal polarity inversion circuit having a first input terminal and a second input terminal connected to the first output terminal and the second output terminal of the first voltage-current conversion circuit, respectively, and outputting the current output from the first voltage-current conversion circuit with a positive phase or a negative phase polarity; a load capacitance connected to the second signal polarity inversion circuit, for obtaining a voltage based on a current output from the second signal polarity inversion circuit; a compensation circuit connected to a first terminal of the load capacitance and a first node which is a connection point between the first output terminal of the first voltage-to-current converter circuit and a first input terminal of the second signal polarity inversion circuit, and connected to a second terminal of the load capacitance and a second node which is a connection point between the second output terminal of the first voltage-to-current converter circuit and a second input terminal of the second signal polarity inversion circuit, the compensation circuit extracting an input error component current corresponding to the input error component from a voltage across both terminals of the load capacitance which includes the input error component of the first voltage-to-current converter circuit, and negatively feeding back the extracted input error component current to the first node and the second node; An amplifier comprising:

2. the amplifier is configured to operate periodically; The compensation circuit a second voltage-current conversion circuit connected to the load capacitance and configured to generate a current based on a voltage across the load capacitance; a sample and hold integration circuit having a capacitance and connected to the second voltage-current conversion circuit, which removes the signal component from a current output from the second voltage-current conversion circuit in which the signal component and the input error component are mixed, extracts the input error component current, and outputs the output voltage, and, where n is a natural number indicating the number of cycles of the operation, stores the magnitude of the input error component in the nth cycle as a charging voltage of the capacitance, and has integration characteristics that start sampling of the input error component in the (n+1)th cycle from the charging voltage in the nth cycle; 2. The amplifier according to claim 1, further comprising: a third voltage-current conversion circuit connected to the sample-and-hold integrator circuit, converting a voltage between a first output terminal and a second output terminal of the sample-and-hold integrator circuit into the input error component current and supplying the input error component current to the first node and the second node.

3. the sample-and-hold integration circuit includes a pair of capacitors connectable in parallel as the capacitors; The capacitance pair includes a first capacitance that samples a charge based on a current output from a first voltage-current converter circuit when the second signal polarity inversion circuit outputs a signal in a positive phase relationship, and a second capacitance that samples a charge based on a current output from the first voltage-current converter circuit when the second signal polarity inversion circuit outputs a signal in a negative phase relationship.

3. The amplifier of claim 2.

Images