Method for manufacturing printed wiring board

Abstract

To provide a printed wiring board having high quality.SOLUTION: A method for manufacturing a printed wiring board includes: forming a resin insulation layer; forming a protective film on a first surface of the resin insulation layer; forming an opening for a via conductor; removing the protective film; cleaning the first surface; forming a second conductor layer; and forming a via conductor. The resin insulation layer contains a resin and inorganic particles, and the inorganic particles contain first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin. The cleaning includes forming the first inorganic particles from the second inorganic particles. The formation of the second conductor layer includes: forming a seed layer on the first surface of the resin insulation layer; forming a plating resist on the seed layer using DI exposure; forming an electrolytic plating layer; removing a plating resist; and removing a seed layer exposed from the electrolytic plating layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a printed wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board. The examples of Patent Document 1 disclose a manufacturing method including forming blind holes in an insulating resin layer, forming fine irregularities on the surface of the insulating resin layer, forming a power supply layer using electroless copper plating, and forming a plating resist using a photomask. The plating resist is removed using an oxidizing agent. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-217526 Summary of the Invention

[0004] [Problem of Patent Document 1] According to the examples in Patent Document 1, the power supply layer (seed layer) is an electroless copper plating film formed on the surface of an insulating resin layer having an uneven surface. It is believed that the power supply layer follows the unevenness of the surface of the insulating resin layer. It is believed that the top surface of the power supply layer has an uneven surface. It is believed that the examples in Patent Document 1 cannot reduce the transmission loss of the wiring due to the unevenness of the power supply layer. It is believed that the contact area between the photoresist used to form the plating resist and the power supply layer is small due to the unevenness of the top surface of the power supply layer. It is believed that the plating resist peels off from the power supply layer during development. It is believed that peeling is particularly likely to occur when the width of the plating resist is small. It is believed that the examples in Patent Document 1 make it difficult to form fine wiring. [Means for solving the problem]

[0005] A method for manufacturing a printed wiring board of the present invention includes forming a resin insulating layer having a first surface and a second surface opposite to the first surface on a first conductor layer, forming a protective film on the first surface of the resin insulating layer, forming openings for via conductors that simultaneously penetrate the protective film and the resin insulating layer and reach the first conductor layer, removing the protective film from the resin insulating layer after forming the openings, cleaning the first surface of the resin insulating layer, forming a second conductor layer on the first surface of the resin insulating layer, and forming via conductors in the openings that connect the first conductor layer and the second conductor layer. The resin insulating layer includes resin and inorganic particles, and the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles being approximately spherical in shape, and the second inorganic particles being approximately spherical in shape. The cleaning includes selectively removing the resin so that portions of the second inorganic particles protrude from the first surface of the resin insulating layer. The first inorganic particles are formed from the second inorganic particles by selectively removing the resin. The first inorganic particles are formed of a first portion protruding from the resin and a second portion buried in the resin, and the first surface is formed by an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface. Forming the second conductor layer includes forming a seed layer on the first surface of the resin insulating layer by sputtering, forming a plating resist on the seed layer using DI exposure, forming an electrolytic plating layer on the seed layer exposed from the plating resist, removing the plating resist, and removing the seed layer exposed from the electrolytic plating layer.

[0006] According to the method for manufacturing a printed wiring board of an embodiment of the present invention, almost no recesses are formed on the first surface of the resin insulating layer. The first surface of the resin insulating layer has almost no recesses. The upper surface of the seed layer formed on the first surface of the resin insulating layer by sputtering also has almost no recesses. For example, when an electrical signal propagates through a signal wiring, the embodiment can reduce transmission loss. The embodiment can reduce transmission loss of the wiring. Because the seed layer is formed by sputtering, the adhesive strength between the resin insulating layer and the seed layer is high. The conductor circuit is less likely to peel off from the resin insulating layer. The embodiment can form a continuous seed layer even when the sputtering film is thin. When the seed layer is removed, the embodiment can reduce the amount of etching required to remove the seed layer. Furthermore, because the upper surface of the seed layer has almost no recesses, the embodiment can form a fine plating resist having dimensions close to the target value by using DI exposure. The embodiment can form fine signal wiring. The embodiment can form a high-quality printed wiring board. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view schematically showing a printed wiring board according to an embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment. [Figure 3] FIG. 2 is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment. [Figure 4] FIG. 2 is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment. [Figure 5] FIG. 2 is an enlarged cross-sectional view schematically showing a part of the printed wiring board according to the embodiment. [Figure 6A] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6B] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6C] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6D] 5A to 5C are enlarged cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6E] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6F] 5A to 5C are enlarged cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 6G] 1A to 1C are cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. [Figure 7] 5A to 5C are enlarged cross-sectional views schematically illustrating a method for manufacturing a printed wiring board according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Embodiment] Fig. 1 is a cross-sectional view showing a printed wiring board 2 of an embodiment. Figs. 2 to 5 are enlarged cross-sectional views showing a portion of the printed wiring board 2 of the embodiment. As shown in Fig. 1, the printed wiring board 2 has an insulating layer 4, a conductor layer (first conductor layer) 10, a resin insulating layer (first resin insulating layer) 20, a conductor layer (second conductor layer) 30, via conductors 40, a resin insulating layer (second resin insulating layer) 120, a conductor layer (third conductor layer) 130, and via conductors 140.

[0009] The insulating layer 4 is formed using a resin. The insulating layer 4 may contain inorganic particles such as silica. The insulating layer 4 may contain a reinforcing material such as glass cloth. The insulating layer 4 has a third surface 6 and a fourth surface 8 opposite to the third surface 6.

[0010] The first conductor layer 10 is formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 includes signal wiring 12 and pads 14. Although not shown in the figure, the first conductor layer 10 also includes conductor circuits other than the signal wiring 12 and pads 14. The first conductor layer 10 is mainly made of copper. The first conductor layer 10 is formed of a seed layer 10a on the insulating layer 4 and an electroplated layer 10b on the seed layer 10a. The thickness of the seed layer 10a is less than 0.5 μm. The seed layer 10a is formed of a first layer 11a on the third surface 6 and a second layer 11b on the first layer 11a. The first layer 11a is in contact with the insulating layer 4. The ratio of the thickness of the first layer 11a to the thickness of the second layer 11b (thickness of the first layer / thickness of the second layer) is 0.25 or more and 0.7 or less. It is preferable that the thickness of the second layer 11b be thicker than the thickness of the first layer 11a.

[0011] The first layer 11a is formed of an alloy (copper alloy) containing copper and a metal other than copper. For example, the first layer 11a is formed of an alloy containing copper and aluminum. The first layer 11a is formed of an alloy containing copper, aluminum, and a specific metal. Examples of the specific metal are nickel, zinc, gallium, silicon, and magnesium. The alloy preferably contains one specific metal, two specific metals, or three specific metals. An example of the specific metal is silicon. The aluminum content in the alloy is 1.0 at% or more and 15.0 at% or less. When the alloy contains a specific metal, the content of the specific metal in the alloy is 0.5 at% or more and 10.0 at% or less. The first layer 11a may contain impurities. Examples of impurities are oxygen and carbon. The first layer 11a may contain oxygen or carbon. The first layer 11a may contain oxygen and carbon. In an embodiment, the alloy further contains carbon. The carbon content in the alloy is 50 ppm or less. The alloy further contains oxygen. The oxygen content in the alloy is 100 ppm or less. The above content values ​​of each element are examples. Among the elements forming the first layer 11a, the amount of copper is the largest, followed by the amount of aluminum. When the alloy contains a specific metal, the amount of the specific metal is smaller than the amount of aluminum. Therefore, copper is the main metal, aluminum is the first minor metal, and the specific metal is the second minor metal. The amount of impurities is smaller than the amount of the specific metal.

[0012] The second layer 11b is made of copper. The electrolytic plated layer 10b is made of copper.

[0013] The copper content in the copper alloy forming first layer 11a is greater than 90 at%. The copper content in the alloy is less than 99 at%. The copper content in the copper alloy is 98 at% or less. The copper content in second layer 11b is 99.9 at% or more. The copper content in second layer 11b is preferably 99.95 at% or more. Electroplated layer 10b is formed of copper. The copper content in electroplated layer 10b is 99.9 at% or more. The copper content in electroplated layer 10b is preferably 99.95 at% or more.

[0014] The resin insulating layer (first resin insulating layer) 20 is formed on the third surface 6 of the insulating layer 4 and the first conductor layer 10. The first resin insulating layer 20 has a first surface 22 and a second surface 24 opposite the first surface 22. The second surface 24 of the first resin insulating layer 20 faces the first conductor layer 10. The first resin insulating layer 20 has an opening (opening for a via conductor) 26 exposing the pad 14. The diameter of the bottom of the opening 26 is 20 μm or more and 50 μm or less. The resin insulating layer (first resin insulating layer) 20 is formed of a resin 80 and a large number of inorganic particles 90 dispersed within the resin 80. The resin 80 has an upper surface 80R and a lower surface 80S opposite the upper surface 80R. The upper surface 80R forms the first surface 22, and the lower surface 80S forms the second surface 24. The resin 80 is an epoxy-based resin. Examples of resins include thermosetting resins and photocurable resins. The inorganic particles 90 are, for example, glass particles or alumina particles. The inorganic particles 90 preferably contain oxygen elements. The average particle size of the inorganic particles 90 is 0.5 μm or less. The amount of the inorganic particles 90 in the resin insulating layer 20 is 75 wt % or more.

[0015] 1 and 2, the inorganic particles 90 include first inorganic particles 91 that are partially embedded in the resin 80 and second inorganic particles 92 that are embedded within the resin 80. The first inorganic particles 91 and the second inorganic particles 92 are substantially spherical in shape. As shown in FIG. 2, the first inorganic particles 91 are formed of a first portion 91a that protrudes from the resin 80 and a second portion 91b that is embedded in the resin 80. The first surface 22 of the resin insulating layer 20 is formed by an upper surface 80R of the resin 80 and an exposed surface of the first portion 91a that is exposed from the upper surface of the resin 80.

[0016] The ratio R of the volume of the first portion 91a to the volume of the first inorganic particles 91 (volume of first portion / volume of first particle) is greater than 0 and less than 0.4. The ratio R is preferably less than 0.2. The ratio R is more preferably less than 0.1. The ratio R is most preferably less than 0.05. When the first portion 91a protrudes from the resin 80, the first surface 22 of the resin insulating layer 20 has slight irregularities. However, the upper surface 80R of the resin 80 is not roughened. Therefore, the first surface 22 has almost no recesses. The arithmetic mean roughness (Ra) of the first surface 22 is less than 0.08 μm. The roughness Ra of the first surface 22 is preferably less than 0.05 μm. The roughness Ra of the first surface 22 is more preferably less than 0.03 μm.

[0017] As shown in FIGS. 1 and 3, the inorganic particles 90 further include third inorganic particles 93 that form the inner wall surface (first inner wall surface) 27 of the opening (opening for via conductor) 26. The shape of the third inorganic particles 93 is obtained by cutting a sphere along a plane. The shape of the third inorganic particles 93 is obtained by cutting the second inorganic particles 92 along a plane. The third inorganic particles 93 are formed from the second inorganic particles 92. The third inorganic particles 93 are obtained by removing a portion of the second inorganic particles 92. The shape of the third inorganic particles 93 is essentially a spherical indentation. A spherical indentation is a three-dimensional object obtained by cutting a sphere along a substantially flat plane. A three-dimensional object obtained by cutting a sphere along a plane passing through the center of the sphere is a hemisphere, and a hemisphere is a type of spherical indentation. In the embodiment, the surface exposed by cutting a sphere along a substantially flat plane is referred to as the cut surface. The third inorganic particles 93 have a flat portion 93a. The flat portion 93a forms the inner wall surface 27. The inner wall surface 27 is formed by the resin 80 and the flat portion 93a. The flat portion 93a and the surface (first resin surface) 80a of the resin 80 that forms the inner wall surface 27 form an approximately common surface. No irregularities are formed on the resin 80 that forms the inner wall surface 27. The surface 80a of the resin 80 that forms the inner wall surface 27 is approximately smooth. No irregularities are formed on the exposed surface 93b of the flat portion 93a (the surface that forms the inner wall surface 27). The exposed surface (first exposed surface) 93b of the flat portion 93a is smooth. The inner wall surface 27 is formed smoothly. The arithmetic mean roughness (Ra) of the inner wall surface 27 is 1.0 μm or less. The roughness (Ra) of the surface 80a of the resin 80 that forms the inner wall surface 27 is 1.0 μm or less.

[0018] The inner wall surface 27 may have a step (first step) between the flat portion 93a and the surface 80a of the resin 80 that forms the inner wall surface 27. The exposed surface (first exposed surface) 93b of the flat portion 93a protrudes from the surface 80a of the resin 80 that forms the inner wall surface 27. Alternatively, the exposed surface 93b of the flat portion 93a is recessed from the surface 80a of the resin 80 that forms the inner wall surface 27. A protruding surface is preferable. The size of the step (first step) (the distance between the exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 that forms the inner wall surface 27) is 5 μm or less. The size of the first step is preferably 3 μm or less. The size of the first step is more preferably 1.5 μm or less. Even if a step (first step) is formed, the step is small, so that exposed surface 93b of flat portion 93a and surface 80a of resin 80 forming inner wall surface 27 form a substantially common surface.

[0019] As shown in Fig. 1, the second conductor layer 30 is formed on the first surface 22 of the resin insulating layer (first resin insulating layer) 20. The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34, and a land 36. Although not shown in the figure, the second conductor layer 30 also includes conductor circuits other than the first signal wiring 32, the second signal wiring 34, and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring. The first signal wiring 32 and the second signal wiring 34 are adjacent to each other.

[0020] The conductor layer (second conductor layer) 30 is mainly made of copper. The second conductor layer 30 is formed of a seed layer 30a on the first surface 22 and an electroplated layer 30b on the seed layer 30a. The seed layer 30a is formed of a first layer 31a on the first surface 22 and a second layer 31b on the first layer 31a. The thickness of the seed layer 30a is less than 0.5 μm. The first conductor layer 10 and the second conductor layer 30 are similar. The relationship between the thickness of the first layer 31a and the thickness of the second layer 31b and the relationship between the thickness of the first layer 11a and the thickness of the second layer 11b are similar. The first layer 31a and the second layer 31b form the second conductor layer 30, and the first layer 11a and the second layer 11b form the first conductor layer 10. The first layer 31a is formed of the same alloy (copper alloy) as the first layer 11a. The second layer 31b is formed of copper. The electrolytic plating layer 30b is made of copper. The first layer 31a is in contact with the first surface 22.

[0021] The via conductor (first via conductor) 40 is formed in the opening (opening for the via conductor) 26. The opening 26 penetrates the first resin insulating layer 20 and reaches the first conductor layer 10. The via conductor (first via conductor) 40 connects the first conductor layer 10 and the second conductor layer 30. In FIG. 1, the via conductor 40 connects the pad 14 and the land 36. The via conductor 40 is formed of a seed layer 30a and an electrolytic plating layer 30b on the seed layer 30a. The seed layer 30a forming the via conductor 40 and the seed layer 30a forming the second conductor layer 30 are common. The first layer 31a forming the via conductor 40 and the first layer 31a forming the second conductor layer 30 are common. The first layer 31a is in contact with the inner wall surface 27. The second layer 31b forming the via conductor 40 and the second layer 31b forming the second conductor layer 30 are common. The electrolytic plated layer 30b forming the via conductor 40 and the electrolytic plated layer 30b forming the second conductor layer 30 are common.

[0022] The first layer 11a forming the first conductor layer 10, the first layer 31a forming the second conductor layer 30, and the first layer 31a forming the via conductor 40 are all similar. Both layers 11a and 31a are formed of similar elements. The elements forming both layers 11a and 31a have similar amounts. The second layer 11b forming the first conductor layer 10, the second layer 31b forming the second conductor layer 30, and the second layer 31b forming the via conductor 40 are all similar. The second layers 11b and 31b are all formed of similar elements. The second layers 11b and 31b are all formed of approximately the same amounts of elements. The electroplated layer 10b forming the first conductor layer 10, the electroplated layer 30b forming the second conductor layer 30, and the electroplated layer 30b forming the via conductor 40 are all similar. The electroplated layers 10b and 30b are all formed of similar elements. The electroplated layers 10b and 30b are all formed of approximately the same amounts of elements.

[0023] As shown in FIG. 4, the seed layer 30a forming the via conductor 40 may have a substantially smooth first portion (first film) 60 and a substantially smooth second portion (second film) 70. The first portion 60 and the second portion 70 are electrically connected. The first portion 60 and the second portion 70 are continuous. A part of the first portion 60 is formed on the second portion 70. The leading end 62 of the first portion 60 is formed on the trailing end 72 of the second portion 70. The first portion 60 and the second portion 70 are formed simultaneously. The cross section of the seed layer 30a covering the inner wall surface 23 has a substantially stepped shape.

[0024] As shown in FIG. 4, the first layer 31a of the seed layer 30a has a first portion (first film) 60a and a second portion (second film) 70a. The first portion 60a and the second portion 70a are electrically connected. The first portion 60a and the second portion 70a are continuous. The leading end 62a of the first portion 60a is formed on the rear end 72a of the second portion 70a. The cross section of the first layer 31a covering the inner wall surface 23 has a substantially stepped shape. The first layer 31a on the inner wall surface 27 is in contact with the inner wall surface 27.

[0025] The second layer 31b of the seed layer 30a has a first portion (first film) 60b and a second portion (second film) 70b. The first portion 60b and the second portion 70b are electrically connected. A leading end 62b of the first portion 60b is formed on a trailing end 72b of the second portion 70b. The cross section of the second layer 31b formed on the inner wall surface 23 has a substantially stepped shape.

[0026] A portion of the first portion 60 is stacked on the second portion 70. A portion of the first portion 60 overlaps the second portion 70. The leading end 62 of the first portion 60 is stacked on the rear end 72 of the second portion 70. The leading end 62 of the first portion 60 overlaps the rear end 72 of the second portion 70.

[0027] A second resin insulating layer 120 is formed on the first surface 22 of the second conductor layer 30 and the first resin insulating layer 20. The second resin insulating layer 120 has a first surface 122 and a second surface 124 opposite the first surface 122. The second surface 124 of the second resin insulating layer 120 faces the second conductor layer 30. The second resin insulating layer 120 has an opening 126 (opening for a via conductor). The opening 126 penetrates the second resin insulating layer 120 and reaches the second conductor layer 30.

[0028] The second resin insulating layer 120 is formed of resin 80 and inorganic particles 90. The first resin insulating layer 20 and the second resin insulating layer 120 are similar. Therefore, the resin 80 forming the second resin insulating layer 120 is similar to the resin 80 forming the first resin insulating layer 20. The inorganic particles 90 forming the second resin insulating layer 120 are similar to the inorganic particles 90 forming the first resin insulating layer 20. As with the first resin insulating layer 20, the inorganic particles 90 forming the second resin insulating layer 120 include first inorganic particles 91, second inorganic particles 92, and third inorganic particles 93. The first inorganic particles 91 in the first resin insulating layer 20 are similar to the first inorganic particles 91 in the second resin insulating layer 120. The second inorganic particles 92 in the first resin insulating layer 20 are similar to the second inorganic particles 92 in the second resin insulating layer 120. The third inorganic particles 93 in the first resin insulating layer 20 and the third inorganic particles 93 in the second resin insulating layer 120 are similar.

[0029] The first surface 22 of the first resin insulating layer 20 is similar to the first surface 122 of the second resin insulating layer 120. The first surface 122 of the resin insulating layer (second resin insulating layer) 120 is formed by the upper surface of the resin 80 that forms the resin insulating layer (second resin insulating layer) 120 and the exposed surface of the first portion 91a that is exposed from the upper surface of the resin 80.

[0030] An opening (opening for a via conductor) 126 penetrating the second resin insulating layer 120 is similar to an opening (opening for a via conductor) 26 penetrating the first resin insulating layer 20. Therefore, an inner wall surface (second inner wall surface) 127 of the opening 126 is similar to an inner wall surface (first inner wall surface) 27 of the opening 26. The second inner wall surface 127 is formed by the resin 80 and the flat portions 93a of the third inorganic particles 93. Like the first inner wall surface 27, the second inner wall surface 127 is formed by the surface (second resin surface) of the resin 80 that forms the second inner wall surface 127 and the flat portions 93a of the third inorganic particles 93 that form the second resin insulating layer 120. Like the flat portions 93a of the third inorganic particles 93 that form the first resin insulating layer 20, the flat portions 93a of the third inorganic particles 93 that form the second resin insulating layer 120 have an exposed surface (second exposed surface). The second resin surface and the second exposed surface forming the inner wall surface 127 form a substantially common surface. Similar to the first inner wall surface 27, the second inner wall surface 127 can have a step (second step) between the second resin surface and the second exposed surface. The first step and the second step are similar. The size of the second step and the size of the first step are similar. Therefore, even if the second inner wall surface 127 has the second step, the second resin surface and the second exposed surface form a substantially common surface.

[0031] As shown in FIG. 1, a third conductor layer 130 is formed on the first surface 122 of the second resin insulating layer 120. A via conductor (second via conductor) 140 connecting the second conductor layer 30 and the third conductor layer 130 is formed in the opening 126. The third conductor layer 130 and the second conductor layer 30 are identical. The second via conductor 140 and the first via conductor 40 are identical. The third conductor layer 130 and the second via conductor 140 are formed by a seed layer 130a consisting of a first layer 131a and a second layer 131b on the first layer 131a, and an electrolytic plating layer 130b on the seed layer 130a. The first layer 131a forming the third conductor layer 130 and the second via conductor 140 are identical to the first layer 31a of the second conductor layer 30. The second layer 131b forming the third conductor layer 130 and the second via conductor 140 is similar to the second layer 31b of the second conductor layer 30. The electrolytic plated layer 130b forming the third conductor layer 130 and the second via conductor 140 is similar to the electrolytic plated layer 30b of the second conductor layer 30. The first layer 131a contacts the first surface 122 of the second resin insulating layer 120. The first layer 131a contacts the inner wall surface (second inner wall surface) 127. The layers (first layer 31a, second layer 31b, electrolytic plated layer 30b) forming the second conductor layer 30 and the layers (first layer 131a, second layer 131b, electrolytic plated layer 130b) forming the third conductor layer 130 have similar thicknesses and compositions. The layers (first layer 31a, second layer 31b, electrolytically plated layer 30b) that form second conductor layer 30 and the layers (first layer 131a, second layer 131b, electrolytically plated layer 130b) that form third conductor layer 130 are formed of similar elements. The elements contained in the layers (first layer 31a, second layer 31b, electrolytically plated layer 30b) that form second conductor layer 30 and the elements contained in the layers (first layer 131a, second layer 131b, electrolytically plated layer 130b) that form third conductor layer 130 have similar amounts.

[0032] Fig. 5 shows an enlarged cross-sectional view of the first signal wiring 32 of the second conductor layer 30. As shown in Fig. 5, the first signal wiring 32 is formed by a seed layer 30a on the first surface 22 of the first resin insulating layer 20 and an electroplated layer 30b on the seed layer 30a. The seed layer 30a has a first layer 31a on the first surface 22 and a second layer 31b on the first layer 31a. The first layer 31a is in contact with the first surface 22. The electroplated layer 30b is formed directly on the second layer 31b.

[0033] 5, the width (length in the left-right direction in the figure) of seed layer 30a of first signal wiring 32 is smaller than the width of electroplated layer 30b. The width of first signal wiring 32 is smallest at boundary portion B between seed layer 30a and electroplated layer 30b. Width D2 of first layer 31a is larger than width D3 of second layer 31b, and width D1 of electroplated layer 30b is larger than width D2 of first layer 31a.

[0034] 5, widths D1, D2, and D3 are the distances between the side surfaces of the wiring. Width D1 is the distance between the side surfaces of first signal wiring 32. Width D1 is measured near the top surface of first signal wiring 32. The top surface of first signal wiring 32 is the surface away from first surface 22. Width D2 is measured on first surface 22. Width D3 is measured at the interface between second layer 31b and electroplated layer 30b.

[0035] 5 illustrates the first signal wiring 32, the other conductor circuits (second signal wiring 34 and land 36) in the second conductor layer 30 also have the same configuration as the first signal wiring 32. The conductor circuits in the third conductor layer 130 also have the same configuration as the first signal wiring 32.

[0036] The length of each side of the printed wiring board 2 is 50 mm or more. Preferably, the length of each side is 100 mm or more. The length of each side is 250 mm or less.

[0037] The printed wiring board 2 may have a solder resist layer on the first surface 122 of the second resin insulating layer 120 and on the third conductor layer 130. The insulating layer 4 may form a core material.

[0038] [Method for manufacturing printed wiring board 2 according to the embodiment] Figures 6A to 6G and 7 show a method for manufacturing a printed wiring board 2 according to an embodiment. Figures 6A to 6C, 6E, and 6G are cross-sectional views. Figures 6D, 6F, and 7 are enlarged cross-sectional views. Figure 6A shows an insulating layer 4 and a conductor layer (first conductor layer) 10 formed on the third surface 6 of the insulating layer 4. The first conductor layer 10 is formed by a semi-additive method. The first layer 11a and the second layer 11b are formed by sputtering. The first layer 11a and the second layer 11b are formed in a vacuum. The electroplated layer 10b is formed by electroplating.

[0039] As shown in FIG. 6B , a resin insulating layer (first resin insulating layer) 20 and a protective film 50 are formed on the insulating layer 4 and the first conductor layer 10. Forming the resin insulating layer 20 and the protective film 50 on the insulating layer 4 and the first conductor layer 10 includes forming the resin insulating layer 20 on the insulating layer 4 and the first conductor layer 10 and forming the protective film 50 on the resin insulating layer 20. Forming the resin insulating layer 20 and the protective film 50 on the insulating layer 4 and the first conductor layer 10 includes forming the resin insulating layer 20 with the protective film 50 on the insulating layer 4 and the first conductor layer 10. The manufacturing method including forming the resin insulating layer 20 on the first conductor layer 10 and forming the protective film 50 on the resin insulating layer 20 includes a manufacturing method including preparing the resin insulating layer 20 with the protective film 50 and forming the resin insulating layer 20 with the protective film 50 on the first conductor layer 10. The second surface 24 of the resin insulating layer 20 faces the third surface 6 of the insulating layer 4. A protective film 50 is formed on the first surface 22 of the first resin insulating layer 20. The resin insulating layer 20 has a resin 80 and inorganic particles 90. The inorganic particles 90 are embedded in the resin 80. An example of the inorganic particles 90 is glass particles.

[0040] The protective film 50 completely covers the first surface 22 of the resin insulating layer 20. An example of the protective film 50 is a film made of polyethylene terephthalate (PET). A release agent is formed between the protective film 50 and the resin insulating layer 20.

[0041] As shown in FIG. 6C, laser light L is irradiated from above the protective film 50. The laser light L penetrates the protective film 50 and the resin insulating layer 20 at the same time. An opening (opening for a via conductor) 26 is formed that reaches the pad 14 of the first conductor layer 10. After irradiation with the laser light, an inner wall surface 27b of the opening 26 is formed. The laser light L is, for example, UV laser light or CO2 laser light. The pad 14 is exposed by the opening 26. When the opening 26 is formed, the first surface 22 is covered with the protective film 50. Therefore, even if resin scatters when the opening 26 is formed, the resin is prevented from adhering to the first surface 22.

[0042] 6D shows the inner wall surface 27b of the opening 26 after irradiation with laser light. By irradiating the resin insulating layer 20 with laser light L, some of the second inorganic particles 92 embedded in the resin 80 form the inner wall surface 27b after irradiation with laser light. The inner wall surface 27b is formed by the resin 80 and the inorganic particles 90 protruding from the resin 80. Some of the second inorganic particles embedded in the resin insulating layer 20 partially protrude from the inner wall surface 27b. The second inorganic particles 92 that form the inner wall surface 27b after irradiation with laser light are formed by protruding portions P protruding from the resin 80 and portions E embedded in the resin 80.

[0043] The inner wall surface 27b is formed of resin 80 and inorganic particles 90 protruding from the resin 80. In order to control the shape of the inner wall surface, the inner wall surface 27b is treated after the laser beam irradiation. It is preferable to selectively remove the inorganic particles 90 protruding from the resin 80. As a result, third inorganic particles 93 are formed from the inorganic particles 90. For example, by treating the inner wall surface 27b after the laser beam irradiation with a chemical, the inorganic particles 90 protruding from the resin 80 are selectively removed. Alternatively, by treating the inner wall surface 27b after the laser beam irradiation with plasma, the inorganic particles 90 protruding from the resin 80 are selectively removed. Selective removal includes the etching rate of the inorganic particles 90 being higher than the etching rate of the resin 80. For example, the difference in etching rate between the two is 10 times or more. Alternatively, the difference in etching rate between the two is 50 times or more. Alternatively, the difference in etching rate between the two is 100 times or more. By processing the inner wall surface 27b after the laser beam irradiation, third inorganic particles 93 having flat portions 93a (FIG. 3) are obtained. The shape of the inner wall surface 27b can be controlled by controlling the conditions for processing the inner wall surface 27b after the laser beam irradiation. Examples of the conditions include temperature, concentration, time, and the type and pressure of gas. The etching rate of the inorganic particles 90 and the etching rate of the resin are controlled.

[0044] By irradiating the resin insulating layer 20 with laser light L, a portion of the second inorganic particles 92 embedded in the resin 80 forms an inner wall surface 27b after laser light irradiation. The second inorganic particles 92 that form the inner wall surface 27b after laser light irradiation are composed of protruding portions P protruding from the resin 80 and portions E embedded in the resin 80. The inner wall surface 27b after laser light irradiation is treated. For example, the inner wall surface 27b is treated with plasma of a gas containing tetrafluoromethane. The protruding portions P are selectively removed to form the inner wall surface 27 (FIGS. 1 and 3) of the embodiment. By treating the inner wall surface 27b, third inorganic particles 93 are formed from the second inorganic particles 92. The protruding portions P are selectively removed to form third inorganic particles 93 having flat portions 93a. The flat portions 93a are flat. When the second inorganic particles 92, which have an approximately spherical shape, are cut along a plane, the shape of the third inorganic particles 93 is obtained. The inner wall surface 27 is formed by the flat portion 93a and the surface 80a of the resin 80. The exposed surface 93b of the flat portion 93a and the surface 80a of the resin 80 are located on approximately the same plane. For example, when a seed layer 30a is formed on the inner wall surface 27b by sputtering, the protruding portion P inhibits the growth of the sputtered film. For example, a continuous seed layer 30a is not formed on the inner wall surface 27b. Alternatively, the thickness of the seed layer 30a must be increased. Fine conductor circuits cannot be formed. In the embodiment, the protruding portion P is removed. In the embodiment, the thickness of the seed layer 30a formed by sputtering can be reduced. Even if the thickness of the seed layer 30a formed by sputtering is thin, a continuous seed layer 30a can be obtained. The thickness of the seed layer 30a is 0.05 μm or more and less than 0.5 μm.

[0045] Forming the opening 26 includes forming inorganic particles (second inorganic particles 92) 90 having protruding portions P. The protruding portions P protrude from the resin 80 that forms the inner wall surface 27b of the opening 26. The third inorganic particles 93 are formed by removing the protruding portions P of the inorganic particles (second inorganic particles 92) 90. The inner wall surface 27 of the opening 26 includes exposed surfaces 93b of the third inorganic particles 93. The exposed surfaces 93b of the third inorganic particles 93 are formed by removing the protruding portions P.

[0046] Obtaining the shape of the third inorganic particles 93 by cutting the substantially spherical second inorganic particles 92 along a plane includes removing the protruding portions P of the inorganic particles 90. The inner wall surfaces 27 of the actual openings 26 are substantially curved surfaces. Since the flat portions 93a are formed by removing the protruding portions P, the exposed surfaces 93b of the flat portions 93a include curved surfaces. In other words, forming a common surface between the flat portions 93a and the resin 80 includes forming the inner wall surfaces 27 that are substantially curved surfaces.

[0047] No irregularities are formed on the inner wall surface 27. The inner wall surface 27 is formed smoothly. The size of the irregularities can be controlled by controlling the conditions for processing the inner wall surface 27b after the laser light irradiation.

[0048] The inside of the opening 26 is cleaned. By cleaning the inside of the opening 26, resin residue generated when the opening 26 is formed is removed. The inside of the opening 26 is cleaned using plasma. That is, the cleaning is performed by a dry process. The cleaning includes a desmearing process. The first surface 22 of the resin insulating layer 20 is not affected by the plasma because it is covered with the protective film 50. At this point, no irregularities are formed on the first surface 22 of the resin insulating layer 20. The inorganic particles 90 are not exposed on the first surface 22. The first surface 22 is not roughened.

[0049] When processing the inner wall surface 27b after the laser light irradiation includes cleaning the inside of the opening 26, the embodiment can omit cleaning the inside of the opening 26.

[0050] 6E, after cleaning the inside of opening 26, protective film 50 is removed from resin insulating layer 20. If treating inner wall surface 27b after laser light irradiation includes cleaning the inside of opening 26, protective film 50 is removed from resin insulating layer 20 after treating inner wall surface 27b after laser light irradiation. When inner wall surface 27b after laser light irradiation is treated, protective film 50 covers first surface 22 of resin insulating layer 20.

[0051] After removing the protective film 50, the first surface 22 of the resin insulating layer 20 is cleaned. The first surface 22 is dry-etched. The dry etching is performed by sputtering using argon gas (argon sputtering). Figures 6F(a) and 6F(b) schematically show the first surface 22 of the resin insulating layer 20 before and after dry etching. As shown in Figures 6F(a) and 6F(b), the resin 80 forming the resin insulating layer 20 is removed by approximately 20 nm by dry etching. For example, the adhesive used to bond the protective film 50 to the resin insulating layer 20 is removed. The resin 80 is selectively removed by dry etching. The thickness of the resin 80 is reduced. Some of the inorganic particles 90 (second inorganic particles 92) are partially exposed from the upper surface of the resin 80 by dry etching. The first inorganic particles 91 are obtained by exposing the second inorganic particles 92 embedded in the resin 80 from the upper surface of the resin 80. The first inorganic particles 91 are formed from the second inorganic particles 92. The first inorganic particles 91 and the second inorganic particles 92 have the same shape. Both are spherical. As shown in FIG. 6F(b), the first inorganic particles 91 are formed of a first portion 91a protruding from the resin 80 and a second portion 91b buried in the resin 80. The first surface 22 of the resin insulating layer 20 is formed of the upper surface 80R of the resin 80 and an exposed surface 91aR of the first portion 91a protruding from the upper surface 80R of the resin 80. The exposed surface 91aR of the first portion 91a is exposed by dry etching. The first surface 22 of the resin insulating layer 20 is not roughened. Therefore, almost no recesses are formed on the first surface 22.

[0052] The ratio R is calculated, for example, using the cross-sectional view of the first inorganic particle 91 shown in FIG. 6F(b). FIG. 6F(b) is obtained by cutting the resin insulating layer 20 along a plane perpendicular to the upper surface 80R. The second conductor layer 30 is omitted from FIG. 6F(b). The second conductor layer 30 is formed on the first inorganic particle 91 in FIG. 6F(b). The exposed surface 91aR in FIG. 6F(b) is covered with the second conductor layer 30. Using FIG. 6F(b), the cross-sectional area 91aS of the first portion 91a is calculated. Similarly, the cross-sectional area 91S of the first inorganic particle 91 is calculated. For example, the ratio R is represented by the ratio of the cross-sectional area 91aS to the cross-sectional area 91S (cross-sectional area 91aS of the first portion 91a / cross-sectional area 91S of the first inorganic particle 91). For example, when the ratio R is evaluated, 50 first inorganic particles 91 are observed. The ratio R is satisfied by 50 first inorganic particles 91 .

[0053] As shown in FIG. 6G, a seed layer 30a is formed on the first surface 22 of the resin insulating layer 20. The seed layer 30a is formed by sputtering. The seed layer 30a is formed by a dry process. A first layer 31a is formed on the first surface 22 by sputtering. At the same time, the first layer 31a is formed on the inner wall surface 27 exposed from the opening 26 and on the pad 14 by sputtering. Almost no recesses are formed on the first surface 22. Therefore, the first layer 31a on the first surface 22 is formed to be almost flat. Then, a second layer 31b is formed on the first layer 31a by sputtering. The second layer 31b is formed to be almost flat. The first layer 31a and the second layer 31b are formed in a vacuum. The seed layer 30a is also formed on the upper surface of the pad 14 exposed from the opening 26 and on the inner wall surface 27 of the opening 26. The first layer 31a is formed of an alloy containing copper and aluminum. Aluminum has high ductility and malleability. Therefore, the adhesion between the resin insulating layer 20 and the first layer 31a is strong. Even if the resin insulating layer 20 expands and contracts due to heat cycles, the seed layer 30a containing aluminum is thought to be able to follow the expansion and contraction. Even if the first surface 22 of the resin insulating layer 20 is smooth, the seed layer 30a is unlikely to peel off from the resin insulating layer 20. Aluminum is thought to be easily oxidized. When the third inorganic particles 93 are inorganic particles 90 containing oxygen (oxygen element), the first layer 31a formed on the inner wall surface 27 is thought to adhere to the third inorganic particles 93 via the oxygen in the inorganic particles 90 forming the inner wall surface 27. The first layer 31a and the inner wall surface 27 are strongly bonded. In the embodiment, the adhesion between the inner wall surface 27 and the first layer 31a can be increased. The seed layer 30a is unlikely to peel off from the inner wall surface 27. It is preferable that the third inorganic particles 93 forming the inner wall surface 27 contain oxygen element. When the first inorganic particles 91 are inorganic particles 90 containing oxygen (oxygen element), it is believed that the first layer 31a formed on the first surface 22 adheres to the first inorganic particles 91 via the oxygen in the inorganic particles 90 forming the first surface 22. The first layer 31a and the first surface 22 are strongly bonded. In the embodiment, the adhesion between the first surface 22 and the first layer 31a can be increased. The seed layer 30a is less likely to peel off from the first surface 22. The first inorganic particles 91 forming the first surface 22 preferably contain oxygen element. The first layer 31a can further contain silicon.In this case, silicon is the specific metal, and the first layer 31a is formed of an alloy containing copper, aluminum, and silicon. If the inorganic particles 90 are glass particles, the first layer 31a and the first inorganic particles 91 both contain silicon. It is believed that they are strongly bonded together via the silicon. It is believed that this embodiment can further increase the adhesive strength between the first layer 31a and the first surface 22. The first layer 31a and the third inorganic particles 93 both contain silicon. It is believed that they are strongly bonded together via the silicon. It is believed that this embodiment can further increase the adhesive strength between the first layer 31a and the inner wall surface 27. The second layer 31b is formed of copper.

[0054] The first surface 22 has almost no recesses. The inner wall surface 27 has almost no recesses. The first surface 22 is formed almost smoothly. The inner wall surface 27 is formed almost smoothly. Therefore, even if the thickness of the sputtering film (first layer 31a, second layer 31b) is thin, the embodiment can form a continuous seed layer 30a. As a result, the embodiment can form fine wiring. The embodiment can form a high-density wiring group with, for example, L / S = 3 / 3 μm, 2 / 2 μm, etc.

[0055] The first layer 31a formed on the inner wall surface 27 may have a first portion 60a and a second portion 70a (FIG. 4). The first portion 60a and the second portion 70a are formed simultaneously. The first portion 60a and the second portion 70a are electrically connected. The leading end 62a of the first portion 60a is formed on the rear end 72a of the second portion 70a. The cross section of the first layer 31a covering the inner wall surface 27 has a substantially stepped shape. When the inner wall surface 27 has a step (first step), the first layer 31a is easily formed on the inner wall surface 27 so that the cross section of the first layer 31a has a stepped shape. Examples of sputtering conditions are as follows: The distance between the target and the first surface 22 of the resin insulating layer 20 is 50 mm or more and 250 mm or less. The voltage is 15 eV or more and 50 eV or less. The gas concentration is 0.1 Pa or more and 1.0 Pa or less.

[0056] The second layer 31b formed on the first layer 31a covering the inner wall surface 27 has a first portion 60b and a second portion 70b. The first portion 60b and the second portion 70b are formed simultaneously. The first portion 60b and the second portion 70b are electrically connected. The leading end 62b of the first portion 60b is formed on the trailing end 72b of the second portion 70b. The cross section of the second layer 31b formed on the inner wall surface 27 has a substantially stepped shape. The sputtering conditions are substantially the same as those described above.

[0057] In the printed wiring board 2 of the embodiment, a portion of the first portion 60 of the seed layer 30a covering the inner wall surface 27 of the opening 26 is formed on the second portion 70. The first portion 60 and the second portion 70 partially overlap. Therefore, the embodiment can increase the strength of the seed layer 30a. The seed layer 30a is less likely to break. The seed layer 30a is formed of a substantially smooth first portion 60 and a substantially smooth second portion 70. Therefore, transmission loss is small when a high-frequency signal is transmitted. A high-quality printed wiring board 2 is provided.

[0058] A resin layer for forming a plating resist is formed on the seed layer 30a. The resin layer is formed by attaching a photosensitive resin film (plating resist film) onto the seed layer 30a. The resin layer may also be formed by applying a liquid photosensitive resin onto the seed layer 30a.

[0059] After forming the resin layer, pressure is applied to the resin layer via gas. Applying pressure and forming the resin layer are performed separately. For example, when a plating resist film is attached to the seed layer 30a, pressure is applied to the plating resist film. The pressure applied at this time differs from the pressure applied via gas. When pressure is applied to the resin layer via gas, pressure is not applied to the resin layer via a medium other than gas. An example of a medium other than gas is vacuum. Heat is then applied to the resin layer. Applying pressure to the resin layer and applying heat to the resin layer are performed simultaneously. Heat is applied to the resin layer via gas. By applying pressure to the resin layer, embodiments can eliminate, reduce, or minimize voids between the seed layer 30a and the resin layer. By applying heat and pressure to the resin layer, embodiments can eliminate, reduce, or minimize voids between the seed layer 30a and the plating resist. For example, the intermediate substrate is placed in an apparatus (pressure apparatus) for applying pressure to the intermediate substrate. The intermediate substrate is a substrate having a seed layer 30a and a resin layer on the seed layer 30a. Then, gas is introduced into the pressure device. By introducing the gas into the pressure device, pressure is applied to the resin layer via the gas. The pressure device may have a heater. Heat is applied to the gas in the pressure device by the heater. Heat is applied to the resin layer via the gas. The intermediate substrate may further have a protective film on the resin layer. If a protective film is present on the resin layer, pressure is applied to the resin layer via the protective film and the gas. Pressure and heat are applied to the resin layer via the protective film and the gas.

[0060] The resin layer is irradiated with exposure light using DI exposure. DI exposure is also called direct exposure. DI exposure is a type of exposure method used to form a plating resist having a desired pattern. DI exposure irradiates light directly onto the resin layer without using a mask. Therefore, DI exposure has high productivity. Examples of DI exposure according to the embodiment are disclosed in JP 2006-301591 A and JP 2010-122526 A.

[0061] The DI exposure of the embodiment includes the following steps. As shown in FIG. 7 , the position of the boundary between the resin layer 300 and the seed layer 30a is measured by a sensor 400. The sensor 400 emits measurement light 500. The sensor 400 measures the position by detecting the measurement light 500 reflected by the detection object. The sensor 400 may measure the position of the upper surface of the resin layer 300 instead of the position of the boundary between the resin layer 300 and the seed layer 30a. If a protective film is present on the resin layer 300, the sensor 400 may measure the position of the boundary between the resin layer 300 and the protective film or the position of the upper surface of the protective film.

[0062] For example, the position of the boundary between the resin layer 300 and the seed layer 30a at location L1 is measured. The focus of the light for exposure is corrected based on the measurement results. Based on the correction results, the resin layer 300 formed over a predetermined distance (between location L1 and location L2) is irradiated with exposure light. The depth of focus is, for example, ±5 μm. Next, the position of the boundary between the resin layer 300 and the seed layer 30a at location L2 is measured. The focus of the light is corrected based on the measurement results. Based on the correction results, the resin layer 300 formed over a predetermined distance (between location L2 and location L3) is irradiated with exposure light. By repeating this process, light is irradiated to form a desired pattern on the resin layer 300.

[0063] In the conventional technology, the first surface 22 of the resin insulation layer 20 is roughened. In the conventional technology, unevenness is formed on the first surface 22 of the resin insulation layer 20. In the conventional technology, the seed layer 30a on the first surface 22 of the resin insulation layer 20 should follow the unevenness of the first surface 22 of the resin insulation layer 20. In the conventional technology, the upper surface of the seed layer 30a should have unevenness. Therefore, in the conventional technology, when the resin layer 300 is formed on the seed layer 30a, it is thought that a void 600 is formed between the seed layer 30a and the resin layer 300 due to the unevenness on the upper surface of the seed layer 30a. In the example of Figure 7, a void 600 is formed between the seed layer 30a and the resin layer 300 located at location L2.

[0064] Location L2 has a void 600 between the seed layer 30a and the resin layer 300. The resin layer 300 and the void 600 are made of different materials. Therefore, when the measurement light 500 emitted from the sensor 400 is irradiated onto location L2, the measurement light 500 should be refracted at the interface between the resin layer 300 and the void 600. Due to the influence of the void 600, the sensor 400 cannot accurately measure the position of the boundary between the seed layer 30a and the resin layer 300. As a result, the focus of the exposure light is not accurately corrected. The exposure light is irradiated onto the resin layer 300 formed at a predetermined distance (between locations L2 and L3) based on inaccurate information. For example, the light is not focused when the exposure light is irradiated. Design values ​​and actual values ​​are unlikely to match. The actually formed plating resist pattern is likely to differ from the design values. The design values ​​are the width of the plating resist and the spacing between adjacent plating resists. Conventional techniques are prone to voids 600. Conventional techniques make it difficult to form fine wiring.

[0065] On the other hand, the first surface 22 of the resin insulation layer 20 of the embodiment has almost no recesses. The seed layer 30a formed on the first surface 22 conforms to the first surface 22. The upper surface of the seed layer 30a has almost no recesses. When a resin layer is formed on the seed layer 30a, no voids are formed between the seed layer 30a and the resin layer, or the voids are few or small.

[0066] Location L1 does not have a void 600 between the seed layer 30a and the resin layer 300. Even if a void 600 exists, the size of the void 600 is small enough not to affect the position measurement. Therefore, when the measurement light 500 emitted from the sensor 400 is irradiated onto location L1, the sensor 400 can accurately measure the position of the boundary between the seed layer 30a and the resin layer 300. The focus of the exposure light is accurately corrected based on the measurement results. Based on the accurate information, the exposure light is irradiated onto the resin layer 300 formed at a predetermined distance (between location L1 and location L2). For example, the focus is correct when the exposure light is irradiated. The actually formed plating resist pattern substantially matches the design value. The embodiment is unlikely to have a void 600 that affects the position measurement. The embodiment can form fine wiring.

[0067] In the embodiment, DI exposure, which has high productivity, can be used to form the plating resist. The plating resist has openings for forming the first signal wiring 32, the second signal wiring 34, and the lands 36. If the first surface 22 has recesses, air due to the recesses is likely to be trapped between the plating resist and the seed layer 30a. However, in the embodiment, the first surface 22 has almost no recesses. Therefore, the seed layer 30a on the first surface 22 is formed almost flat. The seed layer 30a has almost no recesses. Air (voids) are unlikely to remain between the plating resist and the seed layer 30a. The contact area between the plating resist and the seed layer 30a is large. Even if the width of the plating resist for forming the space between the first signal wiring 32 and the second signal wiring 34 is 10 μm or less, the plating resist is unlikely to peel off from the top surface of the seed layer 30a. In the embodiment, the plating resist can be formed on the seed layer 30a even if the width of the plating resist is 3 μm or more and 8 μm or less. Even if the width of the plating resist is 6 μm or less, the plating resist is unlikely to peel off from the seed layer 30a.

[0068] An electrolytic plated layer 30b is formed on the seed layer 30a exposed from the plating resist. The electrolytic plated layer 30b is made of copper. The electrolytic plated layer 30b fills the opening 26. The seed layer 30a and the electrolytic plated layer 30b on the first surface 22 form a first signal wiring 32, a second signal wiring 34, and a land 36. The second conductor layer 30 is formed. The seed layer 30a and the electrolytic plated layer 30b in the opening 26 form a via conductor (first via conductor) 40. The via conductor 40 connects the pad 14 and the land 36. The first signal wiring 32 and the second signal wiring 34 form a pair wiring. The first via conductor 40 connects the conductor layer (first conductor layer) 10 and the conductor layer (second conductor layer) 30.

[0069] The plating resist is removed. The seed layer 30a exposed from the electroplated layer 30b is removed. The seed layer 30a is removed by wet etching. The etchant used for wet etching is an aqueous solution containing hydrogen peroxide and sulfuric acid. The first layer 31a and the second layer 31b are simultaneously removed by wet etching. The second conductor layer 30 and the via conductor 40 are simultaneously formed. The width D2 of the first layer 31a is larger than the width D3 of the second layer 31b, and the width D1 of the electroplated layer 30b is larger than the width D2 of the first layer 31a. The etching rate of the seed layer 30a is larger than the etching rate of the electroplated layer 30b. The etching rate of the seed layer is 1.1 to 1.5 times the etching rate of the electroplated layer. The seed layer 30a formed by sputtering has a higher ratio of amorphous structural portions to metal crystalline portions than the electroplated layer 30b. Generally, amorphous structural portions have many crystal defects. The greater the amount of crystal defects, the higher the etching rate. The etching rate of the seed layer 30a is higher than that of the electroplated layer 30b. Therefore, when the seed layer 30a is removed, the amount of etching of the electroplated layer 30b is small. The conductor circuit is less likely to be removed excessively. In this embodiment, the width of the conductor circuit is approximately equal to the design value. When the seed layer 30a is removed by etching, the width of the seed layer 30a forming the conductor circuit (first signal wiring 32, second signal wiring 34, land 36) of the second conductor layer 30 is smaller than the width of the electroplated layer 30b. If the first layer 31a is formed of a copper alloy and the second layer 31b is formed of copper, only the first layer 31a is an alloy. Therefore, in this embodiment, the difference in etching rate between the two can be increased. An etching solution that dissolves the second layer 31b more than the first layer 31a is preferred as the etching solution for removing the seed layer 30a. The width of the wiring (the distance between the sidewalls of the wiring) is smallest at the boundary portion B between the second layer 31b and the electroplated layer 30b. Since the stress is greatest at the boundary portion B, the adhesion between the first layer 31a and the first resin insulating layer 20 is improved.

[0070] Because the first surface 22 has almost no recesses, the embodiment allows the thickness of the first layer 31a to be small. The thickness of the first layer 31a is sufficiently thinner than the thickness of the electroplated layer 30b. Therefore, the orientation of the particles forming the first layer 31a is likely to be lower than the orientation of the particles forming the electroplated layer 30b. Alternatively, the density of the first layer 31a is likely to be lower than the density of the electroplated layer 30b. Alternatively, the crystallinity of the first layer 31a is likely to be lower than the crystallinity of the electroplated layer 30b. Because the first surface 22 has almost no recesses, the embodiment allows the thickness of the second layer 31b to be small. The thickness of the second layer 31b is sufficiently thinner than the thickness of the electroplated layer 30b. Therefore, the orientation of the particles forming the second layer 31b is likely to be lower than the orientation of the particles forming the electroplated layer 30b. Alternatively, the density of the second layer 31b is likely to be lower than the density of the electroplated layer 30b. Alternatively, the crystallinity of the second layer 31b tends to be lower than that of the electroplated layer 30b. Therefore, the etching rates of the first layer 31a and the second layer 31b are higher than that of the electroplated layer 30b. When the seed layer 30a exposed from the electroplated layer 30b is removed, the width D1 of the electroplated layer 30b is larger than the width D2 of the first layer 31a. The width D1 of the electroplated layer 30b is larger than the width D3 of the second layer 31b. The etching rate of the electroplated layer 30b is lower than that of the seed layer 30a. Therefore, the amount of soluble components in the etching solution consumed to dissolve the electroplated layer 30b is small. According to the embodiment, the soluble components reach the seed layer 30a sufficiently. The seed layer 30a is efficiently dissolved. The embodiment can form a signal wiring having a target width. The first layer 31a is covered with the second layer 31b. The soluble components are consumed to dissolve the second layer 31b. Therefore, in the embodiment, the amount of dissolution of the first layer 31a can be made smaller than the amount of dissolution of the second layer 31b. When the seed layer 30a exposed from the electroplated layer 30b is removed, the width D2 of the first layer 31a is larger than the width D3 of the second layer 31b.

[0071] A resin insulating layer (second resin insulating layer) 120 is formed on the first surface 22 of the first resin insulating layer 20 and the second conductor layer 30 in the same manner as the first resin insulating layer 20. The second resin insulating layer 120 has a first surface 122, a second surface 124 opposite the first surface 122, and an opening (opening for a via conductor) 126. The second surface 124 of the second resin insulating layer 120 faces the second conductor layer 30. The opening 126 exposes the second conductor layer 30. A conductor layer (third conductor layer) 130 is formed on the first surface 122 of the second resin insulating layer 120 in the same manner as the second conductor layer 30. A via conductor (second via conductor) 140 connecting the second conductor layer 30 and the third conductor layer 130 is formed in the opening (second opening) 126 in the same manner as the first via conductor 40. The printed wiring board 2 of the embodiment is obtained.

[0072] Each resin insulation layer is formed of resin 80 and inorganic particles 90. The resin forming each resin insulation layer is the same as the resin 80 forming the first resin insulation layer 20. The inorganic particles forming each resin insulation layer are the same as the inorganic particles 90 forming the first resin insulation layer 20. Each resin insulation layer contains first inorganic particles, second inorganic particles, and third inorganic particles, and the particles in each resin insulation layer are the same as the particles in the first resin insulation layer 20. Each resin insulation layer has a first surface, and the first surface of each resin insulation layer is the same as the first surface 22 of the first resin insulation layer 20. Each resin insulation layer has openings (openings for via conductors), and the openings penetrating each resin insulation layer are the same as the openings 26 penetrating the first resin insulation layer. The inner wall surfaces of the openings penetrating each resin insulation layer are the same as the inner wall surface 27 of the openings 26 penetrating the first resin insulation layer 20.

[0073] Each conductor layer is formed of a seed layer and an electrolytically plated layer on the seed layer. The seed layer that forms each conductor layer and the seed layer 30a that forms the second conductor layer 30 are the same. The first layer that forms each conductor layer and the first layer 31a that forms the second conductor layer 30 are the same. The second layer that forms each conductor layer and the second layer 31b that forms the second conductor layer 30 are the same. The electrolytically plated layer that forms each conductor layer and the electrolytically plated layer 30b that forms the second conductor layer 30 are the same.

[0074] Each via conductor is formed of a seed layer and an electroplated layer on the seed layer. The seed layer forming each via conductor is the same as the seed layer 30a forming the first via conductor 40. The first layer forming each via conductor is the same as the first layer 31a forming the first via conductor 40. The second layer forming each via conductor is the same as the second layer 31b forming the first via conductor 40. The electroplated layer forming each via conductor is the same as the electroplated layer 30b forming the first via conductor 40.

[0075] In the printed wiring board 2 of the embodiment, almost no recesses are formed on the first surface 22 of the resin insulating layer 20. The first surface 22 of the resin insulating layer 20 has almost no recesses. The upper surface of the seed layer 30a formed on the first surface 22 of the resin insulating layer 20 by sputtering also has almost no recesses. When an electrical signal propagates through the signal wiring, the embodiment can reduce transmission loss. Because the seed layer 30a is formed by sputtering, the adhesive strength between the resin insulating layer 20 and the seed layer 30a is high. The conductor circuit is less likely to peel off from the resin insulating layer 20. Even if the thickness of the sputtering film is thin, the embodiment can form a continuous seed layer 30a. When the seed layer 30a is removed, the embodiment can reduce the amount of etching. Furthermore, because the upper surface of the seed layer 30a is substantially flat, the embodiment can form a fine plating resist having dimensions close to the target value using DI exposure. The embodiment can form fine signal wiring. The embodiment can form a high-quality printed wiring board 2.

[0076] Even if the thickness of the sputtering film is thin, the embodiment can form a continuous seed layer 30a. The inner wall surface 27 of the opening 26 is formed by the flat portion 93a of the third inorganic particles 93 and the resin 80. The flat portion 93a and the surface 80a of the resin 80 that forms the inner wall surface 27 form a common plane. The inner wall surface 27 is formed smoothly. Therefore, a seed layer 30a having a uniform thickness is formed on the inner wall surface 27 of the opening 26. The thickness of the seed layer 30a is thin. The first surface 22 is formed by the upper surface 80R of the resin 80 and the exposed surface 91aR of the first portion 91a exposed from the upper surface 80R of the resin 80. The first surface 22 does not have a recess. Therefore, a seed layer 30a having a uniform thickness is formed on the first surface 22. The thickness of the seed layer 30a is thin. When the seed layer 30a is removed, the etching amount is small. Therefore, the etching amount of the electroplated layer 30b is small. The second conductor layer 30 having the first signal wiring 32 and the second signal wiring 34 has a width as designed. Fine wiring is formed. A high-quality printed wiring board 2 is provided.

[0077] When the first layer 31a of the seed layer 30a contains aluminum and the third inorganic particles 93 contain oxygen elements, the embodiment can increase the adhesive strength between the first layer 31a and the inner wall surface 27. Even if the diameter of the opening 26 is small, the via conductor 40 is unlikely to peel off from the inner wall surface 27. Therefore, the connection resistance through the via conductor 40 is unlikely to increase. As shown in FIG. 6G, the diameter D of the via conductor 40 (the diameter of the opening 26) is measured on the pad 14. The diameter D is 20 μm or more and 50 μm or less. Even if the length of each side of the printed wiring board 2 exceeds 50 mm, the connection resistance through the via conductor 40 is unlikely to increase. Even if the length of each side of the printed wiring board 2 is 100 mm or more, the connection resistance is unlikely to increase over a long period of time. A printed wiring board 2 with high connection reliability is provided.

[0078] In the embodiment, the thickness of the first layer 31a forming the via conductor 40 can be reduced. In the embodiment, the thickness of the second layer 31b forming the via conductor 40 can be reduced. The first layer 31a and the second layer 31b form the seed layer 30a. In the embodiment, the volume of the opening for the via conductor after the seed layer is formed can be increased. The opening for the via conductor after the seed layer is formed may also be called the opening after the seed layer is formed. By forming an electrolytic plating layer in the opening after the seed layer is formed, a via conductor consisting of the seed layer and the electrolytic plating layer is formed. Even if the diameter of the opening for the via conductor is small, the electrolytic plating solution easily enters the opening for the via conductor after the seed layer is formed. The electrolytic plating layer forming the via conductor is less likely to contain voids. A low-resistance via conductor is formed. An example of an opening 260 after the seed layer is formed is shown in Figure 6G. The opening 260 after the seed layer is formed is surrounded by the seed layer. The bottom and side surfaces of the opening 260 are in contact with the seed layer.

[0079] In the embodiment, the thickness of the first layer 31a made of an alloy containing aluminum can be reduced. The aluminum content in the signal wiring is small and the copper content is large. In the embodiment, low-resistance signal wiring can be provided. In the embodiment, low-resistance signal wiring having high adhesion to the resin insulating layer can be provided.

[0080] In the printed wiring board 2 of the embodiment, the first surface 22 of the resin insulation layer 20 has almost no recesses. The standard deviation of the relative dielectric constant in the vicinity of the first surface 22 of the resin insulation layer 20 is suppressed from increasing. The relative dielectric constant of the first surface 22 of the resin insulation layer 20 does not vary significantly depending on the location. Even when multiple signal wirings are in contact with the first surface 22 of the resin insulation layer 20, the embodiment can reduce the difference in the propagation speed of electrical signals between the signal wirings. Therefore, noise is reduced in the printed wiring board 2 of the embodiment. Even when a logic IC is mounted on the printed wiring board 2 of the embodiment, data transmitted through each signal wiring arrives at the logic IC almost simultaneously. The embodiment can reduce malfunction of the logic IC. Even when the length of each signal wiring is 5 mm or more, the embodiment can reduce the difference in propagation speed. Even when the length of each signal wiring is 10 mm or more and 20 mm or less, the embodiment can reduce malfunction of the logic IC. The first surface 122 of the second resin insulation layer 120 is similar to the first surface 22 of the resin insulation layer 20. Therefore, the signal wiring in the third conductor layer 130 has the same effect as the signal wiring in the second conductor layer 30. A high-quality printed wiring board 2 is provided.

[0081] When the first layer contains silicon as the specific metal and the inorganic particles are glass particles, the first layer and third inorganic particles 93 on the inner wall surface contain silicon. The first layer and first inorganic particles 91 on the first surface contain silicon. It is believed that the two are strongly bonded via silicon. The seed layer, which is made of an alloy containing copper, aluminum, and silicon, is difficult to peel off from the inner wall surface. The seed layer is difficult to peel off from the first surface. The seed layer is difficult to peel off from the resin insulating layer.

[0082] When the first layer contains aluminum and the inorganic particles (first inorganic particles 91, second inorganic particles 92, third inorganic particles 93) 90 contain oxygen, it is believed that the first layer and the inorganic particles (oxygen-containing inorganic particles such as glass particles) 90 are strongly bonded. When the first layer contains aluminum and the inorganic particles 90 contain oxygen, the first layer may be formed of copper, aluminum, and impurities.

[0083] [Another Example 1 of the embodiment] In another embodiment, the specific metal is selected from titanium, nickel, chromium, tin, and calcium.

[0084] [Second Alternative Embodiment] In a second modification of the embodiment, the first layers 11a, 31a of the seed layers 10a, 30a are formed of copper and a second element. The second element is selected from silicon, aluminum, titanium, nickel, chromium, carbon, oxygen, tin, and calcium. The first layers 11a, 31a are formed of an alloy containing copper. The second layers 11b, 31b are formed of copper. The amount of copper forming the second layers 11b, 31b is 99.9 at% or more. Preferably, the amount of copper is 99.95 at% or more.

[0085] Each cross-sectional view is obtained by cutting printed wiring board 2 along a plane perpendicular to first surface 22. When the cross-sectional view includes a conductive circuit, the side surface of the conductive circuit is perpendicular to the cross-sectional view.

[0086] In this specification, the term "plane" is used to refer to the shape of the inner wall surface 27, the shape of the flat portion 93a, and the shape of the third inorganic particles 93. The meaning of the term "plane" used in these respects is shown in FIGS. 1 and 3. That is, in FIGS. 1 and 3, the inner wall surface 27 is depicted as being almost straight. The shape of the inner wall surface 27 in FIGS. 1 and 3 is almost straight. In this specification, the term "plane" includes a substantially straight line shown in a cross section. As shown in the cross section of the third inorganic particle 93 in FIGS. 1 and 3, in a cross section, cutting with a plane includes cutting with a straight line. In this specification, the term "plane" does not mean a perfect plane but includes a substantially flat surface. A substantially flat surface may include small irregularities. [Explanation of symbols]

[0087] 2: Printed wiring board 4: Insulating layer 10: First conductor layer 20: Resin insulating layer 22: 1st page 24:Second side 26 :Aperture 27: Inner wall surface 30: Second conductor layer 30a: seed layer 31a: 1st layer 31b: 2nd layer 40: Via conductor 80: Resin 90: Inorganic particles 91: 1st inorganic particle 92:Second inorganic particle 93:Third inorganic particle

Claims

1. forming a resin insulating layer on a first conductor layer, the resin insulating layer having a first surface and a second surface opposite to the first surface; forming a protective film on the first surface of the resin insulating layer; forming an opening for a via conductor that penetrates the protective film and the resin insulating layer simultaneously and reaches the first conductor layer; removing the protective film from the resin insulating layer after forming the opening; cleaning the first surface of the resin insulating layer; forming a second conductor layer on the first surface of the resin insulating layer; forming a via conductor in the opening that connects the first conductor layer and the second conductor layer, the resin insulating layer includes a resin and inorganic particles, the inorganic particles include first inorganic particles partially embedded in the resin and second inorganic particles completely embedded in the resin, the first inorganic particles are approximately spherical in shape, and the second inorganic particles are approximately spherical in shape; the cleaning step includes selectively removing the resin so that some of the second inorganic particles protrude from the first surface of the resin insulating layer; the resin is selectively removed to form the first inorganic particles from the second inorganic particles; the first inorganic particles are formed of a first portion protruding from the resin and a second portion buried in the resin, and the first surface is formed of an upper surface of the resin and an exposed surface of the first portion exposed from the upper surface, Forming the second conductor layer includes forming a seed layer by sputtering on the first surface of the resin insulating layer, forming a plating resist on the seed layer using DI exposure, forming an electrolytic plating layer on the seed layer exposed from the plating resist, removing the plating resist, and removing the seed layer exposed from the electrolytic plating layer.

2. 2. The method for manufacturing a printed wiring board according to claim 1, wherein the first surface of the resin insulating layer is not roughened before forming the seed layer.

3. 2. A method for manufacturing a printed wiring board according to claim 1, wherein the second conductor layer has a conductor circuit, the seed layer has a first layer formed on the first surface and a second layer formed on the first layer, the conductor circuit is formed by the seed layer and the electroplated layer on the seed layer, and in a cross section of the conductor circuit, the width of the first layer is larger than the width of the second layer, and the width of the electroplated layer is larger than the width of the first layer.

4. 2. A method for manufacturing a printed wiring board according to claim 1, wherein the seed layer has a first layer formed on the first surface and a second layer formed on the first layer, the first layer being made of an alloy containing copper and aluminum, and the second layer being made of copper.

5. 2. The method for manufacturing a printed wiring board of claim 1, wherein the inorganic particles further include third inorganic particles that form the inner wall surface of the opening, the third inorganic particles are formed from the second inorganic particles by processing the inner wall surface, the third inorganic particles have flat portions, the shape of the third inorganic particles is approximately spherical, and the flat portions form the inner wall surface.

6. 6. A method for manufacturing a printed wiring board according to claim 5, wherein forming the opening includes forming inorganic particles having protruding portions that protrude from the resin that forms the inner wall surface of the opening, and the third inorganic particles are formed by removing the protruding portions of the inorganic particles.

7. 2. The method for manufacturing a printed wiring board according to claim 1, wherein the cross section of the seed layer on the inner wall surface of the opening has a substantially stepped shape.

8. 2. The method for manufacturing a printed wiring board of claim 1, wherein forming the plating resist includes forming a resin layer for forming the plating resist on the seed layer and applying pressure to the resin layer via a gas.

9. 9. The method for manufacturing a printed wiring board according to claim 8, wherein the application of pressure is performed after the formation of the resin layer.

10. 10. The method for manufacturing a printed wiring board according to claim 9, wherein forming the plating resist further includes applying heat to the resin layer, and applying the pressure and applying the heat are carried out simultaneously.

11. 11. The method for manufacturing a printed wiring board according to claim 10, wherein the application of pressure and the formation of the resin layer are carried out separately.

12. 12. The method for manufacturing a printed wiring board according to claim 11, wherein the heat is applied via the gas.

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