Light-emitting device and display device

Abstract

To achieve both high definition and stable electrical connection between layers.SOLUTION: In an LED display device 1, during the manufacture of an LED display unit 2, a protrusion 32C is formed from a GaAs layer 32, a cathode connection wiring layer 35C is formed on top of this, and a wiring hole 72C is formed penetrating a transparent insulating layer 41 and a transparent insulating layer 36 above it. This makes it possible in the LED display device 1 to keep the ratio of the depth to the diameter of the wiring hole 72C etc. to a sufficiently small value, such that the sputtering of the seed layer can reach the bottom of the wiring hole 72C in sputtering, and a good interlayer connection electrode 43C can be formed on the inner surface of the wiring hole 72C, thereby stabilizing the electrical connection between layers.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a light emitting device and a display device, and is suitable for application to, for example, a light emitting device in which a semiconductor element is mounted on a circuit board. [Background technology]

[0002] In recent years, a display device that displays an image has been proposed that uses a light-emitting device that selectively drives a plurality of semiconductor elements mounted in a matrix on a circuit board to emit light (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2023-32326 A (Figs. 1 and 2, etc.) Summary of the Invention [Problem to be solved by the invention]

[0004] In the light-emitting device described above, each pixel has a structure in which semiconductor layers of each color that emit red, green, and blue light are stacked, and vias may be appropriately formed to make electrical connections between the layers.

[0005] On the other hand, in light-emitting devices, it is conceivable to reduce the area of ​​each semiconductor element on the light-emitting surface in response to demands for higher definition, etc. In this case, the diameter of the vias in the light-emitting device will also be reduced along with other parts. On the other hand, in light-emitting devices, the required strength, manufacturing constraints, etc. may make it difficult to sufficiently reduce the thickness.

[0006] As a result, in light-emitting devices, when vias are formed by sputtering during the semiconductor manufacturing process, the depth relative to the diameter of the hole that forms the via (called the aspect ratio) is relatively large, which means that the sputtered seed layer does not reach far enough, and there is a risk that an appropriate via will not be formed.

[0007] The present invention has been made in consideration of the above points, and aims to propose a light-emitting device and a display device that can achieve both high definition and stable electrical connections between layers. [Means for solving the problem]

[0008] In order to solve this problem, the light-emitting device of the present invention has a substrate layer on which a conductive substrate wiring member is provided, a first layer including a first light-emitting element stacked on the substrate layer and having a first light-emitting portion whose light-emitting direction is in the opposite direction to the substrate layer, and an insulating member covering the first light-emitting element, and a second layer stacked on the light-emitting direction side of the first layer and including a second light-emitting element having a second light-emitting portion, the second light-emitting element having a second light-emitting portion, the second light-emitting element having a second light-emitting portion arranged in a position that overlaps with the first light-emitting portion of the first light-emitting element when viewed from the light-emitting direction, and the first layer has a protrusion that is part of the first light-emitting element and protrudes in the light-emitting direction at a position different from the first light-emitting portion when viewed from the light-emitting direction, a conductive first wiring member arranged above the protrusion on the light-emitting direction side, an opening formed in a range from the first layer light-emitting surface, which is the surface on the light-emitting direction side, to the first wiring member arranged above the protrusion, and an opening electrode arranged in the opening and electrically connecting the second layer to the first wiring member.

[0009] Furthermore, a display device according to the present invention includes the above-described light-emitting device.

[0010] In the present invention, a protrusion is formed in the first layer by a first light-emitting element having a light-emitting portion, a first wiring member is arranged on the light-emitting side of the protrusion, an opening is provided on the light-emitting side that communicates with the second layer, and an aperture electrode is arranged in this opening. Therefore, compared to a configuration in which a protrusion is not formed, the present invention allows the first wiring member to be arranged closer to the light-emitting side, and the depth of the opening, which is the length along the light-emitting direction, can be kept short. As a result, even when the diameter of the opening is made small, the present invention allows the aspect ratio to be kept sufficiently small, and stable electrical connection can be obtained at the aperture electrode. [Effects of the Invention]

[0011] According to the present invention, it is possible to realize a light emitting device and a display device that can achieve both high definition and stable electrical connection between layers. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view showing the configuration of an LED display device. [Figure 2] 2A and 2B are a schematic plan view and a schematic side view showing the configuration of an LED display unit. [Figure 3] 3 is a schematic diagram showing division of a pixel unit into a plurality of regions in an XY plane. [Figure 4] 3A to 3C are schematic side views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 5] 3A to 3C are schematic side views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 6] 3A to 3C are schematic side views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 7] 3A to 3C are schematic side views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 8] 3A to 3C are schematic plan views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 9] 3A to 3C are schematic plan views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 10] 3A to 3C are schematic plan views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 11] 3A to 3C are schematic plan views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 12] 3A to 3C are schematic plan views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 13] FIG. 2 is a schematic side view showing the configuration of a GaAs layer. [Figure 14]3A to 3C are schematic cross-sectional views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 15] 3A to 3C are schematic cross-sectional views illustrating a manufacturing process of the LED display unit according to the first embodiment. [Figure 16] FIG. 2 is a schematic plan view showing wiring between pixel units in the first embodiment. [Figure 17] 10A to 10C are schematic side views showing a manufacturing process of the LED display unit according to the second embodiment. [Figure 18] 10A to 10C are schematic side views showing a manufacturing process of the LED display unit according to the second embodiment. [Figure 19] 10A to 10C are schematic side views showing a manufacturing process of the LED display unit according to the second embodiment. [Figure 20] 10A to 10C are schematic side views showing a manufacturing process of the LED display unit according to the second embodiment. [Figure 21] 10A to 10C are schematic side views showing a manufacturing process of the LED display unit according to the second embodiment. [Figure 22] 10A to 10C are schematic side views showing a manufacturing process of the LED display unit according to the second embodiment. [Figure 23] 10A to 10C are schematic plan views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 24] 10A to 10C are schematic plan views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 25] 10A to 10C are schematic plan views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 26] 10A to 10C are schematic plan views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 27] 10A to 10C are schematic plan views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 28] 10A to 10C are schematic plan views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 29] 10A to 10C are schematic cross-sectional views illustrating a manufacturing process of the LED display unit according to the second embodiment. [Figure 30] 10A to 10C are schematic cross-sectional views illustrating a manufacturing process of the LED display unit according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[0014] 1. First Embodiment [1-1. LED display device configuration] As shown in Fig. 1, an LED (Light Emitting Diode) display device 1 includes an LED display unit 2, a heat dissipation member 3, a connection cable 4, and a connection terminal unit 5. The LED display device 1 as a display device is also called a micro LED display, and is a display device in which a set of LED elements that respectively emit red, green, and blue light corresponds to one pixel. In the first embodiment, each LED element is driven by a so-called passive matrix driving method.

[0015] As shown in the schematic diagrams of FIGS. 2(A) and 2(B), the LED display unit 2 serving as a light-emitting device has a thin film layer group 20 provided on the surface of a flat substrate layer 10 on the +Z direction side.

[0016] The substrate layer 10 has a wiring layer, and drive elements and drive circuits (neither of which are shown) connected to the wiring layer. It is a substrate that is electrically connected to the LEDs of each pixel and selectively drives the LEDs. Hereinafter, the direction from left to right on the paper in Figure 1 will be referred to as the +X direction, the direction from the bottom left to the top right on the paper will be referred to as the +Y direction, and the direction from bottom to top on the paper will be referred to as the +Z direction. Hereinafter, the surface on the +Z direction side of each part will be referred to as the top surface, and the surface on the -Z direction side will be referred to as the bottom surface.

[0017] The thin film layer group 20 is configured by sequentially stacking three thin film layers, namely, a first thin film layer 30, a second thin film layer 40, and a third thin film layer 50, from the -Z direction to the +Z direction. In addition, in the thin film layer group 20, a plurality of pixel units 8 constituting each pixel are formed so as to be arranged in a lattice pattern (matrix pattern) along the X direction and the Y direction within the display area 2A of the LED display unit 2. In other words, in the LED display unit 2, a plurality of pixel units 8 are arranged in an array along the X direction and the Y direction.

[0018] Each pixel unit 8 occupies a square region when viewed from the Z direction side, and is arranged in a grid pattern along the X and Y directions. Specifically, the length of each pixel unit 8 in both the X and Y directions is 1 mm or more, and the thickness in the Z direction (i.e., the thickness of the thin film layer group 20) is 100 μm or less. Hereinafter, the surface of each pixel unit 8 closest to the Z direction, i.e., the surface from which light is emitted, will also be referred to as the light-emitting surface 8S, and the length of one side of each pixel unit 8 in the X and Y directions will also be referred to as the pixel length 8L.

[0019] As shown in FIG. 2(B), in each pixel unit 8, a first light-emitting unit 39 that emits red light is formed in the first thin film layer 30, a second light-emitting unit 49 that emits green light is formed in the second thin film layer 40, and a third light-emitting unit 59 that emits blue light is formed in the third thin film layer 50. Each pixel unit 8 also has wiring and the like that supplies power to the first light-emitting unit 39, the second light-emitting unit 49, and the third light-emitting unit 59 (hereinafter collectively referred to as light-emitting units 9). The light-emitting units 9 of each color are each configured as inorganic light-emitting diodes, and emit light in response to power supplied via the wiring and the like. This allows each pixel unit 8 to emit light of various colors and light intensities from its light-emitting surface 8S in the Z direction (details will be described later).

[0020] In this way, the LED display unit 2 is a display device in which multiple pixel units 8 are arranged in a matrix on a substrate layer 10, which is an active matrix circuit board, and an image can be displayed in the display area 2A by making each pixel unit 8 emit light of a desired color.

[0021] The heat dissipation member 3 (FIG. 1) is made of a metal material with relatively high thermal conductivity, such as aluminum, and is configured as a flat rectangular parallelepiped overall. The heat dissipation member 3 is installed so as to abut against the LED display unit 2 on the -Z direction side of the LED display unit 2, i.e., on the side opposite to the surface on which images are displayed, thereby dissipating heat from the substrate layer 10. The connection cable 4 is electrically connected to a predetermined control device (not shown) via a connection terminal portion 5, thereby transmitting image signals supplied from the control device to the substrate layer 10. As a result, the LED display device 1 displays an image based on the image signal supplied from the control device (not shown) or the like in the display area 2A of the LED display unit 2.

[0022] Hereinafter, the direction in which light emitted from the display area 2A of the LED display unit 2 mainly travels, and the direction perpendicular to the upper surface of the substrate layer 10 (the surface on which the thin film layers are formed) or the upper surfaces of the thin film layers (first thin film layer 30, second thin film layer 40, and third thin film layer 50) (i.e., Z direction) will also be referred to as the light emission direction E. Furthermore, below, the direction in which the first thin film layer 30, second thin film layer 40, and third thin film layer 50 are stacked (i.e., Z direction) will also be referred to as the stacking direction.

[0023] [1-2. LED display configuration] Next, the detailed configuration of the LED display unit 2 (FIG. 2) will be described with reference to FIGS. 3 to 12, focusing on one pixel unit 8. The LED display unit 2 is manufactured by sequentially stacking layers from the bottom to the top through semiconductor processes. That is, the LED display unit 2 is roughly divided into a substrate layer 10, a first thin film layer 30, a second thin film layer 40, and a third thin film layer 50, which are manufactured in this order.

[0024] Fig. 3(A) is a schematic diagram showing how the entire area on the XY plane is divided into multiple areas when one pixel unit 8 is viewed from the +Z direction in the first embodiment. Figs. 4 to 7 are schematic side views viewed from the -Y direction, showing each step of manufacturing the pixel unit 8. Figs. 8 to 12 are schematic plan views viewed from the +Z direction, showing some steps of manufacturing the pixel unit 8.

[0025] 3, in the first embodiment, on the XY plane, a circular area WA is provided in the center of a square area (hereinafter referred to as the entire area WO) corresponding to one pixel unit 8. This area WA corresponds to the above-mentioned light-emitting units 9 (39, 49, and 59), and its diameter is approximately 1 / 3 to 1 / 4 of the length of one side of the entire area WO (i.e., the pixel length 8L (FIG. 2)).

[0026] In pixel unit 8, the upper half of the area remaining after excluding area WA from entire area WO is area WB. Furthermore, in pixel unit 8, the area remaining after excluding areas WA and WB from entire area WO is roughly divided into four areas along the X direction, which are areas WC, WD, WE, and WF from the -X side to the +X side. In the following, the combined area of ​​areas WC and WD will be referred to as area WCD, and the combined area of ​​areas WE and WF will be referred to as area WEF.

[0027] [1-3. Manufacturing of LED display parts] Next, the manufacturing process of the LED display unit 2 will be explained for each step of the substrate layer 10, the first thin film layer 30, the second thin film layer 40, and the third thin film layer 50.

[0028] First, a substrate layer 10 is formed. In the first step, as shown in the side view of Fig. 4(A) and the plan view of Fig. 8(A), a circuit board 11 is formed over the entire region WO, and a substrate wiring portion 12 is provided on the upper surface of the circuit board 11. The circuit board 11 is made mainly of, for example, silicon.

[0029] The substrate wiring portion 12, which serves as a substrate wiring member, is made of a conductive metal material such as gold, copper, titanium, etc. The substrate wiring portion 12 is formed with a through wiring portion 12Y, which is a portion that penetrates the entire region WO in the Y direction, slightly on the +X side from the center in the X direction, and an extended wiring portion 12X, which is a portion of the through wiring portion 12Y that extends from within the region WE toward the region WF along the X direction.

[0030] [1-3-1. Manufacturing of the first thin film layer] From this point on, a red first thin film layer 30 is sequentially formed on the upper side of the substrate layer 10. In the first step of the first thin film layer 30 as the first layer, a transparent insulating layer 31 is formed over the entire area on the upper side (+Z direction side) of the substrate layer 10, as shown in the side view of Figure 4(B). This transparent insulating layer 31 is made of a transparent insulating material such as SiO2, SiN, transparent polyimide, etc., and has the property of sufficiently transmitting visible light (i.e., being transparent) and the property of providing good electrical insulation.

[0031] In the next step, as shown in the side view of Fig. 4(C), a GaAs layer 32 is attached to the entire region WO on the upper side of the transparent insulating layer 31. The GaAs layer 32 as the first light-emitting element is manufactured, for example, by a method in which a functional layer grown on a separate substrate (not shown) via a sacrificial layer is peeled off by sacrificial layer etching, or by a method in which a layer grown on a sapphire substrate is peeled off by laser lift-off. As shown in the schematic side view of Fig. 13(A), this GaAs layer 32 is bonded to a lower (-Z side) n-type semiconductor layer 32TN and an upper (+Z side) p-type semiconductor layer 32TP, and the bonded portion between the two forms a light-emitting layer 32TL.

[0032] In the next step, as shown in the side view of Fig. 4(D) and the plan view of Fig. 8(B), a portion of the GaAs layer 32 is removed by etching. In this step, the patterning is performed such that the central region WA is left as the red light-emitting portion 32A and the region WCD is left as the red electrode connection portion 32D, while the GaAs layer 32 is removed in the other regions WB, WE, and WF.

[0033] In this process, a protrusion 32C is formed in the region WC on the -X side of the region WCD, slightly toward the -Y direction from the center in the Y direction, so as to have a square shape when viewed from the Z direction. That is, in the GaAs layer 32 in the region WCD, the protrusion 32C remains completely unremoved, as shown in the schematic side view of FIG. 13(B), while in the portion other than the protrusion 32C, the p-type semiconductor layer 32TP, the light-emitting layer 32TL, and a portion of the n-type semiconductor layer 32TN are removed from above. In the region WCD of the GaAs layer 32, the remaining portion of the n-type semiconductor layer 32TN forms the red electrode connection portion 32D (hereinafter also referred to as the first-layer electrode connection portion). In other words, the distance to the surface in the +Z direction, i.e., the height, of the GaAs layer 32 relative to the interface with the transparent insulating layer 31 is the same for the red light-emitting portion 32A and the protrusion 32C.

[0034] Furthermore, in this process, as shown in Fig. 14(A) which is a cross-sectional view taken along line A1-A2 in Fig. 8(B), the transparent insulating layer 31 is partially removed by etching at a position directly above the extended wiring portion 12X (Fig. 8(A)) of the substrate wiring portion 12 in the region WF, to form a wiring hole 71F. This wiring hole 71F is a circular hole that penetrates the transparent insulating layer 31 in the Z direction and reaches the upper surface of the extended wiring portion 12X in the substrate layer 10. Furthermore, the wiring hole 71F has a shape in which the diameter decreases as it extends downward (in the -Z direction), i.e., it has a mortar shape.

[0035] In the next step, as shown in the side view of FIG. 4(E) and the plan view of FIG. 9(A), electrodes 33 are formed from a predetermined conductive material in three mutually spaced locations. Specifically, an anode electrode 33A serving as the anode terminal of the first light-emitting section 39 is formed in region WA, and a cathode electrode 33D (hereinafter also referred to as the first-layer electrode) serving as the cathode terminal of the first light-emitting section 39 is formed in region WD. Furthermore, as shown in FIG. 14(B), which is a cross-sectional view taken along line B1-B2 in FIG. 9(A), an interlayer connection electrode 33F is formed in region WF so as to cover the inner surface of the wiring hole 71F. This interlayer connection electrode 33F is electrically connected to the extended wiring section 12X of the substrate layer 10.

[0036] In the next step, as shown in the side view of FIG. 4(F) and the plan view of FIG. 9(B), insulating layers 34 are first formed at three mutually spaced locations. Specifically, insulating layer 34A is formed from the anode electrode 33A in region WA toward the Y direction to reach the interior of region WB. Furthermore, insulating layer 34C (hereinafter also referred to as insulating member or first protruding insulating member) is formed linearly along the X direction from the −X side end of protrusion 32C in region WC to the cathode electrode 33D in region WD. Furthermore, insulating layer 34E is formed between cathode electrode 33D in region WD and interlayer connection electrode 33F in region WF, linearly connecting mainly within region WE along the X direction.

[0037] Next, in this process, multiple wiring layers 35 are formed using a conductive material. Specifically, a linear anode-adjacent wiring layer 35B is formed along the X direction at a location slightly away from the Y-direction end of region WB. A linear anode connection wiring layer 35A is formed along the Y direction between the anode electrode 33A in region WA and the X-direction center of the anode-adjacent wiring layer 35B in region WB. A linear cathode connection wiring layer 35C (hereinafter also referred to as a first wiring member) is formed along the X direction from near the −X-side end of the protrusion 32C in region WC, via the cathode electrode 33D in region WD, to the interlayer connection electrode 33F in region WF. In other words, the cathode connection wiring layer 35C is disposed above the protrusion 32C in region WC, i.e., above the light-emitting direction E side of the protrusion 32C.

[0038] Furthermore, in this process, a transparent insulating layer 36 is formed so as to cover the entire region WO from above. This transparent insulating layer 36 is made of a transparent and insulating material, similar to the transparent insulating layer 31. This results in the first thin film layer 30 being in a substantially completed state. For convenience of explanation, hereinafter, the upper surface of the transparent insulating layer 36, which is the upper surface of the first thin film layer 30 (i.e., the surface on the +Z direction side), will also be referred to as the first-layer light-emitting surface.

[0039] [1-3-2. Manufacturing of the second thin film layer] From this point on, the green second thin film layer 40 is sequentially formed on the upper side (+Z direction side) of the first thin film layer 30. In the first step of the second thin film layer 40 as the second layer, a transparent insulating layer 41 is formed over the entire area above the transparent insulating layer 36, as shown in the side view of FIG. 5(A). This transparent insulating layer 41 is made of a material that is transparent and insulating, similar to the transparent insulating layer 31 and the like.

[0040] In this process, a GaN layer 42 is subsequently attached to the entire region WO on the upper side of the transparent insulating layer 41. The GaN layer 42 as the second light-emitting element is manufactured, similarly to the GaAs layer 32, by, for example, a method of growing a functional layer on a separate substrate (not shown) via a sacrificial layer and then peeling it off by sacrificial layer etching, or by a method of growing a functional layer on a sapphire substrate and then peeling it off by laser lift-off. Similarly to the GaAs layer 32, the GaN layer 42 is formed by bonding an n-type semiconductor layer on the lower side (-Z side) to a p-type semiconductor layer on the upper side (+Z side), and the bonded portion between the two forms a light-emitting layer (FIG. 13(A)).

[0041] In the next step, as shown in the side view of FIG. 5(B) and the plan view of FIG. 10(A), a portion of the GaN layer 42 is removed by etching. In this step, patterning is performed symmetrically with respect to the X direction with respect to the GaAs layer 32 (FIG. 8(B)). Specifically, the central region WA is left as the green light-emitting portion 42A, and the region WEF is left as the green electrode connection portion 42E, while the GaN layer 42 is removed from the other regions WB, WC, and WD.

[0042] In this process, protrusion 42F having a configuration similar to protrusion 32C ( FIG. 8B ) is formed in region WF on the +X side of region WEF. Specifically, protrusion 42F is formed in region WF slightly toward the −Y direction from the center in the Y direction so as to have a square shape when viewed from the Z direction. That is, in the portion of region WEF of GaN layer 42, as in the case of GaAs layer 32 ( FIG. 13B ), the portion of protrusion 42F remains without being removed, while in the portions other than protrusion 42F, the p-type semiconductor layer, the light-emitting layer, and portions of the n-type semiconductor layer are removed from above, and the remaining portion of the n-type semiconductor layer becomes green electrode connection portion 42E.

[0043] Furthermore, in this process, the transparent insulating layer 41 and the transparent insulating layer 36 of the first thin film layer 30 are partially removed by etching at a position directly above the protruding portion 32C (FIG. 9(B)) in the region WC, to form a wiring hole 72C as an opening. This wiring hole 72C has a shape similar to the wiring hole 71F (FIG. 8(B)) overall, and is a circular hole that penetrates the transparent insulating layer 41 and the transparent insulating layer 36 in the Z direction and reaches the upper surface of the cathode connecting wiring layer 35C in the first thin film layer 30.

[0044] The wiring hole 72C has a shape in which the diameter decreases in the direction opposite to the light emission direction (i.e., the -Z direction), and the inner wall distance, which is the distance between the inner walls, decreases in the -Z direction, resulting in a so-called mortar shape. The diameter of the wiring hole 72C at the bottom is shorter than the length of the short side of the cathode connection wiring layer 35C, i.e., the length along the Y direction. In other words, the length in the XY plane of the protruding portion 32C of the first thin-film layer 30, i.e., the length in the orthogonal direction, which is a direction orthogonal to the +Z direction, which is the light emission direction, is sufficiently longer than the length of the wiring hole 72C at the bottom in the orthogonal direction.

[0045] In the next step, as shown in the side view of FIG. 5(C) and the plan view of FIG. 10(B), electrodes 43 are formed from a predetermined conductive material in three mutually spaced locations. Specifically, an anode electrode 43A that serves as the anode terminal of the second light-emitting section 49 is formed in region WA, and a cathode electrode 43E (hereinafter also referred to as the second-layer electrode) that serves as the cathode terminal of the second light-emitting section 49 is formed in region WE. Furthermore, an interlayer connection electrode 43C that serves as an opening electrode is formed in region WC so as to cover the inner surface of the wiring hole 72C. This interlayer connection electrode 43C is electrically connected to the cathode connection wiring layer 35C of the first thin-film layer 30.

[0046] In the next step, as shown in the side view of FIG. 6A and the plan view of FIG. 11A, insulating layers 44 are first formed in three mutually spaced locations. Specifically, insulating layer 44A is formed from the anode electrode 43A in region WA toward the Y direction to reach the interior of region WB. Furthermore, linear insulating layer 44F is formed along the X direction from near the +X side end of protrusion 42F in region WF to reach the cathode electrode 43E in region WE. Furthermore, insulating layer 44D is formed between cathode electrode 43E in region WE and interlayer connection electrode 43C in region WC, providing a linear connection mainly within region WD along the X direction.

[0047] Next, in this process, a plurality of wiring layers 45 are formed from a conductive material. Specifically, a linear anode-adjacent wiring layer 45B is formed along the X direction at a location slightly away from the Y-direction end of region WB. Furthermore, a linear anode-connecting wiring layer 45A is formed along the Y direction between the anode electrode 43A in region WA and the X-direction center of the anode-adjacent wiring layer 45B in region WB. Furthermore, a cathode-connecting wiring layer 45F (hereinafter also referred to as a second wiring member) is formed over a range from near the X-side end of the protruding portion 42F in region WF, via the cathode electrode 43E in region WE, to the interlayer-connecting electrode 43C in region WC.

[0048] Furthermore, in this process, a transparent insulating layer 46 is formed so as to cover the entire region WO from above. This transparent insulating layer 46 is made of a transparent and insulating material, similar to the transparent insulating layer 41, etc. This brings the second thin film layer 40 into a substantially completed state.

[0049] [1-3-3. Manufacturing of the third thin film layer] From this point on, a blue third thin film layer 50 is sequentially formed on the upper side (+Z direction side) of the second thin film layer 40. In the first step, as shown in the side view of FIG. 6(B), a transparent insulating layer 51 is formed over the entire area above the transparent insulating layer 46. This transparent insulating layer 51 is made of a transparent and insulating material, similar to the transparent insulating layer 31 and the like.

[0050] In this process, a GaN layer 52 is subsequently attached to the entire WO region on the upper side of the transparent insulating layer 51. This GaN layer 52 is manufactured, as in the case of the GaAs layer 32 and the like, by a method in which a functional layer grown on a separate substrate (not shown) via a sacrificial layer is peeled off by sacrificial layer etching, or by a method in which a functional layer grown on a sapphire substrate is peeled off by laser lift-off. Similarly to the GaAs layer 32 and the like, this GaN layer 52 is formed by bonding an n-type semiconductor layer on the lower side (-Z side) to a p-type semiconductor layer on the upper side (+Z side), and the bonded portion between the two forms a light-emitting layer (FIG. 13(A)).

[0051] In the next step, as shown in the side view of FIG. 6(C) and the plan view of FIG. 11(B), a portion of the GaN layer 52 is removed by etching. In this step, patterning is performed such that the protruding portion 32C is omitted from the GaAs layer 32 (FIG. 8(B)). Specifically, the central region WA is left as the blue light-emitting portion 52A, and the region WCD is left as the blue electrode connection portion 52D, while the GaN layer 52 is removed in the other regions WB, WE, and WF. In the region WCD, the p-type semiconductor layer, the light-emitting layer, and portions of the n-type semiconductor layer are removed from the upper side of the GaN layer 52, so that the remaining portion of the n-type semiconductor layer becomes the blue electrode connection portion 52D.

[0052] Furthermore, in this process, the transparent insulating layer 51 and the transparent insulating layer 46 of the second thin film layer 40 are partially removed by etching at a position directly above the protruding portion 42F (FIG. 11(A)) in the region WF, thereby forming a wiring hole 73F. This wiring hole 73F is configured similarly to the wiring hole 72C (FIG. 10(A)), etc., and is a circular hole that penetrates the transparent insulating layer 51 and the transparent insulating layer 46 in the Z direction and reaches the upper surface of the cathode connecting wiring layer 45F in the second thin film layer 40. Furthermore, the wiring hole 73F has a shape in which the diameter (inner wall distance) decreases as it progresses downward (in the -Z direction), i.e., it has a mortar shape.

[0053] In the next step, as shown in the side view of Fig. 7(A) and the plan view of Fig. 12(A), electrodes 53 are formed from a predetermined conductive material in three mutually spaced locations. Specifically, an anode electrode 53A that serves as the anode terminal of the third light-emitting section 59 is formed in region WA, and a cathode electrode 53D that serves as the cathode terminal of the third light-emitting section 59 is formed in region WD. Furthermore, an interlayer connection electrode 53F is formed in region WF so as to cover the inner surface of the wiring hole 73F. This interlayer connection electrode 53F is electrically connected to the cathode connection wiring layer 45F of the second thin-film layer 40.

[0054] In the next step, as shown in the side view of Fig. 7(B) and the plan view of Fig. 12(B), insulating layers 54 are first formed in two mutually spaced locations. Specifically, insulating layer 54A is formed over the portion extending from anode electrode 53A in region WA toward the Y direction to reach the interior of region WB. Additionally, insulating layer 54E is formed between cathode electrode 53D in region WD and interlayer connection electrode 53F in region WF, providing a linear connection mainly within region WE along the X direction.

[0055] Next, in this process, multiple wiring layers 55 are formed from a conductive material. Specifically, a linear anode-adjacent wiring layer 55B is formed along the X direction at a location slightly away from the Y-direction end of region WB. Furthermore, a linear anode connecting wiring layer 55A is formed along the Y direction between the anode electrode 53A in region WA and the center of the anode-adjacent wiring layer 55B in region WB in the X direction. Furthermore, a cathode connecting wiring layer 55F is formed along the X direction between the cathode electrode 53D in region WD and the interlayer connecting electrode 53F in region WF.

[0056] Furthermore, in this process, a transparent insulating layer 56 is formed so as to cover the entire region WO from above. This transparent insulating layer 56 is made of a transparent and insulating material, similar to the transparent insulating layer 41, etc. As a result, the first red thin film layer 30, the second green thin film layer 40, and the third blue thin film layer 50 are sequentially stacked on the substrate layer 10, and the LED display unit 2 is completed.

[0057] [1-3-4. Electrical connection between layers] In the LED display unit 2 manufactured in this manner, the light-emitting units 9 of each color (first light-emitting unit 39, second light-emitting unit 49, and third light-emitting unit 59) formed on each layer are each configured as an LED element. The anode terminal and cathode terminal of each light-emitting unit 9 are electrically connected to the other layers.

[0058] Fig. 15 shows a cross-sectional view taken along C1-C2 in Fig. 12(B). As can be seen from Fig. 15, in the pixel unit 8, the cathode electrode 33D is electrically connected to the extension wiring portion 12X of the substrate wiring portion 12 in the substrate layer 10 via the interlayer connection electrode 33F and the cathode connection wiring layer 35C. That is, in the pixel unit 8, for the first light-emitting portion 39 in the first thin-film layer 30, the cathode electrode 33D, which is the cathode terminal of the LED element, is electrically connected to the substrate wiring portion 12.

[0059] In the pixel unit 8, the cathode electrode 43E is electrically connected to the cathode electrode 33D of the first thin-film layer 30 via the cathode connecting wiring layer 35C, the interlayer connecting electrode 43C of the second thin-film layer 40, and the cathode connecting wiring layer 45F. That is, in the pixel unit 8, the cathode electrode 43E, which is the cathode terminal of the LED element, is electrically connected to the substrate wiring unit 12 for the second light-emitting unit 49 in the second thin-film layer 40.

[0060] Furthermore, in the pixel unit 8, the cathode electrode 53D is electrically connected to the cathode electrode 43E via the cathode connecting wiring layer 45F, the interlayer connecting electrode 53F of the third thin film layer 50, and the cathode connecting wiring layer 55F. That is, in the pixel unit 8, the cathode electrode 53D, which is the cathode terminal of the LED element, is electrically connected to the substrate wiring unit 12 for the third light-emitting unit 59 in the third thin film layer 50.

[0061] In this way, in the pixel section 8, the substrate wiring section 12 of the substrate layer 10 and the cathode electrodes 33D of each color are electrically connected via the interlayer connection electrodes 33F and the cathode connection wiring layer 35C provided in each layer.

[0062] 16 is a plan view schematically illustrating a portion of the LED display unit 2 in which the pixel units 8 are arranged in a grid pattern, and is a schematic diagram illustrating the arrangement and connection of the wiring layers when viewed from the Z direction. As can be seen from Fig. 16, in the LED display unit 2, the through wiring portions 12Y provided in the substrate layer 10 of each pixel unit 8 are connected to the pixel units 8 adjacent to each other in the Y direction. The through wiring portions 12Y are connected to drive elements and drive circuits (not shown).

[0063] In the LED display section 2, the anode-adjacent wiring layers 35B provided on the first thin film layer 30 of each pixel section 8 are connected to each other between pixel sections 8 adjacent to each other in the X direction. Furthermore, in the LED display section 2, the anode-adjacent wiring layers 45B provided on the second thin film layer 40 and the anode-adjacent wiring layers 55B provided on the third thin film layer 50 are also connected to each other in the same manner. The anode-adjacent wiring layers of each color are connected to drive elements and drive circuits (not shown).

[0064] With this configuration, the LED display unit 2 can function as a passive matrix driving LED display.

[0065] [1-4. Effects, etc.] In the above configuration, the LED display section 2 of the LED display device 1 according to the first embodiment is manufactured by sequentially stacking the substrate layer 10, the first thin film layer 30, the second thin film layer 40 and the third thin film layer 50, and the cathode electrodes of the light-emitting sections 9 of each color are electrically connected to the substrate wiring section 12 of the substrate layer 10 via each wiring layer and each interlayer connection electrode, etc.

[0066] At this time, in the pixel section 8 of the LED display unit 2, a protruding portion 32C is formed by the GaAs layer 32 in the region WC of the first thin film layer 30, and an insulating layer 34C and a cathode connecting wiring layer 35C are formed overlapping the protruding portion 32C (FIGS. 4(D) and 8(B)). Also, in the pixel section 8, in the region WC of the second thin film layer 40 and the first thin film layer 30, a wiring hole 72C penetrating the transparent insulating layer 41 and the transparent insulating layer 36 is formed, an interlayer connecting electrode 43C is formed on the inner surface thereof, and a cathode connecting wiring layer 45F is formed overlapping the upper side thereof (FIGS. 6(A) and 11(A)).

[0067] As a result, in the pixel section 8, compared to a typical configuration in which the cathode connecting wiring layer 35C is formed without forming the protrusion 32C, the distance from the upper surface of the transparent insulating layer 41 to the cathode connecting wiring layer 35C can be significantly shortened, and the ratio of the depth to the diameter (i.e., the aspect ratio) of the wiring hole 72C can be reduced. Also, in the pixel section 8, with respect to the wiring hole 73F formed in the region WF of the third thin film layer 50 and the second thin film layer 40, the formation of the protrusion 42F allows the aspect ratio to be reduced, similar to that of the wiring hole 72C.

[0068] In other words, in the LED display section 2, when the pixel length 8L of each pixel section 8 is configured to be relatively short in response to the demand for higher resolution, the aspect ratio can be kept to a sufficiently small value even if the diameters of the wiring holes 72C and 73F are made relatively small without changing the thickness of each layer much.

[0069] As a result, in the LED display unit 2, when the interlayer connection electrode 43C of each pixel unit 8 is formed by sputtering, the sputtered seed layer can be made to sufficiently reach and settle at the bottom of the wiring hole 72C, i.e., the upper surface of the cathode connection wiring layer 35C. Similarly, in the LED display unit 2, when the interlayer connection electrode 53F of each pixel unit 8 is formed by sputtering, the sputtered seed layer can be made to sufficiently reach and settle at the bottom of the wiring hole 73F, i.e., the upper surface of the cathode connection wiring layer 45F.

[0070] As a result, in the LED display device 1 having the LED display section 2, each pixel section 8 can be configured with high resolution, while interlayer connection electrodes 43C and 53F that are electrically connected well to the cathode connection wiring layers 35C and 45F can be formed, i.e., the electrical connection between layers can be stabilized.

[0071] In particular, in the pixel section 8, the GaAs layer 32 for forming the first light-emitting section 39 is mainly used, and the protrusions 32C and the like are formed by etching (FIGS. 4(D) and 8(B)). Therefore, in the pixel section 8, compared to a general configuration in which the protrusions 32C and the like are not formed, there is no need to add a process (semiconductor process) for forming the protrusions 32C and the like, and the protrusions 32C and the like can be formed simply by changing the mask pattern for etching. In other words, in the pixel section 8, a good cathode connection wiring layer 35C and the like can be formed without increasing the manufacturing cost or the required time due to the addition of a manufacturing process.

[0072] Furthermore, in the pixel section 8, when forming the protrusion 32C, the GaAs layer 32 region for the protrusion 32C is not removed at all, and the protrusion 32C is made to have the same height as the upper surface (surface in the +Z direction) of the red light-emitting section 32A (FIG. 13). Therefore, in the pixel section 8, the upper surface of the protrusion 32C can be set to the highest position that can be formed based on the GaAs layer 32, and the depth of the wiring hole 72C can be minimized. The same applies to the protrusion 42F.

[0073] Furthermore, in the pixel section 8, an insulating layer 34C is formed so as to overlap the protrusion 32C, and a cathode connecting wiring layer 35C is formed on top of that, thereby electrically insulating the protrusion 32C from the cathode connecting wiring layer 35C (FIG. 4(F)). This makes it possible to prevent problems caused by inadvertent current flowing through the protrusion 32C in the pixel section 8, and also allows the cathode connecting wiring layer 35C to be positioned at a higher position than if the insulating layer 34C were not provided on the top surface of the protrusion 32C. The same applies to the protrusion 42F.

[0074] According to the above configuration, in the LED display device 1 according to the first embodiment, during the manufacture of the LED display unit 2, the protrusion 32C is formed from the GaAs layer 32, the cathode connection wiring layer 35C is formed on top of this, and the wiring hole 72C is formed penetrating the transparent insulating layer 41 and the transparent insulating layer 36 above it. As a result, in the LED display device 1, the ratio of the depth to the diameter of the wiring hole 72C etc. can be kept sufficiently small, so that the sputtering of the seed layer can reach the bottom of the wiring hole 72C in sputtering, and a good interlayer connection electrode 43C can be formed on the inner surface of the wiring hole 72C, thereby stabilizing the electrical connection between layers.

[0075] 2. Second Embodiment [2-1. LED display device configuration] An LED display device 201 (FIG. 1) according to the second embodiment is configured similarly to the LED display device 1 according to the first embodiment, except that it has an LED display unit 202 instead of the LED display unit 2. Also, unlike the first embodiment, the second embodiment drives each LED element by a so-called active matrix driving method.

[0076] 2(A) and 2(C), the LED display unit 202 has a substrate layer 210 and a thin film layer group 220 instead of the substrate layer 10 and the thin film layer group 20. The thin film layer group 220 has a configuration similar to that of the first embodiment, in which a first thin film layer 230, a second thin film layer 240, a third thin film layer 250, and an electrode layer 260 are sequentially stacked from the -Z direction to the +Z direction. In addition, in the thin film layer group 220, a plurality of pixel units 208 that constitute each pixel are formed so as to be arranged in a lattice pattern along the X direction and the Y direction within a display region 202A of the LED display unit 202.

[0077] In each pixel section 208, a first light-emitting section 239 that emits red light is formed in the first thin film layer 230, a second light-emitting section 249 that emits green light is formed in the second thin film layer 240, and a third light-emitting section 259 that emits blue light is formed in the third thin film layer 250.

[0078] [2-2. LED display configuration] Next, the detailed configuration of the LED display unit 202 (FIG. 2) will be described with reference to FIGS. 16 to 30, focusing on one pixel unit 208, as in the first embodiment. As in the first embodiment, the LED display unit 202 is manufactured by sequentially stacking layers from the bottom to the top through semiconductor processes. That is, the LED display unit 202 is roughly divided into a substrate layer 210, a first thin film layer 230, a second thin film layer 240, a third thin film layer 250, and an electrode layer 260, which are manufactured in this order.

[0079] 3(B), which corresponds to FIG. 3(A), is a schematic diagram showing how the entire area on the XY plane is divided into multiple areas when one pixel unit 208 is viewed from the +Z direction in the second embodiment. FIGS. 16 to 21 are schematic side views, viewed from the -Y direction, of each process for manufacturing the pixel unit 208. FIGS. 22 to 27 are schematic plan views, viewed from the +Z direction, of some of the processes for manufacturing the pixel unit 208. FIGS. 28 and 29 are schematic cross-sectional views of some of the processes for manufacturing the pixel unit 208.

[0080] 3(B), in the second embodiment, a square region (hereinafter referred to as the entire region WO as in the first embodiment) corresponding to one pixel unit 208 on the XY plane is divided into a grid pattern. Specifically, the entire region WO is divided into approximately three equal parts along the X and Y directions, resulting in nine square regions (regions WH, WJ, WK, WL, WM, WN, WP, WQ, and WR).

[0081] [2-3. Manufacturing of LED display parts] Next, the manufacturing process of the LED display unit 202 will be described step by step. First, a substrate layer 210 is formed. In the first step, as shown in the side view of FIG. 17(A) and the plan view of FIG. 23(A), a circuit board 211 is formed over the entire region WO, and a board wiring portion 212 is provided on the upper surface of the circuit board 211. The circuit board 211 is made mainly of, for example, silicon.

[0082] Similar to the substrate wiring portion 12 in the first embodiment, the substrate wiring portion 212 is made of a conductive metal material such as gold, copper, titanium, etc. The substrate wiring portion 212 is provided with substrate wiring portions 212H, 212K, and 212R in the region WH, the region WK, and the region WR, respectively. The substrate wiring portions 212H, 212K, and 212R are all formed in a square shape when viewed from the +Z direction.

[0083] [2-3-1. Manufacturing of the first thin film layer] From this point on, a first thin film layer 230 having a red first light-emitting portion 239 is formed on the upper side (+Z direction side) of the substrate layer 210. In the first step, as shown in the side view of Fig. 17(B), a transparent insulating layer 231 is formed over the entire region WO on the upper side of the substrate layer 210. This transparent insulating layer 231 is made of the same transparent insulating material as the transparent insulating layer 31 in the first embodiment, and is transparent and insulating.

[0084] 17(C), a GaAs layer 232 is attached to the entire region WO on the upper side of the transparent insulating layer 231. This GaAs layer 232 is manufactured by the same method as the GaAs layer 32 in the first embodiment. As shown in FIG. 13, the GaAs layer 232 has an n-type semiconductor layer on the lower side (-Z side) and a p-type semiconductor layer on the upper side (+Z side) joined together, and the junction between the two forms a light-emitting layer.

[0085] 17(D) and the plan view of Fig. 23(B), part of the GaAs layer 232 is removed by etching. In this patterning step, a circular region inscribed in the central region WM is designated as the red light-emitting portion 232M, and the range extending from region WP to near the center of region WQ is designated as the red electrode connection portion 232P, while the GaAs layer 232 is removed from regions WH and WK, and from near the center of region WQ to region WR.

[0086] In this process, protruding portions 232J, 232L, and 232N are formed in the vicinity of the center of each of the regions WJ, WL, and WN, respectively, so as to have a square shape when viewed from the Z direction. These protruding portions 232J, 232L, and 232N correspond to the protruding portions in this embodiment. That is, in the region WJ of the GaAs layer 232, as in the case shown in FIG. 13(B), the portion of the protruding portion 232J is left without being removed at all, while portions of the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer are removed from above in the portions other than the protruding portion 232J. Similarly, in the regions WL and WN, portions of the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer are removed from above in the portions other than the protruding portions 232L and 232N.

[0087] Furthermore, in this process, the transparent insulating layer 231 is partially removed by etching at positions directly above the substrate wiring portions 212H, 212K, and 212R (FIG. 23(A)) in the regions WH, WK, and WR, respectively, to form wiring holes 271H, 271K, and 271R, respectively. Of these, the wiring hole 271R is a circular hole that penetrates the transparent insulating layer 231 in the Z direction, and reaches the upper surface of the substrate wiring portion 212R in the substrate layer 210, as shown in FIG. 29(A), which is a cross-sectional view taken along D1-D2 in FIG. 23(B). The wiring hole 271R has a shape in which the diameter (inner wall distance) decreases as it extends downward (in the -Z direction), i.e., a mortar shape. The wiring holes 271H and 271K are each configured in a similar manner.

[0088] In the next step, as shown in the side view of Fig. 17(E) and the plan view of Fig. 24(A), electrodes 233 are formed from a predetermined conductive material at five mutually spaced locations. Specifically, an anode electrode 233M that serves as the anode terminal of the first light-emitting section 239 is formed in the region WM, and a cathode electrode 233P that serves as the cathode terminal of the first light-emitting section 239 is formed in the region WP.

[0089] 29(B), which is a cross-sectional view taken along line E1-E2 in FIG. 24(A), an interlayer connection electrode 233R is formed so as to cover the inner surface of wiring hole 271R. Interlayer connection electrode 233R is electrically connected to substrate wiring portion 212R of substrate layer 210. Similarly, in region WH, an interlayer connection electrode 233H is formed so as to cover the inner surface of wiring hole 271H. Interlayer connection electrode 233H is electrically connected to substrate wiring portion 212H of substrate layer 210. Furthermore, in region WK, an interlayer connection electrode 233K is formed so as to cover the inner surface of wiring hole 271K. Interlayer connection electrode 233K is electrically connected to substrate wiring portion 212K of substrate layer 210.

[0090] In the next step, as shown in the side view of Fig. 17(F) and the plan view of Fig. 24(B), first, insulating layers 234 are formed at four mutually spaced locations. Specifically, a linear insulating layer 234M is formed along the +XY direction (i.e., a diagonal direction) over a range from the anode electrode 233M in region WM to the interlayer connection electrode 233R in region WR. Also, a linear insulating layer 234L is formed along the Y direction over a range from near the +Y side end of the protrusion 232L in region WL to the cathode electrode 233P in region WP.

[0091] Furthermore, a linear insulating layer 234J is formed along the X direction from near the +X side end of the protruding portion 232J in region WJ to the interlayer connection electrode 233H in region WH. Also, a linear insulating layer 234N is formed along the Y direction between near the -Y side end of the protruding portion 232N in region WN and the interlayer connection electrode 233K in region WK.

[0092] Next, in this process, a plurality of wiring layers 235 are formed from a conductive material. Specifically, a linear anode connection wiring layer 235M is formed along the +XY direction (i.e., a diagonal direction) between the anode electrode 233M in region WM and the interlayer connection electrode 233R in region WR. Furthermore, a linear cathode connection wiring layer 235L is formed along the Y direction over a range from near the +Y side end of the protrusion 232L in region WL to the cathode electrode 233P in region WP. In other words, the cathode connection wiring layer 235L is disposed above the protrusion 232L in region WL, i.e., above the protrusion 232L on the light-emitting direction E side.

[0093] Furthermore, a wiring layer 235J is formed linearly along the X direction from near the +X side end of the protrusion 232J in region WJ to the interlayer connection electrode 233H in region WH. Also, a wiring layer 235N is formed linearly along the Y direction from near the -Y side end of the protrusion 232N in region WN to the interlayer connection electrode 233K in region WK.

[0094] Furthermore, in this process, a transparent insulating layer 236 is formed so as to cover the entire region WO from above. This transparent insulating layer 236 is made of a transparent and insulating material, similar to the transparent insulating layer 231, etc. This brings the first thin film layer 230 into a substantially completed state.

[0095] [2-3-2. Manufacturing of the second thin film layer] From this point on, the second thin film layer 240 having the green second light-emitting portion 249 is formed on the upper side (+Z direction side) of the first thin film layer 230 having the red first light-emitting portion 239. In the first step, as shown in the side view of Fig. 18(A), a transparent insulating layer 241 is formed over the entire region WO on the upper side of the transparent insulating layer 236. This transparent insulating layer 241 is made of the same transparent insulating material as the transparent insulating layer 231, etc., and has transparency and insulating properties.

[0096] 18(A), a GaN layer 242 is attached to the entire region WO on the upper side of the transparent insulating layer 241. This GaN layer 242 is manufactured by the same method as the GaN layer 42 in the first embodiment. As shown in FIG. 13, the GaN layer 242 is formed by joining an n-type semiconductor layer on the lower side (-Z side) and a p-type semiconductor layer on the upper side (+Z side), and the junction between the two forms a light-emitting layer.

[0097] In the next step, as shown in the side view of Fig. 18(B) and the plan view of Fig. 25(A), a portion of the GaN layer 242 is removed by etching. In this step, patterning is performed to define a circular region inscribed in the central region WM as a green light-emitting portion 242M, and a range from region WP to region WQ as a green electrode connection portion 242P, while removing the GaN layer 242 in regions WJ, WL, WN, and WR.

[0098] Furthermore, in this step, protruding portions 242H and 242K are formed near the center of each of regions WH and WK so as to have a square shape when viewed from the Z direction. That is, in region WH of GaN layer 242, as in the case shown in Fig. 13(B), the portion of protruding portion 242H is left without being removed at all, while in the portions other than protruding portion 242H, portions of the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer are removed from above. Similarly, in region WK, in the portions other than protruding portion 242K, portions of the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer are removed from above.

[0099] Furthermore, in this process, in each of the regions WJ, WL, and WN, the transparent insulating layer 241 and the transparent insulating layer 236 of the first thin film layer 230 are partially removed by etching at positions directly above the protrusions 232J, 232L, and 232N (FIG. 24(B)), forming wiring holes 272J, 272L, and 272N, respectively. Of these, the wiring hole 272L is a circular hole that penetrates the transparent insulating layer 241 and the transparent insulating layer 236 in the Z direction, and reaches the upper surface of the cathode connection wiring layer 235L of the first thin film layer 230, as shown in FIG. 29(C), which is the F1-F2 cross-sectional view of FIG. 25(A). The wiring hole 272L has a shape in which the diameter (inner wall distance) decreases as it extends downward (in the -Z direction), i.e., a mortar shape. The wiring holes 272J and 272N are each configured in a similar manner.

[0100] In the next step, as shown in the side view of Fig. 18(C) and the plan view of Fig. 25(B), electrodes 243 are formed from a predetermined conductive material at five mutually spaced locations. Specifically, an anode electrode 243M that serves as the anode terminal of the second light-emitting section 249 is formed in the region WM, and a cathode electrode 243P that serves as the cathode terminal of the second light-emitting section 249 is formed in the region WP.

[0101] In region WJ, an interlayer connection electrode 243J is formed so as to cover the inner surface of wiring hole 272J. The interlayer connection electrode 243J is electrically connected to wiring layer 235J of the first thin film layer 230. Similarly, in region WL, an interlayer connection electrode 243L is formed so as to cover the inner surface of wiring hole 272L. The interlayer connection electrode 243L is electrically connected to cathode connection wiring layer 235L of the first thin film layer 230. Furthermore, in region WN, an interlayer connection electrode 243N is formed so as to cover the inner surface of wiring hole 272N. The interlayer connection electrode 243N is electrically connected to wiring layer 235N of the first thin film layer 230.

[0102] 19(A) and the plan view of FIG. 26(A), first, insulating layers 244 are formed at four mutually spaced locations. Specifically, insulating layer 244M is formed linearly along the X direction over the range from anode electrode 243M in region WM to interlayer connection electrode 243N in region WN. Furthermore, insulating layer 244P is formed linearly along the Y direction over the range from cathode electrode 243P in region WP to interlayer connection electrode 243L in region WL.

[0103] Furthermore, an insulating layer 244H is formed along the Y direction from near the +Y side end of the protruding portion 242H in region WH toward the −Y direction to reach the interlayer connection electrode 243L in region WL. Also, an insulating layer 244K is formed along the X direction from near the +X side end of the protruding portion 242K in region WK toward the −X direction to reach the interlayer connection electrode 243J in region WJ.

[0104] Next, in this process, a plurality of wiring layers 245 are formed from a conductive material. Specifically, an anode connection wiring layer 245M is formed linearly along the X direction between the anode electrode 243M in region WM and the interlayer connection electrode 243N in region WN. Furthermore, a cathode connection wiring layer 245H is formed linearly along the Y direction from near the +Y side end of the protrusion 242H in region WH, via the interlayer connection electrode 243L in region WL, to the cathode electrode 243P in region WP. Furthermore, a wiring layer 245K is formed linearly along the X direction from near the +X side end of the protrusion 242K in region WK to the interlayer connection electrode 243J in region WJ.

[0105] Furthermore, in this process, a transparent insulating layer 246 is formed so as to cover the entire region WO from above. This transparent insulating layer 246 is made of a transparent and insulating material, similar to the transparent insulating layer 231, etc. This brings the second thin film layer 240 into a substantially completed state.

[0106] [2-3-3. Manufacturing of the third thin film layer] From this point on, the blue third thin film layer 250 is sequentially formed on the upper side (+Z direction side) of the green second thin film layer 240. In the first step, as shown in the side view of Fig. 19(B), a transparent insulating layer 251 is formed over the entire region WO on the upper side of the transparent insulating layer 246. This transparent insulating layer 251 is made of the same transparent insulating material as the transparent insulating layer 231, etc., and has transparency and insulating properties.

[0107] 19(B), a GaN layer 252 is attached to the entire region WO on the upper side of the transparent insulating layer 251. This GaN layer 252 is manufactured by the same method as the GaN layer 42 in the first embodiment. As shown in FIG. 13, the GaN layer 252 is formed by joining an n-type semiconductor layer on the lower side (-Z side) and a p-type semiconductor layer on the upper side (+Z side), and the junction between the two forms a light-emitting layer.

[0108] 19(C) and the plan view of Fig. 26(B), part of GaN layer 252 is removed by etching. In this patterning step, a circular region inscribed in central region WM is designated as blue light-emitting portion 252M, and approximately half of region WL on the -Y direction side and approximately half of region WQ on the -X direction side, centered on region WP, are collectively designated as blue electrode connection portion 252L, while the remaining portion of GaN layer 242 is removed.

[0109] In this step, protruding portions 252P are formed near the center of region WP so as to have a square shape when viewed from the Z direction. That is, in blue electrode connection portion 252L centered on region WP of GaN layer 252, the portions of protruding portions 252P are left without being removed at all, as in the case shown in Fig. 13(B), while in the portions other than protruding portions 252P, portions of the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer are removed from above.

[0110] Furthermore, in this process, in each of the regions WH and WK, the transparent insulating layer 251 and the transparent insulating layer 246 of the second thin film layer 240 are partially removed by etching at positions directly above the protrusions 242H and 242K (FIG. 26(A)), forming wiring holes 273H and 273K, respectively. Of these, the wiring hole 273H is a circular hole that penetrates the transparent insulating layer 251 and the transparent insulating layer 246 in the Z direction, and reaches the upper surface of the cathode connection wiring layer 245H, as shown in FIG. 29(D), which is a cross-sectional view of G1-G2 in FIG. 26(B). The wiring hole 273H has a shape in which the diameter (inner wall distance) decreases as it extends downward (in the -Z direction), i.e., a mortar shape. The wiring hole 273K is configured in a similar manner.

[0111] In the next step, as shown in the side view of Fig. 20(A) and the plan view of Fig. 27(A), electrodes 253 are formed from a predetermined conductive material at four mutually spaced locations. Specifically, an anode electrode 253M that serves as the anode terminal of the third light-emitting section 259 is formed in region WM, and a cathode electrode 253L that serves as the cathode terminal of the third light-emitting section 259 is formed on the -Y direction side of region WL (i.e., on the blue electrode connection section 252L).

[0112] In the region WH, an interlayer connection electrode 253H is formed so as to cover the inner surface of the wiring hole 273H. The interlayer connection electrode 253H is electrically connected to the cathode connection wiring layer 245H of the second thin film layer 240. Similarly, in the region WK, an interlayer connection electrode 253K is formed so as to cover the inner surface of the wiring hole 273K. The interlayer connection electrode 253K is electrically connected to the wiring layer 245K of the second thin film layer 240.

[0113] 20(B) and the plan view of Fig. 27(B), first, insulating layers 254 are formed at three mutually spaced locations. Specifically, linear insulating layers 254M are formed along the +X+Y direction (i.e., diagonal directions) over a range from the anode electrode 243M in region WM to the interlayer connection electrode 253K in region WK.

[0114] Also, an insulating layer 254P is formed linearly along the Y direction from near the -Y side end of the protruding portion 252P in the region WP to the cathode electrode 253L in the region WL. Furthermore, an insulating layer 254L is formed linearly along the Y direction from the cathode electrode 253L in the region WL to the interlayer connection electrode 253H in the region WH.

[0115] Next, in this process, a plurality of wiring layers 255 are formed from a conductive material. Specifically, a linear anode connection wiring layer 255M is formed along the +X+Y direction (i.e., a diagonal direction) between the anode electrode 253M in region WM and the interlayer connection electrode 253K in region WK. Also, a linear cathode connection wiring layer 255P is formed along the Y direction over a range from near the -Y side end of the protrusion 252P in region WP, via the cathode electrode 253L in region WL, to the interlayer connection electrode 253H in region WH.

[0116] Furthermore, in this process, a transparent insulating layer 256 is formed so as to cover the entire region WO from above. This transparent insulating layer 256 is made of a transparent and insulating material, similar to the transparent insulating layer 231, etc. This brings the third thin film layer 250 into a substantially completed state.

[0117] [2-3-4. Manufacturing of electrode layer] From this point on, an electrode layer 260 is formed on the upper side (+Z direction side) of the third thin film layer 250. In the first step, as shown in the side view of Fig. 21(A), a conductive layer 261 is formed over the entire region WO on the upper side of the transparent insulating layer 256. This conductive layer 261 is made of a conductive metal material such as aluminum, gold, copper, or titanium.

[0118] In the next step, as shown in the side view of Fig. 21(B) and the plan view of Fig. 28(A), the light transmission hole 261M and the wiring hole 274P are formed by etching. Of these, the light transmission hole 261M is formed in a circular shape by removing only the conductive layer 261 over a relatively wide range including the region WM and its periphery.

[0119] The wiring hole 274P is formed as a round hole that penetrates the conductive layer 261 and the transparent insulating layer 256 in the Z direction by partially removing the conductive layer 261 and the transparent insulating layer 256, and reaches the upper surface of the cathode connecting wiring layer 255P in the third thin film layer 250. The wiring hole 274P has a shape in which the diameter (inner wall distance) decreases as it extends downward (-Z direction), i.e., it has a mortar shape.

[0120] 22 and the plan view of Fig. 28(B), in the next step, a common cathode electrode 262 is formed in the region WP using a predetermined conductive material so as to cover the inner surface of the wiring hole 274P. This common cathode electrode 262 is electrically connected to the cathode connecting wiring layer 255P of the third thin film layer 250.

[0121] [2-3-5. Electrical connection between layers] In the LED display unit 202 manufactured in this way, the light-emitting portions 209 of each color formed on each layer are configured as LED elements, and the anode terminal and cathode terminal of each light-emitting portion 209 are electrically connected to the other layers.

[0122] Specifically, with regard to the first light-emitting portion 239 of the first thin film layer 230, as shown in Figures 17(F) and 24(B), the anode electrode 233M, which is the anode terminal, is electrically connected to the substrate wiring portion 212R of the substrate layer 210 via the anode connection wiring layer 235M and the interlayer connection electrode 233R.

[0123] 30, a schematic cross-sectional view taken along H1-H2 in Fig. 28(B), the cathode electrode 233P, which is the cathode terminal of the first light-emitting section 239, is electrically connected to the second thin-film layer 240. Specifically, the cathode electrode 233P is electrically connected to the cathode electrode 243P, which is the cathode terminal in the second light-emitting section 249, via the cathode connecting wiring layer 235L, the interlayer connecting electrode 243L, and the cathode connecting wiring layer 245H.

[0124] With regard to the second light-emitting portion 249 of the second thin film layer 240, the anode electrode 243M, which is an anode terminal, is electrically connected to the substrate wiring portion 212K of the substrate layer 210 via the anode connection wiring layer 245M, the interlayer connection electrode 243N, the wiring layer 235N and the interlayer connection electrode 233K, as shown in Figures 19(A), 27(B) and 24(B).

[0125] 30, the cathode electrode 243P, which is the cathode terminal in the second light-emitting portion 249, is connected to the cathode electrode 233P of the first light-emitting portion 239, as well as to the third thin-film layer 250. Specifically, the cathode electrode 243P is electrically connected to the cathode electrode 253L, which is the cathode terminal in the third light-emitting portion 259, via the cathode connecting wiring layer 245H, the interlayer connecting electrode 253H, and the cathode connecting wiring layer 255P.

[0126] 27(B), 26(A), and 24(B), the anode electrode 253M serving as the anode terminal of the third light-emitting portion 259 of the third thin-film layer 250 is connected to the wiring layer 235J of the first thin-film layer 230 via the anode connection wiring layer 255M, the interlayer connection electrode 253K, the wiring layer 245K of the second thin-film layer 240, and the interlayer connection electrode 243J. Furthermore, the wiring layer 235J is electrically connected to the substrate wiring portion 212H of the substrate layer 210 via the interlayer connection electrode 233H.

[0127] 30, the cathode electrode 253L which is the cathode terminal of the third light-emitting portion 259 is electrically connected to the cathode electrode 233P of the first light-emitting portion 239 and the cathode electrode 243P of the second light-emitting portion 249, as well as to the conductive layer 261 between the electrode layer 260 and the cathode connecting wiring layer 255P and the common cathode electrode 262. As a result, the conductive layer 261 is electrically connected to the cathode terminals of the light-emitting portions 209 of each color, respectively.

[0128] Furthermore, in the LED display unit 202, the substrate wiring portions 212H, 212K, and 212R of the substrate layer 210 are connected to drive elements and drive circuits (not shown), respectively. Also, in the LED display unit 202, the conductive layer 261 is connected to drive elements and drive circuits (not shown).

[0129] With this configuration, the LED display unit 202 can individually drive each of the light-emitting units 209 of each color (first light-emitting unit 239, second light-emitting unit 249, and third light-emitting unit 259) formed in each pixel unit 208, and can function as an active matrix drive LED display as a whole.

[0130] [2-4. Effects, etc.] In the above configuration, the LED display unit 202 of the LED display device 201 according to the second embodiment is manufactured by sequentially laminating the substrate layer 210, the first thin film layer 230, the second thin film layer 240, the third thin film layer 250, and the electrode layer 260. In the pixel unit 208 of the LED display unit 202, the anode terminals of the light-emitting units 209 of each color are electrically connected to the substrate wiring portions 212H, 212K, and 212R of the substrate layer 210, respectively, and the cathode terminals are all electrically connected to the electrode layer 260.

[0131] At this time, in the pixel unit 208, a protruding portion 232J is formed by the GaAs layer 32 in the region WJ of the first thin film layer 230, and an insulating layer 234J and a wiring layer 235J are formed overlapping the protruding portion 232J (FIG. 24(B)). Also, in the pixel unit 208, in the region WJ of the second thin film layer 240 and the first thin film layer 230, a wiring hole 272J penetrating the transparent insulating layer 241 and the transparent insulating layer 236 is formed, an interlayer connection electrode 243J is formed on the inner surface thereof, and a wiring layer 245K is formed overlapping the upper side thereof (FIG. 26(A)). As a result, in the pixel unit 208, as in the first embodiment, the aspect ratio of the wiring hole 272J can be made smaller compared to a general configuration.

[0132] In the pixel section 208, the wiring holes 272L, 272N, 273H, 273K, and 274P also have protrusions (such as the protrusion 242L) formed therein, so that the aspect ratio can be reduced in the same way as the wiring hole 272J.

[0133] That is, in the LED display unit 202, as in the first embodiment, when the pixel length 208L of each pixel unit 208 is configured to be relatively short in response to the demand for higher definition, the aspect ratio can be kept to a sufficiently small value even if the diameter of the wiring hole 272J, etc. is made relatively small without changing the thickness of each layer substantially.

[0134] As a result, in the LED display section 202, when forming the interlayer connection electrodes 243J etc. of each pixel section 208 by sputtering, the sputtered seed layer can be allowed to sufficiently reach the bottom of the wiring holes 272J etc., i.e., the top surface of the wiring layer 235J etc., and be fixed there.

[0135] As a result, in the LED display device 201 having the LED display section 202, it is possible to form each pixel section 208 with high resolution while forming interlayer connection electrodes 243J etc. that are electrically connected well to the wiring layer 235J etc., i.e., it is possible to stabilize the electrical connection between layers.

[0136] In other respects, the LED display device 201 according to the second embodiment can achieve the same effects as the LED display device 1 according to the first embodiment.

[0137] 3. Other Embodiments In the first embodiment described above, when forming protrusion 32C, the region of GaAs layer 32 for protrusion 32C is not removed at all, and the height is set to be the same as the upper surface (surface in the +Z direction) of red light-emitting portion 32A. However, the present invention is not limited to this. For example, the region of GaAs layer 32 for protrusion 32C may be partially removed from the upper side to make the height different from the upper surface of red light-emitting portion 32A. The same applies to protrusion 42F, and also to the second embodiment.

[0138] In the first embodiment described above, the protrusion 32C has a square shape when viewed from above. However, the present invention is not limited to this, and various other shapes, such as a circle or a hexagon, may be used. In this case, it is sufficient that the shape and size of the protrusion 32C are such that when the cathode connecting wiring layer 35C is formed on the protrusion 32C and then the wiring hole 72C penetrating the transparent insulating layer 41 and the transparent insulating layer 36 is formed, the wiring hole 72C does not protrude from the cathode connecting wiring layer 35C. The same applies to the protrusion 42F and the second embodiment.

[0139] Furthermore, in the first embodiment described above, the wiring hole 72C is a round hole, i.e., a circular hole as viewed from the +Z direction. However, the present invention is not limited to this, and the shape as viewed from the +Z direction may be various shapes, such as a square, hexagon, or ellipse. In any shape, by forming the hole into a cone shape in which the diameter or outer shape (i.e., the inner wall distance) decreases as the hole progresses in the -Z direction, the interlayer connection electrode 43C and the like can be formed well in the subsequent sputtering process. The same applies to the wiring hole 73F and the like, and also to the second embodiment.

[0140] Furthermore, in the first embodiment described above, the cathode terminals of each color in the light-emitting portions 9 of each color are electrically connected to the substrate wiring portion 12 of the substrate layer 10, and the anode terminals of each color are electrically connected to the anode terminals of adjacent pixel portions 8 via the anode-adjacent wiring layer 35B or the like. However, the present invention is not limited to this, and a configuration in which the wiring connected to the anode terminal and the wiring connected to the cathode terminal are interchanged for each color may also be used. Specifically, for example, the anode terminals of each color may be electrically connected to the substrate wiring portion 12 of the substrate layer 10, and the cathode terminals of each color may be electrically connected to the cathode terminals of adjacent pixel portions 8.

[0141] Furthermore, in the second embodiment described above, the anode terminals of the light-emitting units 209 of each color are electrically connected to the plurality of substrate wiring portions 212 provided on the substrate layer 210, respectively, and the cathode terminals of each color are electrically connected together to the conductive layer 261. However, the present invention is not limited to this, and a configuration in which the wiring connected to the anode terminal and the wiring connected to the cathode terminal are interchanged for each color may also be used. Specifically, for example, the cathode terminals of each color may be electrically connected to the plurality of substrate wiring portions 212 provided on the substrate layer 210, respectively, and the anode terminals of each color may be electrically connected together to the conductive layer 261.

[0142] Furthermore, in the first embodiment described above, when the cathode connection wiring layer 35C is formed in the first thin film layer 30 so as to straddle the protrusion 32C and the cathode electrode 33D, the protrusion 32C is provided in the region WC and the cathode electrode 33D is provided in the region WD, and so on, and the protrusion and the cathode electrode are disposed in regions adjacent to each other. However, the present invention is not limited to this, and for example, the protrusion and the cathode electrode may be disposed in regions separated from each other. The same applies to the protrusion 42F and the cathode electrode 43E of the second thin film layer 40.

[0143] Furthermore, in the first embodiment described above, a configuration has been described in which the first thin film layer 30 having the red first light-emitting portion 39, the second thin film layer 40 having the green second light-emitting portion 49, and the third thin film layer 50 having the blue third light-emitting portion 59 are sequentially stacked from the -Z direction side to the +Z direction side in the LED display unit 2 (FIG. 2, etc.). However, the present invention is not limited to this, and the thin film layers may be sequentially stacked so that the colors are in a different order. The same applies to the second embodiment.

[0144] Furthermore, in the first embodiment described above, three thin film layers, namely, the first thin film layer 30 having the first light-emitting portion 39, the second thin film layer 40 having the second light-emitting portion 49, and the third thin film layer 50 having the third light-emitting portion 59, are stacked along the Z direction in the LED display unit 2. However, the present invention is not limited to this, and may be configured such that, for example, two or four or more thin film layers each having a light-emitting portion are stacked along the Z direction. The same applies to the second embodiment.

[0145] Furthermore, in the first embodiment described above, the first light-emitting section 39 is configured using the GaAs layer 32. However, the present invention is not limited to this, and the first light-emitting section 39 may be configured using a material layer containing various other materials. The same applies to the second light-emitting section 49 and the third light-emitting section 59, and also to the second embodiment.

[0146] Furthermore, in the first embodiment described above, the present invention is applied to a direct-view LED display device 1. However, the present invention is not limited to this, and may be applied to a display device used as, for example, a projector or a light source. The same applies to the second embodiment.

[0147] Furthermore, in the first embodiment described above, the light-emitting units 9 (39, 49, and 59) are diodes that emit light as semiconductor elements. However, the present invention is not limited to this, and various other semiconductor elements, such as photodiodes and transistors, may also be used. The same applies to the second embodiment.

[0148] Furthermore, the present invention is not limited to the above-described embodiments and other embodiments, and the scope of application of the present invention extends to embodiments in which the above-described embodiments and other embodiments are combined in part or in whole, or in which only a part of the above-described embodiments is extracted.

[0149] Furthermore, in the first embodiment described above, the LED display unit 2 as a light-emitting device is configured using the substrate layer 10 as a substrate layer, the first thin-film layer 30 as a first layer, and the second thin-film layer 40 as a second layer. The first layer further includes a protrusion 32C as a protrusion, a cathode connection wiring layer 35C as a first wiring member, a wiring hole 72C as an opening, and an interlayer connection electrode 43C as an opening electrode. However, the present invention is not limited to this, and a light-emitting device may be configured using a substrate layer, the first layer, and the second layer having various other configurations. For example, the cathode connection wiring layer and the anode connection wiring layer may be reversed. In other words, the conductivity type is not limited to the above-described embodiment. In this case, the first layer may be configured using a protrusion, a first wiring member, an opening, and an opening electrode having various configurations. The same applies to the second embodiment. [Industrial Applicability]

[0150] The present invention can be used not only in LED display devices in which multiple LEDs are arranged in a plane, but also in wearable devices such as smart glasses equipped with an LED display device, and head-up display devices.

[0151] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a substrate layer provided with a conductive substrate wiring member; a first layer that is stacked on the substrate layer and includes a first light-emitting element having a first light-emitting portion that emits light in a direction opposite to the substrate layer, and an insulating member that covers the first light-emitting element; a second layer including a second light-emitting element having a second light-emitting portion, the second layer being stacked on the light-emitting direction side of the first layer; and the second light-emitting element is arranged at a position where the second light-emitting portion overlaps the first light-emitting portion of the first light-emitting element when viewed from the light-emitting direction, The first layer is a protrusion that is a part of the first light emitting element and protrudes in the light emitting direction at a position different from the first light emitting portion when viewed from the light emitting direction; a first wiring member that is electrically conductive and is arranged above the protrusion on the light-emitting side; an opening formed in a range from a first layer light emitting surface, which is the surface on the light emitting direction side, to the first wiring member arranged above the protrusion; an opening electrode provided in the opening and electrically connecting the second layer and the first wiring member; A light emitting device comprising: (Appendix 2) The second layer is a second layer electrode electrically connected to the second light emitting element; a second wiring member that electrically connects the opening electrode and the second layer electrode; 2. The light-emitting device according to claim 1, comprising: (Appendix 3) The first wiring member is electrically connected to the first light-emitting portion. 3. The light-emitting device according to claim 1 or 2. (Appendix 4) The first wiring member is insulated from the first light-emitting portion. 3. The light-emitting device according to claim 1 or 2. (Appendix 5) The first layer has a first protruding insulating member that electrically insulates the protruding portion from the first wiring member. 5. The light emitting device according to claim 1, wherein: (Appendix 6) The first light emitting element has a p-type semiconductor layer and an n-type semiconductor layer stacked with a light emitting layer interposed between the first light emitting portion and the protruding portion. 6. The light emitting device according to any one of claims 1 to 5, (Appendix 7) the first light-emitting element has a first layer electrode connection portion formed by a layer of the p-type semiconductor layer or the n-type semiconductor layer that is closer to the substrate layer at a location different from the first light-emitting portion and the protrusion when viewed from the light-emitting direction, the first layer electrode connection portion being electrically connected to the first light-emitting portion; The first layer has a first layer electrode provided at the first layer electrode connection portion, The first wiring member is electrically connected to the first layer electrode. 7. The light-emitting device according to claim 6, (Appendix 8) The protrusion has a height in the light emission direction with respect to the boundary surface with the substrate layer as a reference, the height being equal to that of the first light emitting portion. 8. The light emitting device according to any one of claims 1 to 7, (Appendix 9) The opening is formed so that the distance between the inner walls decreases in the direction opposite to the light emission direction. 9. The light emitting device according to any one of claims 1 to 8, (Appendix 10) The length of the protrusion in a direction perpendicular to the light-emitting direction is longer than the length of the bottom of the opening in the direction perpendicular to the light-emitting direction. 10. The light emitting device according to any one of claims 1 to 9, (Appendix 11) A light-emitting device according to any one of claims 1 to 10. A display device characterized by: [Explanation of symbols]

[0152] 1, 201...LED display device, 2, 202...LED display unit, 8, 208...pixel unit, 9, 209...light-emitting unit, 10, 210...substrate layer, 11, 211...circuit board, 12, 212...substrate wiring unit, 12X...extension wiring unit, 12Y...through wiring unit, 30, 230...first thin film layer, 31, 41, 51, 231, 241, 251...transparent insulating layer, 32, 232...GaAs layer, 32A, 232M...red light-emitting unit, 32C, 42F, 232J, 232L, 232N, 2 42H, 242K, 242L, 252P...protrusion, 32D, 232P...red electrode connection, 32TL...light-emitting layer, 32TN...n-type semiconductor layer, 32TP...p-type semiconductor layer, 33, 43, 53, 233, 243, 253...electrodes, 33A, 43A, 53A, 233M, 243M, 253M...anode electrode, 33D, 43E, 53D, 233P, 243P, 253L...cathode electrode, 33F, 43C, 53F, 233H, 233K, 233R, 243J, 243L, 243N, 253 H, 253K...interlayer connection electrode, 34, 44, 54, 234, 244, 254...insulating layer, 35, 45, 55, 235, 245, 255...wiring layer, 35C, 45F, 55F, 235L, 245H, 255P...cathode connection wiring layer, 36, 46, 56, 236, 246, 256...transparent insulating layer, 39, 239...first light-emitting portion, 40, 240...second thin film layer, 42, 242...GaN layer, 42A, 242M...green light-emitting portion, 42E, 242P...green electrode connection portion, 49, 249...first 2 Light-emitting portion, 50, 250...third thin film layer, 52, 252...GaN layer, 52A, 252M...blue light-emitting portion, 52D, 252L...blue electrode connection portion, 59, 259...third light-emitting portion, 71F, 72C, 73F, 271H, 271K, 271R, 272J, 272L, 272N, 273H, 273K, 274P...wiring hole, 235M, 245M, 255M...anode connection wiring layer, 259...third light-emitting portion, 260...electrode layer, 261...conductive layer, 262...common cathode electrode, E...light-emitting direction.

Claims

1. a substrate layer provided with a conductive substrate wiring member; a first layer including a first light-emitting element stacked on the substrate layer and having a first light-emitting portion whose light-emitting direction is opposite to the substrate layer, and an insulating member covering the first light-emitting element; a second layer stacked on the first layer in the light-emitting direction and including a second light-emitting element having a second light-emitting portion; and the second light-emitting element is arranged at a position where the second light-emitting portion overlaps the first light-emitting portion of the first light-emitting element when viewed from the light-emitting direction, The first layer is a protrusion that is a part of the first light-emitting element and that protrudes in the light-emitting direction at a position different from the first light-emitting portion when viewed from the light-emitting direction; a first wiring member that is electrically conductive and is arranged above the protrusion on the light-emitting side; an opening formed in a range from a first layer light emitting surface, which is the surface on the light emitting direction side, to the first wiring member arranged above the protrusion; an opening electrode provided in the opening and electrically connecting the second layer and the first wiring member; A light emitting device comprising:

2. The second layer is a second layer electrode electrically connected to the second light emitting element; a second wiring member that electrically connects the opening electrode and the second layer electrode; 2. The light emitting device according to claim 1, further comprising:

3. The first wiring member is electrically connected to the first light-emitting unit.

3. The light emitting device according to claim 2.

4. The first wiring member is insulated from the first light-emitting unit.

3. The light emitting device according to claim 2.

5. The first layer has a first protruding insulating member that electrically insulates the protruding portion from the first wiring member.

2. The light emitting device according to claim 1.

6. The first light emitting element has a p-type semiconductor layer and an n-type semiconductor layer stacked with a light emitting layer interposed between the first light emitting portion and the protruding portion.

2. The light emitting device according to claim 1.

7. the first light-emitting element has a first layer electrode connection portion formed by a layer of the p-type semiconductor layer or the n-type semiconductor layer that is closer to the substrate layer at a location different from the first light-emitting portion and the protrusion when viewed from the light-emitting direction, the first layer electrode connection portion being electrically connected to the first light-emitting portion; The first layer has a first layer electrode provided at the first layer electrode connection portion, The first wiring member is electrically connected to the first layer electrode.

7. The light emitting device according to claim 6.

8. The protrusion has a height in the light emission direction with respect to the boundary surface with the substrate layer as a reference, the height being equal to that of the first light emitting portion.

2. The light emitting device according to claim 1.

9. The opening is formed so that the distance between the inner walls decreases in the direction opposite to the light emission direction.

2. The light emitting device according to claim 1.

10. The length of the protrusion in a direction perpendicular to the light-emitting direction is longer than the length of the bottom of the opening in the direction perpendicular to the light-emitting direction.

10. The light emitting device according to claim 9.

11. A light-emitting device according to any one of claims 1 to 10. A display device characterized by:

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