Current switching dac
The current-switching DAC design addresses power and speed challenges by using differential switches and bias control circuits to manage current paths, achieving low power consumption and high-speed operation in digital-to-analog conversion.
Patent Information
- Application Number
- JP2024051398
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-03-27
- Publication Date
- 2025-10-09
AI Technical Summary
Current-switching DACs face challenges in achieving both low power consumption and high-speed operation due to continuous current flow when digital signal logic switches and the need for current stabilization, which affects current consumption and operating speed.
A current-switching DAC design that includes unit current sources with differential switches, bias voltage control circuits, and bias control signal generation circuits to manage current paths based on digital input signals, reducing current consumption during idle states and stabilizing current values quickly for high-speed operation.
The design achieves both low power consumption and high-speed operation by controlling current paths and stabilizing current values efficiently, enabling applications with binary and unary codes while minimizing power usage.
Smart Images
Figure 2025150497000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to current-switching DACs. [Background technology]
[0002] In recent years, with the spread of smartphones and the Internet of Things (IoT), there has been an increasing need for low-power analog circuit technology. One of the key blocks in analog circuits is the DAC (digital-to-analog conversion circuit), and current-switching DACs are widely used due to their high-speed operation. However, to ensure high operating speed, current-switching DACs have a differential switch in each unit current source. When the digital signal logic is at the L level and the current source is disconnected from the output, the current source is connected to the power supply path, allowing a constant current to continue to flow. Therefore, there are challenges in reducing current consumption.
[0003] Current Switching DAC (Non-Patent Document 1) is an alternative technology to current switching DACs. In a current switching DAC, when the logic of a digital signal is at L level and the current source is disconnected from the output, the current source is not connected to the power supply path, and the output of the current source becomes high impedance, thereby reducing current consumption. However, when the logic of the digital signal switches to H level, it takes time for the current flowing through the current source to stabilize, which makes it unsuitable for high-speed operation. Therefore, a technology that achieves both low current consumption and high-speed operation is needed.
[0004] In Japanese Patent Laid-Open Publication No. 6-177766 (Patent Document 1), in a current-switching DAC, a power-down signal output during standby when no DA conversion operation is performed is simultaneously supplied to a pull-up section provided in each current source, thereby stopping the operation of each current source and reducing current consumption during standby. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] Japanese Patent Application Publication No. 6-177766 [Non-patent literature]
[0006] [Non-Patent Document 1] B. Razavi, "The current-steering DAC [a circuit for all seasons]", IEEE Solid-St. Circ., vol. 10, no. 1, pp. 11-15, 2018. Summary of the Invention [Problem to be solved by the invention]
[0007] However, in the circuit configuration of Patent Document 1, all current sources are activated at the same time as the DA conversion operation is started, so even current sources that are disconnected from the output when the logic of the digital signal is at L level continue to flow current, and it is not possible to reduce the current consumption during the DA conversion operation.
[0008] The present disclosure has been made to solve such problems, and has an object to provide a current-switching DAC that can achieve both low power consumption and high-speed operation. [Means for solving the problem]
[0009] The current-switching DAC disclosed herein is a current-switching DAC that converts a plurality of digital input signals into an analog output signal, and includes: a plurality of unit current sources provided corresponding to the plurality of digital input signals, each capable of supplying a predetermined current in accordance with the corresponding digital input signal; a pair of output terminals connected to the plurality of unit current sources, respectively, and capable of outputting the sum of the predetermined current values of the unit current sources; and a bias voltage supply unit that outputs a bias voltage to be supplied to each of the plurality of unit current sources. Each unit current source includes a current source for supplying the predetermined current in accordance with the bias voltage, a differential switch connected to the current source for switching current paths between the pair of output terminals in accordance with the corresponding digital input signal, a bias voltage control circuit for controlling the supply of the bias voltage to drive the current source, and a bias control signal generation circuit that generates a control signal to control the bias voltage control circuit in accordance with the corresponding digital input signal. [Effects of the Invention]
[0010] A current-switching DAC according to one disclosure can achieve both low power consumption and high-speed operation. [Brief explanation of the drawings]
[0011] [Figure 1] 1 is a diagram illustrating an example of a circuit configuration of a current switching DAC 101 according to a first embodiment. [Figure 2] The unit current source I1 of the current switching DAC 101 according to the first embodiment <k>FIG. 1 is a diagram illustrating an example of a circuit configuration. [Figure 3] Unit current source I1 according to the first embodiment <k>10A and 10B are timing charts illustrating the operation of the [Figure 4] FIG. 1 is a diagram illustrating an example of a circuit configuration of a current switching DAC 100 according to a comparative example. [Figure 5] Unit current source I0 of current switching type DAC 100 according to the comparative example <k>FIG. 1 is a diagram illustrating an example of a circuit configuration. [Figure 6] Unit current source I0 according to the comparative example <k>10A and 10B are timing charts illustrating the operation of the [Figure 7] FIG. 10 is a diagram illustrating an example of a circuit configuration of a current switching DAC 102 according to a second embodiment. [Figure 8] Unit current source I2 of current switching type DAC 102 according to the second embodiment <k>FIG. 1 is a diagram illustrating an example of a circuit configuration. [Figure 9] Unit current source I2 according to the second embodiment <k>10A and 10B are timing charts illustrating the operation of the [Figure 10] FIG. 10 is a diagram illustrating an example of a circuit configuration of a current switching DAC 103 according to a third embodiment. [Figure 11] The unit current source I3 of the current switching DAC 103 according to the third embodiment <k>FIG. 1 is a diagram illustrating an example of a circuit configuration. [Figure 12] Unit current source I3 according to the third embodiment <k>10A and 10B are timing charts illustrating the operation of the DETAILED DESCRIPTION OF THE INVENTION
[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, identical or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.
[0013] Embodiment 1 1 is a diagram showing an example of a circuit configuration of a current switching DAC 101 according to the first embodiment. Referring to FIG. 1, the current switching DAC 101 receives a plurality of digital input signals D <n:0>(n is any natural number) and a digital input signal D <n:0>A digital input signal DB with the opposite polarity to <n:1>an input terminal for receiving an input of the analog output signal, a pair of output terminals IOUT and IOUTB for outputting an analog output signal, a power supply VDD, a power supply VSS, a bias voltage supply unit 10, a resistor R1, and a plurality of unit current sources I1 capable of supplying a predetermined current. <n:1>where: <n:0>The symbol indicates 0 to n.
[0014] The bias voltage supply unit 10 includes a plurality of unit current sources I1 <n:1>A bias voltage Vbias is supplied to each of the units. Resistor R1 is connected between an arbitrary power supply VDD and the output terminal IOUTB. Multiple unit current sources I1 <n:1>Each of these has a pair of input terminals, one additional input terminal, a pair of output terminals, a GND terminal, and a bias terminal.
[0015] Unit current source I1 according to the first embodiment <k>In this case, a pair of input terminals receives a digital input signal D <k>、DB <k>(k is any natural number less than or equal to n) input. The additional input terminal is a digital input signal D <k-1>The pair of output terminals are connected to the output terminals IOUT and IOUTB. The GND terminal is connected to the power supply VSS. The bias terminal is supplied with the bias voltage Vbias.
[0016] The current-switching DAC101 receives the digital input signal D <n:0>and DB <n:1>According to the input of multiple unit current sources I1 <n:1>A predetermined current is generated by the resistors 11 and 12, and the sum of the generated currents is output as an analog output signal to the output terminal IOUT.
[0017] FIG. 2 shows the unit current source I1 of the current switching DAC 101 according to the first embodiment. <k>2 is a diagram illustrating an example of a circuit configuration of a unit current source I1. <k>is the digital input signal D <k>、DB <k>A pair of input terminals that receive the input of a digital input signal <k-1>a pair of output terminals connected to the output terminals IOUT and IOUTB, a bias terminal supplied with a bias voltage Vbias, and a GND terminal.
[0018] Unit current source I1 <k>includes a transistor NM5 constituting a current source, a differential switch 20 connected to the current source for switching a current path between the pair of output terminals in accordance with a corresponding digital input signal, a bias voltage control circuit 30 for controlling the supply of a bias voltage for driving the current source, and a bias control signal generation circuit 40 for generating a control signal for controlling the bias voltage control circuit 30 in accordance with the corresponding digital input signal.
[0019] The transistor NM5, which serves as a current source, is provided between the node Va and the GND terminal, and its gate receives an output signal from the bias voltage control circuit 30. The differential switch 20 includes a transistor NM1 (first NMOS transistor) and a transistor NM2 (second NMOS transistor) for complementary switching of current paths between a pair of output terminals in accordance with the input signal. The transistor NM1 is provided between the node Va and the output terminal IOUT, and its gate receives a digital input signal D <k>The transistor NM2 is provided between the node Va and the output terminal IOUTB, and its gate receives the digital input signal DB <k>Receives input.
[0020] The bias voltage control circuit 30 includes a transistor NM3 (third NMOS transistor) and a transistor NM4 (fourth NMOS transistor) that operate complementarily to control the supply or cutoff of the bias voltage Vbias in accordance with a control signal. The transistor NM3 is provided between the node Vb and the bias terminal, and its gate receives a control signal input from the bias control signal generation circuit 40. The transistor NM4 is provided between the node Vb and the GND terminal, and its gate receives a control signal input from the bias control signal generation circuit 40.
[0021] The bias control signal generating circuit 40 includes a NOR circuit NR1 and an inverter INV1. The NOR circuit NR1 receives a digital input signal D <k>and digital input signal D <k-1>and outputs the NOR logic operation result to inverter INV1. Inverter INV1 is connected to NOR circuit NR1, and outputs the inverted signal of the output signal of NOR circuit NR1 to the gate of transistor NM3 as a control signal. The output signal of NOR circuit NR1 is output to the gate of transistor NM4 as a control signal.
[0022] FIG. 3 shows the unit current source I1 according to the first embodiment. <k>3 is a timing chart illustrating the operation of the unit current source I1. <k>Digital input signal D <k> 、D <k-1>10 shows the time change of the logic and the time change of the current I5 of the transistor NM5.
[0023] In the current switching DAC 101 according to the first embodiment, in the period before time t0 in FIG. <k> 、D <k-1>The logic of both is L level, and the digital input signal DB <k>The logic of the unit current source I1 according to the first embodiment is at the H level. <k>In this case, the transistor NM1 is OFF and the transistor NM2 is ON, so the drain of the transistor NM5 is disconnected from the output terminal IOUT and connected to the output terminal IOUTB. <k> 、D <k-1>When both of the logics of the digital input signal D are at the L level, the NOR circuit NR1 and the inverter INV1 turn the transistor NM3 OFF and the transistor NM4 ON. The node Vb is pulled down, the transistor NM5 turns OFF, and the current I5 does not flow. Therefore, the digital input signal D <k> 、D <k-1>When the logic of both is low, the digital input signal DB <k>When the logic is at the H level, the unit current source I1 <k>is a state in which almost no current is consumed.
[0024] On the other hand, in the current switching DAC 101 according to the first embodiment, during the period from time t0 to time t1 in FIG. <k>is at the L level, and the digital input signal DB <k>is at a high logic level, and the digital input signal D <k-1>The logic of unit current source I1 is at H level. <k>In this case, the NOR circuit NR1 and the inverter INV1 of the bias control signal generating circuit 40 turn the transistor NM3 ON and the transistor NM4 OFF, and the bias voltage Vbias is supplied to the gate of the transistor NM5, and the current I5 of the transistor NM5 starts to flow. <k>This makes it possible to provide a preparatory period for stabilizing the current value of the current I5 of the transistor NM5 just before the logic of becomes H and the transistor NM5 is connected to the output terminal IOUT. The current I5 is shown stabilizing from 0 A to a constant current value during the period from time t0 to t1. Therefore, the configuration of the current switching DAC 101 makes it possible to achieve both low power consumption and high-speed operation.
[0025] 4 is a diagram showing an example of a circuit configuration of a current switching DAC 100 according to a comparative example. Referring to FIG. 4, the current switching DAC 100 according to the comparative example has a unit current source I0 <n:1>The input terminals of the pair of digital input signals D <k>,DB <k>The difference is that there is no input terminal for receiving other digital input signals. The other circuit configuration is the same as that of the current-switching DAC 101 shown in FIG. 1, so detailed description thereof will not be repeated.
[0026] FIG. 5 shows a unit current source I0 of a current switching DAC 100 according to a comparative example. <k>5 is a diagram illustrating an example of a circuit configuration of a unit current source I0 of a current switching DAC 100 according to a comparative example. <k>is the unit current source I1 of the current switching type DAC101 <k>2 in that it does not include the bias voltage control circuit 30 and the bias control signal generation circuit 40. As for other circuit configurations, the unit current source I1 shown in FIG. <k>Since it is similar to the above, detailed description thereof will not be repeated.
[0027] FIG. 6 shows a comparative example of a unit current source I0 <k>6 is a timing chart illustrating the operation of the unit current source I0 <k>Digital input signal D <k>10 shows the time change of the logic and the time change of the current I5 of the transistor NM5.
[0028] In the current switching DAC 100 according to the comparative example, in the period before time t2 in FIG. <k>The logic of is L level and the digital input signal DB <k>The logic of the unit current source I0 according to the comparative example is at the H level. <k>In this case, since the transistor NM1 is OFF and the transistor NM2 is ON, the drain of the transistor NM5 is disconnected from the output terminal IOUT, and the current I5 does not affect the output terminal IOUT. <k>The current generated by the current switching DAC 100 does not affect the output terminal IOUT of the current switching DAC 100. On the other hand, as shown by the current I5 in FIG. 6, a constant current continues to flow to the output terminal IOUTB. Therefore, there is a problem in reducing power consumption. <k>The logic of is L level and the digital input signal DB <k>The reason why the current I5 continues to flow even when the logic is at H level is because the unit current source I0 <k>Once the current I5 of the transistor NM5 is stopped, the digital input signal D <k>The logic of is H level and the digital input signal DB <k>This is because when the logic of switches to L level and the current I5 starts to flow, it takes time for the current value to stabilize, which slows down the operating speed.
[0029] In the current switching DAC 101 according to the first embodiment, as described above, in the period before time t0 in FIG. <k>In the period from time t0 to t1, the transistor NM5 consumes almost no current. Also, as described above, during the period from time t0 to t1, a preparation period can be provided in which the current value of the current I5 of the transistor NM5 is stabilized beforehand just before the transistor NM5 is connected to the output terminal IOUT. FIG. 3 shows how the current I5 stabilizes from 0 A to a constant current value during the period from time t0 to t1. Therefore, the configuration of the current switching DAC 101 according to the first embodiment makes it possible to achieve both low power consumption and high-speed operation.
[0030] The current switching DAC 101 according to the first embodiment is configured to <k> 、D <k-1>Using the unit current source I1 <k>In order to control the ON / OFF of transistor NM5, if the upper bits of the binary code are turned OFF and the other lower bits are turned ON (10000... → 01111...), the current I5 flowing through transistor NM5 of the unit current source for the lower bits will not yet be stable when transistor NM5 is connected to the output terminal IOUT, making high-speed operation difficult. Therefore, binary code cannot be used in the current switching DAC 101.
[0031] On the other hand, in the case of unary code (thermometer code), the logic level monotonically changes from low-order bits to high-order bits, making the current-switching DAC 101 applicable. In the current-switching DAC according to the comparative example, when the high-order bits, especially the MSB, switch (01111... → 10000...), all current sources other than the MSB switch from ON to OFF, while the MSB current source switches from OFF to ON. This causes a large error if there is a mismatch in the elements, making it difficult to ensure linearity. Therefore, a segmented approach is widely used, where the low-order bits are binary code and the high-order bits are unary code. Because the current value increases with increasing bit order, applying the current-switching DAC 101 to the high-order unary code bits, which consume relatively large amounts of current, can significantly reduce current consumption.
[0032] The current switching DAC 101 according to the first embodiment performs temperature compensation such as changing the current value according to the temperature information stored in the register, and the like, to compensate for the digital input signal D <n:1>This is particularly effective in applications where the digital input signal D <n:1>In this example, the bias control signal generation circuit 40 can be appropriately modified to deal with the case where the change in the digital input signal D is not monotonous and has jumps by increasing the number of inputs to the NOR circuit NR1. <k> 、D <k-1>However, the present invention is not limited to this, and other digital input signals may be used, or a specific digital input signal may be used.
[0033] In this example, the current switching type DAC 101 is described as being configured with all NMOS transistors, but it is obvious that this example also holds true when all transistors are configured with PMOS transistors.
[0034] Embodiment 2 7 is a diagram showing an example of a circuit configuration of a current switching DAC 102 according to the second embodiment. Referring to FIG. 7, the current switching DAC 102 according to the second embodiment includes a power supply VDD, a power supply VSS, an input terminal, a clock input terminal, a pair of output terminals IOUT and IOUTB, a bias voltage supply unit 10, a resistor R1, and a plurality of unit current sources I2 capable of supplying a predetermined current. <n:1>It is equipped with:
[0035] The bias voltage supply unit 10 includes a plurality of unit current sources I2 <n:1>A bias voltage Vbias is supplied to each of the units. Resistor R1 is connected between an arbitrary power supply VDD and the output terminal IOUTB. Multiple unit current sources I2 <n:1>Each of these has an input terminal, a clock input terminal, a pair of output terminals, a GND terminal, and a bias terminal.
[0036] Unit current source I2 according to the second embodiment <k>In this case, the input terminal is a digital input signal D <k>The clock terminal receives the clock signal CLK as an input. The pair of output terminals are connected to the output terminals IOUT and IOUTB. The GND terminal is connected to the power supply VSS. The bias terminal is supplied with the bias voltage Vbias.
[0037] The current-switching DAC102 receives the digital input signal D <n:1>and multiple unit current sources I2 according to the input of the clock signal CLK. <n:1>A predetermined current is generated by the resistors 11 and 12, and the sum of the generated currents is output as an analog output signal to the output terminal IOUT.
[0038] FIG. 8 shows the unit current source I2 of the current switching DAC 102 according to the second embodiment. <k>8 is a diagram illustrating an example of a circuit configuration of a unit current source I2 <k>is the digital input signal D <k>a clock input terminal that receives a clock signal CLK; a pair of output terminals connected to the output terminals IOUT and IOUTB; a bias terminal that receives a bias voltage Vbias; and a GND terminal.
[0039] Unit current source I2 <k>includes a transistor NM5 constituting a current source, a differential switch 20 connected to the current source and for switching a current path between the pair of output terminals in accordance with a corresponding digital input signal, a bias voltage control circuit 30 for controlling the supply of a bias voltage for driving the current source, a bias control signal generation circuit 41 for generating a control signal for controlling the bias voltage control circuit 30 in accordance with the corresponding digital input signal, and a flip-flop circuit FF1.
[0040] The configurations of the current source, differential switch 20, and bias voltage control circuit 30 are similar to those described in FIG. 2, and therefore detailed description thereof will not be repeated.
[0041] The bias control signal generating circuit 41 includes inverters INV1 and INV2. The inverter INV2 outputs an inverted signal of the corresponding digital input signal as a control signal to the gate of the transistor NM4, and the inverter INV1 outputs an inverted signal of the input signal from the inverter INV2 as a control signal to the gate of the transistor NM3.
[0042] Flip-flop circuit FF1 includes an input terminal, a clock input terminal, and a pair of output terminals.
[0043] The input terminal of the flip-flop circuit FF1 is the digital input signal D <k>The clock input terminal receives a clock signal CLK. The pair of output terminals are connected to nodes Q and QB, respectively, with the gate of transistor NM1 connected to node Q and the gate of transistor NM2 connected to node QB.
[0044] FIG. 9 shows a unit current source I2 according to the second embodiment. <k>9 is a timing chart illustrating the operation of the unit current source I2 <k>Digital input signal D <k>, and show the time change in the logic of the clock signal CLK and the time change in the current I5 of the transistor NM5, respectively.
[0045] The operation of the current switching DAC 102 according to the second embodiment will be described. <k>In this case, the digital input signal D <k>、DB <k>A glitch may occur if there is a timing discrepancy between the signals input to the current switching DAC 102 according to the second embodiment. A flip-flop circuit is provided for each gate of the transistor NM1 and the transistor NM2.
[0046] By synchronizing with the clock signal CLK and outputting a signal from the flip-flop circuit FF1 to the transistors NM1 and NM2 at the same time, it is possible to suppress the occurrence of glitches and achieve high-speed operation.
[0047] In this configuration, the digital input signal D <k>Even if the logic of is H level, the transistor NM1 remains OFF and the transistor NM2 remains ON as long as the logic of the clock signal CLK does not become H level, and therefore the current I5 does not affect the output terminal IOUT.
[0048] Therefore, as shown in FIG. 8, the digital input signal D <k>is input to the bias control signal generation circuit 41.
[0049] The bias control signal generation circuit 41 receives a digital input signal D <k>During the period from when the logic of the transistor NM3 changes to H level until the logic of the clock signal CLK changes to H level, the control signal is outputted to turn on the transistor NM3 and turn off the transistor NM4 in advance.
[0050] Therefore, by activating the transistor NM5 in advance, a preparation period can be provided until the current I5 stabilizes, thereby realizing high-speed operation while suppressing current consumption.
[0051] Unit current source I2 according to the second embodiment <k>The operation of the digital input signal D is specifically described below. <k>The logic of node Q is at H level, the logic of clock signal CLK is at L level, and the logic of node QB is at H level until the logic of clock signal CLK changes to H level. Since transistor NM1 is OFF and transistor NM2 is ON, the current I5 of transistor NM5 flows through IOUTB, and there is no effect on the output terminal IOUT. At time t3, the digital input signal D <k>becomes high, and thus, during the period until time t4 when the logic of the clock signal CLK changes to high, transistor NM3 is turned on, transistor NM4 is turned off, and transistor NM5 is turned on via inverters INV2 and INV1. When transistor NM5 turns on, current I5 begins to flow, and it becomes possible to stabilize current I5 during the period until time t4.
[0052] After time t4 when the logic of the clock signal CLK becomes H level, the logic of node Q switches to H level and the logic of node QB switches to L level, so that transistor NM1 turns ON and transistor NM2 turns OFF, and current I5 of transistor NM5 flows through output terminal IOUT. Current I5 begins to affect output terminal IOUT, but because current I5 is already stable at that time, high-speed operation becomes possible.
[0053] The current switching DAC 101 according to the first embodiment is configured to <k> 、D <k-1>Using the unit current source I1 <k>However, the current switching type DAC 102 according to the second embodiment can be applied only to the unary code (thermometer code) in order to control the ON / OFF of the transistor NM5. <k-1>is not used, and the unit current source I2 <k>Own digital input signal D <k>Therefore, it can be applied to not only unary codes but also binary codes.
[0054] In this example, the current switching DAC 102 is described as being configured with all NMOS transistors, but it is obvious that this example also holds true when all transistors are configured with PMOS transistors.
[0055] Embodiment 3 10 is a diagram showing an example of a circuit configuration of a current switching DAC 103 according to the third embodiment. Referring to FIG. 10, the current switching DAC 103 according to the third embodiment includes a power supply VDD, a power supply VSS, an input terminal, a pair of output terminals IOUT and IOUTB, a bias voltage supply unit 10, a resistor R1, and a plurality of unit current sources I3 capable of supplying a predetermined current. <n:1>(n is any natural number) and a timing control signal generation circuit 50.
[0056] The bias voltage supply unit 10 includes a plurality of unit current sources I3 <n:1>A bias voltage Vbias is supplied to each of the resistors. Resistor R1 is connected between an arbitrary power supply VDD and the output terminal IOUTB.
[0057] The timing control signal generation circuit 50 generates a digital input signal D <n:1>and DB <n:1>and outputs the timing control signal EN <n:1>Specifically, the timing control signal generation circuit 50 monitors the timing of changes in a plurality of digital input signals, and generates a plurality of timing control signals corresponding to the plurality of digital input signals, respectively, based on the monitoring results. For example, when the digital input signal D <k>(k is any natural number less than or equal to n) logic is L level, digital input signal DB <k>While the logic is at H level, the timing control signal EN <k>The logic of is controlled to be L level, and the digital input signal D <k>The logic of is H level, and the digital input signal DB <k>Just before the logic of the timing control signal EN <k>The logic is controlled to be H.
[0058] Multiple unit current sources I3 <n:1>Each of these has a pair of input terminals, one input control terminal, a pair of output terminals, a GND terminal, and a bias terminal.
[0059] Unit current source I3 according to the third embodiment <n:1>In this case, a pair of input terminals receives a digital input signal D <k>、DB <k>(k is any natural number less than or equal to n) input. One input control terminal is the timing control signal EN <k>The pair of output terminals is connected to the output terminals OUT and IOUTB, and the GND terminal is connected to the power supply VSS. The bias terminal is supplied with the bias voltage Vbias.
[0060] The current-switching DAC103 generates a digital input signal D based on the input data VIN. <n:0>and DB <n:1>According to the input of multiple unit current sources I3 <n:1>A predetermined current is generated by the resistors 11 and 12, and the sum of the generated currents is output as an analog output signal to the output terminal IOUT.
[0061] FIG. 11 shows the unit current source I3 of the current switching DAC 103 according to the third embodiment. <k>11 is a diagram showing an example of a circuit configuration of the unit current source I3 <k>is the digital input signal D <k>、DB <k>A pair of input terminals for receiving the input of the timing control signal EN <k>a pair of output terminals connected to the output terminals IOUT and IOUTB, a bias terminal supplied with a bias voltage Vbias, and a GND terminal.
[0062] Unit current source I3 <k>includes a transistor NM5 constituting a current source, a differential switch 20 connected to the current source for switching a current path between the pair of output terminals in accordance with a corresponding digital input signal, a bias voltage control circuit 30 for controlling the supply of a bias voltage for driving the current source, and a bias control signal generation circuit 42 for generating a control signal for controlling the bias voltage control circuit 30 in accordance with the corresponding digital input signal.
[0063] The configurations of the current source, differential switch 20, and bias voltage control circuit 30 are similar to those described in FIG. 2, and therefore detailed description thereof will not be repeated.
[0064] The bias control signal generating circuit 42 includes inverters INV1 and INV2. Inverter INV2 receives the timing control signal EN <k>The inverter INV1 outputs an inverted signal of the input signal from the inverter INV2 as a control signal to the gate of the transistor NM3.
[0065] FIG. 12 shows the unit current source I3 according to the third embodiment. <k>12 is a timing chart illustrating the operation of the unit current source I3 <k>Digital input signal D <k>, timing control signal EN <k>10 shows the time change of the logic and the time change of the current I5 of the transistor NM5.
[0066] The operation of the current switching DAC 103 according to the third embodiment will be described. In the current switching DAC 103 according to the third embodiment, in the period before time t5 in FIG. <k>The logic of is L level, and the digital input signal DB <k>The logic of the unit current source I3 according to the third embodiment is at the H level. <k>In this state, the transistor NM1 is OFF and the transistor NM2 is ON, so the drain of the transistor NM5 is disconnected from the output terminal IOUT, and the current I5 does not affect the output terminal IOUT. <k>The logic of is controlled to the L level. Therefore, the inverters INV2 and INV1 of the bias control signal generation circuit 42 turn the transistor NM3 OFF, the transistor NM4 ON, and the transistor NM5 OFF. As a result, no current flows through the transistor NM5, reducing power consumption.
[0067] Next, during the period from time t5 to time t6 in FIG. 12, the digital input signal D <k>、DB <k>Since the logic of the period before time t5 is the same as that before time t5, in FIG. 11, the transistor NM1 is OFF, the transistor NM2 is ON, and the current I5 does not affect the output terminal IOUT. <k>、DB <k>The timing control signal generation circuit 50 shown in FIG. <k>The logic of is controlled to H level. Therefore, the inverters INV2 and INV1 of the bias control signal generation circuit 42 turn the transistor NM3 ON, the transistor NM4 OFF, and the transistor NM5 ON. As a result, the current I5 of the transistor NM5 starts to flow. Note that the period from time t5 to t6 is assumed to be a sufficient time for the current value of the current I5 to stabilize.
[0068] Next, in FIG. 12, at time t6, the digital input signal D <k>The logic of is H level, and the digital input signal DB <k>The logic of this signal switches to the L level. At this time, in FIG. 11, transistor NM1 is ON and transistor NM2 is OFF, so current I5 switches to a state that affects the output terminal IOUT. However, the current value of current I5 is already stable at time t6, so high-speed operation is possible. As a result of the above, the current-switching DAC 103 can achieve both low current consumption and high-speed operation.
[0069] The current switching DAC 101 of the first embodiment is configured to <k> 、D <k-1>Using the unit current source I1 <k>However, the current switching type DAC 103 according to the third embodiment can be applied only to the unary code (thermometer code) in order to control the ON / OFF of the transistor NM5. <k-1>is not used, and the unit current source I3 <k>Own digital input signal D <k>Therefore, it can be applied to not only unary codes but also binary codes.
[0070] In this example, the current switching type DAC 103 is described as being configured with all NMOS transistors, but it is obvious that this example also holds true when all transistors are configured with PMOS transistors.
[0071] The embodiments disclosed herein are intended to be combined as appropriate within the scope of compatibility. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]
[0072] 10 bias voltage supply unit, 20 differential switch, 30 bias voltage control circuit, 40, 41, 42 bias control signal generation circuit, 50 timing control signal generation circuit, 100, 101, 102, 103 current switching type DAC, FF1 flip-flop circuit, I0, I1, I2, I3 unit current source.< / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>
Claims
1. A current-switching DAC that converts a plurality of digital input signals into analog output signals, a plurality of unit current sources provided corresponding to the plurality of digital input signals, each capable of supplying a predetermined current in response to the corresponding digital input signal; a pair of output terminals connected to the plurality of unit current sources, respectively, and capable of outputting a sum of predetermined current values of the unit current sources; a bias voltage supply unit that outputs a bias voltage to be supplied to each of the plurality of unit current sources, Each of the unit current sources is a current source for supplying a predetermined current in accordance with the bias voltage; a differential switch connected to the current source for switching a current path between the pair of output terminals according to the corresponding digital input signal; a bias voltage control circuit for controlling the supply of the bias voltage for driving the current source; a bias control signal generating circuit that generates a control signal for controlling the bias voltage control circuit according to the corresponding digital input signal.
2. the differential switch includes first and second switches for complementary switching of current paths to the pair of output terminals in accordance with the input signal; 2. The current-switching DAC according to claim 1, wherein the bias voltage control circuit includes third and fourth switches that operate complementarily to control supply or cut-off of the bias voltage in accordance with the control signal.
3. 3. The current-switching DAC according to claim 2, wherein the bias control signal generation circuit includes a logic circuit that generates the control signal based on the corresponding digital input signal and another digital input signal of the plurality of digital input signals.
4. 3. The current-switching DAC according to claim 2, wherein each of the unit current sources further includes a flip-flop circuit for outputting a drive signal for driving the third and fourth switches in accordance with a clock signal for a corresponding digital input signal.
5. a timing control signal generation circuit that monitors change timings of the plurality of digital input signals and generates a plurality of timing control signals corresponding to the plurality of digital input signals based on the monitoring results; 3. The current-switching DAC according to claim 2, wherein the bias control signal generating circuit generates the control signal according to a corresponding timing signal.
Citation Information
Patent Citations
D / A conversion circuit
JP1994177766A