Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of reducing inter-wire capacitance.SOLUTION: A semiconductor device 101 comprises an interlayer dielectric (ILD) made of an antiferroelectric material. The minimum relative permittivity of the interlayer dielectric (ILD) is less than 2. The materials constituting the interlayer dielectric ILD1 is at least one selected from the group consisting of HfO2, ZrO2, Pb(In0.5Nb0.5) O3, NbNaO3, ZrPbO3, TiZrLaPbO3, TiZrPbO3, NH4H2PO4, or NH4H2AsO4.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] In semiconductor devices, with the increasing integration density of semiconductor elements, multilayer wiring technology is being adopted and the wiring is becoming increasingly finer. As a result, the problem of electrical signal propagation delay is becoming apparent. To address this propagation delay, low-dielectric-constant materials (low-k materials) are being explored as materials for constituting interlayer insulating films in order to reduce the capacitance between wirings sandwiching the interlayer insulating film. The dielectric constant k of low-dielectric-constant materials in practical use as interlayer insulating films is approximately 2.6 or more and 2.9 or less.

[0003] Japanese Patent Application Laid-Open No. 2009-004408 describes a wiring structure made up of a low dielectric constant insulating film and wiring buried in a wiring trench formed in the insulating film. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-004408 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, semiconductor devices have been required to further reduce the capacitance between interconnects. As a result, materials with an even lower dielectric constant than SiOCH are being searched for as materials for forming interlayer insulating films.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] The semiconductor device according to one embodiment includes an interlayer insulating film ILD made of an antiferroelectric material, and the minimum value of the relative dielectric constant of the interlayer insulating film ILD is less than 2.

[0008] A semiconductor device according to another embodiment includes a semiconductor substrate having a first surface, a gate electrode formed on the first surface via a gate insulating film, sidewall insulating films covering each side surface of the gate insulating film and the gate electrode, and an interlayer insulating film formed on the first surface so as to cover the gate electrode and the sidewall insulating film. The interlayer insulating film and the antiferroelectric material are arranged at an interval from each other.

[0009] A method for manufacturing a semiconductor device according to one embodiment includes a first step of forming a semiconductor element on a first surface of a semiconductor substrate, and a second step of forming an interlayer insulating film covering the semiconductor element on the first surface. The interlayer insulating film is made of an antiferroelectric material. In the second step, the temperature of the interlayer insulating film is set below the Curie point of the antiferroelectric material. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a semiconductor device that can reduce the capacitance between interconnects compared to a semiconductor device that includes an interlayer insulating film made of SiOCH. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a configuration example of a semiconductor device according to a first embodiment. [Figure 2] 2 is a partially enlarged plan view showing a configuration example of a semiconductor element included in the semiconductor device according to the first embodiment. FIG. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor element shown in FIG. [Figure 4] 1 is a graph showing the relationship between the electric field and polarization of an antiferroelectric material, obtained by simulation. [Figure 5] 10 is a graph showing the relationship between the electric field and the relative dielectric constant of an antiferroelectric material, obtained by simulation. [Figure 6]3 is a flowchart showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 2 is a circuit diagram showing an example of a circuit that is realized when an ESD pulse enters the semiconductor device according to the first embodiment. FIG. [Figure 8] 10 is a graph showing the change over time of a current flowing through a MOS transistor after an ESD pulse enters the semiconductor device according to the first embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of a circuit that is realized when an ESD pulse enters the semiconductor device according to the second embodiment. [Figure 11] 11 is a partially enlarged plan view showing a configuration example of a semiconductor element included in a semiconductor device according to a third embodiment. FIG. [Figure 12] 10 is a partially enlarged plan view showing a configuration example of a semiconductor element included in a semiconductor device according to a fourth embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0013] (Embodiment 1) <Configuration of semiconductor device> FIG. 1 is a plan view of a semiconductor device 101 according to a first embodiment. As shown in FIG. 1, the semiconductor device 101 according to the first embodiment has a scribe region 1 and a module region 2. The scribe region 1 has the outer periphery of the semiconductor device 101 formed by scribing a semiconductor substrate. The module region 2 is formed inside the scribe region 1 in a plan view. The module region 2 has, for example, an input / output circuit IOC, an analog circuit ANA, a logic circuit LC, a memory circuit MEM, etc. The memory circuit MEM includes a plurality of memory cells.

[0014] The module region 2 includes a plurality of semiconductor elements. The plurality of semiconductor elements include at least one of transistors and diodes. The plurality of semiconductor elements include, for example, vertical insulated gate field effect transistors. The insulated gate field effect transistors are, for example, MIS (Metal Insulator Semiconductor) transistors. The MIS (Metal Insulator Semiconductor) transistors are, for example, MOS (Metal Oxide Semiconductor) transistors. The MOS transistors are, for example, included in each of a plurality of memory cells in the memory circuit MEM. Note that there are no particular limitations on the semiconductor elements included in the module region 2.

[0015] FIG. 2 is a partially enlarged plan view showing a MOS transistor included in one memory cell in the semiconductor device 101. FIG. 3 is a cross-sectional view taken along arrow III-III in FIG. 2. As shown in FIG. 2, the semiconductor device 101 is formed using a semiconductor substrate SUB. The semiconductor substrate SUB has a first surface SF1. The MOS transistor TR is formed on the first surface SF1.

[0016] In this specification, two directions along the first surface SF1 that are perpendicular to each other are referred to as the X direction and the Y direction. The direction perpendicular to the first surface SF1 is referred to as the Z direction. In the Z direction, the direction from the single crystal layer 30 toward the bulk layer 10 is referred to as the downward direction, and the direction from the bulk layer 10 toward the single crystal layer 30 is referred to as the upward direction. A viewpoint viewed from above in the Z direction is referred to as a planar view.

[0017] The semiconductor substrate SUB is, for example, an SOI (Silicon On Insulator) substrate. The SOI substrate includes a bulk layer 10, a substrate isolation film 20, and a single-crystal layer 30. The bulk layer 10, the substrate isolation film 20, and the single-crystal layer 30 are stacked in this order in the Z direction. The substrate isolation film 20 is disposed between the bulk layer 10 and the single-crystal layer 30. The bulk layer 10 is made of, for example, p-type single-crystal silicon. The substrate isolation film 20 is, for example, a buried oxide film (BOX). The substrate isolation film 20 is made of, for example, an n-type silicon oxide film. The single-crystal layer 30 is made of, for example, single-crystal silicon. The single-crystal layer 30 includes a p-type well PW, n-type impurity regions (drain DR and source SO), and a channel region between the drain DR and source SO. The semiconductor substrate SUB of the semiconductor device 101 is not limited to an SOI substrate.

[0018] The MOS transistor TR1 is, for example, an NMOS (N-channel MOS) transistor. The MOS transistor TR1 includes a p-type well PW, a source SO and a drain DR which are n-type impurity regions, a channel region between the source SO and the drain DR, and a gate electrode GE. The p-type well PW, the source SO and the drain DR, and the channel region are formed in a single crystal layer 30. The drain DR, the source SO, and the channel region are formed above the p-type well PW. The source SO and the drain DR are spaced apart in the X direction. The gate electrode GE is formed on the channel region via a gate insulating film GI. Sidewall insulating films SW are formed on the side walls of the gate insulating film GI and the gate electrode GE. The sidewall insulating film SW includes, for example, at least one of a silicon oxide film and a silicon nitride film. Each of the source SO and the drain DR is connected to a plurality of first wiring layers M1A (described later) via a first contact CT layer C1A. Each of the source SO and the drain DR may have an LDD (Lightly Doped Drain) structure. The MOS transistor TR1 may be a PMOS (P-channel MOS) transistor.

[0019] The semiconductor device 101 further includes a contact element for fixing the potential of the p-type well PW in addition to the MOS transistor TR. The contact element is arranged alongside the MOS transistor TR in, for example, the X direction. The contact element includes, for example, a p-type impurity region HPR and a second contact CTB. The p-type impurity region HPR is formed in an upper portion of the p-type well PW. The second contact CTB is connected to the p-type impurity region HPR. The second contact CTB is arranged at an interval from the first contact CTA in, for example, the X direction.

[0020] The semiconductor device 101 further includes an isolation film ISL. The isolation film ISL is formed, for example, between MOS transistors TR adjacent to each other in the X direction or the Y direction, and between the MOS transistor TR and the contact element. The isolation film ISL is arranged so as to surround each of the MOS transistor TR and the contact element in a plan view. The MOS transistor TR1 is electrically isolated from each of the other semiconductor elements and the contact elements by the isolation film ISL. The isolation film ISL has, for example, a shallow trench isolation (STI) structure. The isolation film ISL is, for example, a silicon oxide film.

[0021] The semiconductor device 101 further includes, for example, a plurality of wiring layers M, a plurality of interlayer insulating films ILD, and a plurality of contacts CT. The plurality of wiring layers M and the plurality of interlayer insulating films ILD are stacked in the Z direction. The plurality of wiring layers M are disposed on the upper surfaces of the plurality of interlayer insulating films ILD or in wiring grooves formed in the upper surfaces of the plurality of interlayer insulating films ILD. Each of the plurality of wiring layers M may be formed by a damascene method. A through-hole is formed in each of the plurality of interlayer insulating films ILD. Each of the plurality of contacts CT is formed in the through-hole.

[0022] The multiple interlayer insulating films ILD include a lower interlayer insulating film ILD1 located at the lowest position, an upper interlayer insulating film ILD2 located at the highest position, and at least one middle interlayer insulating film ILD3 located between the lower interlayer insulating film ILD1 and the upper interlayer insulating film ILD2.

[0023] The lower interlayer insulating film ILD1 is formed on the first surface SF1 so as to cover the gate electrode GE and the sidewall insulating film SW. The lower interlayer insulating film ILD1 is in contact with, for example, the gate electrode GE, the sidewall insulating film SW, and the element isolation film ISL. The lower interlayer insulating film ILD1 is in contact with, for example, the source SO and the drain DR. The lower interlayer insulating film ILD1 is not in contact with the gate insulating film GI.

[0024] The plurality of wiring layers M include a lower wiring layer M1 located at the lowest position, an upper wiring layer located at the highest position, and at least one intermediate wiring layer located between the lower wiring layer M1 and the upper wiring layer.

[0025] The lower wiring layer M1 is disposed on the upper surface of the lower interlayer insulating film ILD1 or in a groove formed on the upper surface. The lower wiring layer M1 includes a plurality of first wiring layers M1A and second wiring layers M1B that are disposed at intervals from each other in at least one of the X and Y directions. Each of the plurality of first wiring layers M1A is connected to the drain DR or source SO of the MOS transistor TR via a first contact CTA. The second wiring layer M1B is connected to the p-type well PW via a second contact CTB. The first contact CTA and the second contact CTB are formed in a through hole formed in the lower interlayer insulating film ILD1.

[0026] The upper wiring layer is formed on the upper interlayer insulating film. The upper wiring layer includes a pad. Each of the plurality of interlayer insulating films ILD overlaps with the pad in the Z direction.

[0027] The lower interlayer insulating film ILD1 is made of an antiferroelectric material AFD. In an antiferroelectric material, when no external electric field is applied, each of the multiple sublattices in the crystal has a dielectric polarization. However, two adjacent sublattices have dielectric polarizations in opposite directions, resulting in almost no polarization as a whole crystal. From a different perspective, when no external electric field is applied, the overall electric susceptibility χ of the antiferroelectric material constituting the lower interlayer insulating film ILD1 is lower than that of a typical low-k material. The lower interlayer insulating film ILD1 is made of an antiferroelectric material whose overall electric susceptibility χ is less than 1. In other words, the minimum relative dielectric constant of the lower interlayer insulating film ILD1 is less than 2. Typical low-k materials include SiOCH, methyl-containing SiO2, parylene, and polyaryl ether. Their relative dielectric constants are 2.6 to 2.9.

[0028] The materials constituting the lower interlayer insulating film ILD1 are HfO2, ZrO2, Pb(In 0.5 Nb 0.5 )O3, NbNaO3, ZrPbO3, TiZrLaPbO3, TiZrPbO3, NH4H2PO4, or NH4H2AsO4.

[0029] Preferably, the antiferroelectric material constituting the lower interlayer insulating film ILD1 has an amorphous structure or a polycrystalline structure. Alternatively, the antiferroelectric material constituting the lower interlayer insulating film ILD1 may be a relaxor dielectric. In these cases, the overall electric susceptibility χ of the antiferroelectric material constituting the lower interlayer insulating film ILD1 is substantially zero. Therefore, the minimum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is substantially 1.

[0030] The maximum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is greater than 2.9. Preferably, the maximum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is 4.3 or more.

[0031] Figure 4 is a graph showing the relationship between the electric field and polarization of 2-trichloromethylbenzimidazole (TCMBI), an example of an antiferroelectric, obtained by simulation. The boundary element method was used for the simulation. The open circles in Figure 4 represent the relationship when the applied voltage is increased from negative to positive, while the filled circles represent the relationship when the applied voltage is decreased from positive to negative. As shown in Figure 4, the polarization-electric field curve of the antiferroelectric material constituting the lower interlayer insulating film ILD1 shows a double hysteresis loop. As shown in Figure 4, when the external electric field applied to the antiferroelectric material is smaller than a certain magnitude, the antiferroelectric material undergoes polarization, similar to a paraelectric material. When the external electric field applied to the antiferroelectric material is larger than a certain magnitude, the polarization directions of the multiple sublattices in the antiferroelectric material align, and spontaneous polarization (spontaneous polarization) occurs, similar to a ferroelectric material. In this case, the relative permittivity of the antiferroelectric material is greater than 2.9, e.g., greater than 4.0. The polarization (residual polarization) of the antiferroelectric when the external electric field applied to the antiferroelectric is set to zero is 15 μC / cm 2 or less. In other words, the remanent polarization of the antiferroelectric is almost zero. The spontaneous polarization and remanent polarization of the lower interlayer insulating film ILD1 can be determined based on a DE curve obtained by measuring the electric flux density D when an electric field E is applied to the lower interlayer insulating film ILD1, for example.

[0032] Fig. 5 is a graph showing the relationship between the electric field and the dielectric constant when the applied electric field is gradually increased, obtained by the above simulation, for the example of the antiferroelectric material shown in Fig. 4. As shown in Fig. 5, the dielectric constant of the antiferroelectric material constituting the lower interlayer insulating film ILD1 is kept less than 2 until the strength of the electric field exceeds a specific value, and becomes greater than 2.9 when the strength of the electric field exceeds the specific value. The specific value is, for example, 50 kV / cm or more and 70 kV / cm or less.

[0033] In the semiconductor device 101, during normal operation, the electric field applied between a pair of conductors via the lower interlayer insulating film ILD1 is set to be less than the electric field that generates spontaneous polarization in the antiferroelectric material.

[0034] In this specification, the normal operation of a semiconductor device refers to a normal operation predetermined for the semiconductor device, in which no electrical charges are generated due to cosmic rays, ESD (Electro-Static Discharge), or the like. In this specification, cosmic rays refer to radiation coming from outer space or particles resulting from such radiation, having energies on the order of several MeV to GeV. Cosmic rays are particle radiation or high-energy electromagnetic radiation. Examples of particle radiation include alpha rays, beta rays, neutron rays, and proton rays. Examples of electromagnetic radiation include gamma rays and X-rays. The radiation-induced particles are, for example, neutrons generated when cosmic rays collide with atomic nuclei such as oxygen or nitrogen when penetrating the atmosphere.

[0035] In the semiconductor device 101, the electric field applied to the lower interlayer insulating film ILD1 due to cosmic rays is set to be less than the electric field that causes a phase transition of the antiferroelectric material constituting the lower interlayer insulating film ILD1 to a ferroelectric material. Preferably, the electric field applied to the lower interlayer insulating film ILD1 due to ESD is set to be less than the electric field that causes a phase transition of the antiferroelectric material constituting the lower interlayer insulating film ILD1 to a ferroelectric material.

[0036] The lower interlayer insulating film ILD1 does not have a plurality of pores. The lower interlayer insulating film ILD1 does not include a porous material. The Young's modulus of the lower interlayer insulating film ILD1 is higher than the Young's modulus of a low-k material made of a porous material. The Young's modulus of the lower interlayer insulating film ILD1 is 8 GPa or more.

[0037] The thickness of the lower interlayer insulating film ILD1 is equal to or greater than 2 nm and less than 50 nm, and is the dimension of the lower interlayer insulating film ILD1 in the Z direction.

[0038] <Method of manufacturing a semiconductor device> An example of a method for manufacturing the semiconductor device 101 will now be described with reference to FIG.

[0039] First, a semiconductor substrate SUB is prepared (first step S1). The semiconductor substrate SUB has a first surface SF1. The semiconductor substrate SUB is prepared as, for example, an SOI substrate.

[0040] Second, semiconductor elements are formed on the first surface SF1 of the semiconductor substrate SUB (second step S2). In this step, the MOS transistor TR and the contact elements are formed.

[0041] Third, the lower interlayer insulating film ILD1 is formed on the first surface SF1 so as to cover the MOS transistor TR (third step S3). The lower interlayer insulating film ILD1 is made of an antiferroelectric material. In this step, the lower interlayer insulating film ILD1 is formed at a temperature below the Curie point of the antiferroelectric material. Furthermore, after this step, the lower interlayer insulating film ILD1 is not heated to a temperature equal to or higher than the Curie point of the antiferroelectric material. This prevents the antiferroelectric material constituting the lower interlayer insulating film ILD1 from transforming into a ferroelectric material.

[0042] Fourth, the contact CT and the wiring layer M1 are formed (fourth step S4). The wiring layer M1 is formed by, for example, the damascene method. In this manner, the semiconductor device 101 shown in FIGS. 2 and 3 is manufactured. In this step, post-metallization annealing (PMA) may be performed. In this case, the heating temperature is set to a temperature below the Curie point of the antiferroelectric material constituting the lower interlayer insulating film ILD1. Thereafter, an intermediate interlayer insulating film, an intermediate wiring layer, an upper interlayer insulating film, an upper wiring layer, etc. are formed.

[0043] In the second to fourth steps, the layout pattern of each element is formed using photolithography. The layout pattern of each element is designed and verified based on the specifications required for the semiconductor device 101. The layout pattern of each element is designed based on the results of a circuit simulation that simulates the operation of a circuit including the MOS transistor TR, or by an automatic place and route (P&R) program. One example of the circuit simulation is SPICE (Simulation Program with Integrated Circuit Emphasis).

[0044] The manufacturing method of the semiconductor device 101 may further include a step (fifth step) of adjusting the relative dielectric constant of the lower interlayer insulating film ILD1 by, for example, heating at least a part of the lower interlayer insulating film ILD1 after the third step S3. The fifth step is performed, for example, before the fourth step S4. The fifth step may be performed within the third step. The fifth step may be performed as an annealing treatment of the lower interlayer insulating film ILD1. For example, when the lower interlayer insulating film ILD1 is made of an antiferroelectric material having a perovskite structure, a solvent containing the antiferroelectric material can be spin-coated on the first surface SF1, and then the solvent can be volatilized by irradiating it with electromagnetic waves under predetermined conditions, thereby obtaining the lower insulating film ILD1 with an adjusted dielectric constant. The electromagnetic waves may be laser light. In the case of annealing treatment using electromagnetic wave irradiation such as laser light, the lower insulating film ILD1 is rapidly cooled after the irradiation of the electromagnetic waves is stopped, and therefore the crystal structure of the lower insulating film ILD1 can be made amorphous or polycrystalline. In the case of annealing by electromagnetic wave irradiation, the electromagnetic wave irradiation conditions may be such that only the surface of the lower interlayer insulating film ILD1 is heated.

[0045] The fifth step may be performed as an annealing treatment using a hot plate. In this case, the lower insulating film ILD1 is gradually cooled after heating by the hot plate is stopped, so that the crystal structure of the lower insulating film ILD1 can be made single crystal.

[0046] Furthermore, the fifth step may reduce the uniformity of at least one of the film quality and film thickness of the lower insulating film ILD1. For example, the lower insulating film ILD1 after the fifth step may contain at least one of a large number of aggregates and voids. Therefore, in the fifth step, a process for improving the uniformity of the film quality, film thickness, etc. of the lower insulating film ILD1 may be performed before the process for adjusting the relative dielectric constant. As such a process, for example, a solvent such as chlorobenzene, dimethylformamide, or 1-cyclohexyl-2-pyrrolidone may be spin-coated on a solvent containing an antiferroelectric material spin-coated on the first surface SF1.

[0047] <Effects of the semiconductor device 101> The effects of the semiconductor device 101 will be described in comparison with a comparative example. The semiconductor device according to comparative example 1 differs from the semiconductor device 101 only in that the interlayer insulating film is made of a general low-dielectric-constant material. As described above, the relative dielectric constant of general low-dielectric-constant materials is 2.6 or higher. Therefore, in order to suppress propagation delay in the semiconductor device according to comparative example 1, it is necessary to increase the distance between two adjacent conductors separated by an interlayer insulating film and reduce the capacitance between the two conductors. Therefore, in the semiconductor device according to comparative example 1, it is difficult to simultaneously achieve high integration of semiconductor elements and miniaturization of each wiring while suppressing the propagation delay that accompanies such increases.

[0048] In contrast, in the semiconductor device 101, the lower interlayer insulating film ILD1 is made of an antiferroelectric material. Therefore, in a state where an external electric field is not applied, the overall electric susceptibility χ of the antiferroelectric material constituting the lower interlayer insulating film ILD1 is lower than that of a general low-dielectric constant material and is less than 1. In other words, the minimum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is less than 2. Therefore, in the semiconductor device 101, the capacitance between two adjacent conductors sandwiching the lower interlayer insulating film ILD1 (for example, the capacitance between the first wiring layer M1A and the second wiring layer M1B) is smaller than the capacitance between two adjacent conductors sandwiching the interlayer insulating film ILD made of a general low-dielectric constant material in the semiconductor device according to Comparative Example 1. Therefore, the semiconductor device 101 can achieve higher integration of semiconductor elements and finer wiring while suppressing the accompanying propagation delay, compared to the semiconductor device according to Comparative Example 1.

[0049] The size and spacing of the semiconductor elements and wiring in semiconductor device 101 may be the same as those in the semiconductor device of Comparative Example 1, in which case the operating speed can be increased compared to the semiconductor device of Comparative Example 1.

[0050] Furthermore, in the semiconductor device according to Comparative Example 1, since the interlayer insulating film is made of a general low-dielectric-constant material, it is difficult to suppress the occurrence of soft errors caused by cosmic rays. Cosmic rays that reach the earth from outer space include high-energy radiation and secondary neutrons generated when the radiation collides with and destroys the nuclei of atoms such as oxygen in the atmosphere. These cosmic rays have energies ranging from several MeV to GeV, and when they enter a semiconductor device, they destroy the nuclei of the atoms that make up the semiconductor device, ultimately generating a large amount of electric charge (hereinafter referred to as anomalous charge). The large amount of anomalous charge is not captured by the inter-wiring capacitance, which uses the interlayer insulating film made of a low-dielectric-constant material as a dielectric, but reaches the impurity region that constitutes the storage node in the memory circuit. In an n-type MOS transistor, the anomalous charge reaches the drain.

[0051] Specifically, when cosmic rays destroy the nuclei of atoms constituting, for example, an interconnect layer, a dipole consisting of a proton and an electron is generated. The energy of the dipole is on the order of 10 MV immediately after its generation, but attenuates as the distance between the proton and electron increases. When the distance between the two increases to the order of a few atoms, the dipole becomes an electron-hole pair with an energy of the order of keV. As the electron-hole pair moves through the semiconductor device, its energy weakens to the order of 10 eV, but the electrons and holes are not captured by the inter-wiring capacitance, which uses an interlayer insulating film made of a low-dielectric-constant material as a dielectric, and reach the impurity region constituting the storage node in the memory circuit. As a result, the semiconductor device according to Comparative Example 1 has a problem in which data stored in the storage node is inverted, making it susceptible to soft errors.

[0052] In contrast, in the semiconductor device 101, since the lower interlayer insulating film ILD1 is made of an antiferroelectric material, the relative dielectric constant of the lower interlayer insulating film ILD1 becomes higher than the relative dielectric constant of the lower interlayer insulating film ILD1 during normal operation only when the strength of the electric field applied to the lower interlayer insulating film ILD1 by the abnormal charge exceeds the specific value. Therefore, part of the abnormal charge can be trapped in the inter-wiring capacitance with the lower interlayer insulating film ILD1 as the dielectric. As a result, the semiconductor device 101 can achieve both high integration of semiconductor elements and miniaturization of each wiring, as well as suppression of the accompanying propagation delay and occurrence of soft errors.

[0053] In the semiconductor device 101, the maximum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is greater than 2.9. That is, the maximum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is higher than the relative dielectric constant of a low-k material. The semiconductor device 101 can suppress the occurrence of the soft errors as compared to the semiconductor device of Comparative Example 1. Preferably, the maximum value of the relative dielectric constant of the element isolation film ISL is greater than 4.3. That is, the maximum value of the relative dielectric constant of the element isolation film ISL is higher than the relative dielectric constant of a silicon oxide film. The semiconductor device 101 can suppress the occurrence of the soft errors as compared to the semiconductor device of Comparative Example 1. The semiconductor device 101 is particularly suitable for technical fields where high integration of semiconductor elements and suppression of the soft errors are simultaneously required, such as automobiles, aerospace systems, and medical equipment. In aerospace systems, the atmosphere cannot be expected to provide a shielding effect against cosmic rays, and therefore even a very small probability of soft errors cannot be tolerated. The semiconductor device 101 is also suitable for such cases.

[0054] Furthermore, in the semiconductor device according to Comparative Example 1, the relative dielectric constant of the interlayer insulating film can be reduced by using a low-dielectric-constant material in which a plurality of voids are formed for the interlayer insulating film. However, the mechanical strength of the interlayer insulating film in which a plurality of voids are formed is lower than the mechanical strength of an interlayer insulating film in which a plurality of voids are not formed. Therefore, when a wire is bonded to a pad by a wire bonding method, an abnormality such as a crack is likely to occur in the interlayer insulating film in which a plurality of voids are formed. When a wiring layer is formed by a damascene method or the like, an abnormality such as a dent is likely to occur in the interlayer insulating film in which a plurality of voids are formed. Such an abnormality may cause a hard error in the semiconductor device.

[0055] In contrast, the lower interlayer insulating film ILD1 of the semiconductor device 101 does not have multiple pores. The Young's modulus of the lower interlayer insulating film ILD1 is 8 GPa or more, which is higher than the Young's modulus of a porous low-dielectric-constant material. Therefore, in the semiconductor device 101, abnormalities such as cracks and dents are less likely to occur in the lower interlayer insulating film ILD1. Therefore, in the semiconductor device 101, the occurrence of hard errors can also be suppressed.

[0056] Furthermore, in the semiconductor device 101, the remanent polarization of the antiferroelectric material constituting the lower interlayer insulating film ILD1 is 15 μC / cm 2 Because the temperature is less than 100°C, abnormal charges are less likely to remain.

[0057] In the semiconductor device 101, the thickness of the lower interlayer insulating film ILD1 is 2 nm or more and 50 nm or less. When the lower interlayer insulating film ILD1 and an interlayer insulating film ILD made of a general low-dielectric-constant material having the same thickness are compared, the minimum value of the relative dielectric constant of the lower interlayer insulating film ILD1 is lower than the relative dielectric constant of the general low-dielectric-constant material. Therefore, in the semiconductor device 101, if the thickness of the lower interlayer insulating film ILD1 is equivalent to that of the interlayer insulating film ILD of the semiconductor device according to Comparative Example 1, the capacitance value of the lower interlayer insulating film ILD1 during normal operation can be made smaller than the capacitance value of the interlayer insulating film ILD made of a general low-dielectric-constant material. On the other hand, in the semiconductor device 101, if the capacitance value of the lower interlayer insulating film ILD1 during normal operation is equivalent to that of the interlayer insulating film ILD of the semiconductor device according to Comparative Example 1, the thickness of the lower interlayer insulating film ILD1 can be made thicker than the thickness of the interlayer insulating film ILD made of a general low-dielectric-constant material. As a result, in the semiconductor device 101, compared to the semiconductor device according to Comparative Example 1, it is possible to reduce leakage current while also reducing capacitance between interconnects, thereby enabling higher performance.

[0058] In the semiconductor device 101, the electric field applied between a pair of adjacent conductors sandwiching the lower interlayer insulating film ILD1 during normal operation is set to be less than the electric field at which spontaneous polarization occurs in the antiferroelectric, so that the relative dielectric constant of the lower interlayer insulating film ILD1 can be maintained at less than 2 during normal operation. For example, the electric field applied between the pair of conductors during normal operation may be less than 50 kV / cm. The electric field at which spontaneous polarization occurs in the antiferroelectric may be 50 kV / cm or more.

[0059] Furthermore, in the semiconductor device 101, the external electric field applied to the lower interlayer insulating film ILD1 due to cosmic rays is set to be less than the electric field that causes a phase transition of the antiferroelectric material constituting the lower interlayer insulating film ILD1 to a ferroelectric material. Therefore, after the application of the external electric field is stopped, the relative dielectric constant of the lower interlayer insulating film ILD1 becomes less than 2 again, and abnormal charges are gradually released from the lower interlayer insulating film ILD1. As a result, in the semiconductor device 101, even if the external electric field is repeatedly applied with intervals, the occurrence of the soft error can be suppressed each time, and further, propagation delay can be suppressed during normal operation after the external electric field is removed.

[0060] An external electric field equal to or greater than the electric field that causes a phase transition of the antiferroelectric material constituting the lower interlayer insulating film ILD1 to a ferroelectric material may be applied to the lower interlayer insulating film ILD1. The lower interlayer insulating film ILD1 may also transition from an antiferroelectric material to a ferroelectric material. In this case, the above-described effects of the lower interlayer insulating film ILD1 can be reproduced in the semiconductor device 101 by performing a process to return the lower interlayer insulating film ILD1 from a ferroelectric material to an antiferroelectric material. Examples of a process to return the lower interlayer insulating film ILD1 from a ferroelectric material to an antiferroelectric material include a process of alternately applying positive and negative voltages, such as an AC voltage, to the lower interlayer insulating film ILD1 and gradually decreasing this voltage. This process disrupts the ferroelectric material's crystal structure, thereby reproducing the antiferroelectric material's crystal structure. Another example of a process is to heat the lower interlayer insulating film ILD1 and then rapidly cool it. This process destroys the ferroelectric material's crystal structure, thereby reproducing the antiferroelectric material's crystal structure.

[0061] Furthermore, in the semiconductor device according to Comparative Example 1, when abnormal charges due to ESD enter from the pad, the interlayer insulating film made of a low dielectric constant material cannot capture the abnormal charges.

[0062] In contrast, in the semiconductor device 101, when an ESD pulse penetrates through a pad, an external electric field of 50 kV / cm or more is applied to the lower interlayer insulating film ILD1 located between the pad and the semiconductor element. As a result, the relative dielectric constant of the lower interlayer insulating film ILD1 becomes higher than the relative dielectric constant of the low-k material, and part of the abnormal charge caused by ESD can be trapped in the inter-wiring capacitance with the lower interlayer insulating film ILD1 as the dielectric.

[0063] FIG. 7 is a circuit diagram showing an example of a circuit included in the semiconductor device 101 that is realized only when an ESD pulse enters through a pad. FIG. 8 is a graph showing the change over time in current flowing through a MOS transistor after an ESD pulse enters the semiconductor device. The solid line in FIG. 8 indicates the change over time in current flowing through the MOS transistor TR in the semiconductor device 101, and the dashed line indicates the change over time in current flowing through the MOS transistor in the semiconductor device according to Comparative Example 1. As shown in FIG. 7, the lower interlayer insulating film ILD1 can function as a capacitor that prevents some of the abnormal charge caused by ESD from reaching the MOS transistor TR. As a result, as shown in FIG. 8, in the semiconductor device 101, the current value flowing through the MOS transistor TR can be suppressed to less than the current threshold BD at which the MOS transistor TR is destroyed. As a result, the semiconductor device 101 can prevent ESD-induced destruction of semiconductor elements.

[0064] In the manufacturing method of the semiconductor device 101, in the step of forming the lower interlayer insulating film ILD1, the temperature of the lower interlayer insulating film ILD1 is set to be lower than the Curie point of the antiferroelectric material constituting the lower interlayer insulating film ILD1, so that the antiferroelectric material constituting the lower interlayer insulating film ILD1 can be prevented from transitioning to a ferroelectric material.

[0065] In the semiconductor device 101, the lower interlayer insulating film ILD1 is not in contact with the gate insulating film GI, and therefore, the charges trapped in the lower interlayer insulating film ILD1 can be prevented from reaching the gate insulating film GI.

[0066] (Embodiment 2) Unless otherwise specified, the semiconductor device 102 according to the second embodiment has the same configuration, operating principle, and effects as those of the first embodiment. Therefore, the same configuration, operating principle, and effects as those of the first embodiment will not be described repeatedly.

[0067] 9, the semiconductor device 102 according to the second embodiment differs from the semiconductor device 101 in that the upper interlayer insulating film ILD2 is made of an antiferroelectric material. The antiferroelectric material constituting the upper interlayer insulating film ILD2 may be equivalent to the antiferroelectric material constituting the lower interlayer insulating film ILD1 in the semiconductor device 101. The upper interlayer insulating film ILD2 made of an antiferroelectric material is provided so that spontaneous polarization occurs in the antiferroelectric material when an electric field of 50 kV / cm or more is applied to the pad.

[0068] The lower interlayer insulating film ILD1 is made of, for example, a paraelectric material. Preferably, the antiferroelectric constituting the upper interlayer insulating film ILD2 has an amorphous structure. The mechanical strength of such an antiferroelectric is expected to be higher than that of an antiferroelectric having a single crystal structure. The antiferroelectric constituting the upper interlayer insulating film ILD2 may have a polycrystalline structure. In this case, it is preferable that the polycrystalline antiferroelectric is such that each of a plurality of single crystals is bonded without a binder. The mechanical strength of such an antiferroelectric is also expected to be higher than that of an antiferroelectric having a single crystal structure.

[0069] The semiconductor device 102 includes an upper interlayer insulating film ILD2 made of an antiferroelectric material, and therefore, like the semiconductor device 101, it is possible to achieve high integration of semiconductor elements and miniaturization of each wiring, while simultaneously suppressing the propagation delay and the occurrence of soft errors, and to suppress damage to semiconductor elements due to ESD.

[0070] 10 is a circuit diagram showing an example of a circuit that is implemented only when an ESD pulse enters through a pad in the semiconductor device 102. As shown in FIG. 10, the upper interlayer insulating film ILD1 is disposed directly below the pad PAD and can function as a capacitor that prevents some of the abnormal charge caused by ESD from reaching the MOS transistor TR and other electronic components. Therefore, the semiconductor device 102 has a higher ESD protection capability due to the antiferroelectric than the semiconductor device 101.

[0071] Furthermore, cracks are less likely to occur in the upper interlayer insulating film ILD2 of the semiconductor device 102 during wire bonding, and recesses are less likely to occur when the wiring layer M1 is formed by a machine method.

[0072] In the semiconductor device 102, the lower interlayer insulating film ILD1 may be made of the above-mentioned general low-dielectric-constant material.

[0073] In the semiconductor device 102, the lower interlayer insulating film ILD1 may also be made of an antiferroelectric material. In this case, the lower interlayer insulating film ILD1 and the upper interlayer insulating film ILD2 can each function as a capacitor for preventing a portion of the abnormal charge caused by ESD from reaching the MOS transistor TR and other electronic components. Therefore, in this semiconductor device 102, the antiferroelectric material provides a higher level of protection against ESD than the configurations shown in FIGS. 8 and 10.

[0074] Each of the plurality of interlayer insulating films ILD may be made of an antiferroelectric material. The antiferroelectric materials constituting each of the plurality of interlayer insulating films ILD may be the same as or different from each other.

[0075] (Embodiment 3) Unless otherwise specified, semiconductor device 103 according to embodiment 3 has the same configuration, operating principle, and effects as those of embodiment 1. Therefore, the same configuration, operating principle, and effects as those of embodiment 1 will not be described repeatedly.

[0076] 11, the semiconductor device 103 according to the third embodiment is different from the semiconductor device 101 in that not only the lower interlayer insulating film ILD1 but also the element isolation film is made of an antiferroelectric. The antiferroelectric constituting the element isolation film may be equivalent to the antiferroelectric constituting the lower interlayer insulating film ILD1 in the semiconductor device 101.

[0077] The semiconductor device 103 is configured so that the voltage applied between two regions separated by an isolation film ISL during normal operation is less than twice the drive voltage of the MOS transistor TR1 formed in that region. When the drive voltage of the MOS transistor TR1 is 1 V, the semiconductor device 103 is configured so that the voltage applied between the two regions separated by the isolation film ISL during normal operation is less than 2 V. When the drive voltage of the MOS transistor TR1 is 3.3 V, the semiconductor device 103 is configured so that the voltage applied between the two regions separated by the isolation film ISL during normal operation is less than 6.6 V.

[0078] The electric field applied between the two regions separated by the element isolation film ISL during normal operation is, for example, less than 50 kV / cm.

[0079] <Effects of the semiconductor device 103> The effects of the semiconductor device 103 will be described in comparison with the comparative example. The semiconductor device according to comparative example 2 differs from the semiconductor device 103 only in that the isolation film is made of a typical low-dielectric-constant material. As described above, the relative dielectric constant of typical low-dielectric-constant materials is 2.6 or more and 2.9 or less. Therefore, the semiconductor device according to comparative example 2 can achieve a higher operating speed of the semiconductor element compared to a semiconductor device including an isolation film made of a dielectric material with a relative dielectric constant greater than 2.9. However, in the semiconductor device according to comparative example 2, when cosmic rays are incident on the single-crystalline layer 30 immediately below the gate insulating film GI, a large number of electron-hole pairs are generated in the single-crystalline layer 30 immediately below the gate insulating film GI, resulting in electrical conduction between the source and drain. As a result, the semiconductor device according to comparative example 2 has difficulty in suppressing the occurrence of soft errors caused by cosmic rays while suppressing a decrease in the operating speed of the semiconductor element.

[0080] In contrast, in the semiconductor device 103, the element isolation film ISL is made of an antiferroelectric material, and therefore the relative dielectric constant of the element isolation film ISL becomes higher than the relative dielectric constant of the element isolation film ISL during normal operation only when the strength of the electric field applied to the element isolation film ISL by the abnormal charge exceeds the above-mentioned specific value. Therefore, a part of the abnormal charge can be captured by the element isolation film ISL. As a result, in the semiconductor device 103, it is possible to suppress the occurrence of soft errors while suppressing a decrease in the operating speed of the semiconductor element.

[0081] Furthermore, in the semiconductor device according to Comparative Example 2, it is difficult to narrow the width of the isolation film in the X or Y direction in order to suppress a decrease in the operating speed of the semiconductor element due to an increase in the capacitance value of the isolation film. In other words, in the semiconductor device according to Comparative Example 2, it is difficult to reduce the chip area while suppressing a decrease in the operating speed of the semiconductor element.

[0082] In contrast, in semiconductor device 103, the element isolation film is made of an antiferroelectric material, and the minimum value of the relative dielectric constant of the antiferroelectric material is less than 2. Therefore, in semiconductor device 103, compared to the semiconductor device according to Comparative Example 2, an increase in the capacitance value of the element isolation film can be suppressed even if the width of the element isolation film in the X direction or Y direction is narrowed. As a result, in semiconductor device 103, it is possible to reduce the chip area while suppressing a decrease in the operating speed of the semiconductor element.

[0083] The size and spacing of the semiconductor elements and wiring in semiconductor device 103 may be the same as those in the semiconductor device of comparative example 2, in which case the operating speed can be increased compared to the semiconductor device of comparative example 2.

[0084] The semiconductor device 103 may have the same configuration as the semiconductor device 102, except that the element isolation film is made of an antiferroelectric material.

[0085] (Fourth embodiment) Unless otherwise specified, semiconductor device 104 according to embodiment 4 has the same configuration, operating principle, and effects as those of embodiment 1. Therefore, the same configuration, operating principle, and effects as those of embodiment 1 will not be described repeatedly.

[0086] As shown in FIG. 12, the semiconductor device 104 according to the fourth embodiment differs from the semiconductor device 101 in that not only the lower interlayer insulating film ILD1 but also the substrate isolation film is made of an antiferroelectric material.

[0087] The antiferroelectric material constituting the substrate isolation film may be equivalent to the antiferroelectric material constituting the lower interlayer insulating film ILD1 in the semiconductor device 101.

[0088] The semiconductor device 104 is provided so that the voltage applied between the bulk layer 10 and the single-crystal layer 30, which are separated by the substrate isolation film 20, during normal operation is less than twice the drive voltage of the MOS transistor TR1 formed in that region. When the drive voltage of the MOS transistor TR1 is 1 V, the semiconductor device 103 is provided so that the voltage applied between the two regions separated by the substrate isolation film 20 during normal operation is less than 2 V. When the drive voltage of the MOS transistor TR1 is 3.3 V, the semiconductor device 103 is provided so that the voltage applied between the two regions separated by the substrate isolation film 20 during normal operation is less than 6.6 V.

[0089] The electric field applied between the two regions separated by the substrate isolation film 20 during normal operation is, for example, less than 50 kV / cm.

[0090] <Effects of the semiconductor device 104> The effects of the semiconductor device 104 will be described in comparison with the comparative example. The semiconductor device according to comparative example 3 differs from the semiconductor device 104 only in that the substrate isolation film is made of a typical low-dielectric-constant material. As described above, the relative dielectric constant of typical low-dielectric-constant materials is 2.6 or more and 2.9 or less. Therefore, the semiconductor device according to comparative example 3 can achieve a higher operating speed of the semiconductor element compared to a semiconductor device including a substrate isolation film made of a dielectric material with a relative dielectric constant greater than 2.9. However, in the semiconductor device according to comparative example 3, when cosmic rays are incident on the single-crystalline layer 30 immediately below the gate insulating film GI, a large number of electron-hole pairs are generated in the single-crystalline layer 30 immediately below the gate insulating film GI, resulting in electrical conduction between the source and drain. As a result, the semiconductor device according to comparative example 3 has difficulty in suppressing the occurrence of soft errors caused by cosmic rays while suppressing a decrease in the operating speed of the semiconductor element.

[0091] In contrast, in the semiconductor device 104, since the substrate isolation film 20 is made of an antiferroelectric material, the relative dielectric constant of the substrate isolation film 20 becomes higher than the relative dielectric constant of the substrate isolation film 20 during normal operation only when the strength of the electric field applied to the substrate isolation film 20 by the abnormal charge exceeds the specific value. Therefore, a portion of the abnormal charge can be captured by the substrate isolation film 20. As a result, in the semiconductor device 104, the occurrence of soft errors can be suppressed while suppressing a decrease in the operating speed of the semiconductor element.

[0092] The semiconductor device 104 may have the same configuration as the semiconductor device 102 or the semiconductor device 103, except that the substrate isolation film is made of an antiferroelectric material.

[0093] As described for the semiconductor device 101, the interlayer insulating film, element isolation film, and substrate isolation film made of an antiferroelectric may also be transformed from an antiferroelectric to a ferroelectric in the semiconductor devices 102 to 104. In this case, by performing a process to return the interlayer insulating film, element isolation film, and substrate isolation film from a ferroelectric to an antiferroelectric, the above-mentioned effects achieved by the interlayer insulating film, element isolation film, and substrate isolation film made of an antiferroelectric in the semiconductor devices 101 to 104 can be reproduced. As described above, an example of a process for returning the interlayer insulating film, element isolation film, and substrate isolation film from a ferroelectric to an antiferroelectric is to apply alternating positive and negative voltages, such as AC, to the element isolation film and substrate isolation film, and gradually reduce this voltage. This process disrupts the ferroelectric crystal structure, allowing the antiferroelectric crystal structure to be reproduced. Another example of a process is to heat the element isolation film and substrate isolation film and then rapidly cool them. This process destroys the ferroelectric crystal structure, allowing the antiferroelectric crystal structure to be reproduced.

[0094] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0095] 1 scribe area, 2 module area, SUB semiconductor substrate, SF1 first surface, 10 bulk layer, 20 substrate isolation film, 30 single crystal layer, 101, 102, 103, 104 semiconductor device, IOC input / output circuit, ANA analog circuit, LC logic circuit, MEM memory circuit, CT contact, C1A first contact CT layer, C1B second contact CT layer, DR drain, SO source, GE gate electrode, GI gate insulating film, ILD interlayer insulating film, ILD1 lower interlayer insulating film, ILD2 upper interlayer insulating film, ILD3 top interlayer insulating film, ISL element isolation film, M, M1 wiring layer, M1A first wiring layer, M1B second wiring layer, M2 top wiring layer, PW p-type well, SW sidewall insulating film, TR MOS transistor.

Claims

1. an interlayer insulating film made of an antiferroelectric material; a minimum value of the relative dielectric constant of the interlayer insulating film being less than 2;

2. 2. The semiconductor device according to claim 1, wherein the maximum value of the relative dielectric constant of said interlayer insulating film is greater than 2.

9.

3. 2. The semiconductor device according to claim 1, wherein the Young's modulus of said interlayer insulating film is 8 GPa or more.

4. 2. The semiconductor device according to claim 1, wherein said interlayer insulating film does not have a plurality of voids formed therein.

5. The residual polarization of the interlayer insulating film is 15 μC / cm 2 2. The semiconductor device according to claim 1, wherein:

6. The material constituting the antiferroelectric is HfO 2 , ZrO 2 , Pb(In 0.5 Nb 0.5 ) O 3 , NbNaO 3 , ZrPbO 3 , TiZrLaPbO 3 , TiZrPbO 3 , N.H. 4 H 2 P.O. 4 , or NH 4 H 2 AsO 4 2. The semiconductor device according to claim 1, wherein the semiconductor device is at least one selected from the group consisting of:

7. 2. The semiconductor device according to claim 1, wherein the thickness of said interlayer insulating film is equal to or greater than 2 nm and less than 50 nm.

8. a pair of conductors sandwiching the interlayer insulating film; 2. The semiconductor device according to claim 1, wherein an electric field applied between said pair of conductors during normal operation is less than an electric field at which spontaneous polarization occurs in said antiferroelectric material.

9. 9. The semiconductor device according to claim 8, wherein an electric field applied between said pair of conductors during normal operation is less than 50 kV / cm.

10. 9. The semiconductor device according to claim 8, wherein said pair of conductors is a pair of wiring layers arranged with said interlayer insulating film therebetween.

11. a pad disposed on the interlayer insulating film; 2. The semiconductor device according to claim 1, wherein spontaneous polarization occurs in said antiferroelectric material when an electric field of 50 kV / cm or more is applied to said pad.

12. After the application of the electric field is stopped, the polarization of the interlayer insulating film is 15 μC / cm 2 12. The semiconductor device according to claim 11, wherein:

13. 2. The semiconductor device according to claim 1, wherein spontaneous polarization occurs in said antiferroelectric material when cosmic rays are incident thereon.

14. the cosmic rays include particle radiation and / or high-energy electromagnetic radiation; the particle radiation includes at least one selected from the group consisting of α rays, β rays, neutron rays, and proton rays; The semiconductor device according to claim 13 , wherein the high-energy electromagnetic radiation includes at least one of gamma rays and X-rays.

15. further comprising a semiconductor substrate having a first surface; the interlayer insulating film is formed on the first surface, a second interlayer insulating film formed between the semiconductor substrate and the interlayer insulating film; 2. The semiconductor device according to claim 1, wherein said second interlayer insulating film is made of a paraelectric conductor.

16. a semiconductor substrate having a first surface; a second interlayer insulating film formed on the first surface; the interlayer insulating film is formed on the second interlayer insulating film, the interlayer insulating film has a second surface; further comprising a pad formed on the second surface; the second interlayer insulating film is made of a paraelectric conductor; 2. The semiconductor device according to claim 1, wherein said antiferroelectric material constituting at least said second surface of said interlayer insulating film has an amorphous structure or a polycrystalline structure.

17. a semiconductor substrate having a first surface; a gate electrode formed on the first surface via a gate insulating film; a sidewall insulating film covering each side surface of the gate insulating film and the gate electrode; an interlayer insulating film formed on the first surface so as to cover the gate electrode and the sidewall insulating film; the interlayer insulating film is made of an antiferroelectric material, The interlayer insulating film is disposed at a distance from the gate insulating film.

18. 18. The semiconductor device according to claim 17, wherein said interlayer insulating film is in contact with said sidewall insulating film.

19. a first step of providing a semiconductor substrate having a first surface; a second step of forming a semiconductor element on the first surface; a third step of forming an interlayer insulating film on the first surface to cover the semiconductor element; the interlayer insulating film is made of an antiferroelectric material, In the third step, the interlayer insulating film is formed at a temperature lower than the Curie point of the antiferroelectric material.

20. 20. The method for manufacturing a semiconductor device according to claim 19, wherein said third step includes a step of adjusting a relative dielectric constant of said interlayer insulating film.

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