Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing bleeding of an adhesive.SOLUTION: A semiconductor device according to an embodiment comprises: a substrate having a first surface; a first adhesive arranged on the first surface; and a first semiconductor chip arranged on the first surface via the first adhesive. Furthermore, the semiconductor device comprises a first insulating member arranged on the first surface in contact with at least a part of the first adhesive. Furthermore, a thickness of the first insulating member is greater than or equal to a thickness of the first adhesive in a first direction perpendicular to the first surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] A semiconductor package is known in which a semiconductor chip is mounted on a substrate using an adhesive. However, bleeding, where the adhesive spreads and flows, is a problem. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-60306 [Patent Document 2] Japanese Patent Application Laid-Open No. 2012-79854 [Patent Document 3] Patent Publication No. 2021-15922 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suppressing bleeding of an adhesive is provided. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a substrate having a first surface, a first contact disposed on the first surface, and a and a first semiconductor chip disposed on the first surface via a first adhesive. In addition, in the semiconductor device according to the embodiment, the first surface is in contact with at least a portion of the first adhesive. Further, the thickness of the first insulating member is The thickness of the first adhesive in a first direction perpendicular to the first direction is equal to or greater than the thickness of the first adhesive. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a top view showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is an enlarged cross-sectional view showing the vicinity of an insulating member of the semiconductor device according to the first embodiment. [Figure 4] 3 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] 2A to 2C are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are schematic cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] FIG. 4 is a cross-sectional view showing a configuration example of a semiconductor device according to a first modified example of the first embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to a second modification of the first embodiment. [Figure 13] FIG. 10 is a top view showing a configuration example of a semiconductor device according to a second modification of the first embodiment. [Figure 14] FIG. 10 is an enlarged cross-sectional view showing the vicinity of an insulating member of a semiconductor device according to a second modification of the first embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to a third modified example of the first embodiment. [Figure 16] FIG. 10 is a top view showing a configuration example of a semiconductor device according to a third modified example of the first embodiment. [Figure 17] FIG. 10 is an enlarged cross-sectional view showing the vicinity of an insulating member of a semiconductor device according to a third modification of the first embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to a third modified example of the first embodiment. [Figure 19] FIG. 10 is a top view showing a configuration example of a semiconductor device according to a third modified example of the first embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment. [Figure 21] FIG. 10 is a top view showing a configuration example of a semiconductor device according to a second embodiment. [Figure 22] FIG. 10 is an enlarged cross-sectional view showing the vicinity of a side surface of a substrate within an opening according to a second embodiment. [Figure 23] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to another modified example. [Figure 24] FIG. 10 is a cross-sectional view showing a configuration example of a semiconductor device according to another modified example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings.

[0008] The drawings referred to below are schematic and do not show the relationship between thickness and planar dimensions or the thickness of each layer. The proportions may differ from the actual figures. In the following description, the same functions and configurations may be used. The same reference numerals are used for the components having the same structure. The letters in the alphabet and the like refer to elements that are referenced by reference symbols containing the same letters and have similar configurations. In this specification, the process includes not only an independent process but also a It also includes combinations with other processes and treatments.

[0009] First, the X direction, Y direction, and Z direction will be defined. The X direction and the Y direction will be described later. The Z direction is a direction parallel to the first surface of the substrate. The Z direction intersects with the X and Y directions (for example, That is, the Z direction is the thickness direction of the adhesive and the insulating member, and the Z direction is the thickness direction of the substrate. The first direction corresponds to the Z direction. The second direction corresponds to the , a direction intersecting the first direction and corresponding to the X direction. This is a direction that intersects with the second direction and corresponds to the Y direction.

[0010] (First embodiment) FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 100 according to the first embodiment. 2 is a top view showing an example of the configuration of the semiconductor device 100 according to the first embodiment. 1, the semiconductor device 100 is a semiconductor device including a substrate, a semiconductor device including a sealing resin 30, and a semiconductor device including a sealing resin 30. 10, adhesive 20, semiconductor chip 21, connecting member 23, sealing resin 30, and metal bar The solder resist 50 is provided.

[0011] The substrate 10 includes solder resists 11a and 11b, a core material 12, a wiring layer 13a, and a The substrate 10 has a first surface 10, a second surface 13b, a via 14, a pad 15, and an electrode 18. The core material 12 has a third surface 10a and a second surface 10b opposite to the first surface 10a. The core material 12 has a fourth surface 12b opposite to the third surface 12a. The substrate 10 is made of an insulating material such as glass epoxy resin. It may also be a multi-layer wiring structure formed by laminating a plurality of insulating layers.

[0012] The solder resist 11a is disposed on the third surface 12a of the core material 12. The strip 11 a covers the third surface 12 a of the core material 12 except for the portion corresponding to the pad 15 . The solder resist 11a is an example of a first insulating layer. The solder resist 11b is disposed on the surface 12b of the substrate 4 except for the portion corresponding to the electrode 18. The solder resist 11b covers the fourth surface 12b of the core material 12. The solder resist 11b is an example of a second insulating layer. In addition, when there is no need to particularly distinguish between the solder resists 11a and 11b, The solder resist 11 is formed on the wiring layers 13a and 13b. are electrically insulated and protected.

[0013] The wiring layer 13a is disposed on the third surface 12a. The wiring layer 13b is disposed on the fourth surface 12b. The wiring layers 13a and 13b are electrically connected to each other through vias 14. When there is no need to particularly distinguish between the line layers 13a and 13b, they will be described as the wiring layer 13.

[0014] The pad 15 is disposed on the third surface 12a of the core material 12. The pad 15 is connected to the first electrode The pad 15 includes a conductive material such as copper (Cu). The metal bump 40 may be a part of the second surface 10b of the substrate 10. The metal bump 40 is electrically connected to the wiring layer 13b via the electrode 18. The metal bump 40 may be a part of the wiring layer 13b. It is used.

[0015] The semiconductor chip 21 is disposed on the first surface 10a via an adhesive 20. The semiconductor chip 21 has pads 2 on the periphery of its surface. The pad 22 is an example of a second electrode. The pad 15 and the pad 22 are The pad 15 is electrically connected to the substrate 10 using a conductive connecting member 23 such as a bonding wire. The connecting member 23 is an example of a first connecting member. .

[0016] The semiconductor chip 21 is, for example, a semiconductor chip such as a NAND flash memory. For example, but not limited to, DRAM (Dynamic Random Access Memory) memory, such as a memory device, a computing device, such as a microprocessor, Any semiconductor chip, such as a signal processing element, can be used. 21 may be a single sheet or a stack of multiple sheets.

[0017] The adhesive 20 is a thermosetting resin. For example, the adhesive 20 is an epoxy resin, a polyimide resin, or the like. The adhesive 20 is, for example, a vinyl resin, an acrylic resin, or a mixture of these. For example, DAF (Die Attach Film) and FOW (Fiber Optic Wire) are available. Film On Wire (FOD) that can embed semiconductor chips In the first embodiment, a film adhesive such as an adhesive 2 The case where 0 is the DAF will be described. The adhesive 20 is an example of the first adhesive.

[0018] When the semiconductor chip 21 is placed on the first surface 10a, the outer edge of the adhesive 20 is in contact with the semiconductor chip 21. In other words, as shown in FIG. 2, the Z direction When viewed from the front, the outer size of the adhesive 20 is larger than the outer size of the semiconductor chip 21. The adhesive 20 spreading and flowing out in this manner will be referred to as "bleeding" hereinafter. The ease of bleeding tends to depend on the thickness and elastic modulus of the adhesive.

[0019] Returning to the explanation of FIG. 1, the sealing resin 30 includes the adhesive 20, the semiconductor chip 21, the connecting member 23, and the like. The sealing resin 30 seals the solder resist 50 and the first surface 10a of the substrate 10. For example, a thermosetting resin such as an epoxy resin is used.

[0020] The solder resist 50 is formed on the first surface 10a of the substrate 10, and covers at least a part of the adhesive 20. The solder resist 50 is an example of a first insulating member. The resist 50 has a gap G1 between it and the semiconductor chip 21 in the X direction or the Y direction. In the example shown in FIGS. 1 and 2, the solder resist is formed and arranged as viewed from the Z direction. The solder resist 50 completely surrounds the adhesive 20. That is, the solder resist 50 is The solder resist 21 is disposed with a gap G1 formed between it and all four sides of the solder resist 21. The solder paste 50 may not be disposed in a portion of the periphery of the adhesive 20. The resist 50 may be disposed around at least a portion of the adhesive 20 when viewed from the Z direction. stomach.

[0021] FIG. 3 is an enlarged cross-sectional view showing the vicinity of the solder resist 50 of the semiconductor device 100. As shown in FIG. 3, the thickness T1 of the adhesive 20 in the Z direction is The thickness T2 of the solder resist 50 is smaller than the thickness T2 of the solder resist 50 in the Z direction. T2 is equal to or greater than the thickness T1 of the adhesive 20 in the Z direction.

[0022] (Method for manufacturing a semiconductor device according to the first embodiment) FIG. 4 is a flowchart used to explain the manufacturing process of the semiconductor device 100 according to the first embodiment. 5 to 10 are diagrams illustrating steps in the manufacture of the semiconductor device 100 according to the first embodiment. 4 is a cross-sectional view showing an example of a cross-sectional structure in the middle of the process. An example of a manufacturing process for the semiconductor device 100 according to this embodiment will be described.

[0023] (Step S1: Substrate Preparation) First, a through hole is formed in the core material 12 using a drill or the like. The via 14 is formed by filling the inside of the through hole with copper or the like. The vias 14 may be formed by plating with copper or the like. As a result, the wiring layer 13, the pads 15, and the electrodes 18 are formed. A solder resist is applied to each of the third surface 12a and the fourth surface 12b. A mask is applied to the solder resist applied to each of the third surface 12a and the fourth surface 12b. The mask has openings at positions corresponding to the pads 15 and electrodes 18. Next, By performing etching using a mask, solder resists 11a and 11b are formed. As a result, the pads 15 and electrodes 18 are exposed to the outside. A substrate 10 as shown in FIG. 5 is manufactured.

[0024] (Step S2: Step of placing an insulating member on a substrate) As shown in FIG. 6, a solder paste is applied to the first surface 10a of the substrate 10 by, for example, silk printing. The solder resist 50 is disposed on the third surface 12a of the core material 12. After the application, a mask is formed at a position corresponding to the solder resist 50, and the solder resist 50 is then applied. The solder resist 50 may be formed by etching the solder resist 50. The solder resist 50 is a part of the solder resist 11a.

[0025] (Step S3: Place the semiconductor chip on the substrate) As shown in FIG. 7, a semiconductor chip 21 with adhesive 20 attached to the backside is mounted on a substrate 10. The solder resist 50 is arranged on the first surface 10a in the X direction or the Y direction. The semiconductor chip 21 is disposed with a gap G1 formed between it and the semiconductor chip 21. The adhesive 20 may bleed due to stress when it is applied to the first surface 10a. Although FIG. 7 shows a case where the adhesive 20 and the solder resist 50 are not in contact with each other, Depending on the degree of bleeding, the adhesive 20 and the solder resist 50 may come into contact with each other. do.

[0026] (Step S4: Baking process) As shown in FIG. 8, the substrate 10 is baked to remove moisture and volatile organic compounds. The adhesive 20 may also bleed during the baking process. In this case, at least a portion of the solder resist 50 and the adhesive 20 are in contact with each other.

[0027] (Step S5: Step of electrically connecting the semiconductor chip and the substrate) As shown in FIG. 9, the pad 15 formed on the third surface 12a of the core material 12 and the semiconductor chip The pads 22 formed on the outer periphery of the surface of the cap 21 are electrically connected by the connecting members 23. To be continued.

[0028] (Step S6: Sealing process) As shown in FIG. 10, an adhesive 20, a semiconductor chip 21, a connecting member 23, a solder resist The entire first surface 10a of the substrate 10 is covered with the sealing resin 30 so that the entire surface of the substrate 10 is covered with the sealing resin 30. The sealing resin 30 is applied by a known method such as a drying process, a heat curing process, or an ultraviolet curing process. , and hardened.

[0029] (Step S7: Forming metal bumps on the substrate) First, a metal ball is placed on the electrode 18 to which flux has been applied. The metal ball is melted and joined to the electrode 18. After that, the flux residue is removed. In this way, metal bumps are formed on the second surface 10b of the substrate 10. By the above steps, the semiconductor device according to the first embodiment shown in FIG. The device 100 is manufactured.

[0030] (Effects of the first embodiment) Mounting Temperature Cycling Test (TCT) ), stress occurs due to the difference in thermal expansion coefficient between the semiconductor chip 21 and the substrate 10. At this time, if the adhesive 20 is thin, it will not be able to absorb the stress sufficiently, and the semiconductor chip 2 There is a concern that the solder resist 50 may peel off from the substrate 10. is disposed on the first surface 10a of the substrate 10 in contact with at least a portion of the adhesive 20. Therefore, it is possible to prevent the thickness of the adhesive 20 from becoming thin due to bleeding. This makes it possible to relieve the stress between the cup 21 and the substrate 10 .

[0031] Furthermore, according to the first embodiment, the thickness of the solder resist 50 in the Z direction is Since the thickness of the adhesive 20 in the direction is greater than or equal to the thickness of the adhesive 20 in the direction Furthermore, according to the first embodiment, When viewed from the Z direction, the solder resist 50 surrounds the entire periphery of the adhesive 20. It is possible to more reliably suppress bleeding of the adhesive 20.

[0032] Furthermore, the adhesive 20 bleeds out, and the surface on which the pads 22 of the semiconductor chip 21 are formed is If the flatness of the pad 22 is impaired, wire bonding cannot be performed under optimal conditions. There is a concern that the bonding strength between the solder and the connecting member 23 may not be ensured. The adhesive 20 is prevented from bleeding by the photoresist 50, and the adhesion in the Z direction is improved. Since the variation in the thickness T1 of the adhesive 20 can be suppressed, step S5 (wire bonding) As a result, the pad 22 and the connection member 23 can be bonded to each other under optimal conditions. The bonding strength can be improved.

[0033] (First Modification) FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device 200 according to a first modification of the first embodiment. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. Detailed explanations will be omitted.

[0034] The first modification differs from the first embodiment in the material of the insulating member. The modified example differs from the first embodiment in that it includes epoxy ink 60. 0 is an example of an insulating member. In the first modification, for example, the first Epoxy ink 60 is applied to the surface 10a of the insulating member 1. Even if the material is different from that of the sheet 11, bleeding of the adhesive 20 can be suppressed. The basic manufacturing method of the first modified example is the same as that of the first embodiment. , the same or similar effects as those of the first embodiment described above can be obtained.

[0035] (Second Modification) FIG. 12 is a cross-sectional view showing a configuration example of a semiconductor device 300 according to a second modification of the first embodiment. 13 is a diagram showing an example of the configuration of a semiconductor device 300 according to a second modification of the first embodiment. 13 is a top view showing the adhesive 20, the semiconductor chip 21, the connecting member 23, The sealing resin 30 is not shown in the drawings. In these cases, the same reference numerals are used and detailed explanations are omitted.

[0036] The second modification differs from the first embodiment in that the semiconductor device 300 is made of an adhesive 320, a semiconductor The semiconductor device further includes a conductor chip 321, a connecting member 323, and a solder resist 350. In the first embodiment, the adhesive 20 is a DAF. In a variant, the adhesive 20 is a FOD that embeds the semiconductor chip 321. More specifically, The adhesive 20 includes a pad 315, an adhesive 320, a semiconductor chip 321, a connecting member 323, and a solder resist 350 is coated.

[0037] The first surface 10a has a first region 10a1 corresponding to the outer shape of the adhesive 20 when viewed from the Z direction. The first region 10a1 has a second region 10a2 different from the first region 10a1. , is an example of a first region, and second region 10a2 is an example of a second region.

[0038] The pad 315 is disposed in an area of ​​the third surface 12a corresponding to the first area 10a1. The pad 315 is an example of a third electrode. The pad 315 is made of a conductive material such as copper (Cu). The pad 315 may be a part of the wiring layer 13a.

[0039] The semiconductor chip 321 is attached to the first area 10a1 of the first surface 10a via an adhesive 320. The semiconductor chip 321 is, for example, a controller. , has a chip area smaller than that of the semiconductor chip 21. That is, the semiconductor chip 21 has a chip area smaller than that of the semiconductor chip 21. The semiconductor chip 321 has a larger chip area than the second semiconductor chip 321. The semiconductor chip 321 has pads 322 on the periphery of its surface. The pad 315 and the pad 322 are connected by a connecting member 323. The connecting member 323 is an example of a second connecting member. The semiconductor chip 321 is connected to the first pad 322. It may be flip-chip mounted on the first region 10a1 of the surface 10a.

[0040] The adhesive 320, which is the DAF, is thinner than the adhesive 20, which is the FOD. The thickness T1 of the adhesive 20 in the Z direction is larger than the thickness T3 of the adhesive 320 in the Z direction, which will be described later. The adhesive 320 is an example of a second adhesive. As shown in FIG. 13, when viewed from the Z direction, When the adhesive 320 is attached to the semiconductor chip 321, the outer size of the adhesive 320 is larger than the outer size of the semiconductor chip 321. Hey.

[0041] Returning to the description of FIG. 12, the solder resist 350 is at least partly composed of the adhesive 320. The solder resist 350 is disposed in the first region 10a1 in contact with the second insulating member The solder resist 350 is an example of the semiconductor chip 12 and 13, a gap G2 is formed between the Z When viewed from the other direction, the solder resist 350 completely surrounds the adhesive 320. The layer resist 350 forms a gap G2 between itself and all four sides of the semiconductor chip 321. However, the solder resist 350 is partially formed around the adhesive 320. Therefore, the solder resist 350 does not have to be disposed on the adhesive 3 when viewed from the Z direction. 20 at least partially around the periphery thereof.

[0042] FIG. 14 is an enlarged cross-sectional view showing the vicinity of the solder resist 350 of the semiconductor device 300. As shown in FIG. 14, the thickness T3 of the adhesive 320 in the Z direction is It is thinner than the thickness T4 of the solder resist 350. That is, the thickness of the solder resist in the Z direction The thickness T4 of 350 is equal to or greater than the thickness T3 of adhesive 320 in the Z direction.

[0043] The basic manufacturing method of the second modified example is the same as that of the first embodiment. In this case, the same or similar effects as those of the first embodiment can be obtained. Since the semiconductor chip 321 is embedded in the adhesive 20, the semiconductor device This allows the size of the device 300 to be reduced.

[0044] According to the second modification, an adhesive having a thickness capable of embedding the semiconductor chip 321 is used. The adhesive 20 may bulge in the Z direction due to bleeding. The rise of the adhesive 20 may cause a bump when stacking another semiconductor chip on the semiconductor chip 21. According to the second modification, the solder resist 50 is The adhesive 20 is disposed on the first surface 10a in contact with at least a portion of the adhesive 20. Even if bleeding of adhesive 20 occurs, it is possible to prevent adhesive 20 from swelling in the Z direction. Cut.

[0045] (Third Modification) FIG. 15 is a cross-sectional view showing a configuration example of a semiconductor device 400 according to a third modification of the first embodiment. FIG. 16 shows an example of the configuration of a semiconductor device 400 according to a third modification of the first embodiment. 16 is a top view showing the adhesives 20b and 20c, the semiconductor chip 21b, and 21c, connecting members 23 and 423, and sealing resin 30 are omitted from the illustration. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. do.

[0046] In the first embodiment, when one semiconductor chip 21 is arranged on the first surface 10a, However, in the third modification, as shown in FIG. 15, a plurality of semiconductor chips 21a to 21b are provided. 1c are stacked in a stepped manner and arranged on the first surface 10a. The pads 15 and 22a are provided on the respective surfaces of the pads 22a to 22c. 22c are electrically connected using a connecting member 23.

[0047] The semiconductor chip 21a is attached to the first area 10a1 of the first surface 10a via the adhesive 20a. The semiconductor chip 21b is arranged on the semiconductor chip 21 so as not to cover the pads 22a. a) in the X direction, and is arranged on the semiconductor chip 21a via the adhesive 20b. The semiconductor chip 21c is attached to the semiconductor chip 21b so as not to cover the pads 22b. The semiconductor chip 21b is disposed on the semiconductor chip 21b via an adhesive 20c while being shifted in the X direction. do.

[0048] In the first embodiment, the adhesive 20 is a DAF. In the example, the adhesive 20a is a FOW that embeds at least a portion of the connection member 423. Specifically, the adhesive 20a covers at least a portion of the pad 415 and the connecting member 423. The adhesives 20b and 20c are DAF.

[0049] The third modification further differs from the first embodiment in that the semiconductor device 400 is 0, a semiconductor chip 421, a connecting member 423, and a solder resist 450. This is the point.

[0050] The pad 415 is disposed in an area of ​​the third surface 12a corresponding to the first area 10a1. The pad 415 is an example of a third electrode. The pad 415 is made of a conductive material such as copper (Cu). The pad 415 may be part of the wiring layer 13a.

[0051] The semiconductor chip 421 has a second region 10a1 different from the first region 10a1 on the first surface 10a. 0a2 via adhesive 420. The semiconductor chip 421 is, for example, a controller The semiconductor chip 421 is an example of a second semiconductor chip. The substrate 1 has a pad 422 on the outer periphery of its surface. The pad 422 is an example of a fourth electrode. The pad 415 and the pad 422 are electrically connected using a connecting member 423. The member 423 is an example of a second connecting member. The pad 415 and the pad 422 are in a one-to-one relationship. are connected.

[0052] The adhesive 420, which is the DAF, is thinner than the adhesive 20a, which is the FOW. The thickness T1 of the adhesive 20a in the Z direction is smaller than the thickness T5 of the adhesive 420 in the Z direction, which will be described later. The adhesive 420 is an example of a second adhesive. When viewed from the outside, the outer size of the adhesive 420 is larger than the outer size of the semiconductor chip 421. It's also big.

[0053] FIG. 17 is an enlarged cross-sectional view showing the vicinity of the solder resist 450 of the semiconductor device 400. As shown in FIG. 17, the thickness T5 of the adhesive 420 in the Z direction is It is thinner than the thickness T6 of the solder resist 450. That is, the thickness of the solder resist in the Z direction The thickness T6 of 450 is equal to or greater than the thickness T5 of adhesive 420 in the Z direction.

[0054] Returning to the description of FIG. 15, the solder resist 450 is formed in the second region 10 of the first surface 10a. a2, and is disposed in contact with at least a portion of the adhesive 420. The solder resist 450 is an example of a second insulating member. 15 and 16, the semiconductor chip 421 is disposed with a gap G3 formed therebetween. In the example shown in FIG. 6, the solder resist 450 is formed on the entire periphery of the adhesive 420 when viewed from the Z direction. That is, the solder resist 450 surrounds all four sides of the semiconductor chip 421. However, as shown in FIGS. 18 and 19, the solder The resist 450 may not be disposed in a part of the periphery of the adhesive 420. The adhesive 420 is surrounded by the photoresist 450. As shown in FIG. 19, the solder resist 450 may be a frame-shaped solder resist. In this way, the entire periphery of the adhesive 420 is covered with the solder. The photoresist 50 and 450 may surround the photoresist.

[0055] The basic manufacturing method of the third modified example is the same as that of the first embodiment. In this case, the same or similar effects as those of the first embodiment described above can be obtained.

[0056] According to the third modification, the first area 10a1 of the first surface 10a on which the adhesive 20a is applied is In such a case, the semiconductor chip 421 is disposed in a second region 10a2 different from the first region 10a. Since at least a part of the connecting member 423 is embedded in the adhesive 20a, the connecting member 423 is This allows the size of the semiconductor device 400 to be reduced in the direction.

[0057] (Second embodiment) 20 is a cross-sectional view showing an example of the configuration of a semiconductor device 500 according to the second embodiment. 1 is a top view showing a configuration example of a semiconductor device 500 according to a second embodiment. In the second embodiment, the sealing resin 30 is not shown. The same reference numerals are used for these components, and detailed explanations will be omitted.

[0058] The second embodiment differs from the first embodiment in that the substrate 10' has an opening 16 and the first surface 1 of the substrate 10' is This embodiment differs from the first embodiment in that no insulating member is provided at Oa.

[0059] The solder resist 11a has a first portion 11a1 disposed in the opening 16 and a second portion 11a2 disposed in the opening 16. The solder resist 11a has a shape of an opening. It corresponds to the shape of part 16.

[0060] The semiconductor chip 21 is disposed in the opening 16 of the substrate 10' via the adhesive 20. The body chip 21 forms a gap G4 between itself and the side surface 19 of the substrate 10' in the opening 16. At least a portion of the adhesive 20 adheres to the side surface 11 of the substrate 10′ within the opening 16. 21, when viewed from the Z direction, the outer size of the opening 16 is The thickness is larger than the outer size of the semiconductor chip 21.

[0061] FIG. 22 is an enlarged cross-sectional view showing the vicinity of the side surface 19 of the substrate 10' in the opening 16. FIG. 22 is also an enlarged view of the dotted frame D in FIG. 20. As shown in FIG. 22, The thickness T7 of the second portion 11a2 of the solder resist 11a is That is, the depth of the opening 16 in the Z direction is equal to or greater than the thickness T1 of the opening 16 in the Z direction. The thickness of the adhesive 20 is equal to or greater than T1.

[0062] The basic manufacturing method of the second embodiment is the same as that of the first embodiment. According to this, the same or similar effects as those of the first embodiment described above can be obtained. The configuration does not require an insulating member, which reduces the cost of the insulating member material. This makes it possible.

[0063] (Other variations) The above-described embodiments and modifications may be combined with each other to the extent possible. For example, , the first embodiment can be combined with the second embodiment as shown in FIG. 23. As shown in FIG. 4, the first variant of the first embodiment can be combined with the second embodiment.

[0064] Although several embodiments of the present invention have been described, these embodiments are presented by way of example only. These novel embodiments are not intended to limit the scope of the invention. It is possible to implement the invention in various other forms, and various modifications are possible without departing from the spirit of the invention. These embodiments and their modifications are within the scope of the invention. It is included in the summary and in the scope of the invention described in the claims and their equivalents. . [Explanation of symbols]

[0065] 10, 10'... substrate, 11... solder resist, 12... core material, 13... wiring layer, 14... bipolar plate A, 15,315,415...pad, 16...opening, 18...electrode, 19...side, 20,3 20,420...Adhesive, 21,321,421...Semiconductor chips, 22,322,422... Pads, 23, 323, 423...connecting members, 30...sealing resin, 40...metal bumps, 50, 350,450...Solder resist, 60...Epoxy ink, 100,200,300, 400, 500, 600, 700...Semiconductor equipment

Claims

1. a substrate having a first surface; a first adhesive disposed on the first surface; a first semiconductor chip disposed on the first surface via the first adhesive; a first insulating portion disposed on the first surface in contact with at least a portion of the first adhesive; Materials and Equipped with In a first direction perpendicular to the first surface, the thickness of the first insulating member is The thickness is equal to or greater than the thickness of the first adhesive. Semiconductor device.

2. The first insulating member is configured to have a first surface extending in a second direction parallel to the first surface. a gap is formed between the semiconductor chip and the The semiconductor device according to claim 1 .

3. When viewed from the first direction, the first insulating member surrounds the entire periphery of the first adhesive. Surround, The semiconductor device according to claim 1 .

4. When viewed from the first direction, the outer size of the first adhesive is It is larger than the outer size of the The semiconductor device according to claim 1 .

5. the substrate has a first electrode on the first surface; the first semiconductor chip has a second electrode on the outer periphery of its surface; a first connection member that electrically connects the first electrode and the second electrode; Further provided with The semiconductor device according to claim 1 .

6. the substrate has a third electrode in a first region where the first adhesive is disposed; a second adhesive disposed in a second region different from the first region; a fourth electrode disposed on the second region via the second adhesive and on the outer periphery of the surface; a second semiconductor chip; a second insulating layer disposed in the second region in contact with at least a portion of the second adhesive; The components and a second connection member that electrically connects the third electrode and the fourth electrode; Furthermore, At least a portion of the second connection member is embedded in the first adhesive. The semiconductor device according to claim 5 .

7. a second adhesive disposed on the first surface; a second semiconductor chip disposed on the first surface via the second adhesive; a second insulating portion disposed on the first surface in contact with at least a portion of the second adhesive; Materials and Furthermore, In the first direction, the thickness of the first adhesive is greater than the thickness of the second adhesive. Large, The first adhesive is a material that is bonded to the second semiconductor chip, the second adhesive, and the second insulating material. Embedding edge members, The semiconductor device according to claim 1 .

8. In the first direction, the thickness of the second insulating member is equal to or greater than the thickness of the second adhesive. Above, The semiconductor device according to claim 7 .

9. the substrate has a second surface opposite the first surface; a first insulating layer on the first surface and a second insulating layer on the second surface; further comprising The semiconductor device according to claim 1 .

10. the first insulating member is made of the same material as the first and second insulating layers; The semiconductor device according to claim 9 .

11. the first insulating member is made of a material different from the first and second insulating layers; The semiconductor device according to claim 9 .

12. a first surface and a second surface opposite the first surface, and an opening in the first surface; A substrate; a substrate disposed in the opening and at least a portion of the substrate being in contact with the side surface of the opening; a first adhesive; a first semiconductor chip disposed in the opening via the first adhesive; Equipped with In a first direction perpendicular to the first surface, the depth of the opening is The thickness of the adhesive is greater than or equal to Semiconductor device.

13. The substrate has a first insulating layer on the first surface and a second insulating layer on the second surface; and The first insulating layer has a first portion disposed inside the opening and a second portion disposed outside the opening. a second part; and further comprising The semiconductor device according to claim 12.

14. When viewed from the first direction, the outer size of the opening is equal to or larger than the outer size of the first semiconductor chip. Larger than the size of the shape The semiconductor device according to claim 12.

15. the substrate has a first electrode on the first surface; the first semiconductor chip has a second electrode on the outer periphery of its surface; a first connection member that electrically connects the first electrode and the second electrode; The first semiconductor chip, the first adhesive, and the first a sealing resin that covers the connection member; Further provided with The semiconductor device according to claim 12.

16. a substrate having a first surface and a second surface opposite the first surface; a first adhesive disposed on the first surface; a first semiconductor chip disposed on the first surface via the first adhesive; When viewed from a first direction perpendicular to the first surface, a portion of the adhesive surrounding the first adhesive is a first insulating member disposed on the first surface in contact with at least a portion of the first adhesive; 、 a first insulating member for embedding the first semiconductor chip, the first adhesive, and the first insulating member; 2 adhesives, a chip area larger than that of the first semiconductor chip, and a second semiconductor chip disposed on the first surface; When viewed from the first direction, the adhesive layer surrounds the second adhesive and at least a second insulating member disposed on the first surface in contact with a portion of the first surface; Equipped with Semiconductor device.

17. The first insulating member is configured to have a first surface extending in a second direction parallel to the first surface. a gap is formed between the semiconductor chip and the The second insulating member is disposed between the second semiconductor chip and the second insulating member in the second direction. are arranged to form gaps, The semiconductor device according to claim 16.

18. The substrate has a first insulating layer on the first surface and a second insulating layer on the second surface; and the first and second insulating members are made of the same material as the first and second insulating layers; The semiconductor device according to claim 16.

19. The substrate has a first insulating layer on the first surface and a second insulating layer on the second surface; and The first and second insulating members are made of a material different from that of the first and second insulating layers. 、 The semiconductor device according to claim 16.

20. When viewed from the first direction, the outer size of the first adhesive is It is larger than the outer size of the When viewed from the first direction, the outer size of the second adhesive is It is larger than the outer size of the The semiconductor device according to claim 16.

Images